Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
>On the PCI bus (64-bit, 66MHz), it shows that for every frame that >was fetch by the MAC, it has to read one descriptor and then write >one descritor, to release the ownership. From the datasheet, we cannot >find ways to burst the frames, in order to decrease the overhead >due to the handling of descriptors. Or is there? Where are the descriptors stored? Off chip RAM? If so, consider putting them on chip. Or you could add special logic to cache a clump of descriptors on chip. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 68851
"arkaitz" <arkagaz@yahoo.com> escribió en el mensaje news:c1408b8c.0404200442.645ab522@posting.google.com... > Hi, > > I have a FF in my design whose reset and set are separate conditions: > > process( rst, clk ) > begin > if ( rst = '1' ) then > output <= '0'; > elsif ( clk'event and clk = '1' ) then > if ( set = '1' ) then > output <= '1'; > end if; > if ( reset = '1' ) then > output <= '0'; > end if; > end if; > end process; > you have two resets on the same FF? one synchronous and another one asynchronous, but i guess you know that :) what are you using "output" for? > This works fine but now I want the reset condition to be a rising edge > detector signal, so: > > process( rst, clk ) > begin > if ( rst = '1' ); > aux <= '0'; > if ( clk'event and clk = '1' ) then > aux <= input; > end if; > end process; > > reset <= not(aux) and input; > so you want to reset the first FF on a rising edge of "input"? then why dont you write the code like that then? > The "input" signal is synchronous to my design and periodical but its > period is about 16 times the clock period. When I execute the > functional simulationwith ModelSim SE 5.6f, the "reset" signal appears > as a glitch since the "input" and "aux" signals change their values in > the same clock edge. > > Because of this, the "output" signal is never reseted. > > I believe that the timing simulation may vary and the design could > work correctly because of the "clock to output" of the FFs, but I'n > not sure. > > Any suggestions? > if you think it'd work in the reality because of the delays, you could use "after" on the signal assignations. you could also try using the asynchronous reset of the first FF but still, i dont think i understand what you're trying to do > Thanks in advance, > > Arkaitz. > > --------------------------- > Electronics Area > IKERLAN > Pº J. M. Arizmendiarrieta, 2 > 20500 Arrasate (Gipuzkoa) > ---------------------------Article: 68852
Peter Alfke wrote: > > Clock Enables vs multiple clocks is a trade-off. > If you are not concerned about power, then a single low0skew global clock > and a "sloppier" network of CEs requires the least amount of thinking. > Multiple derived clocks mean that you have to think about clock transfer > from one clock domain to the next, you may have to use multiple > PLL/DLL/DCMs. That reminds me of another issue. When you use a single clock with clock enables, you have to produce timing constraints to allow the enabled parts of the circuit to be routed with lesser constraints. But this is one part of the design process that is prone to error and has no method of verification that I am aware of. Of course some would say that you only need to "pay careful attention" to the timing constraints, but you can make that argument about *any* part of the design process. The point is that if you use separate clocks, the timing constraints are very simple and much harder to mess up. With a single clock and multiple clock enables, the timing constraints are not so simple and very easy to make mistakes. What is really needed is a method of verification of timing constraints, just like we have verification of other aspects of the design process. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 68853
Thomas Bartzick wrote > what's better for a reliable and compact (fpga!)-design: > - To compose the design structure in state machines as much as > possible? A state machine is a quite limited subset of the synthesizable descriptions available in the synchronous vhdl process template. If you want to try a vhdl description, focus first on learning the synchronous process. > or > - To make strong use of small single components (e.g. FFs, counters, > etc.), for which there can be implemented as library-elements or as > behavioural parts. Schematic or netlist design entry might be reasonable if you don't have time to learn an HDL. > Is there existing a application dependent guide of "good" design? A good design has a working functional testbench, meets static timing, fits in the intended device, and is easy to read and change. -- Mike TreselerArticle: 68854
Hi Muthu, PLLs and DLLs are used to generate clocks of different frequencies by making use of a single input clock. An important characteristic of PLL and DLL output clocks is that they are 'locked' to the input clock. If the clocks are used to clock data through an FPGA, a PLL or DLL will generate an output clock that is a precisely-specified multiple or fraction of the input clock. That is, a PLL or DLL should prevent "clock creep", where data-clocking rates vary ever-so-slightly so that your data processing logic experiences long-term problems with buffer overflows or under-runs. I hope I will be corrected if I am wrong about DLLs, but DLLs will clean up a certain amount of input clock 'jitter' (also called phase-noise). If the relationship between the input frequency and the output frequency is divisible by a power of two, the DLL's output clock should have very little jitter. If the relationship is more arbitrary, the output clock will have a certain amount of jitter. DLL's are great for doubling, quadrupling, or halving input clock rates. They aren't so great if you want a clock division of, say, seven-elevenths, or a clock multiplication of 19.842. A PLL/VCO combination is generally (I believe) less tolerant of input clock jitter, but can produce a more arbitrary clock division or multiplication within a reduce operating range, while minimizing output clock jitter. For example, if you want your FPGA logic to perform a rate conversion of digital audio data from 44.1 KSPS to 32 KSPS while observing jitter restrictions imposed by a standard like AES3, you would likely use a PLL/VCO to perform the clock conversion. If, in this example, jitter was not a concern, a DLL could be used to perform the conversion. If you want parts of your FPGA logic to, say, operate at twice or 4x the input clock rate, you could use a DLL to generate a logic clock that is a multiple of your input clock rate. Best regards, Dwayne Surdu-MillerArticle: 68855
Ray, I've seen that idea presented before but I don't think I can combine mixing/filtering in my case because I'm using the IF mixer to do carrier synchronization so I need to be able to precisely control the LO with an NCO. -Kevin "Ray Andraka" <ray@andraka.com> wrote in message news:408466B4.85D6AF45@andraka.com... > You need a filter in there (unless you are not downsampling and there is no > out-of-band signal), however you can play some optimization tricks with the > math to roll the mixer into the filter if the LO is a multiple of your input > sample rate. What you end up with is a polyphase filter that has the mixer > convolved with it so that you get both mixing and filtering. If you want to > run the mixer slower, that can be done by bandlimiting the signal before the > mix and subsampling. > > Kevin Neilson wrote: > > > When digitally mixing an IF down to baseband, one is left with a spectrum > > that consists of the baseband (Fif - Fmix = 0Hz) and an image (Fif + Fmix). > > If the IF is greater than the Nyquist freq, the image will wrap back into > > the first Nyquist zone (0 to Fn). > > > > Normally the next step in demodulation is decimation, which consists of > > lowpass filtering out the image (often with CICs) and then dropping some of > > the resultant samples to get a lower sample rate. > > > > Is there a method by which an image-reject mixer could mix the IF down to > > baseband while simultaneously cancelling the image? If so, it seems like > > there would be no filtering required for decimation, which would consist > > entirely of throwing samples out. Then it also seems that the mixer itself > > could run at the slower decimated rate. > > > > Or is that all just another way of saying "undersampling"? > > -Kevin > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759 > >Article: 68856
t.bartzick@gmx.net (Thomas Bartzick) wrote in message news:<cdd36e13.0404200619.175f2416@posting.google.com>... > Hi, > > what's better for a reliable and compact (fpga!)-design: > > - To compose the design structure in state machines as much as > possible? > > or > > - To make strong use of small single components (e.g. FFs, counters, > etc.), for which there can be implemented as library-elements or as > behavioural parts. > > Any preferences? My preference is for a design that functions reliably and can be understood by a human six weeks after it was coded. In other words, neither of your choices. Some designs lend themselves well to formal state-machine descriptions (like, say, an SDRAM controller). Others will need a mixture of things. A DMA controller will usually have some sort of state-machine control, but will use counters for the addressing mechanisms, and will have some other glue logic to handle corner cases and such. I avoid directly instantiating vendor library models as much as possible, as it makes porting between vendors (and even device families within a single vendor's portfolio) difficult. If there's something that I must instantiate, I put it in a module instantiated by the higher-level code. A generate can be used to select the module with the library element or a different module with a behavioral model, or a module with a library element for a different device/family. Really, trying to pigeonhole all of your designs into one style of coding is a bad idea. -aArticle: 68857
Andrew Leo wrote: > > Hi, there: > > I went for an interview with a R&D center of an american company. > One week after the interview the interviewer sent me a letter asking me > to sign a paper for background check..What does that mean? AFAIK > this is not customery in my country...Under what circumstance do they > ask for background check? How do I know whether they abuse my > rights? What kind of information may they check and what not? Is it > compulsory for an american co to perform this check? Some employers are now asking for information about the potential employee that would have been considered an invasion of privacy just 10 years ago. One notable company is Tellabs. A few years ago they invited me to interview with them and sent me a package of papers to sign prior to the interview. In the package were four different forms asking permission to investigate aspects of my private life. One was a financial form for them to look into my credit and financial accounts. Another was a background investigation for them to look up my personal/criminal history. A third was permission to give me a drug test. But the one that really got me was the permission to look into my medical records!!! I told them that this was not acceptable. I should have simply not interviewed at all, but they compromised to let me interview without signing the forms with the understanding that I would have to sign before they would hire me. The interview was equally strange. They had a "hiring" lobby with very small interview rooms at one end. It was clear that this entire area was a "poor stepchild" with broken tables and no decorations; just the opposite of how most companies present themselves to prospective employees. In the end they did not follow through with a follow up interview or an offer. But I am sure at least part of this was due to my balking at signing the permission forms. The entire hiring process requires a certain amount of trust on the part of both parties. That is why hiring is not permanent. I don't see how offering a job is such a momentous financial commitment that it requires giving up personal privacy that would otherwise be illegal. You don't have to release medical records even for a security clearance. To answer your question, a background check can include anything about your past that they care to investigate. It will clearly include a criminal history check and employment verification. I can also include interviews with family, friends and those or may not be so friendly. When the government does this, you are guaranteed an opportunity to respond to any negative comments. But with an employeer, you have no rights if they don't like what they hear. In fact, you will likely never be told what was even said that they didn't like. My suggestion is to walk away from this employer and to explain to them why. Their attitude is likely that if you don't want to allow a check, you must have something to hide. But if enough potential employees take the high road, they will eventually realize that their policy is hurting them more than it is helping. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 68858
arkagaz@yahoo.com (arkaitz) wrote in message news:<c1408b8c.0404200442.645ab522@posting.google.com>... > Hi, > > I have a FF in my design whose reset and set are separate conditions: > > process( rst, clk ) > begin > if ( rst = '1' ) then > output <= '0'; > elsif ( clk'event and clk = '1' ) then > if ( set = '1' ) then > output <= '1'; > end if; > if ( reset = '1' ) then > output <= '0'; > end if; > end if; > end process; Ask yourself: "What happens when both set and reset are simultaneously asserted?" You may have a problem here. > This works fine but now I want the reset condition to be a rising edge > detector signal, so: > > process( rst, clk ) > begin > if ( rst = '1' ); > aux <= '0'; > if ( clk'event and clk = '1' ) then > aux <= input; > end if; > end process; > > reset <= not(aux) and input; > > The "input" signal is synchronous to my design and periodical but its > period is about 16 times the clock period. When I execute the > functional simulationwith ModelSim SE 5.6f, the "reset" signal appears > as a glitch since the "input" and "aux" signals change their values in > the same clock edge. I notice that the second process doesn't have "elsif (clk'event ...)," rather, it's simply an "if" in parallel with the async reset. What does the signal "aux" look like in your simulation? > Because of this, the "output" signal is never reseted. > > I believe that the timing simulation may vary and the design could > work correctly because of the "clock to output" of the FFs, but I'n > not sure. No, it looks like a coding error to me. --aArticle: 68859
"rickman" <spamgoeshere4@yahoo.com> wrote in message news:408551E5.132C60F3@yahoo.com... > The point is that if you use separate clocks, the timing constraints are > very simple and much harder to mess up. With a single clock and > multiple clock enables, the timing constraints are not so simple and > very easy to make mistakes. Hey Rick, Very true! The only exception could be that bit in the multi-clock design where the signals travel from one clock domain to another. If you go the 'enabled' route you need only worry about getting that enable correct. The multi-clock route could have a lot of places where signals cross domains, each needing attention in the timing constraints, both delay and skew. So, I'm a convert to the 'enabled' way. I use that circuit you stuck on here a few months back (ta very much!) to generate my enables, and I have a Perl script to work out the MAXDELAYs from the two clock rates, net delays and Tckos, Ticks. I've found that the NET "CLK_EN" TNM=FFS "CLK_EN_FFS"; is pretty reliable these days, especially if you use the 'direct_enable' directive in Synplify. It would be even nicer if you could group stuff into timing groups in the source code, but that's not really there yet. Which makes me think, why isn't easy timing constraints part of the RTL HDL languages? cheers, Syms.Article: 68860
Arkaitz, Logic looks OK except I would have used elsif clause. I suspect that your "input" signal, although synchronous, is external to the block you're simulating. If so, assert it _in_the_simulation_ on a falling clock edge. Think of it this way. Label the rising edges T=0,1,2,3. Then if input goes high on clk T=2, it really goes high "a little while after" T=2 but well before T=3 (we hope! but timing is outside the scope of functional simulation). So by asserting it at T=2.5 (ie falling edge) you're telling the simulator that "input" was low at T=2 but high at T=3... which is (hopefully) what you want. I found it confusing at first but got used to it after a while. Other people may think of it differently and perhaps more elegantly. Hope this helps, -rajeev- --------------- arkagaz@yahoo.com (arkaitz) wrote in message news:<c1408b8c.0404200442.645ab522@posting.google.com>... > Hi, > > I have a FF in my design whose reset and set are separate conditions: > > process( rst, clk ) > begin > if ( rst = '1' ) then > output <= '0'; > elsif ( clk'event and clk = '1' ) then > if ( set = '1' ) then > output <= '1'; > end if; > if ( reset = '1' ) then > output <= '0'; > end if; > end if; > end process; > > This works fine but now I want the reset condition to be a rising edge > detector signal, so: > > process( rst, clk ) > begin > if ( rst = '1' ); > aux <= '0'; > if ( clk'event and clk = '1' ) then > aux <= input; > end if; > end process; > > reset <= not(aux) and input; > > The "input" signal is synchronous to my design and periodical but its > period is about 16 times the clock period. When I execute the > functional simulationwith ModelSim SE 5.6f, the "reset" signal appears > as a glitch since the "input" and "aux" signals change their values in > the same clock edge. > > Because of this, the "output" signal is never reseted. > > I believe that the timing simulation may vary and the design could > work correctly because of the "clock to output" of the FFs, but I'n > not sure. > > Any suggestions? > > Thanks in advance, > > Arkaitz. > > --------------------------- > Electronics Area > IKERLAN > Pº J. M. Arizmendiarrieta, 2 > 20500 Arrasate (Gipuzkoa) > ---------------------------Article: 68861
In article <c635ne$sjp$1@reader01.singnet.com.sg>
asdf@aef.com "Andrew Leo" writes:
> Hi, there:
>
> I went for an interview with a R&D center of an american company.
> One week after the interview the interviewer sent me a letter asking me
> to sign a paper for background check..What does that mean? AFAIK
> this is not customery in my country...Under what circumstance do they
> ask for background check? How do I know whether they abuse my
> rights? What kind of information may they check and what not? Is it
> compulsory for an american co to perform this check?
Most often the background check will be with former employers. However,
depending on the type of work you are interviewing for, you may find
that the employer will need more in-depth details of your background.
Whatever they want they should make it clear what checks they are
conducting. The only exception may be a government company when
they will really run you through the mill. When they do it can be
quite daunting for you, your family and your friends.
My current clients, like another respondent, also asked permission
to obtain my medical history. All with nothing but the best of
intentions of course as I am a classified radiation worker in my
current position. In addition to the gaining of the medical history
they also put me through a very thorough medical each and every year.
The best advice is:-
* ensure that they make the reasons for asking for the background
check very clear to you. The final appointment may depend on you
being trustworthy enough for the position (especially if there
is an element of responsibility for money).
* be honest with them, even if your past is not quite so squeaky
clean.
--
********************************************************************
Paul E. Bennett ....................<email://peb@amleth.demon.co.uk>
Forth based HIDECS Consultancy .....<http://www.amleth.demon.co.uk/>
Mob: +44 (0)7811-639972 .........NOW AVAILABLE:- HIDECS COURSE......
Tel: +44 (0)1235-811095 .... see http://www.feabhas.com for details.
Going Forth Safely ..... EBA. www.electric-boat-association.org.uk..
********************************************************************
Article: 68862Thanks for the hint Paulo. I did follow the Project Options flow as you suggested the first time around. The only time the sub-module flow in Nav created a BMM file with BRAM locations is when I selected the sub-module (as top design) only and did the full implementation. My top level schematic was out of the picture using this method, so that implementation with the sub-module as a the new top level design was not useful. I read that Xilinx only allows association of the BMM file with the top level design. Trying to move the BMM file from the sub-module to associate with the schematic top level design only resulted in a BRAM error, which I expected. My understanding of a sub-module is for instantiation in a top level design. Since the BMM with placements is generated only for a top level design, I would never get a BMM file with placements with my schematic top level design, since the BMM file is associated with a sub-module. So my conclusion is that XPS allows exporting a sub-module to an existing top level design in Nav, but Nav is inconsistent in that it won't generate the placement vesion of the BMM file since the sub-module is by definition not the top level design. If you have a sample project with a XPS submodule and bitgen generated BMM file with placements, I would like to see it. Xilinx gave up on my web case 527286. "Paulo Dutra" <paulo.dutra@xilinx.com> wrote in message news:408470CE.5030802@xilinx.com... > Probably, your hieararchy path in the BMM doesn't correctly > reflect your submodule path. In submodule flow, platgen > generates a system_stub.bmm instead of the system.bmm. The > system_stub.bmm contains hierarchy path of the submodule > in your system. > > In xps, selecting "Project Options" -> "Hierarchy & Flow", > you can submodule flow plus add the instance name of the > instantiate submodule in your schematic toplevel. This > written to system_stub.bmm > > It's bitgen in the iSE flow, that writes out system_stub_bd.bm > that contains the placement info of the blockrams. The > system_stub_bd.bm by data2mem to initialize your bitstream. > > Morris Ho wrote: > > Tools used: EDK and ISE 6.2 on Win2000. I compiled the Memec HelloWorld > > project and successfully ran it on their Spartan IIELC reference design > > board. > > > > With this working project, I changed its properties to a sub-module and > > exported it to Project Navigator project that had a schematic top level > > file. I created the library symbol for the sub-module, placed the > > sub-module and an counter on the schematic and I ran it all the way to > > Generate Programming File. When I downloaded the bit file, the counter > > worked, but the Microblaze did not. Even going back to Platform Studio and > > using the import function did not create a working bit file. > > > > I found by extensive poking around that the Project Navigator does NOT > > automatically update the BMM file with the newly placed locations of BRAM > > that holds the Microblaze program. (The export from XPS did add a > > system.BMM, but that file did not have any placement info--the file just had > > the names of the BRAM instances and the memory bit positions.) Data2Mem > > needs the placement information to create a new download file. I found that > > I could use the FPGA editor in Project Navigator to find out where the last > > PAR operation put the BRAMs. I created a new BMM file from the system.BMM > > and included the placement info. Specifying this BMM file with the .ELF > > allowed Data2Mem to create a WORKING Microblaze sub-module bit file. You > > can manually run Data2Mem in the Project Navigator or use the dialog in XPS > > (which calls Data2Mem in the script) as long as you supply the correct BMM > > file. > > > > A valid line in a BMM text file for Data2Mem is: > > bram_1mb/bram_1mb/ramb4_s2_s2_0 [31:30] PLACED = R3C0; > > > > The BMM files exported to Project Navigator by XPS did not have the field > > starting with "PLACED.." After going from PAR to bit file creation, the BMM > > file still did not change, even though the subsequent Data2Mem procedure to > > combine the ELF data requires placement info in the BMM. It is quite > > reasonable not to supply any placement before PAR, because PAR is allowed to > > move things around, but the final placement info should be extracted and > > updated into the BMM file. In this example, I manually added the placement > > information. > > > > I have seen a few posts regarding this problem. Is there a button or > > procedure in Project Navigator to automatically extract new BRAM locations > > and update the BMM file? Of course I already have a work-around, like > > forgetting about sub-modules and keeping the project exclusively in XPS ! > > > > > > > -- > / 7\'7 Paulo Dutra (paulo.dutra@xilinx.com) > \ \ ` Xilinx hotline@xilinx.com > / / 2100 Logic Drive http://www.xilinx.com > \_\/.\ San Jose, California 95124-3450 USA >Article: 68863
Hi,all After synthesis(Synplify Pro), I got the number of the total LUTs I consumed How to caculate how many logic gates I used? The device is Xilinx VirtexE. Thanks.Article: 68864
Jason, Run the Xilinx Translate tool. Then run the Mapper. Look in the .mrp file, the 'Xilinx Mapping Report File'. It tells you the number of gates. There's a line somewhere that says:- 'Total equivalent gate count for design: 1,790,097' Your number may vary dependent on many things!! Treat it with the contempt it deserves! Cheers, Syms. "Jason" <zhanch@hotmail.com> wrote in message news:48925557.0404201429.674fd077@posting.google.com... > Hi,all > After synthesis(Synplify Pro), I got the number of the total LUTs I consumed > How to caculate how many logic gates I used? > The device is Xilinx VirtexE. > Thanks.Article: 68865
"Symon" <symon_brewer@hotmail.com> wrote in message news:<c63qg2$7ovs9$1@ID-212844.news.uni-berlin.de>... > "rickman" <spamgoeshere4@yahoo.com> wrote in message > news:408551E5.132C60F3@yahoo.com... > > The point is that if you use separate clocks, the timing constraints are > > very simple and much harder to mess up. With a single clock and > > multiple clock enables, the timing constraints are not so simple and > > very easy to make mistakes. > Hey Rick, > Very true! The only exception could be that bit in the multi-clock design > where the signals travel from one clock domain to another. If you go the > 'enabled' route you need only worry about getting that enable correct. The > multi-clock route could have a lot of places where signals cross domains, > each needing attention in the timing constraints, both delay and skew. > So, I'm a convert to the 'enabled' way. I use that circuit you stuck on here > a few months back (ta very much!) to generate my enables, and I have a Perl > script to work out the MAXDELAYs from the two clock rates, net delays and > Tckos, Ticks. I've found that the > NET "CLK_EN" TNM=FFS "CLK_EN_FFS"; > is pretty reliable these days, especially if you use the 'direct_enable' > directive in Synplify. It would be even nicer if you could group stuff into > timing groups in the source code, but that's not really there yet. Which > makes me think, why isn't easy timing constraints part of the RTL HDL > languages? Good question. Recently I've been planing how to incorporate timing constraints in Confluence. Because Confluence has implicit clock enables, I think there is opportunity for semi-automated timing constraints. For example, designers would only have to place constraints on multi-cycle enables; the tools would then automatically determine which paths are multi-cycle. And since clock domains are also implicit, it should be farily straight forward to issue warnings on unconstrained false-paths. Regards, Tom -- Launchbird Design System, Inc. http:www.launchbird.comArticle: 68866
Hi,all After synthesis(Synplify Pro), I got how many LUTs I consumed, How to equally convert it to the number of logic gates? The device is the Xilinx VirtexE. Thanks, JasonArticle: 68867
Hi, I'm doing a project in clockless uart..as u know that the primary function of uart is parallel to serial conversion while transmitting and serial to paralel conversion while receiving..I was wondering if someone could tell me as how can i do a parallel to serial conversion and vice versa without using a clock. Thank You SHASHIArticle: 68868
>After synthesis(Synplify Pro), I got how many LUTs I consumed, >How to equally convert it to the number of logic gates? The device is >the Xilinx VirtexE. Quick answer: There isn't any easy way. It depends upon how much logic your design put in each LUT. Crazy question... What's the most number of gates that anybody has ever put into a LUT? Might be a fun hack to try all possible functions, translate to gates, maybe run some minimization stuff, and remember the worst case. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 68869
Hal Murray wrote: >>After synthesis(Synplify Pro), I got how many LUTs I consumed, >>How to equally convert it to the number of logic gates? The device is >>the Xilinx VirtexE. > > > Quick answer: There isn't any easy way. It depends upon how much > logic your design put in each LUT. > > Crazy question... What's the most number of gates that anybody > has ever put into a LUT? Might be a fun hack to try all possible > functions, translate to gates, maybe run some minimization stuff, > and remember the worst case. No no.. don't even _think_ about that, imagine what the market droids could do with that information!! :) -jgArticle: 68870
Without being specific on your error messages, I can't really help u. But, more than likely you're getting an error in ngdbuild with the associated path in the BMM not matching your hierarchy path. To find the known hierarchy path. Run the design without the BMM in iSE. Once processed through par, bring the design up in FPGA editor. You can find BRAM components with instance paths. Your BMM needs to have the hierarchy path as identified in FPGA editor. Morris Ho wrote: > Thanks for the hint Paulo. > > I did follow the Project Options flow as you suggested the first time > around. The only time the sub-module flow in Nav created a BMM file with > BRAM locations is when I selected the sub-module (as top design) only and > did the full implementation. My top level schematic was out of the picture > using this method, so that implementation with the sub-module as a the new > top level design was not useful. > > I read that Xilinx only allows association of the BMM file with the top > level design. Trying to move the BMM file from the sub-module to associate > with the schematic top level design only resulted in a BRAM error, which I > expected. -- / 7\'7 Paulo Dutra (paulo.dutra@xilinx.com) \ \ ` Xilinx hotline@xilinx.com / / 2100 Logic Drive http://www.xilinx.com \_\/.\ San Jose, California 95124-3450 USAArticle: 68871
Simple answer: You cannot. You can of course generate your own clock... Peter Alfke > From: shashi22k@rediffmail.com (Shashi) > Organization: http://groups.google.com > Newsgroups: comp.arch.fpga > Date: 20 Apr 2004 16:35:16 -0700 > Subject: Issues on Shift Register in a Clockless UART > > Hi, > I'm doing a project in clockless uart..as u know that the primary > function of uart is parallel to serial conversion while transmitting > and serial to paralel conversion while receiving..I was wondering if > someone could tell me as how can i do a parallel to serial conversion > and vice versa without using a clock. > > Thank You > SHASHIArticle: 68872
Many years ago, i tried to come up with the largest number of 2-input NAND gates that could be hidden in a 4-LUT. I thing the number was around 20. It involved many XORs which count as four NANDs. There must be a scientific answer to this: What's the function of four variables that irreducibly requires the largest number of 2NAND functions to implement ? Peter Alfke > From: hmurray@suespammers.org (Hal Murray) > Newsgroups: comp.arch.fpga > Date: Wed, 21 Apr 2004 00:08:31 -0000 > Subject: Re: calculate the number of logic gate in FPGA > >> After synthesis(Synplify Pro), I got how many LUTs I consumed, >> How to equally convert it to the number of logic gates? The device is >> the Xilinx VirtexE. > > Quick answer: There isn't any easy way. It depends upon how much > logic your design put in each LUT. > > Crazy question... What's the most number of gates that anybody > has ever put into a LUT? Might be a fun hack to try all possible > functions, translate to gates, maybe run some minimization stuff, > and remember the worst case. > > -- > The suespammers.org mail server is located in California. So are all my > other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited > commercial e-mail to my suespammers.org address or any of my other addresses. > These are my opinions, not necessarily my employer's. I hate spam. >Article: 68873
hi guys,
im having some trouble with reading from a file, actually the thing is the
opening part.
the problem is that i "dont" know the name of the file to read before
compiling, that is because i've a "configuration" file where i give
commands, one of them being the name of the "input" file.
i know i could use a function, but that only works when i've a small amount
of data to read, cause otherwise, storing a HUGE array slows down the
simulation, without saying that modelsim tells me that i has not enough
memory and will start paging to disk and after a while it says that i got
completely out of memory.
Simulation works perfect if i read one line (of the input file) at the time,
but that means that the filename has to be written on the code (at least
that's how i've been doing, by using ' file fp : TEXT is in "input.dat"; ')
now i need to open an arbitrary file, so i tried "file_open(fp,
filenameString, READ_MODE);" the problem is that somehow it doesnt work, as
it seems that if i open the file in one process (i have to open the file
just once and read it till the end of the file at every rising_edge(clk), so
that's two processes). It doesnt work cause it seems that the file is
"closed" outside the process it was opened (i think i even read about that
issue).
Also i cant find "file_open" declaration.
i also tried with a process like this: (im at home now, so i dont have the
real sources, but i cant sleep so im writing to ask for help :) please)
process
begin
if (filenameString /= nothing) then
file_open(fp, filenameString, READ_MODE);
while (not endfile(fp)) loop
wait until rising_edge(clk);
read(fp, data);
etc, etc
end loop;
file_close(fp);
end if;
end process;
that didnt work either, im not sure if it was because of the file_open part
(i also did a check on the opening, it was succesful) or because the process
get in an infinite loop, modelsim just stop responding (i think that endfile
might return false if the file is not open, giving rise to the infinite
loop, but the loop would at least be "waiting" for "clk" and it would
actually read the data, but that doesnt happen). The file might get closed
once "out" the process (like when another process gets executed) or
something, i have no clue...
do any of you knows or have faced already this kind of situation? namely,
reading a file whose name's specified after compilation (by another file)
line by line (that is, not using a function to read a whole chunk of data
and storing it in an array)
any comments will be appreciated, thanks
Paris
Article: 68874hmurray@suespammers.org (Hal Murray) wrote in message news:<108aipgspj1o8d@corp.supernews.com>... > >On the PCI bus (64-bit, 66MHz), it shows that for every frame that > >was fetch by the MAC, it has to read one descriptor and then write > >one descritor, to release the ownership. From the datasheet, we cannot > >find ways to burst the frames, in order to decrease the overhead > >due to the handling of descriptors. Or is there? > > Where are the descriptors stored? Off chip RAM? If so, consider > putting them on chip. Or you could add special logic to cache > a clump of descriptors on chip. Thanks for your suggestions Hal. In our platform, the FPGA (Spartan IIe-300) connects to the MAC-PHY chip directly via the PCI bus. The CPU (AMD Alchemy) is also on the PCI bus. These are the only 3 devices on the PCI bus. After CPU sets up the transmit frames and descriptors in the FPGA, and set up the necessary registers inside the MAC, it initiates the FPGA to start the traffic generation. The FPGA issues a PCI write transaction to one of the MAC registers to start the operation. The MAC becomes a PCI master, fetching the descriptors and frams from the FPGA. Each time a frame a fetched, the MAC writes a descriptor (in the FPGA) to clear a OWN bit. If the traffic generator operation is still in progress, the FPGA will immediately reset the OWN bit to '1', so that the MAC knows it has ownership of that particular descriptor. I think our PCI bus timing cycles show that the system is working correctly. Just that there is no way to burst a number of frames to the MAC. This is the bottle neck for 64-byte frames. We can only achieve at best 680Mbps on the line side. Regards, LC
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z