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hi,
We are planning a data acquisition system with 4-12 sub units. Each sub unit
produce data of 25MBit/sec. The distance between the boxes and computer is
about 2 meters.
I'm willing to transfer and analyze the data in real-time. I'm willing to
close a control loop in 1-5msec (I. wish 100usec ......).
What is the recommended serial protocol?
The sub units will be in-house made the host computer for data analysis and
storage will be a PC (probably with raid HD).
What communication HW/protocol should I use in my sub units?
What communication HW/protocol should I use in the PC?
Regards
Pini
PS
There is a discussion about this tread at comp.realtime
Article: 69126"RM" <mainr@_spamjam_bigfoot.com> skrev i meddelandet news:P8-dnWASwLiTjBHdRVn-vA@edaptivity.com... > I'm looking a microcontroller with the following properties: > - Includes a USB port interface, which is used for programming all functions > (ideal case). Alternatively, initial function programming could be via JTAG, > but once programmed the device must support USB. > - Program should be flash-based. EZUSB requires initial program load via USB > whenever the device is re-attached to the USB host. I wish to program device > functionality once, and this program should be retained when the device is > detached from USB. > - CPLD (or FPGA with non-volatile program storage / autoload (autoload could > be performed by microcontroller)) to support reconfigurable hardware > functions. > > Anyone know of such a device? > > Thanks, > R. Main. > What is the problems with an external CPLD? What do you want to implemente there? The AT89C5131/AT89C5132/AT89C51SND1 will do everything else. -- Best Regards, Ulf Samuelsson ulf@a-t-m-e-l.com This is a personal view which may or may not be share by my Employer Atmel Nordic ABArticle: 69127
I'm using Quartus II 2.2 with service pack 2 and SoPC Builder 2.7 but when generating the system, I get a number of "grep: not found" errors. I checked the Altera website but I couldn't find anything. Has anyone had similar problems/know why these errors are occuring? Please CC any replies to this group to me at pelletie@caltech.edu. Thanks! A more detailed report is as follows: Altera SOPC Builder Version 2.6 Copyright (c) 1999-2002 Altera Corporation. All rights reserved. # 2004.04.27 15:06:14 (*) mk_custom_sdk starting # 2004.04.27 15:06:14 (*) Reading project # 2004.04.27 15:06:15 (*) Finding all available components # 2004.04.27 15:06:23 (*) Finding all CPUs # 2004.04.27 15:06:23 (*) Finding all peripherals # 2004.04.27 15:06:23 (*) Generating gnu SDK for nios_0 # 2004.04.27 15:06:23 (*) Copying Files for nios_0 # 2004.04.27 15:06:24 (*) Generating Memory Map for nios_0 # 2004.04.27 15:06:24 (*) Generating Makefile and excalibur.h for nios_0 grep: not found grep: not found grep: not found grep: not found grep: not found grep: not found grep: not found grep: not found grep: not found grep: not found grep: not found grep: not found grep: not found grep: not found grep: not found grep: not found # 2004.04.27 15:06:31 (*) Wrote gnu tcl script for nios_0 grep: not found grep: not found grep: not found grep: not found grep: not found grep: not found grep: not found grep: not found # 2004.04.27 15:06:33 (*) Making Library grep: not found grep: not found grep: not found grep: not found grep: not found grep: not found grep: not found grep: not found /c: Can't open /c: No such file or directory make: *** [obj32] Error 2 # 2004.04.27 15:06:36 (*) Building onchip_memory_0_contents.srec using "germs" # 2004.04.27 15:06:36 (*) cd d:/qdesigns/ee52/minimalnios ; nios-build --sdk_directory=d:/qdesigns/ee52/minimalnios/nios_0_sdk -np -s -o onchip_memory_0_contents.srec -b 8192-16384 d:/qdesigns/ee52/minimalnios/nios_0_sdk/lib/nios_germs_monitor.s grep: not found grep: not found grep: not found grep: not found grep: not found grep: not found grep: not found grep: not found Can't locate strict.pm in @INC (@INC contains: /cygdrive/c/altera/excalibur/sopc_builder/bin/perl_lib:/cygdrive/c/altera/excalibur/sopc_builder/bin/europa:/cygdrive/c/altera/excalibur/sopc_builder/bin: .) at - line 3. BEGIN failed--compilation aborted at - line 3. # mk_custom_sdk: WARNING 512 cd d:/qdesigns/ee52/minimalnios ; nios-build --sdk_directory=d:/qdesigns/ee52/minimalnios/nios_0_sdk -np -s -o onchip_memory_0_contents.srec -b 8192-16384 d:/qdesigns/ee52/minimalnios/nios_0_sdk/lib/nios_germs_monitor.s ERROR: Could not build Peripheral Contents for nios_0 Error in processing. System NOT successfully generated.Article: 69128
Hi Bill, Yes my design did not match what I was describing. The other piece that puzzled me was why the register was always in its own LE. And as you say, the enable cannot be fed by the same LE's LUT, which I see now in the Stratix handbook. It all makes sense now. Thanks. -- Pete incorrigible@comcast.net (Bill) wrote in message news:<680e8d30.0404270659.60099863@posting.google.com>... > Pete, > > The way you've coded this, once the enable is active while the xor > equation is true, the flop will be set to "1" and ALWAYS remain "1", > unless the async reset goes active. The flop retains a "1" regardless > of the state of the enable or the 4-input function. Even if you > forced the tool to use the enable, it would still require a 5-input > function (two LEs) This function would be the 4-input equation or'd > with flop's current value. > > When f = a xor b xor c xor d the following truth table represents your > function: > > ena | f | current | next > ------------------------- > 0 | 0 | 0 | 0 > 0 | 1 | 0 | 0 > 1 | 0 | 0 | 0 > 1 | 1 | 0 | 1 > X | X | 1 | 1 > > > The functions are implemented in separate LEs, as Synplify has chosen > to use the flop's enable and in Stratix the enable cannot be driven > directly by the result of the associated LUT. > > I don't think you've coded your intended functionallity. If it's > coded as follows, it implements in a single LE using the clock enable > and the 4-input LUT. In this case, the flop loads the result of the > xor equation when the enable is active and retains its current value > when the enable is inactive. > > process( clk, rst_n ) > begin > if rst_n='0' then > sig <= '0'; > elsif clk'event and clk='1' then > if ena='1' then > if (a xor b xor c xor d)='1' then > sig <= '1'; > else > sig <= '0'; > end if; > end if; > end if; > end process; > > An alternative coding would be: > > process( clk, rst_n ) > begin > if rst_n='0' then > sig <= '0'; > elsif clk'event and clk='1' then > if ena='1' then > sig <= a xor b xor c xor d; > end if; > end if; > end process; > > BillArticle: 69129
>We are planning a data acquisition system with 4-12 sub units. Each sub unit >produce data of 25MBit/sec. The distance between the boxes and computer is >about 2 meters. >I'm willing to transfer and analyze the data in real-time. I'm willing to >close a control loop in 1-5msec (I. wish 100usec ......). >What is the recommended serial protocol? >The sub units will be in-house made the host computer for data analysis and >storage will be a PC (probably with raid HD). >What communication HW/protocol should I use in my sub units? >What communication HW/protocol should I use in the PC? One straw man would be 100 megabit ethernet. That lets you use off-the-shelf gear on the PC end. For 12 sub units, you probably need a gigabit ethernet card on the PC and a 12 port switch with a gigabit uplink. (It also gives you lots of flexibility on the length which might be handy some day.) If you want to build your own PCI card, look at LVDS. 25 megabits should be easy at 2 meters. Manchester encoding costs a factor of 2 in link bandwidth (which you have lots of) but it's real simple to decode. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 69130
>Legacy tracks do not have the appropriate bank. I assumed they would have to fixup the tracks in order to make them good enough to go fast so it would be reasonable to fix the bank at the same time. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 69131
"Symon" <symon_brewer@hotmail.com> wrote in message news:<c6m6p9$dct6o$1@ID-212844.news.uni-berlin.de>... > > > > I believe the newer French track laid down for their highspeed is > > gently banked and with large turning space, well I've only seen tv > > snips in the countryside. I guess in UK (I left 20yrs ago) most of the > > track is in densely populated areas, too late to do anything about it. > > Perhaps the only place to put any new service would be near/over the > > motorway. > > > > regards > > > > johnjakson_usa_com > Hi John, > I heard that the French have a much more 'robust' compulsary purchase scheme > than other countries, i.e. Draw a straight line on the map between Paris to > Lyons and that's where the railway's gonna go! Interesting idea about the > Motorways, here in San Jose I go along Hwy 85 to work, (right past the > Xilinx campus, as it happens, so I'm still on topic ;-)) which is a fairly > new road. There's a light rail system along the central reservation (=Median > for US readers!) for a fair part of the journey. No-one uses it, of course. > No point in owning a Hummer and leaving it at home.... > Jonathan's right about economics of new track in the UK. In order to do > anything, you have to tunnel. Check out > http://news.bbc.co.uk/1/hi/england/2223468.stm The good thing about this is > that French passengers will now arrive at St.Pancras. If you're French, I > guess that's much better than terminating at Waterloo! > cheers, Syms. Hi Symon Well the #5.2B looks pretty cheap compared to the big dig we have here in Boston that only cost $16B I think for a similar cross city tunnel. Still the city will look a lot better afterwards. Thanks to all the US taxpayers :-) regards johnjakson_usa_comArticle: 69132
petersommerfeld@hotmail.com (Peter Sommerfeld) wrote in message news:<5c4d983.0404271459.30275111@posting.google.com>... > Hi Bill, > > Yes my design did not match what I was describing. The other piece > that puzzled me was why the register was always in its own LE. And as > you say, the enable cannot be fed by the same LE's LUT, which I see > now in the Stratix handbook. It all makes sense now. Thanks. > > -- Pete Hi Peter and Bill, It's not quite right to say that the enable input of a register can't be fed by the LUT in the same LE in Stratix. There isn't a dedicated connection from the LUT output to the enable input of the register, but by using a local line, the LUT output can reach the LAB-wide clock enable logic, which then can feed the register enable. So the 2-input LUT in this design can pack into the same LE as the register. However, Quartus won't want to do that unless you set AUTO_PACKED_REGISTERS_STRATIX to MINIMIZE_AREA, or you make a location constraint to force it to happen. Regards, Vaughn AlteraArticle: 69133
tushitjain@yahoo.com (tushit) wrote in message news:<ec6aab0.0404260148.55675258@posting.google.com>... > Hi, > You are right, the trdy,irdy, cben, framen are the problem areas. [... snip ...] > The delay in clock path is about 4ns and this gives a tsu of 13 ns or > so. > It is going through a lot of combo nodes (I think 17!!). Will it help > to do a manual fitting. > > To check if the routing delays could be reduced I cleaned up my device > and did a syn and P&R only with the PCI module. I assume this will > give a better P&R fit but I still got a similar slack for tsu. My > device util. with the full design in 75% of a stratix EP1S80 C6 grade. > With only PCI this goes down to ~20%. > > I also tried the physical synthesis of combo logic option but this > didn't help. > > Someone suggested reducing the fanout of the signals by duplicating > them, but I assume Quartus must be doing that for me. I know xilinx > has a "max fanout" setting, though I couldn't find it in quartus. If I > need to do this manually how will I do this? > > If all else fails I will have to look into redesigning the combo logic > manually. > Thanks and regards > Tushit Hi Tushit, I don't think you'll have much luck with manual placement and routing, or emptying the device of other logic. The problem is simply too many logic levels on the Tsu critical path. Maximum fanout constraints aren't going to be much help here either, since in the PCI cores I've seen the high-fanout signals are trdy and irdy, and since those are sourced by IOs you can't duplicate them. You'll have to redesign the Tsu-critical logic, or guide the technology mapper to a better solution for Tsu by adding lcell buffers to your HDL. Regards, Vaughn AlteraArticle: 69134
Anybody knows if it can be simply done to convert a jedec file read out from an ALtera EP320 and to program into a PALCE16V8 . note it is for repair purposes so I haven't the design software of the ALtera. Regards, MB -- http://matthieu.benoit.free.fr/Article: 69135
Matthieu Benoit wrote: > Anybody knows if it can be simply done to convert > a jedec file read out from an ALtera EP320 and to > program into a PALCE16V8 . > note it is for repair purposes so I haven't the design > software of the ALtera. > Regards, > MB > -- > http://matthieu.benoit.free.fr/ Yes, some companies did/do JEDEC converters. This from the WinPLACE manual, so it looks like you can go EP320 -> 18CV8 -jg http://www.ictpld.com/WinPLACE/index.htm > JEDEC File Translation > The JEDEC-file translation utility of the WinPLACE Software translates > JEDEC files created for programming other PLD's (PAL's, GAL's, EPLD's > etc.,) to JEDEC files used for programming PEEL Devices. The translated > JEDEC file will program a PEEL Device to be a pin-to-pin replacement for > the original PLD. > The JEDEC file translation is available in Options .. Translators .. JEDEC > to JEDEC in the design window. > The translated PEEL JEDEC file is given the name of the original file with > the ".JED" extension modified to ".JEX". The ".JEX" file can then be used to > program your PEEL devices. > Devices that translate to the PEEL18CV8 > PAL16L8 PAL16R8 PAL16R6 PAL16R4 > PAL16P8 PAL16RP8 PAL16RP6 PAL16RP4 > PAL10L8 PAL12L6 PAL14L4 PAL16L2 > PAL10H8 PAL12H6 PAL14H4 PAL16H2 > PAL16H8 PAL16LD8 PAL16HD8 PAL18P8 > PAL18V8 GAL16V8 EP310 EP320 > 5C031 5C032 EP330 PAL18U8Article: 69136
pelletie@caltech.edu (BJP) writes: > I'm using Quartus II 2.2 with service pack 2 and SoPC Builder 2.7 but > when generating the system, I get a number of "grep: not found" It seems like you have problems with your cygwin installation. Have you installed cygwin yourself, or do the one that came with your nios kit? Can you run make from your bash shell? Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 69137
rickman wrote: > Steven wrote: > >> excuse me, Fredrik, I have thought the interface of sdram is almost same from different manufacturers, it seems not so true. >> >> I am now doing a sdram controller design for a special processor architecture The Ram I targets is Micron's sdram MT48LC16M16A2TG, which has 256mb capacity. >> >> Here is the address of it. http://www.micron.com/products/dram/sdram/part.aspx?part=MT48LC16M16A2TG-6A >> >> The signal dqm causes me much wonder. The datasheets says: >> >> --- quote --- Input/Output Mask: DQM is an input mask signal for write accesses and an output enable signal for read accesses. Input data is masked when DQM is sampled HIGH during a WRITE cycle. The output buffers are placed in a High-Z state >> (two-clock latency) when DQM is sampled HIGH during a READ cycle. On the x16, DQML corresponds to DQ0-DQ7 and DQMH corresponds to DQ8-DQ15. DQML and DQMH are considered same state when referenced as DQM. >> >> -- quote end ----- >> >> DQM is input signal, which I falsely thought is output in the first message. Is mask means that I can overwrite just part of address, say 1 byte from 2 bytes cell? This is what was suggested by the above msgs. But what is dqm function in read, what >> means "an output enable signal for read accesses." > > > The above quote is what I remembered about DQM. It is a mask or a byte enable for writing and an output enable for reading. There will be a separate DQM input signal for each byte in the SDRAM. > > In read the output of a byte that is not enabled is held tri-state (Hi-Z). Bytes that are enabled will output data onto the data bus. > > If you don't need independant byte access, you can just tie all DQM signals low and the chip will always read or write the full word of data. > I think it is a very sound and useful observation that one should not assume that all sdram work the same, even if they are supposed to, always read the data sheet. In an earlier post I picked a data-sheet at random, but it was actually a DDR-SDRAM. Rick gave a good explanation on the "enable question", I will just make personal expounding why I would not make use of it in a READ access to the SDRAM. Even if the data output from the SDRAM are tri-stated, there are actually some voltage level on the signal between the SDRAM and the FPGA but not known. It could be below 0.8V (ensured as a logic 0), above 2V (ensured as logic 1) or somewhere between. This make it necessary to implement the SDRAM-controller to ignore the inputs on the signal that are enabled (mask it). Another thing is that the probability that the voltage is between 0.8V and 2V is much higher. You should review your design to ensure that it is robust against meta-stability during the READ. Another argument is that you can save some logic by always having dqm '0' during a read, you must implement the "masking" in the controller anyway. The above reasoning is for connecting only one SDRAM to one controller. One can maybe think of more complex scheemes e.g. several SDRAMS that are read bytewise simultaniously by the same controller. Then tri-stating the drivers are a must. I guess this was a bit out of scope. /PfnaArticle: 69138
user@domain.invalid wrote: > > > rickman wrote: > > Steven wrote: > > > >> excuse me, Fredrik, I have thought the interface of sdram is almost > same from different manufacturers, it seems not so true. > >> > >> I am now doing a sdram controller design for a special processor > architecture The Ram I targets is Micron's sdram MT48LC16M16A2TG, which > has 256mb capacity. > >> > >> Here is the address of it. > http://www.micron.com/products/dram/sdram/part.aspx?part=MT48LC16M16A2TG-6A > >> > >> The signal dqm causes me much wonder. The datasheets says: > >> > >> --- quote --- Input/Output Mask: DQM is an input mask signal for > write accesses and an output enable signal for read accesses. Input data > is masked when DQM is sampled HIGH during a WRITE cycle. The output > buffers are placed in a High-Z state > >> (two-clock latency) when DQM is sampled HIGH during a READ cycle. On > the x16, DQML corresponds to DQ0-DQ7 and DQMH corresponds to DQ8-DQ15. > DQML and DQMH are considered same state when referenced as DQM. > >> > >> -- quote end ----- > >> > >> DQM is input signal, which I falsely thought is output in the first > message. Is mask means that I can overwrite just part of address, say 1 > byte from 2 bytes cell? This is what was suggested by the above msgs. > But what is dqm function in read, what > >> means "an output enable signal for read accesses." > > > > > > The above quote is what I remembered about DQM. It is a mask or a > byte enable for writing and an output enable for reading. There will be > a separate DQM input signal for each byte in the SDRAM. > > > > In read the output of a byte that is not enabled is held tri-state > (Hi-Z). Bytes that are enabled will output data onto the data bus. > > > > If you don't need independant byte access, you can just tie all DQM > signals low and the chip will always read or write the full word of data. > > > > I think it is a very sound and useful observation that one should not > assume that all sdram work the same, even if they are supposed to, > always read the data sheet. In an earlier post I picked a data-sheet at > random, but it was actually a DDR-SDRAM. > > Rick gave a good explanation on the "enable question", I will just make > personal expounding why I would not make use of it in a READ access to > the SDRAM. > > Even if the data output from the SDRAM are tri-stated, there are > actually some voltage level on the signal between the SDRAM and the FPGA > but not known. It could be below 0.8V (ensured as a logic 0), above 2V > (ensured as logic 1) or somewhere between. This make it necessary to > implement the SDRAM-controller to ignore the inputs on the signal that > are enabled (mask it). Another thing is that the probability that the Of course it should ignore the data signals that are disabled. > voltage is between 0.8V and 2V is much higher. You should review your > design to ensure that it is robust against meta-stability during the > READ. Another argument is that you can save some logic by always having > dqm '0' during a read, you must implement the "masking" in the > controller anyway. > > The above reasoning is for connecting only one SDRAM to one controller. > One can maybe think of more complex scheemes e.g. several SDRAMS that > are read bytewise simultaniously by the same controller. Then > tri-stating the drivers are a must. > > I guess this was a bit out of scope. > > /Pfna >Article: 69139
"Leon Heller" <leon_heller@hotmail.com> wrote in message news:408cffe8$0$19420$cc9e4d1f@news-text.dial.pipex.com... > "Rene Tschaggelar" <none@none.net> wrote in message > news:408cd362$0$703$5402220f@news.sunrise.ch... > > Leon Heller wrote: > > > > > I just came across this schematic for the ByteBlaster II: > > > > > > http://www.mcu.cz/atm/index.php?direction=0&order=&directory=EDA > > > > > > Someone has probably worked out the circuit by tracing the connections > on a > > > unit as Altera hasn't published it, AFAIK. > > > > And does it work ? > > I mean to try it, when I get my Cyclone board finished. A problem with this is that the BF550 and BF570 transistors used are unavailable - 20 weeks delivery according to Arrow. 8-( I'll see if I can find equivalent devices. Leon -- Leon Heller, G1HSM http://www.geocities.com/leon_hellerArticle: 69140
Leon I have tried the website, I even registered, but somehow, I cannot click on the "byteblaster.pdf" link to download. How do you get to download the file?? Thanks Ted > I just came across this schematic for the ByteBlaster II: > > http://www.mcu.cz/atm/index.php?direction=0&order=&directory=EDA > > Someone has probably worked out the circuit by tracing the connections on a > unit as Altera hasn't published it, AFAIK. > > LeonArticle: 69141
Narcis, I hope to use FPGA or CPLD to control of train movement (signalling). I prepared some state machines for a small station and it seems to be working. Just think about a conception of the adaptation my solution to a real line in Poland. I would like to implement signalling functions to probably CPLD but there still will be required a software in control center. There are 18 small stations. There are 6 people on each station. Using automatic equipment some people can be moved to other jobs. It is very useful for national railway companies from East Europe block to improve single lines. Regards Jacek Mocki "paris" <273986malaka@email.it> wrote in message news:c6kb9a$1te6$1@avanie.enst.fr... > > "Narcis Nadal" <nnadal@terra.es> escribió en el mensaje > news:unLic.4700406$uj6.16108118@telenews.teleline.es... > > Yes, we have recently designed and produced here in Catalonia some 192x64 > > LED displays with 16 gray levels EN 50155 compliant for the TGV > > Barcelona-Madrid. Those displays have a Xilinx XCS05 industrial grade as a > > coprocessor. > > > > did you mean "intensity" levels? > > wasnt TGV a French train? > i thought in Spain you had AVE or something > > > > > > Regards > > > > Narcis Nadal > > "Jacek Mocki" <jacekmocki@poczta.onet.pl> escribió en el mensaje > > news:c6anq7$7r$1@news.onet.pl... > > Does anyone know some examples of using CPLD or FPGA devices in railways > > equipment? > > > > Regards > > > > Jacek > > > > > >Article: 69142
Austin, Thank you very much for your reaction. There are very important information. I will send you an personal email. Regards Jacek "Austin Lesea" <austin@xilinx.com> wrote in message news:c6bbb4$5691@cliff.xsj.xilinx.com... > Jacek, > > Yes we have FPGAs that have been used in railway equipment. > > The problem is the sometimes close to ten year qualification process* > for railway equipment, which means by the time it is qualified for use, > the parts are well into their obsolesence. > > If you have such an application, you should contact a Xilinx FAE, and > discuss the best choice of product with them (one that we expect will be > around for another > 20 years like the 2K has been, and the 3K will have > been). > > As always, if any of our products are used in an application where human > life despends on the perfect functioning, see the very serious legal > stuff at: > > http://www.xilinx.com/legal.htm > > For example, we heard that a manufacturer wants to use an FPGA in a > nuclear reactor control system. That certainly gets our attention, as > we insisted that the design be done in such a way that is consistent > with the application (ie fully TMR, dual redundant, hot standby, etc etc > etc). > > *(based on what I've heard about a certain railway equipment supplier) > > Austin > > Jacek Mocki wrote: > > Does anyone know some examples of using CPLD or FPGA devices in railways > > equipment? > > > > Regards > > > > JacekArticle: 69143
"Ulf Samuelsson" <ulf@atmel.nospam.com> wrote in message news:H_Ajc.10431$EV2.97101@amstwist00... > > > What is the problems with an external CPLD? > What do you want to implemente there? > The AT89C5131/AT89C5132/AT89C51SND1 will do everything else. > Thanks, Ulf (and other responders) I have been converging toward your suggestion, as there is no "clean" single-chip solution, and there is a definite advantage to keeping the programmable logic 'pristine', so that you can use commonly available development tools. I was aware of some other 'c51 USB micros, but not those from Atmel you mention above - they look like they could be a good solution, coupled with a separate programmable logic part. Cheers, R. Main.Article: 69144
Hi, I had a similar problem when I installed Cygwin for an unrelated purpose after installing SOPC Builder. Are you sure the only Cygwin install on your machine is the one that came with SOPC Builder? At the time, I found a way around it, but I don't remember how anymore. -- Pete > I'm using Quartus II 2.2 with service pack 2 and SoPC Builder 2.7 but > when generating the system, I get a number of "grep: not found" > errors. I checked the Altera website but I couldn't find anything. > Has anyone had similar problems/know why these errors are occuring? > Please CC any replies to this group to me at pelletie@caltech.edu. > Thanks! A more detailed report is as follows: > > Altera SOPC Builder Version 2.6 > > Copyright (c) 1999-2002 Altera Corporation. All rights reserved. > > > > # 2004.04.27 15:06:14 (*) mk_custom_sdk starting > > # 2004.04.27 15:06:14 (*) Reading project > > # 2004.04.27 15:06:15 (*) Finding all available components > > # 2004.04.27 15:06:23 (*) Finding all CPUs > > # 2004.04.27 15:06:23 (*) Finding all peripherals > > # 2004.04.27 15:06:23 (*) Generating gnu SDK for nios_0 > > # 2004.04.27 15:06:23 (*) Copying Files for nios_0 > > # 2004.04.27 15:06:24 (*) Generating Memory Map for nios_0 > > # 2004.04.27 15:06:24 (*) Generating Makefile and excalibur.h for > nios_0 > > grep: not found > grep: not found > grep: not found > grep: not found > grep: not found > grep: not found > grep: not found > grep: not found > grep: not found > grep: not found > grep: not found > grep: not found > grep: not found > grep: not found > grep: not found > grep: not found > # 2004.04.27 15:06:31 (*) Wrote gnu tcl script for nios_0 > > grep: not found > grep: not found > grep: not found > grep: not found > grep: not found > grep: not found > grep: not found > grep: not found > # 2004.04.27 15:06:33 (*) Making Library > > grep: not found > grep: not found > grep: not found > grep: not found > grep: not found > grep: not found > grep: not found > grep: not found > /c: Can't open /c: No such file or directory > make: *** [obj32] Error 2 > # 2004.04.27 15:06:36 (*) Building onchip_memory_0_contents.srec using > "germs" > > # 2004.04.27 15:06:36 (*) cd d:/qdesigns/ee52/minimalnios ; nios-build > --sdk_directory=d:/qdesigns/ee52/minimalnios/nios_0_sdk -np -s -o > onchip_memory_0_contents.srec -b 8192-16384 > d:/qdesigns/ee52/minimalnios/nios_0_sdk/lib/nios_germs_monitor.s > > grep: not found > grep: not found > grep: not found > grep: not found > grep: not found > grep: not found > grep: not found > grep: not found > Can't locate strict.pm in @INC (@INC contains: > /cygdrive/c/altera/excalibur/sopc_builder/bin/perl_lib:/cygdrive/c/altera/excalibur/sopc_builder/bin/europa:/cygdrive/c/altera/excalibur/sopc_builder/bin: > .) at - line 3. > > BEGIN failed--compilation aborted at - line 3. > > # mk_custom_sdk: WARNING 512 cd d:/qdesigns/ee52/minimalnios ; > nios-build --sdk_directory=d:/qdesigns/ee52/minimalnios/nios_0_sdk -np > -s -o onchip_memory_0_contents.srec -b 8192-16384 > d:/qdesigns/ee52/minimalnios/nios_0_sdk/lib/nios_germs_monitor.s > > ERROR: Could not build Peripheral Contents for nios_0 > > > > Error in processing. System NOT successfully generated.Article: 69145
The two FMF packages you need are at http://www.eda.org/fmf/fmf_public_models/packages/ Someone in comp.lang.vhdl replied with how to attach these. -- Pete ALuPin@web.de (ALuPin) wrote in message news:<b8a9a7b0.0404262342.386e049a@posting.google.com>... > Hi, > > I want to simulate a FMF VHDL SRAM model. > In the model itself there is the following declarations: > LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; > USE IEEE.VITAL_timing.ALL; > USE IEEE.VITAL_primitives.ALL; > LIBRARY FMF; USE FMF.gen_utils.ALL; > USE FMF.conversions.ALL; > > > When I try to compile the model with Modelsim I get the following error message: > # ** Error: (vcom-19) Failed to access library 'fmf' at "fmf". > > What can I do about that? Where exactly can I get the library on the FMF site and > how do I have to include it in Modelsim? > > ThanksArticle: 69146
On Sun, 25 Apr 2004 14:11:01 GMT, Phil Hays <Spampostmaster@comcast.net> wrote: > >Have fun. Hi Phil, Thanks for info. You and John have provided invaluable advice for me to start acquainting myself with this world of programmable logic and FPGAs. Take care, JPArticle: 69147
Hi, I'm using a PLL (HCT9046 from Philips) and I should convert a T1 Clock (1.544MHz) to an frequency of 2.048MHz. This is normal possible with an PLL. What I should have is a Divider, which divides my 2.048MHz to a frequency of 1.544MHz. Does anybody know how to do this? The output clock should have if possible a duty cylce of 50% Best regards MartinArticle: 69148
Is there a better Verilog sequence for the polynomial-multiplier
begin
C[10:0] <= A[10:0] & {B[0],B[0],B[0],B[0],B[0],B[0],B[0],B[0],B[0],B[0],B[0]};
C[11:1] <= C[11:1] ^ (A[10:0] & {B[1],B[1],B[1],B[1],B[1],B[1],B[1],B[1],B[1],B[1],B[1]});
...
C[20:10] <= ...
end
or should I be writing Perl to generate the rather stereotyped code above?
What if I want a polynomial-multiplier of user-definable width?
Tom
Article: 69149matthieu asks - >Anybody knows if it can be simply done to convert >a jedec file read out from an ALtera EP320 and to >program into a PALCE16V8 . >note it is for repair purposes so I haven't the design >software of the ALtera. >Regards, >MB >-- >http://matthieu.benoit.free.fr/ > visit the Lattice website - www.latticesemi.com - and download paltogal software. This utility converts almost all SPLD jedec to the equivalent GAL/PAL device, and is FREE - good luck with your design - Michael Thomas LSC FAE NY/NJ
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