Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
I am reading from the 7 segment display. I could read from LED's, it doesn't really matter.Article: 70651
lc wrote: > Thanks for all the comments (both on the list and direct email). > <snip> > > If this is a specific limitation of this particular CPLD or software tool > an error report or a warning would be very welcome. > The reason why only up to 4 signals produce the expected > behavior, I think only Altera can tell... > (would they bother to comment to this poor web licence user ?!) > > I think I'll be another one saying to avoid latches on CPLD designs hi:) It is not uncommon for tools to change their decision paths with logic depth : that's why you should routinely scan the RPT files. My most recent example was an Atmel fitter that misses XOR optimise once the eqns get past a certain logic width. That can be understandable, as digging for XOR with wider AND.OR flattened equations is not trivial. The fix was to create dummy nodes, so the fitter could easily see the XOR term - and the fitter IS smart enough to discard the dummy nodes, so the design still fits. Some PLDS have native support for latches, with .LE terms. Ignoring the gotchas in tool flows, in the context of ALE usage, a latch gives longer access times, but can give more RFI as more transistions appear. A trailing edge register gives minimal transistions, but does have a small hit in access times. -jgArticle: 70652
Austin Lesea wrote: > Symon, > > Very funny. > > So we are unbelievably successful with S3. Is that our fault that we > somehow did not figure that they would be instantly shipped once they > got packaged? > > Triple whammy: 1) great part 2) great price 3)dot.com ending. er ? In this part of the world, (and many others) dot.com == dot.bomb - is that what you meant to convey ? > > Did you bother to read the S3 press release? 500K S3's in 2003? > > That is one helluva lot of FPGAs..... The other press release says $750M in Spartans (all suffixes) and 80M pcs. ( ASP of just over $9) So that makes your 'helluva lot' just 0.625% of the total shipped, and Xilinx gives excuses for not being able to meet demand ?. It is OK to 'chest beat' about "your new asic", but if Xilinx cannot attain ASIC volumes, you will have to work hard to get those design wins. -jgArticle: 70653
I would like to compile my new design to get a baseline number for resource usage. I have done this before, but I don't remember how to set up VHDL component libraries using Quartus. I have a common and a hardware library and a couple of VHDL source files for each. I can't find a way to associate the source files with the particular libraries. In Modelsim you just create the library and make the connection in the GUI. I can create a library in Quartus, but I can't find a way to connect this to a source file. I am also not sure that this is the same as a VHDL library. The help files seem to skirt around this issue... any advice? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 70654
General Schvantzkoph <schvantzkoph@yahoo.com> wrote in message news:<pan.2004.06.20.17.57.34.653961@yahoo.com>... > On Sun, 20 Jun 2004 17:45:27 +0000, Gregg C Levine wrote: > > > Hello from Gregg C Levine > > I have here an XC3020, and matching configuration storage EEPROM, an > > XC1736DPC, the were originally purchased for another project. We ended up not > > doing that project. Now we'd like to use both for something completely different. > > Are these parts still supported by Xilinix? Has anyone heard differently? We'd also > > prefer to do the programming under Linux. > > Gregg C Levine drwho8 atsign att dot net > > The 3000 series hasn't been supported for years. As for programing it in > Linux, Linus was in grade school when the 3000s were current so you aren't > going to find any Linux native tools that support them. However you should > be able to run the old DOS based XACT tools under wine. I believe Foundation series 1.4, 2.1,...support the 3000 parts, and they were window sw, nice tools but they are also obsolete. :(Article: 70655
On Tue, 22 Jun 2004 10:09:31 -0600, Brian Philofsky wrote: > > D wrote: >> [quoted text muted] > > My guess at fixing this would be to either remove the ROM16X1 component > declaration or you can add the attribute: > > attribute BOX_TYPE of > ROM16X1 : component is "PRIMITIVE"; > > Better for you to just remove and not use the component declaration as > it is not necessary and if you mis-declare it, can cause it not to work > properly. The component declaration you have does mis-declare a ROM16X1 > as the generic should be a bit_vector and named INIT not init_val bu the > fact you named it rom_16x1 rather than rom16x1 means that that > declaration is meaningless any ways. > > Also, the INIT attribute needs to be a 4-digit hex value (16-bits) not > 2-digit (8-bits). I also suggest simulating this as it might help you > localize the problem better if these suggestions do not work. > > > -- Brian Thanks for your response Brian, I eventually found out that it wasn't an actual problem with the ROM (you were completely right about the component declaration, a good on my part, but as you mentioned the primitive didn't actually needed to be included because I already had the unisim declaration). The problem was in the fact that in the higher level heirarchy instantiation, I had used a c++ program to generate some of the code and mistakenly kept pointing the output of the ROM's to the same output (signal) name, so they all got collapsed into one by the tools. Live and learn. It's been a while for me. And I had seen the BOX_TYPE attribute before, a long time ago. Probably in the xilinx answer database :) . Anyway thanks again. -DArticle: 70656
Hi all, "Save your debug time using Raven JTAG interface" Raven JTAG interface is 5x faster than the popular Wiggler emulator. "Save your money using Chameleon POD" Amontec company provides a Raven JTAG interface solution for only EUR159.- . Coming with - Multi-ICE adapter - USB Power JTAG connector - FREE Chameleon POD programmer (can be downloadable on http://www.amontec.com/download.shtml) Works with a large part of commercial debugger like IAR, GreenHills (GHS), Mentor XRAY ... Works fine with the FREE GNU GDB ... Our ARM Debug ValuePack is a mature product with about 400 users debugging *ARM7*, *ARM9*, *MIPS* ... daily. Amontec ship product worldwide with 3 days delivery ! Regards, Laurent Gauch www.amontec.com _____________________________ Amontec, a member of the *ARM CONNECTED COMMUNITY* see http://arm.convergencepromotions.com/catalog/m_chome.htm ------------ And now a word from our sponsor ------------------ For a quality usenet news server, try DNEWS, easy to install, fast, efficient and reliable. For home servers or carrier class installations with millions of users it will allow you to grow! ---- See http://netwinsite.com/sponsor/sponsor_dnews.htm ----Article: 70657
Jim, See below, Austin Jim Granville wrote: > Austin Lesea wrote: > >> Symon, >> >> Very funny. >> >> So we are unbelievably successful with S3. Is that our fault that we >> somehow did not figure that they would be instantly shipped once they >> got packaged? >> >> Triple whammy: 1) great part 2) great price 3)dot.com ending. > > > er ? In this part of the world, (and many others) dot.com == dot.bomb > - is that what you meant to convey ? > Yes. >> >> Did you bother to read the S3 press release? 500K S3's in 2003? >> >> That is one helluva lot of FPGAs..... > > > The other press release says $750M in Spartans (all suffixes) and 80M > pcs. ( ASP of just over $9) > So that makes your 'helluva lot' just 0.625% of the total shipped, > and Xilinx gives excuses for not being able to meet demand ?. > It is OK to 'chest beat' about "your new asic", but if Xilinx cannot > attain ASIC volumes, you will have to work hard to get those > design wins. > -jg > I see the glass as half full, you see it as totally empty. All a matter of perspective. One could say that any recently introduced product is a 'failure' because it does not even register on the combined income of the last three products. No excuses offered, merely an explanation.Article: 70658
Austin Lesea wrote: > Jim, > <snip> >>> Did you bother to read the S3 press release? 500K S3's in 2003? >>> >>> That is one helluva lot of FPGAs..... >> >> >> >> The other press release says $750M in Spartans (all suffixes) and 80M >> pcs. ( ASP of just over $9) >> So that makes your 'helluva lot' just 0.625% of the total shipped, >> and Xilinx gives excuses for not being able to meet demand ?. >> It is OK to 'chest beat' about "your new asic", but if Xilinx cannot >> attain ASIC volumes, you will have to work hard to get those >> design wins. >> -jg >> > > I see the glass as half full, you see it as totally empty. All a matter > of perspective. > > One could say that any recently introduced product is a 'failure' > because it does not even register on the combined income of the last > three products. > > No excuses offered, merely an explanation. You may have missed the point a little. * Symon commented on the general availability of S3 devices. * You explained that customer demand exceeded Xilinx's ability to supply. * I looked at the WEB references you gave, and they indeed confirm that actual volumes of the S3 are not great, for 2003. All three can be true, and I am not sure where 'totally empty' and 'failure' come from; your words, not mine. Of course they are new, and yes they are ramping, but the stats indicate a 2003 run rate of maybe 20M pcs/yr in Spartan ( educated guess from 80M over 6 yrs). With S3 numbers being appx 1/40 of Spartan shipments, that would seem to be very early in the ramp - which confirms Symon's observation. Could you give us 1H 2004 volumes, and present lead times, for S3 devices ? As a designer, a valid question is: Has Xilinx 'caught up' enough, so that a design could use these devices, and not have a supply problem ? -jgArticle: 70659
Asteroids Deluxe, the latest release at www.fpgaarcade.com, for your general amusement. VHDL source code available for download, including vector to raster scan convertor and POKEY audio core. Note, this design using the T65 core from Opencores, but with a few bug fixes that are needed for the game to run. These haven't been pushed back into the Opencores release yet. Cheers, MikeJArticle: 70660
This seems to be a bug in projnav when using the XMP as a source file. ISE creates the EDK project in VHDL mode. This has to be changed. The only way to do that today is to open the xmp file in an editor and change VHDL to VERILOG. Basically the projnav could not resolve the path to the edk data from the xmp. One way around this is to generate the netlist in XPS and then take that system.v file and instantiate it as a source in projnav. You will need to remove the xmp as a source. Antti Lukats wrote: > Hi > > does anybody know if it is possible to use EDK system in ISE toplevel if the > toplevel is in verilog? > So far ISE/EDK mixed language support has been always towards VHDL, in last > releases the mixed language support is defenetly better but we still have > some problem with some mixed designs. > > so simple question: > ISE toplevel (verilog) > includes a EDK system, all seems to be OK, but synthesis says that the > system module is not found. > > any workaround, hint what todo? wait for next service pack ??? > > > Antti > > -- / 7\'7 Paulo Dutra (paulo.dutra@xilinx.com) \ \ ` Xilinx hotline@xilinx.com / / 2100 Logic Drive http://www.xilinx.com \_\/.\ San Jose, California 95124-3450 USAArticle: 70661
Hi does anybody know if it is possible to use EDK system in ISE toplevel if the toplevel is in verilog? So far ISE/EDK mixed language support has been always towards VHDL, in last releases the mixed language support is defenetly better but we still have some problem with some mixed designs. so simple question: ISE toplevel (verilog) includes a EDK system, all seems to be OK, but synthesis says that the system module is not found. any workaround, hint what todo? wait for next service pack ??? AnttiArticle: 70662
Hi, I use a board from: http://www.digilentinc.com/ It works great for me. Don't forget to get an IO board too. Cheers, Ashish KapoorArticle: 70663
Hi all, I am trying to implement a small ALU module using the Xilinx ISE web pack and the simulator is Silos. When I try to synthesize this design, it gives me an error for the division. I have implemented division directly, i.e. out <= A / B; All I know is this is a pretty inefficient way of doing it but was not expecting errors. Any tips or pointers will be very helpful. Thanks, AndyArticle: 70664
On Fri, 18 Jun 2004 12:22:44 +0200, David Brown wrote: > Does anyone know if there are concrete plans for a Nios II port of eCos? > There are several other OS'es ported to the Nios II already, such as > uC/OS-II and ucLinux, but I've heard nothing regarding eCos other than > four-year-old promises that Altera and Red Hat were working on it. Go to http://ecos.sourceware.org/ml/ecos-discuss/ and do a search for NIOS and you'll turn up some links to ports for NIOS and people working on NIOS-II. Also, RedHat isn't working on eCos anymore, a while back they gave up on it, but the people who were working on it formed a new company called ecoscentric, and it is still being worked on.Article: 70665
On Wed, 23 Jun 2004 00:29:41 +0100, "MikeJ"
<support@{nospam}fpgaarcade.com> wrote:
That's dead impressive Mike - a pity that you can't make them up and
sell them.
Article: 70666Hi Mike! VERY nice! What has peeked my interest is the POKEY core. I've not had a chance to study the VHDL for it (got to get to work!), but did you write the core specifically for AstDX, or as a general core? I would be most interested in trying to put this core into a CPLD and plug it into a real POKEY socket - more importantly, using 4 together in one chip for the likes of Star Wars and Major Havoc (etc). I presume the random number generator readback is in there somewhere? I'll have a printout and a study on in tonight..... :-) Also, with these designs, what's the cost of the chip they fit into? I read about Pacman using a Virtex 300? Does AstDX use that as well? Yours, Mark. MikeJ wrote: > Asteroids Deluxe, the latest release at www.fpgaarcade.com, for your general > amusement. > > VHDL source code available for download, including vector to raster scan > convertor and POKEY audio core. > > Note, this design using the T65 core from Opencores, but with a few bug > fixes that are needed for the game to run. These haven't been pushed back > into the Opencores release yet. > > Cheers, > > MikeJ > >Article: 70667
Hello all, We are currently doing a project where we would like to evaluate the advantages of the PPC405 hard processor core in the Virtex-II Pro FPGA compared to the Microblaze soft core. We've got the Microblaze up and running but we are struggling to get the PPC to execute any code. The chip is an Engineering Sample: Virtex-II Pro XC2VP7 FF672ALB0237 D127316A 6C-ES The program is a very simple one - just trying to get a diod on the board to flash. In our EDK project, under S/W settings, we are unable to select Mode - Executable. XmdStub is pre-selected and grayed out. Therefore we suspect that the code is compiled to run in a debugging mode. After the circuit has been programmed through the JTAG interface (thus the JTAG is properly connected and working) we try to use the XMD debugger to connect to the PPC405 JTAG port. (We've tried to connect both directly to the PPC405 JTAG and to the normal JTAG chain). XMD then presents us with an error message: ERROR: Unable to connect to PowerPC target. Invalid Prcessor Version No 0x00000000 Unable to establish connection to the PowerPC target. Make sure the PPC405 JTAG signals are connected to the JTAGPPC primitive and the cable connections are correct. The question is - is it possible to get EDK to compile the code to execute straight away without the need of a debugger and JTAG connection? If not, any suggestion on what might be wrong is highly appreciated. Could the error message have anything to do with the fact that we're using an Engineering Sample of the chip? Best Regards, Jonas Floden Bjorn SaeteArticle: 70668
Hi, I have a problem with a Dialogic board "DM/IP301-1e1-PCI". I installed that board in a Piv 1.6Ghz Mainboard D845WN and I can't do it starts. The board's power requirements are 22.5W @ 5V, and using PC Wizard I see that the PCI slot used by the Dialogic board has this description: "In Use (32-bit) 3.3v". Is this a problem? Does the board fail to start by this reason? Can I make the board and the Mainboard compatible? thanks! ByeArticle: 70669
Jim Granville <no.spam@designtools.co.nz> wrote: ... : Could you give us 1H 2004 volumes, and present lead times, for S3 : devices ? : As a designer, a valid question is: Has Xilinx 'caught up' enough, so : that a design could use these devices, and not have a supply problem ? If at least distributors could offer (paid) engineering samples, not only long lead times... -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 70670
Tjena, Yes, The executable can be directly merged into the bitfile, if your executable is running from internal BRAM. If you run out of external memory, you need to download executable to the external memory. How did you create your system? Did you use the Base System Builder? Göran Bilski Jonas Floden wrote: > Hello all, > > We are currently doing a project where we would like to evaluate the > advantages of the PPC405 hard processor core in the Virtex-II Pro FPGA > compared to the Microblaze soft core. We've got the Microblaze up and > running but we are struggling to get the PPC to execute any code. > > The chip is an Engineering Sample: > > Virtex-II Pro > XC2VP7 > FF672ALB0237 > D127316A > 6C-ES > > The program is a very simple one - just trying to get a diod on the > board to flash. In our EDK project, under S/W settings, we are unable to > select Mode - Executable. XmdStub is pre-selected and grayed out. > Therefore we suspect that the code is compiled to run in a debugging > mode. > After the circuit has been programmed through the JTAG interface (thus > the JTAG is properly connected and working) we try to use the XMD > debugger to connect to the PPC405 JTAG port. (We've tried to connect > both directly to the PPC405 JTAG and to the normal JTAG chain). > XMD then presents us with an error message: > > ERROR: Unable to connect to PowerPC target. Invalid Prcessor Version No > 0x00000000 > Unable to establish connection to the PowerPC target. Make sure the > PPC405 JTAG signals are connected to the JTAGPPC primitive and the cable > connections are correct. > > The question is - is it possible to get EDK to compile the code to > execute straight away without the need of a debugger and JTAG > connection? If not, any suggestion on what might be wrong is highly > appreciated. Could the error message have anything to do with the fact > that we're using an Engineering Sample of the chip? > > Best Regards, > > Jonas Floden > Bjorn Saete >Article: 70671
Brian Philofsky <brian.philofsky@no_xilinx_spam.com> writes: > Martin Thompson wrote: > > > When I tried XFLOW, it seemed to want to create a batch file called > > xflow.bat with all the commands in it that needed running. Next time > > I typed an XFLOW command, all it did was run the old xflow.bat from > > the current directory. That had me bemused for a long time - i take > > it everyone that uses it does so on Unix (where . isn't on the path > > like it is in windos land). > > > Interesting. I did not know about this. I generally use XFlow on > Solaris and now Linux so I have not encountered this. For UNIX > machines, it creates an xflow.scr file which is a CSH script of all of > the commands however I personally never use it. Ahh, my understanding of the way it worked was that the script was created and then executed by the XFLOW executable, rather than that executable doing all the execs itself.. > You can also have it write out the script in TCL if you prefer. If > you want, that script can be used to integrate into other scripts or > used stand-alone if you want to get away from the xflow "shell". > Similarly for the .bat file on a PC but I guess it has this > interesting side effect. I will pass this on to that group so that > they can evaluate how to get around that problem. Thanks for the > feedback. > > > > Speaking of batch file processes - does anyone know how to find out > > if > > XST generated any errors - in my experiments, it returns the same > > ERRORLEVEL every time. > > > Don't know about this. I just tried to run XST from xflow where I > introduced a syntax error into one of my Verilog files and got back > the response: > > ERROR:Xflow - Program xst returned error code 6. Aborting flow execution... > > There it looks like XST is specifying an error code that you could key > off of. Perhaps it is specific to the error or situation you have > created. > > Hmmm, more experimentation required at my end then - thanks for the counter-example. > > > I'm sure I've seen this with other tools as well, which means that the > > compilation runs through to completion on the old files! One > > hackaround I've seen from a reputable source is to do your > > implementation in a clean directory every time, copying in the UCF, > > EDF eetc. But that seems nasty! > > > You could start each run in a clean directory or else build into your > script to smarts to either move some of the relevant input files to > the next portion of the flow into another directory (backup of > previous run) or else just delete them. That way when you get to the > next program, it should error out saying file not found if you did not > catch the error code before. I could, but it doesn;t feel like the "right way" to do it. > In my experience however, most programs > do specify non-zero error codes when an error occurs and if you > properly catch them, you can abort the script execution yourself. > When I used CSH as my main scripting language to run the tools, I use > to do it like: <snip> > That almost never failed me but it has been a while since I have run > the tools in this manner. > > Maybe things are different in a Windos cmd.exe shell... I'll have to look into this some more. Thanks, Martin -- martin.j.thompson@trw.com TRW Conekt, Solihull, UK http://www.trw.com/conektArticle: 70672
Hi Aaron, Thanks for your reply. Through a process of trial and error, I managed to find the write port at base_address+3. I was just wondering if the compiler treats data-bitwidth as 32 bits and therefore assign the LSB at base_address+3. Since relevant data is only 8-bits wide, the upper bits would be always 0. But SOPC builder is supposed to have a dynamic bitwidth right so this shouldn't happen. Like u said, the *point1=1 should work (*point4=1 works in this instance) but it doesn't. Might it be something to do with the settings i.e. how the compiler or device and pins settings are made etc. affecting the optimisation process or affecting how data is communicated to the device? My design works but it is at best erratic. I am inserting a multiplier into the blackbox now with 32-bits and it is not working. EdArticle: 70673
On 23 Jun 2004 11:36:48 +0100, Martin Thompson <martin.j.thompson@trw.com> wrote: >Brian Philofsky <brian.philofsky@no_xilinx_spam.com> writes: > >> In my experience however, most programs >> do specify non-zero error codes when an error occurs and if you >> properly catch them, you can abort the script execution yourself. >> When I used CSH as my main scripting language to run the tools, I use >> to do it like: > ><snip> > >> That almost never failed me but it has been a while since I have run >> the tools in this manner. >> >> > >Maybe things are different in a Windos cmd.exe shell... I'll have to >look into this some more. I'm currently doing this with Make, which interprets non-zero exit status as an error. I've previously done this with bash, with the 'set -e' option, which causes bash to exit whenever a command exits with non-zero status. You can get to the exit status in dos-ish command shells with %ERRORLEVEL%. Regards, Allan.Article: 70674
rickman <spamgoeshere4@yahoo.com> wrote in message news:<40D8A954.C61855BA@yahoo.com>... > I would like to compile my new design to get a baseline number for > resource usage. I have done this before, but I don't remember how to > set up VHDL component libraries using Quartus. I have a common and a > hardware library and a couple of VHDL source files for each. I can't > find a way to associate the source files with the particular libraries. > In Modelsim you just create the library and make the connection in the > GUI. I can create a library in Quartus, but I can't find a way to > connect this to a source file. I am also not sure that this is the same > as a VHDL library. > > The help files seem to skirt around this issue... any advice? Rick, 1. set up user libraries under "Settings". Its a little different between QII v3.0 and QII v4.0. Overall I'm happier with 4.0. That's Assignments> Settings>User Libraries 2. I often add scattered files directly using Project>Add/Remove files, with component defs in a separate package. File order does matter. Hope this helps, -rajeev-
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z