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Ted, void* just means a generic pointer. In your code, you're casting it to int*, which should work fine. Since your component has no address input, it spans only a single int* location. I'm not sure I understand what you mean when you say you found the write port at base_address+3. Just to reiterate, I think you have a bug in your HDL which makes it look like you aren't able to access your hardware at the device base address. etd606@hotmail.com (Ted) wrote in message news:<58811c5e.0406230313.53b01cb3@posting.google.com>... > Hi Aaron, > > Thanks for your reply. Through a process of trial and error, I managed > to find the write port at base_address+3. I was just wondering if the > compiler treats data-bitwidth as 32 bits and therefore assign the LSB > at base_address+3. Since relevant data is only 8-bits wide, the upper > bits would be always 0. > > But SOPC builder is supposed to have a dynamic bitwidth right so this > shouldn't happen. Like u said, the *point1=1 should work (*point4=1 > works in this instance) but it doesn't. Might it be something to do > with the settings i.e. how the compiler or device and pins settings > are made etc. affecting the optimisation process or affecting how data > is communicated to the device? > > My design works but it is at best erratic. I am inserting a multiplier > into the blackbox now with 32-bits and it is not working. > > EdArticle: 70701
Phil Moore wrote:
> Hello,
>
> 1.) I was wondering if there was any way that I could
> perform exponential operations on numbers that are stored
> in memory!
Yes. It is easiest if the base is 2. For base 2 (ie. 2^x),
separate off the fractional portion of x, look up the
antilog of the fractional portion from a LUT, and then shift
that by the integer part of x.
>
> 2.) How do I use Coregen to perform addition and
> multiplication to numbers stored in memory in the fpga, or
> should I use Coregen?
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin
Franklin, 1759
Article: 70702"Amit Kasat" <Amit.Kasat@nospam-xilinx.com> wrote in message news:40D9B833.1040304@nospam-xilinx.com... > Antti, > Did you try goign to EDK and doign an Tools-> Export To ProjNav. This > will create a new ProjNav project for you after runnign synthesis for > EDK subsystem. Remember to go to Project Options and select > > * This is submodule of my design > * Implementation Flow: ISE > > Once the new projnav project is created, you can add your own files > there. If there are any chagnes in EDK, you can re-export from EDK to > the existing ProjNav project. > > Amit. Thanks, but I can add system.xmp to the ISE project and everything works 100% fine as long as the toplevel ISE project is VHDL. In case of verilog toplevel synthesis stops on error module not found. If I add system.v (not system.xmp) to the ISE project I can not update the MicroBlaze sources from ISE project !! So there is no solution so far :( hope some next EDK service packs solves the problem! AnttiArticle: 70703
rickman wrote:
> In modelsim, you just create a library, say "common",
> and then click on each file that goes into that library and change its
> association to link it to the library. I gather that Quartus work
> rather differently? Do I need to separately compile the library sources
> or something?
Something.
Find the USE statements referencing the library.
If one says USE WORK.mystuff.ALL
then all the mystuff files must
either be in the WORK group with the other
sources or the group that they are in must
be mapped to WORK.
If your code says
LIBRARY common;
USE common.mystuff.ALL;
Then you must map the mystuff file collection
to the identifier "common".
-- Mike Treseler
Article: 70704Hello, i'am looking for information about booting a fpga (stratix III) together with a xscale processor out of one flash device. Is it possible to use the xilinx serial flash to boot the fpga and once this is finished transfere the remaining code out of the flash to external sdram and use this as program memory of the PXA255? Does anybody have information or links about such a boot sequence? Are there other boot-posibillities? Thank you for your anseres. regards, tobiasArticle: 70705
Hi! This may be interesting to FPGA arcade gamers too: http://members.optushome.com.au/msmcdoug/pace/Nanoboard/nanoboard.html Greetings, Ulrich "Mark (UK)" <jumbos.bazzar@btopenworld.com> schrieb im Newsbeitrag news:cbbfrh$6n$1@sparta.btinternet.com... > Hi Mike! > > VERY nice! What has peeked my interest is the POKEY core. I've not had a > chance to study the VHDL for it (got to get to work!), but did you write > the core specifically for AstDX, or as a general core? I would be most > interested in trying to put this core into a CPLD and plug it into a > real POKEY socket - more importantly, using 4 together in one chip for > the likes of Star Wars and Major Havoc (etc). I presume the random > number generator readback is in there somewhere? I'll have a printout > and a study on in tonight..... :-) > > Also, with these designs, what's the cost of the chip they fit into? I > read about Pacman using a Virtex 300? Does AstDX use that as well? > > Yours, Mark. > > MikeJ wrote: > > Asteroids Deluxe, the latest release at www.fpgaarcade.com, for your general > > amusement. > > > > VHDL source code available for download, including vector to raster scan > > convertor and POKEY audio core. > > > > Note, this design using the T65 core from Opencores, but with a few bug > > fixes that are needed for the game to run. These haven't been pushed back > > into the Opencores release yet. > > > > Cheers, > > > > MikeJ > > > > >Article: 70706
Hello, unfortunately we have edk 6.1, where that tab doesn't exist. // JonasArticle: 70707
Hi all, i need to implement a (D) PLL in a CPLD. Purpose is to multiply a frequency of 32KHz to 4,096KHz. On board PLL's don't work since the freq. is very low How do i start? JimArticle: 70708
Allan Herriman <allan.herriman.hates.spam@ctam.com.au.invalid> writes: > On 23 Jun 2004 11:36:48 +0100, Martin Thompson > <martin.j.thompson@trw.com> wrote: > > >Brian Philofsky <brian.philofsky@no_xilinx_spam.com> writes: > > > >> In my experience however, most programs > >> do specify non-zero error codes when an error occurs and if you > >> properly catch them, you can abort the script execution yourself. > >> When I used CSH as my main scripting language to run the tools, I use > >> to do it like: > > > ><snip> > > > >> That almost never failed me but it has been a while since I have run > >> the tools in this manner. > >> > >> > > > >Maybe things are different in a Windos cmd.exe shell... I'll have to > >look into this some more. > > I'm currently doing this with Make, which interprets non-zero exit > status as an error. > I've previously done this with bash, with the 'set -e' option, which > causes bash to exit whenever a command exits with non-zero status. > > You can get to the exit status in dos-ish command shells with > %ERRORLEVEL%. > Indeed - that's what I was doing, but in my experiment, XST returned the same errorlevel whether it succeeded or failed... I must have done something wrong somewhere, I'll investigate more when I have some time... Thanks for confirming what I thought *should* happen! Martin -- martin.j.thompson@trw.com TRW Conekt, Solihull, UK http://www.trw.com/conektArticle: 70709
Brian Philofsky <brian.philofsky@no_xilinx_spam.com> writes: > Martin Thompson wrote: > >>Interesting. I did not know about this. I generally use XFlow on > >>Solaris and now Linux so I have not encountered this. For UNIX > >>machines, it creates an xflow.scr file which is a CSH script of all of > >> the commands however I personally never use it. > > Ahh, my understanding of the way it worked was that the script was > > created and then executed by the XFLOW executable, rather than that > > executable doing all the execs itself.. > > > Not at all. The bat file is supposed to be more for reference than > for use in my opinion. There is a lot of "smarts" in the tool that > would not happen if it was used in that way. Yes, I thought the smarts were captured each time it was run in the batch file.. is that right? > It is a shame they named > that file xflow.bat and I am going to suggest they rename it to > something like xflowbat.bat to get around the problem you cite. > That would be good! Thanks, Martin -- martin.j.thompson@trw.com TRW Conekt, Solihull, UK http://www.trw.com/conektArticle: 70710
On 24 Jun 2004 12:03:33 +0100, Martin Thompson <martin.j.thompson@trw.com> wrote: >> >> You can get to the exit status in dos-ish command shells with >> %ERRORLEVEL%. >> > >Indeed - that's what I was doing, but in my experiment, XST returned >the same errorlevel whether it succeeded or failed... I must have done >something wrong somewhere, I'll investigate more when I have some time... > >Thanks for confirming what I thought *should* happen! I just tested xst 6.2.03i. It returned 0 for success and 1 for failure. C:\>c:\Xilinx62\bin\nt\xst.exe -ifn no_file Release 6.2.03i - xst G.31a Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. ERROR:Xst:427 - Entry File no_file not found C:\>echo %ERRORLEVEL% 1 C:\> Regards, Allan.Article: 70711
Hi, all
Synthesizer (XST) supports the divisor to be integer power of 2. Then
how about implementing an operation with the divisor to be 11.
result <= data / 11;
thanks.
Jimmy
Article: 70712Hi Rick, I think what you are asking for is how one can compile VHDL design units into specific pre-compiled VHDL libraries - a feature supported by the VHDL language and by simulation tools such as Modelsim. The answer is in QII 4.0 and 4.1 we don't support this feature. All user design units are compiled into the work library. To support designs that expect design units to live in specific library names, we search the work library whenever we fail to find a design unit in a library with the given name. Consider this example: library my_lib; use my_lib.my_package.all; In Modelsim, the user would compile his package my_package into the library my_lib. In Quartus II, we compile the package into the work library. However, when we see the use clause, we notice that my_package doesn't live in the library my_lib because no such library exists, so we look for my_package in work. Note that this makes it impossible for a user design to refer to two packages of the same name. - Subroto Datta Altera Corp "Mike Treseler" <mike_treseler@comcast.net> wrote in message news:CI-dndp7T5EnzEfdRVn-tw@comcast.com... > rickman wrote: > > > In modelsim, you just create a library, say "common", > > and then click on each file that goes into that library and change its > > association to link it to the library. I gather that Quartus work > > rather differently? Do I need to separately compile the library sources > > or something? > > Something. > > Find the USE statements referencing the library. > If one says USE WORK.mystuff.ALL > then all the mystuff files must > either be in the WORK group with the other > sources or the group that they are in must > be mapped to WORK. > > If your code says > LIBRARY common; > USE common.mystuff.ALL; > Then you must map the mystuff file collection > to the identifier "common". > > -- Mike TreselerArticle: 70713
Thank you very much for your help. I installed successfully another Dialogic Board (D\4pciu) that is universal, and can work with 3.3v and 5v supply. This board has been detected and I can start it. So is the previous board incompatible with my hw? The board has got a green led that swithes on and a yellow led that flushes.... Or is the board broken? what do you think about it? Thanks! Bye MarcoArticle: 70714
Hello,
I would like to know if a two stage syncronizer is implemented in the
following way:
SYNC_NAS: process (CLK, RST)
begin
if (RST = '1') then
NAS_1 <= '1';
elsif ( rising_edge(CLK) ) then
NAS_1 <= NAS;
end if;
end process;
SYNC_NAS_1: process (CLK, RST)
begin
if (RST = '1') then
NAS_2 <= '1';
elsif ( rising_edge(CLK) ) then
NAS_2 <= NAS_1;
end if;
end process;
As you can see I have included the RST signal (in my case an external
asynchronous Reset signal), is this RST signal needed for the two
stage synchronizer?. I mean, should I write the two stage synchronizer
as before or:
SYNC_NAS: process (CLK)
begin
if ( rising_edge(CLK) ) then
NAS_1 <= NAS;
end if;
end process;
SYNC_NAS_1: process (CLK)
begin
if( rising_edge(CLK) ) then
NAS_2 <= NAS_1;
end if;
end process;
-----------------------------------------------------------------------------
And another question about Reset and State Machine:
In my State Machine I have:
...
STATE_FLOPS: process (CLK, RST)
begin
if (RST='1') then
PRESENT_STATE <= S0;
elsif ( rising_edge(CLK) ) then
EPRESENT_STATE <= NEXT_STATE;
end if;
end process;
...
the RST is coming asynchronously from the outside world. should I use
also for the RST signal the two stage synchronizer in order to avoid
glitches?
Thanks a lot and best regards,
Javi
Article: 70715
Tobias Müller wrote:
> i'am looking for information about booting a fpga (stratix III) together
> with a xscale processor out of one flash device. Is it possible to use
> the xilinx serial flash to boot the fpga and once this is finished
> transfere the remaining code out of the flash to external sdram and use
> this as program memory of the PXA255?
Consider parallel flash to boot the processor and initialize the sdram.
Use a flash file system to transfer files from from a host.
Have the processor load the fpga image file.
-- Mike Treseler
Article: 70716>Jimmy" <mljiang@eee.hku.hk> wrote in message news:cbei7k$d9i$1@hkueee5.eee.hku.hk... > Hi, all > Synthesizer (XST) supports the divisor to be integer power of 2. Then > how about implementing an operation with the divisor to be 11. > result <= data / 11; > thanks. > Jimmy > > Division by a constant isn't too hard--just multiply by its eciprocal. -KevinArticle: 70717
Hi! That Nexar board they use looks REALLY pretty, but I can feel my wallet shaking when I think about the price!! Yours, Mark. Ulrich Kloidt wrote: > Hi! > > This may be interesting to FPGA arcade gamers too: > > http://members.optushome.com.au/msmcdoug/pace/Nanoboard/nanoboard.html > > Greetings, > Ulrich > > > "Mark (UK)" <jumbos.bazzar@btopenworld.com> schrieb im Newsbeitrag > news:cbbfrh$6n$1@sparta.btinternet.com... > >>Hi Mike! >> >>VERY nice! What has peeked my interest is the POKEY core. I've not had a >>chance to study the VHDL for it (got to get to work!), but did you write >>the core specifically for AstDX, or as a general core? I would be most >>interested in trying to put this core into a CPLD and plug it into a >>real POKEY socket - more importantly, using 4 together in one chip for >>the likes of Star Wars and Major Havoc (etc). I presume the random >>number generator readback is in there somewhere? I'll have a printout >>and a study on in tonight..... :-) >> >>Also, with these designs, what's the cost of the chip they fit into? I >>read about Pacman using a Virtex 300? Does AstDX use that as well? >> >>Yours, Mark. >> >>MikeJ wrote: >> >>>Asteroids Deluxe, the latest release at www.fpgaarcade.com, for your > > general > >>>amusement. >>> >>>VHDL source code available for download, including vector to raster scan >>>convertor and POKEY audio core. >>> >>>Note, this design using the T65 core from Opencores, but with a few bug >>>fixes that are needed for the game to run. These haven't been pushed > > back > >>>into the Opencores release yet. >>> >>>Cheers, >>> >>>MikeJ >>> >>> >> > >Article: 70718
"Jimmy" <mljiang@eee.hku.hk> wrote in message
news:cbei7k$d9i$1@hkueee5.eee.hku.hk...
> Hi, all
> Synthesizer (XST) supports the divisor to be integer power of 2. Then
> how about implementing an operation with the divisor to be 11.
> result <= data / 11;
> thanks.
> Jimmy
Please view the following with a fixed-space font:
If multiplying by the reciprocal isn't what you want, you can perform long
division where each new "digit" is another binary number.
For instance, 58/11
____101
1011)111010
-1011
-------
0111
- 0000
-------
1110
- 1011
-------
11
The result is 5 with a remainder of 3.
You can carry the result further to give a fixed decimal representation.
A better way to implement division involves an add or subtract at each stage
rather than a compare with subtract or do-nothing. If an intermediate value
is positive, subtract and declare a 1 for that stage. If negative, add and
declare a 0. The result is a series of selectable add/subtract stages with
the sign bit of the previous stage selecting the add/subt.
_____101
1011)+111010
- 1011
--------
0111 (positive)
- 1011
--------
11000 (negative)
+ 1011
--------
011 (positive)
The result is again 5 with a remainder of 3. Be warned that negative
remainders will show up in the last stage when the last regular bit is 0.
The positive remainder is the last positive value encountered in the chain.
Or just add the divisor to the negative result for that same positive
remainder.
This is division. It takes time to propagate through many carry chains.
Article: 70719This line in EDIF works to change the IOSTANDARD: (property IOSTANDARD (string "LVCMOS25")) It seems to work whether on the pad instance or the buffer instance. What I can't figure out is how to set the PULLUP/PULLDOWN stuff in EDIF. I end up running the FPGA editor and turning it on manually after every build. I've tried (property PULLUP (string "TRUE")) and (property PULLUP (string "YES")) on both the pad and the buffer but it seems that the tools entirely ignore it. Any ideas? -- Prepend a 'b' to email me. Thanks.Article: 70720
The libraries guide tells you how to instantiate a pullup in your HDL. Look at the EDIF file your synthesiser creates from this. Cheers, Syms. "Brannon King" <bking@starbridgesystems.com> wrote in message news:cbevfv$qpi@dispatch.concentric.net... > This line in EDIF works to change the IOSTANDARD: > > (property IOSTANDARD (string "LVCMOS25")) > > It seems to work whether on the pad instance or the buffer instance. What I > can't figure out is how to set the PULLUP/PULLDOWN stuff in EDIF.Article: 70721
Mike Treseler wrote: > > rickman wrote: > > > In modelsim, you just create a library, say "common", > > and then click on each file that goes into that library and change its > > association to link it to the library. I gather that Quartus work > > rather differently? Do I need to separately compile the library sources > > or something? > > Something. > > Find the USE statements referencing the library. > If one says USE WORK.mystuff.ALL > then all the mystuff files must > either be in the WORK group with the other > sources or the group that they are in must > be mapped to WORK. > > If your code says > LIBRARY common; > USE common.mystuff.ALL; > Then you must map the mystuff file collection > to the identifier "common". Thanks for the advice. That is how it is *supposed* to work and I could not find the way to map the file containing "mystuff" to the library "common". Turns out that the Altera internal compiler does not support this sort of library. But it becomes mostly transparent because they put all user entities and packages in the WORK library when they are compiled and *always* looks for them in the WORK library regardless of what your USE statement says. The only glitch this causes is when you have multiple packages with the same name in different libraries. With this approach they will clash. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 70722
Brannon King wrote: > This line in EDIF works to change the IOSTANDARD: > > (property IOSTANDARD (string "LVCMOS25")) > > It seems to work whether on the pad instance or the buffer instance. > What I can't figure out is how to set the PULLUP/PULLDOWN stuff in > EDIF. I end up running the FPGA editor and turning it on manually > after every build. I've tried > > (property PULLUP (string "TRUE")) > and > (property PULLUP (string "YES")) > > on both the pad and the buffer but it seems that the tools entirely > ignore it. Any ideas? At one point this worked, though the usage may now be deprecated: (property xc_pullup (integer 1))Article: 70723
Hi all, I am looking for some fax software packages (V.34, V.17, V.29, V.27ter, V.21 Channel 2, T.30) in C5000 platform. Any suggestion? Thanks AmyArticle: 70724
Rickman,
Not sure where you got this idea. Xilinx reads take ONE clock cycle from
address to data out. In the case of pre-VirtexII, a write cycle copied the
write data to the read outputs as well. In the newer chips you have the choice
of what data comes out the read port during a write cycle.
rickman wrote:
> Peter Alfke wrote:
> >
> > Xilinx (Virtex2 or Spartan3) BlockRAM reading while writing:
> > Any write operation also performs a read, and outputs it on the Do output.
> > The user can choose: write before read (= output the data that is being
> > witten), or read before write (=output the previous content that is now
> > being overwritten) or "no change"( keep the old data on the Do lines.
>
> But it still has a two cycle delay from writing to read data out,
> right? So if I want the data that was just written on the next clock
> cycle (like in a stack) I need to use an external register and use
> separate read and write addresses. Correct?
>
> --
>
> Rick "rickman" Collins
>
> rick.collins@XYarius.com
> Ignore the reply address. To email me use the above address with the XY
> removed.
>
> Arius - A Signal Processing Solutions Company
> Specializing in DSP and FPGA design URL http://www.arius.com
> 4 King Ave 301-682-7772 Voice
> Frederick, MD 21701-3110 301-682-7666 FAX
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
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Compare FPGA features and resources
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