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> That depends entirely on your timing specs. If you have none, then > they are not likely to be wrong ;) XST will be trying to make every > path meet single clock timing. Sure! I have specified a clock period constraint, which I thought would be enough. See further my reply to Philip. > As others have suggested, if it fails on startup, it could easily be > the async reset vs. clock. I think you made two bad assumptions from > the way you describe your initial state. You indicated you used > "initial values by declarations". I don't think synthesis tools use > initial values as reset values. I have never asked if XST does this > or not since I don't depend on this. Accepted style is to put it > explicitly in your hdl code like this... But this is a well documented feature in XST, see XST User guide, Chapter 6, Initial Values. It says "When you give a register an initial value in a declaration, XST sets this value on the output of the register at global reset, or at power up.". So if the feature is there, it must be OK to use it, and to skip explicit resets? /JerkerArticle: 71126
Or maybe you mean I should add separate logic outside of the state machine? That could work... I'll try that. /JerkerArticle: 71127
Makesh Soundarajan wrote: > Hi, > > The spartan 3 kit from Nu Horizons doesnt come with EDK (for > microblaze) as standard. You have to buy it separately. The kit works > with the free ISE Webpack. You just need a parallel port cable. The > kit is really good. It has A/D, D/A, config flash ,LCD and others. > > Hope this helps > > Makesh > > > > > "Hank" <nospam@nospam.com> wrote in message news:<CNCGc.28775$qw1.92@nwrddc01.gnilink.net>... > >>Hi guys, >> >>I am mostly a newb at fpga design, although I did a teeny bit of work on a >>Spartan II design a few years ago in verilog. >> >>Anyway, I would like to learn vhdl, and get a development board because I like >>to supplement endless reading of textbooks with some hands-on experiments. I >>will probably purchase Ashenden's book soon. >> >>So, I have found two starter boards which look interesting...the $99 Spartan 3 >>starter kit from Xilinx, and the $164 Spartan 3 starter kit from Nu Horizons. >> >>Before I saw the Nu Horizons board, I was ready to get the Xilinx starter kit. >>Now, I am torn between the two. I know nothing about the Microblaze core...does >>the Nu Horizons board come with all the IP you need to do endless experiments >>with this core, or do you need to pay the $495 edk to Xilinx to get usefull IP? >>If you get everything you need with the $164 Nu Horizons board, then I am sold >>on that, because I have several projects in mind that would greatly benefit from >>the larger Sparten 3 part, the 64MB of sdram and the 32MB of flash. The D/A is >>very nice too...I have an application for that as well. >> >>Opinions? >> >>Thanks! >> >>Hank I'm interested in this board as well. But instead of using SRAM (as in Xilinx's board), this board use SDRAM and I haven't design SDRAM controller before. Does the board come with design example for the SDRAM controller? Anyone have the experience of using this board with free SDRAM controller cores from internet? Cheers, JoeArticle: 71128
Jerker Hammarberg (DST) wrote:
>>Each valid state will have a number of hold-until-next-move-true terms,
>>but states not covered will have NO .D terms, and so their NEXT state is
>>Q0.D = 0;
>>Q1.D = 0;
>>or to the 00 state.
>>
>>If you code
>> IF State=11 THEN immediate_next = 00, then no more logic is generated,
>>as that is implicit.
>
>
> All right, NOW I see your point! But it seems to me you're assuming that the
> synthesis tool always generates the transition logic such that illegal
> states always transition to the state vector of all zeroes, and I'm not yet
> convinced that this is the case. I would have believed that the transition
> function would map all illegal states to "Don't care", allowing the tool to
> minimize the transition logic. As a consequence, the illegal states could
> transition to anyting, including the same illegal state, which means it's
> stuck. But I will try to investigate how XST generates the transition logic.
> If you're right, you definitely answered my question no 2.
>
> /Jerker
<paste>
> I'm not so sure... again, XST finds all unreachable states and takes away the logic for them, even states that are legal and have their own "when" clause. I've even seen in another thread on comp.lang.vhdl the suggestion to connect an input pin to ground, then add code to the state machine like
>
> if ground_signal = '1' then
> state <= UNREACHABLE_STATE;
> end if;
>
> just to prevent XST from taking away the logic for UNREACHABLE_STATE. But I was hoping there were better solutions...
>
> /Jerker
To solve any reliance on 'what xxxx tools might choose to do', the best
solution is to code
ELSE
state <= Enumerated_0000_State;
Normally, that should have zero additional hardware logic cost [except
for one-hot], ( because it is implicit in the .D construction), but now
you are more certain you and the tools 'are on the same page'.
I would try to avoid trying to add logic outside the state
expressions, as there you are again on thin-ice, with tool dependance.
-jg
Article: 71129
Re: How to constrain a divide by 3 clock?I don't have much of a choice as those crappy oddballs here wrote all those weird RTL codes...
I am only trying to somehow put their odd eggs into the FPGA.
Is my time specifications ok to do the build and P&R?
I just need some formality thing to show them that I have done what the tools can do and flag 'em
a fail or pass.
Kelvin
"Peter Alfke" <peter@xilinx.com> wrote in message news:BD13115C.761D%peter@xilinx.com...
Kelvin, if for some reason you decide not to use a DCM to do the frequency division, you can do this with two flip-flops and their two LUTs.
The input clock to output Q is exactly one "clock-to-Q" parameter. There can be only one result, unless you insist on doing something weird and non-synchonous..
Peter Alfke, Xilinx Applications
From: "Kelvin" <student@nowhere.com>
Organization: StarHub Internet Pte Ltd
Newsgroups: comp.arch.fpga
Date: Thu, 8 Jul 2004 15:45:54 +0800
Subject: How to constrain a divide by 3 clock?
Hi, there:
My clk_4m is generated from clk_12m through a divide_by_3 state machine...
And I feed clk_4m into a BUFG also...I estimate the time from rising edge of
clk_12m to clk_4m is 3.6 ns...Can I write these two constraints?
NET "clk_12m" TNM = "clk_12m";
TIMESPEC "TS_clk_12m" = PERIOD "clk_12m" 83.3 ns HIGH 50 %;
NET "clk_4m" TNM = "clk_4m";
TIMESPEC "TS_clk_4m" = PERIOD "clk_4m" TS_clk_12m / 3 PHASE + 3.6 ns;
Thanks.
Kelvin
Article: 71130Yeah, try latest WebPACK... Kelvin "Eric Crabill" <eric.crabill@xilinx.com> wrote in message news:40ED71D0.4E9E093C@xilinx.com... > > Hi, > > My suggestion to you is: > > * Revert to Windows 2000, preserve your hardware and software > investment. Windows 2000 isn't that bad... But 2.1i is now > pretty stale. As are the XC4000-style parts, which I assume > you are using. > > * Submit a donation request to the Xilinx University Program, > for software and the hardware you require. It is worth a > shot... At SJSU, we check out one board to groups of two > or three. And I tell them they are always welcome to buy > their own boards. The recently released Spartan-3 board > is cheaper than many textbooks (in the US, anyway...) In > the worst case, you buy 15 ($1500) and WebPACK is free. > > In the future, if at all practical, you might consider having > a nominal "lab fee" like some labs at SJSU. You can save the > proceeds over several years and then use it to upgrade your > hardware in an attempt to stay current. > > When making your decision, you might also consider the overhead > in updating all the coursework to the new tools. I went through > this (2.1i schematic --> 4.2i verilog) and it took a lot of work. > In the end, it was worth it though. You're welcome to pull any > material you want from: > > http://www.engr.sjsu.edu/crabill > > Eric > > Mike Collier wrote: > > > > We have been using Xilinx Student Edition 2.1i in a Third World > > university for several years. Now that we have upgraded to Windows-XP, > > it refuses to install, giving a message that java.exe is producing an > > unhandled exception (looks like stack problem). Does anyone know of a > > fix that would allow us to use the older software on the new operating > > system? If so, it would save us changing devices, software and > > experiment boards with our non-existent foreign currency. Any ideas?Article: 71131
OSX is basically FreeBSD unix under the hood with a very nice GUI. Given the fact that dual processor G5's are essentially high performance Unix workstations that also happen to run all of those so-called 'productivity apps', I'm wondering if we'll see any Commercial EDA apps released for the platform? Most of the OpenSource EDA tools like Icarus, GHDL, GTKWave, etc. are already running on OSX (it's quite easy to port code from Linux to OSX - usually no changes are required). I suspect that support issues would probably be less than those associated with Linux as well because there are less flavors. Having a plethora of choices of distros is one of Linux's strong points and it's just fine as long as you've got the source code for a given tool (like those listed above) but with closed-source tools it can be problematic which is why most EDA vendors still only support RedHat 7.2 (I recall running that version back in '99 :) or maybe RH 8.0. And then there's 64bit support: are you going to support Opteron or Itanium binaries (or both) for example. Don't get me wrong, I still like and use Linux, but after using OSX for a few months I'm really liking not having to be a sysadmin for a laptop. ;-) This would also seem to be a benefit for companies as well. Sure Apple hardware is pricier than PC hardware, but when you compare that price difference (maybe $500 at the highend) with the price of EDA software ($5K - $100K+) the price difference is insignificant compared to the potential benefits. Since each engineer would only need one OSX machine on their desk (it runs those so-called 'productivity apps') that would probably make up for the price difference quite easily. PhilArticle: 71132
> Hi All, > > I'm trying to synthesize the folllowing VHDL file with the Xilinx > WebPack tools. I'm synthesising for a XC3S200 chip. > When I run XST it generates one 256 bits serial register and assigns > outD and outD1 both to the same output of the shift register (I > checked with the RTL schematic viewer). The ISE schematic viewer didn't show you everything. If you implement the design and look at the ncd file with the FPGA editor, you will see that outD and outD1 come from two different places. > Changing outD1 <= fifo(28); to outD1 <= fifo(7); (or any other number > below 16) generates two shift registers as expected. Did I run into a SRL16's are used for the shift registers. Two outputs cannot come from the same SRL16 as it uses one LUT. For bit 0 and 28 case, they can be taken from different SRL16's, so only one 256-bit shift register is needed (16 SRL16). For bit 0 and 7 (or anything < 16) case, two shift registers have to be used (one 249 bit and the other one 7 bit). HTH, Jim (jimwu88NOOOSPAM@yahoo.com remve NOOOSPAM) http://www.geocities.com/jimwu88/chips > XST bug or do I something terribly wrong (I'm new to VHDL). > Version used 6.1.03i (It isn't the latest version I think but happens > to be on the PC I'm using at the moment) > > Thanx, > Peter > > > library IEEE; > use IEEE.STD_LOGIC_1164.ALL; > use IEEE.STD_LOGIC_ARITH.ALL; > use IEEE.STD_LOGIC_UNSIGNED.ALL; > > -- Uncomment the following lines to use the declarations that are > -- provided for instantiating Xilinx primitive components. > -- library UNISIM; > -- use UNISIM.VComponents.all; > > entity test2 is > port ( > clk: in std_logic; > inD: in std_logic; > outD1: out std_logic; > outD: out std_logic > ); > end test2; > > architecture Behavioral of test2 is > signal fifo: std_logic_vector(0 to 255); > > begin > process(clk, inD) > begin > if (clk'event and clk='0') then > fifo <= fifo(1 to 255) & inD; > end if; > end process; > outD1 <= fifo(28); > outD <= fifo(0); > > end Behavioral;Article: 71133
news@sulimma.de (Kolja Sulimma) wrote: > > These are two different things, which seem very similar. > > Probably not. By downloading you are receiving a single copy of the > software. The process of copying was initialized by the seller. Only > the ownership of that copy is transfered, there is no license for > copying necessary, the transaction can be handled as a purchase. > Also, the buyer probably believes this is a purchase anyway, so that a > license contract is likely to be void. IANAL, too. German law is not logical in any ways (as most other laws I asume). Maybe you should google in de.soc.recht.* In short you can't get ownership on software in Germany, but you can get ownership on a CD containing software. For using a software you need the right to use it (Nutzungrecht), often called license. In Germany you get this license either by getting owner of a CD containing the software, or by a license agreement. bye ThomasArticle: 71134
Hi all My problem is I'd like to choose a VHDL file instantiated inside verilog via VHDL configuration To summerize: I have a hierarcy: "top:vhdl - verilog - Verlog -vhdl: bottom" How to write a vhdl configuration to select the file for the bottom instantiation? Rakesh YCArticle: 71135
mx wrote: > Rene Tschaggelar wrote: > >> The whole is solved by a notebook being the work machine at >> the expense of reduced performance. > > > UMMM *NO* the original-poster mentioned somewhere in his rant that > the license terms of Mentor, Cadence, and Synopsys > are *tied* to a physical site. Actually the software license is bound > to 3 specific items: > > a) authorized hardware (license node/server) > <AND> > b) physical site (company location, with defined 'distance radius') > <AND> > c) the party/persons/company named on the purchase-order > > That's *AND* (not OR.) Change any 1 of the above, and you have to > contact the vendor to renew/re-validate your license. (This doesn't > automatically mean you have to *repurchase* the software...) > > (b) Buying a laptop, taking it on the road, and using it to run the > EDA sofware falls under 'running the software outside of the > physical site.' All you've done with your laptop, is place > both the license-server and execution-machine in the same > machine (your laptop), instead of just taking the execution-machine > > The physical-site limitation is so restrictive, that technically > speaking, if a customer merely relocates its office more than a > few miles, their software-liense is invalidated. Obvioualy, > no EDA-vendor requires the customer to repurchase the software. They > merely update the license contract with the customer's new (street) > address. The physical location restriction is completely ridiculus. Upon further thinking about its implications, one could figure that the software is almost infinitely crappy. The implications are such that the user of such a software cannot show it on an exhibition. All the other limitations are dream world stuff. It cannot be legally proven that the software was used at home beside the pool even when it is run by the correct user on the correct machine. Nor can be legally proven that it was shown to a colleage at whatever location. IMO, a very obvious way to try to keep the software off the public eyes. I happend to work once with such kind of software, 40k$ per seat, plus something per year, and the user interface was such awkward and clumsy, that I wished the developpers being beaten up for every minute I had to work with. If such feelings spread too quickly and too openly, the business would be on the downslope rather quick. Since such software is usually purchased by people who will never work with it, the employee on this software has to be eternally gratefull to be able to work with this software and deliver the expected results. IMO, such restrictions are an indication for crap to be stayed away from. ReneArticle: 71136
Does somebody has some paper or document about the speed between FPGA and computer. Please send to me uliverpool@163.com thank you!Article: 71137
Hello people. I will be maintaining recent snapshots of the Icarus Verilog compiler for the Windows platform in easy to use installers at http://armoid.com/icarus/. I have been doing this for more than a year now for the people in my company so I thought, what the heck, for the same effort I can benefit other users out there. If you have other free related goodies that can be posted there --like Verilog test files, utility scripts, etc.-- please email me at mailto:pbleyer2004N@SPAMembedded.cl [N@SPAM->@] Thanks for Stephen Williams for putting together such a nice Verilog compiler for the community. Regards. -- PabloBleyerKocik /"...I didn't want to be kissing Kevin Spacey. pbleyer2004 / Come on! Lying there naked with rose petals?" @embedded.cl /- Kirsten Dunst on turning down American BeautyArticle: 71138
Thank you both for your responses. rickman wrote: > 0 AND anything is always 0. But 1 AND X is not 1. So the OR of two > unknowns is not a known. The value of X is not the same as "don't care" > or not sure if it is a 0 or a 1. It can also be hi-z and will result in > an unknown state on the output of the AND gate. Your point about HiZ is well taken. I had been using 'X' mentally thinking of it as "could be either 0 or 1". > Try using a proper VHDL simulator. I use the Xilinx version of > Modelsim. I fully acknowledge the need to move to a different simulator. My present project has been marching through the design steps, and there's not been a stage where I've been willing to invest the time to learn to use ModelSim. While I have a ModelSim-Xilinx, it would be more straightforward to use the ModelSim-Altera - in particular I anticipate it would be straighforward to feed it Altera specific megafunctions (for example I tend to use lpm_count after having Quartus not infer a couple of counters - perhaps I should have put in more effort understanding how to write the counter so it _would_ be inferred). Though I seem to recall people mentioning in the group that ModelSim-Xilinx offers a more complete feature set. Have you used ModelSim-Altera, and if so has your experience been satisfactory ? > Is this simulation *after* synthesis? If so I have no idea why your two > results would be different. I read your later message and you show the > two outputs use the same equation, but your simulation gives different > results. It *must* be simulating before synthesis. Now that's a mighty interesting question. In the original post I'd given an example from QII v4.0sp1 where 2 expressions (that synthesize the same) give different simulation results, so it sure doesn't appear to be simulating what it's synthesizing. On the other hand, it does force you to execute a step called "Generate Functional Simulation Netlist" before doing the simulation. As I look at it, a netlist is kind of like a wiring list, ie what to connect to what... but you have to know what are the pieces (gates ?)you're connecting in order to simulate -- and that sounds like synthesis to me. The story with QII v3.0sp2 is a little different. I didn't have the "check outputs" checkbox enabled when I ran it, so I must amend an earlier post where I said the results are exactly the same as v4.0sp1. In v3.0sp2, my equations Y and Z synthesize the same and simulate the same, but like eqn Y in v4.0 they give definite results in situations where I believe they should not. Then I plugged in the longer mux expression that Quartus likes to generate, of course it synthesizes the same, but it simulates differently ! So I would say that for QII v3.0sp2 (where the "Generate Functional Simulation Netlist" step doesn't exist) the simulator is not simulating what it has synthesized !Remarkable. Either that or it is not synthesizing what the equations are reporting. Pick your poison, so to speak. As you say, time to move to ModelSim. Martin Thompson <martin.j.thompson@trw.com> wrote in message news:<usmc2ime2.fsf@trw.com>... > rickman <spamgoeshere4@yahoo.com> writes: > <much snippage> > > Rajeev wrote: > > > (1) Is it a bad idea to use 'X' in a simulation ? > > > > It would seem X is not a useful state in this simulator. In a proper > > VHDL simulator X has a defined behavior and is the default for FFs that > > are not init'd or inputs that are not assigned. > > > > To be a bit more specific, 'U' is the undefined or "start-up" state. > 'X' is what appears when you drive two clashing values onto a > std_logic. Or when the simulator sees a D input change inside the > setup-hold window of a FF. Also, Stratix MegaRAM cannot be initialized. When I inspect the contents in the Quartus v4.0 simulator it is full of 'X'. > I've never used an 'X' in simulation - created a few inadvertently > though... > > If you want a "don't-care" use '-' instead. I had imagined '-' as something to be specified on an output that would match any of the other 8 values. I guess I need to study the definitions and usage of these other states. I can see that there are a few things to explore, let me report back perhaps in a couple of weeks. Thanks, -rajeev-Article: 71139
hi I have some problems with frame address calculation for readback on Xilinx Virtex II Pro XC2VP7. This is what I know about FAR: - have to write 00 to bits 26 and 25 for CLB's - have to write 01 to bits 26 and 25 for BRAM's - have to write 10 to bits 26 and 25 for BRAMINT - I have to shift the CLB or BRAM column to bit 17 - I have to shift the number of the frame inside a block to bit 9 My problem is where to find the CLB column. I thougt I could use the X-coordinates from floorplanner or fpga-editor. But this is wrong. Any ideas? -- Andreas Weder Hochschulstraße 8 01069 Dresden, Germany +49 162 / 4099116 andreas@lowtexx.deArticle: 71140
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Article: 71141I'm looking at the DCI (digitally controlled impedance) part of the Spartan-3 spec, and I'm wondering if I can use this to eliminate the series termination resistors on an IDE interface. A typical IDE signal has a 22 ohm series resistor at the driver end and an 82 ohm series resistor at the receiver end. Typical bi-directional signals have a 33 ohm series resistor at both ends. If I understand the spec correctly, it looks like I can get the series resistor at the driver end, but not at the receiver end. Also on the bi-di's I can get 33 ohms at each end, but the received signal would be "picked off" before the 33 ohm resistor rather than after it...something you could not do when the resistor was external. So can I use any of this? or do I need to stick to external termination? Thanks DanArticle: 71142
On Fri, 09 Jul 2004 03:23:08 -0700, guhaoqi wrote: > Does somebody has some paper or document about the speed between FPGA and computer. Please send to me uliverpool@163.com thank you! This is like asking for a paper comparing a tire to a car. If you are interested in a specific application then it becomes a little easier to compare a software solution to a hardware solution but even there it's still apples to oranges.Article: 71143
rickman wrote: > > If this were true, then you would never need to specify that you are > using one-hot encoding. The states that are not used would be detected > as not needing to be decoded and the logic would automatically minimize > to just using one bit to represent each state... Yes, I am talking about one-hot encoding. Where I have seen the problem is on power when, for whatever reason, none of the states are selected. In that case, the state machine is dead. > Where have you seen that a tool will optimize away the others clause? Xilinx XST. -- My real email is akamail.com@dclark (or something like that).Article: 71144
Dan, Simulate it. I doubt seriously that picking off the signal before or after a resistor at the receiver will make any difference at all (after all, the receiver has nearly infinite input impedance, and about 7-8 pF of capacitive loading, so what does a 82 ohm resistor to a 7 pF cap look like? not much I assure you). As for setting the DCI resistance, use 82 ohm, or 33 ohm reference resistors to set the DCI series drive impedance to 82 or 33 ohms. I would simulate it in Hyperlynx using the various IBIS models fromt he different vendors to prove that it works with high and low Vcc, and with fast and slow process corners. A standard is a starting point. Either meet it exactly, and not worry, or simulate what you waht to do differently to prove it will always work the way you intend it to. Your choice. By the way, I even simulate a standard interface, as I do not trust that the standard's body could anticipate every possible use of their precious standard, or that every vendor really 'met' the standard when combined with the other vendors in the design. Austin Dan Kuechle wrote: > I'm looking at the DCI (digitally controlled impedance) part of the > Spartan-3 spec, and I'm wondering if I can use this to eliminate the series > termination resistors on an IDE interface. A typical IDE signal has a 22 > ohm series resistor at the driver end and an 82 ohm series resistor at the > receiver end. Typical bi-directional signals have a 33 ohm series resistor > at both ends. If I understand the spec correctly, it looks like I can get > the series resistor at the driver end, but not at the receiver end. Also on > the bi-di's I can get 33 ohms at each end, but the received signal would be > "picked off" before the 33 ohm resistor rather than after it...something you > could not do when the resistor was external. So can I use any of this? or > do I need to stick to external termination? > > Thanks > Dan > >Article: 71145
Dan, when you use series termination on a unidirectional line with one driver and one receiver (the normal application), then you only series-terminate the driver, and there should be no resistor at the receiving end. The idea is to match the driving end, send a half-amplitude signal down the line, and make it bounce up to full strength at the unterminated receiver. Series termination takes advantage of reflection, unstead of fighting it. DCI is a nice way to manipulate the drive strength such that it matches the line impedance. Peter Alfke, Xilinx Applications > From: "Dan Kuechle" <danielgk@voomtech.com> > Organization: VISI.com > Newsgroups: comp.arch.fpga > Date: Fri, 9 Jul 2004 10:17:48 -0500 > Subject: Spartan 3 termination question (DCI) > > I'm looking at the DCI (digitally controlled impedance) part of the > Spartan-3 spec, and I'm wondering if I can use this to eliminate the series > termination resistors on an IDE interface. A typical IDE signal has a 22 > ohm series resistor at the driver end and an 82 ohm series resistor at the > receiver end. Typical bi-directional signals have a 33 ohm series resistor > at both ends. If I understand the spec correctly, it looks like I can get > the series resistor at the driver end, but not at the receiver end. Also on > the bi-di's I can get 33 ohms at each end, but the received signal would be > "picked off" before the 33 ohm resistor rather than after it...something you > could not do when the resistor was external. So can I use any of this? or > do I need to stick to external termination? > > Thanks > Dan > >Article: 71146
Pablo Bleyer Kocik wrote: > Hello people. > > I will be maintaining recent snapshots of the Icarus Verilog compiler > for the Windows platform in easy to use installers at > http://armoid.com/icarus/. I have been doing this for more than a year > now for the people in my company so I thought, what the heck, for the > same effort I can benefit other users out there. > > If you have other free related goodies that can be posted there > --like Verilog test files, utility scripts, etc.-- please email me at > mailto:pbleyer2004N@SPAMembedded.cl [N@SPAM->@] > > Thanks for Stephen Williams for putting together such a nice Verilog > compiler for the community. > > Regards. > > -- > PabloBleyerKocik /"...I didn't want to be kissing Kevin Spacey. > pbleyer2004 / Come on! Lying there naked with rose petals?" > @embedded.cl /- Kirsten Dunst on turning down American Beauty How does the icarus compiler compare with the commercial ones, e.g. modelsim, ncverilog, etc.?Article: 71147
Pablo Bleyer Kocik wrote: > Hello people. > > I will be maintaining recent snapshots of the Icarus Verilog compiler > for the Windows platform in easy to use installers at > http://armoid.com/icarus/. I have been doing this for more than a year > now for the people in my company so I thought, what the heck, for the > same effort I can benefit other users out there. > > If you have other free related goodies that can be posted there > --like Verilog test files, utility scripts, etc.-- please email me at > mailto:pbleyer2004N@SPAMembedded.cl [N@SPAM->@] > > Thanks for Stephen Williams for putting together such a nice Verilog > compiler for the community. > > Regards. I should add that Pablo has been sending me copies of his installer that I keep in the "precompiled" directory where snapshots are normally found. I should have a link to his site as well, unless I forgot. I still haven't booted Windows recently enough to try his installer (lucky me!) so ride reports to comp.lang.verilog are welcome. -- Steve Williams "The woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep."Article: 71148
In article <BD1414E3.7665%peter@xilinx.com>, Peter Alfke <peter@xilinx.com> writes: >Dan, when you use series termination on a unidirectional line with one >driver and one receiver (the normal application), then you only >series-terminate the driver, and there should be no resistor at the >receiving end. >The idea is to match the driving end, send a half-amplitude signal down the >line, and make it bounce up to full strength at the unterminated receiver. >Series termination takes advantage of reflection, unstead of fighting it. >DCI is a nice way to manipulate the drive strength such that it matches the >line impedance. Also works for a bidirectional line if you put series resistors at both ends. The one at the receiver doesn't get in the way. (At least not much and/or at speeds where you are likely to be using bidirectional lines.) -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 71149
Search on "reconfigurable computing." Almost any paper that implements a compute intensive algorithm has numbers for performance (at least the ones I review) Steve
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