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Messages from 71350

Article: 71350
Subject: Nios reset behavior
From: tns1 <tns1@cox.net>
Date: Thu, 15 Jul 2004 07:51:57 -0700
Links: << >>  << T >>  << A >>
I am trying to understand the low level startup sequence on a custom 
Nios board. When the Nios (3.2) resets, what determines where it fetches 
its very first instruction? Is it always from the onchip bootstrap area 
or is this configurable? I don't have the OCI so I assume I can't just 
step thru from reset on my target (with gdb).

As I understand it, SOPC(4.0) compiles my custom bootstrap and Quartus 
(4.0sp1) adds this code to the pof, but not to the application srec. I 
am confused that the objdump for the bootstrap shows it is compiled for 
my SRAM base, not the onchip area. The Nios manuals say the code is not 
generally relocatable so this does not seem right. I don't see how to 
fix this base in the Nios dialog - it appears to be set correctly.

TIA


Article: 71351
Subject: Re: Spartan 3 termination question (DCI)
From: Austin Lesea <austin@xilinx.com>
Date: Thu, 15 Jul 2004 08:07:00 -0700
Links: << >>  << T >>  << A >>
Brian,

I would appreciate it if you did detail every single omission, 
distortion, or mis-representation.

In fact, I demand it, or an apology.  As you know, when I make a 
mistake, I own up to it immediately.  I expect no less from others.

To say "if you are already drawing no power, then 200 mW is a lot of 
power" is a pretty inane response.

Obviously.  Your point?

Peter's comment is perfectly accurate:  series terminations dissipate 
virtually no power in the series termination resistors.

As for my sarcasm, although sarcasm is known as the "weapon of the 
weak." it does serve a purpose to emphasize a point.  I reserve the 
right to be as entertaining as possible.

Thanks for the suggestion of turning the reference resistors off.  Not a 
bad idea at all.

Power estimation tools lag the rest of the tools.  Entering in the 
omissions on the hotline generates corrective action reports, which gets 
them fixed.  I will check to see where we are.

Austin

Article: 71352
Subject: Clock generation
From: Patrik Eriksson <no.spam@netinsight.net>
Date: Thu, 15 Jul 2004 17:16:36 +0200
Links: << >>  << T >>  << A >>
Hi,

I would like to generate a clock from a refclk according to the 
following function:

clk = refclk*(64/66)

I will implement this function in an VirtexII Pro FPGA and my first 
approach is to divide the refclk by 3 in logic and then use a DCM to 
multiply with 32/11.

clk = refclk*(1/3)*(64/22)
clk = refclk/3*(32/11)

Will this work? The frequencies has to be locked to each other.


------
Patrik Eriksson


Article: 71353
Subject: Re: micron sdram module
From: Duane Clark <junkmail@junkmail.com>
Date: Thu, 15 Jul 2004 08:20:34 -0700
Links: << >>  << T >>  << A >>
Pino wrote:
> 
>  ...   The verilog doesn't work well as I have not
> managed to be able to interface Verilog and VHDL properly within the
> same design.  

There is nothing special required for Modelsim, though I can't say about 
other simulators. You just instantiate a Verilog module as if it were a 
VHDL entity:
    -- MICRON DDR SDRAM Simulation Model
    MEM1 : entity micron.ddr
       port map (
          dq          => DDR_DQ(0 to 15),
          dqs         => DDR_DQS(0 to 1),
          addr        => DDR_Addr,
          ba          => DDR_BankAddr,
          clk         => DDR_Clk,
          clk_n       => DDR_Clkn,
          cke         => DDR_CKE,
          cs_n        => DDR_CSn,
          ras_n       => DDR_RASn,
          cas_n       => DDR_CASn,
          we_n        => DDR_WEn,
          dm          => DDR_DM(0 to 1)
          );


-- 
My real email is akamail.com@dclark (or something like that).

Article: 71354
Subject: Re: FSM in illegal state (conclusion)
From: Duane Clark <junkmail@junkmail.com>
Date: Thu, 15 Jul 2004 08:26:09 -0700
Links: << >>  << T >>  << A >>
Michael Smith wrote:
> 
> Forgive me if I've someone's mentioned it already, but I understand that, in
> Virtex and later devices, synthesis tools do NOT infer the use of the GSR
> from the VHDL Reset signal. Instead the user's Reset is routed using general
> routing resources. (So, timing constraints can be applied to it.) There is
> of course still an issue if the external signal is truly asynchronous to the
> clock.
> 

I am puzzled by how that would work. In normal use, the reset would be 
driven by an internal ROC (in VHDL), or be driven only by the testbench 
(in Verilog). So what would be the source of the reset signal in the 
cases you mention? Or are you referring to an asynchronous reset driven 
from a pin?

-- 
My real email is akamail.com@dclark (or something like that).

Article: 71355
Subject: Re: Altera SOPC SDRAM & CLK Input?
From: kempaj@yahoo.com (Jesse Kempa)
Date: 15 Jul 2004 09:07:39 -0700
Links: << >>  << T >>  << A >>
> 
> Jesse/Ken,
>  
>     Thanks for your responses.  In fact I was debating whether or not
> I needed one, but both your responses definitely eliminate my thought
> of not having to implement one.  I agree that this is required and
> will definitely help me with any board skew as well.   I haven't
> implemented, but will look into the example and try to use some of the
> results from that for the board.  Do you know what the trace-lengths
> (layout) is on the board to configure the proper phase delay
> parameters for the PLL for the 1s10 NIOS eval.board?  Is there a
> recommended number I should use?
> 
> Regards,
> Pino

Look at the "standard" or "standard_32" design in Quartus and
double-click the PLL block to edit it. The wizard has several pages of
settings for the PLL. The one you are concerned with is the "Clock e0"
page, which lets you set a multiplier/divisor for the external clock
going to the PLL (the clock "c0" page lets you setup the clock that is
fed, in the example design, to SOPC Builder/Nios).

These settings let you set a phase shift in degrees or seconds; we
measured the delay between clock generation & signals arriving at
external SDRAM using an oscilloscope for our dev boards and that delay
is where the figure you see comes from. I'm looking at an example for
a 1s40 dev board now and its -3.5ns of shift. I recommend setting
shift in nanoseconds versus degrees of phase, because this way the
shift is constant even if you later tweak the clock speed of your
design.

Also, this PLL wizard is what you would use to change the clock speed
going to your SOPC Builder design (or other user logic).

- Jesse

Article: 71356
Subject: Xilinx EDK PCI
From: "Jackson Pang" <jacpang@cisco.com>
Date: Thu, 15 Jul 2004 09:12:17 -0700
Links: << >>  << T >>  << A >>
Hello

I'd like to know if anybody had any success in using Xilinx OPB/PCI bridge
core using EDK.  I set up the project and configured all the core parameters
correctly. I also double checked the constraint file for pin assignments for
the PCI finger. The compile and programming process goes well without any
error, but I cannot even get my host PC to recognize my development board
with the PCI bitmap. I am using Avnet's Virtex II PCI Development Board.
Thanks for your input in advance.



Article: 71357
Subject: MUXCY-based multiplexers
From: Jo Pletinckx <jo_pletinckx@yahoo.com>
Date: Thu, 15 Jul 2004 18:16:30 +0200
Links: << >>  << T >>  << A >>
Hi,

In the XST manuals, it is mentioned rather cryptically that these type 
of muxes can be more efficient in some cases than the MUXFX versions, 
especially for very large muxes. What is actually meant: very large 
input muxes, or muxes with a limited number of very wide inputs? I fail 
to see how they are more efficient... I've searched the web/news groups 
to no avail.


Thanks for your answer,

with regards,

Jo

Article: 71358
Subject: Re: MUXCY-based multiplexers
From: "M.Randelzhofer" <techseller@gmx.de>
Date: Thu, 15 Jul 2004 18:20:59 +0200
Links: << >>  << T >>  << A >>
"Jo Pletinckx" <jo_pletinckx@yahoo.com> schrieb im Newsbeitrag
news:MPG.1b60cc26cf245af7989680@News.Individual.NET...
> Hi,
>
> In the XST manuals, it is mentioned rather cryptically that these type
> of muxes can be more efficient in some cases than the MUXFX versions,
> especially for very large muxes. What is actually meant: very large
> input muxes, or muxes with a limited number of very wide inputs? I fail
> to see how they are more efficient... I've searched the web/news groups
> to no avail.
>
>
> Thanks for your answer,
>
> with regards,
>
> Jo


see Xilinx techxclusives multiplexer selection from ken chapman:

http://www.xilinx.com/xlnx/xweb/xil_tx_display.jsp?sGlobalNavPick=&sSecondaryNavPick=&category=&iLanguageID=1&multPartNum=1&sTechX_ID=kc_multiplexer

MIKE



Article: 71359
Subject: Re: MUXCY-based multiplexers
From: Jo Pletinckx <jo_pletinckx@yahoo.com>
Date: Thu, 15 Jul 2004 18:50:37 +0200
Links: << >>  << T >>  << A >>
> 
> 
> see Xilinx techxclusives multiplexer selection from ken chapman:
> 
> http://www.xilinx.com/xlnx/xweb/xil_tx_display.jsp?sGlobalNavPick=&sSecondaryNavPick=&category=&iLanguageID=1&multPartNum=1&sTechX_ID=kc_multiplexer
> 
> MIKE
> 

Thanks your quick answer Mike. Unfortunately, it does not really answer 
my question. In fact, the TechExclusive from Ken Chapman uses a 
different approach: he only has one input per LUT, whereas the XST-
generated muxes have 2 two inputs and two selectors and function much in 
the same way as Ken's multiplexer, with one selector en or dis-abling 
the LUT and the other selecting one of both inputs. At two inputs per 
LUT, this in roughly the same ratio as the MUXFX based multiplexers. So 
when does it become more efficient the use the carry-chain?

Or is the gain located only in the implementation, as it reduces the 
probability of routing congestion by spreading the inputs over a taller 
column than the MUXFX multiplexer does?

Article: 71360
Subject: Spartan3 Dev Boards
From: "Brad Smallridge" <bradsmallridge@dslextreme.com>
Date: Thu, 15 Jul 2004 10:28:33 -0700
Links: << >>  << T >>  << A >>

Well I almost bought a development kit from Xilinx's
Online Store, however, I was looking at the schematics
and saw that this is the same board designed by Digilent,
a board that I already had. So I guess my first question
is what do I get with the Xilinx kit that I might not already
have?

I haven't pursued my Digilent board too much because
there didn't seem to be any software for it.  I also bought
a board from Memec and it has a few software examples,
but no VGA port, which is an interest of mine.  If anyone
has any more examples for the Memec board, that would
be of great interest to me.

I would like to see a real VGA driver on a dev kit but I am
also interested in what this Digilent 3 bit shoestring VGA can
do. It seems to simple to believe. Has anybody done anything
with it?

I think the XESS people were going to do a Spartan3 board.
Anyone know about this?

Salutations,

Brad



Article: 71361
Subject: Re: new Lattice FPGAs vs Cyclone and SpartanIII
From: Bassman59a@yahoo.com (Andy Peters)
Date: 15 Jul 2004 10:29:09 -0700
Links: << >>  << T >>  << A >>
"Steven K. Knapp" <steve.knappNO#SPAM@xilinx.com> wrote in message news:<cd4j4e$oeu6@cliff.xsj.xilinx.com>...
> Just FYI, there is an application note on this very topic that demonstrates
> how to configure a Xilinx FPGA from an SPI serial Flash using a small CPLD.
> The application note is written for CoolRunner-II, but practically any
> Xilinx CPLD will do.
> 
> XAPP800:  Configuring Xilinx FPGAs with SPI Flash Memories Using
> CoolRunner-II CPLDs
> http://www.xilinx.com/bvdocs/appnotes/xapp800.pdf

Yeah, but this solution still requires another part.  Perhaps
reasonable if you needed the CPLD for other things, but otherwise it's
not a very good solution.  Some boards are overstuffed as it is!

I remember using a 9536 to interface a parallel EPROM to XC4000-series
parts, but that was ages ago, before the G-dsend known as in-system
JTAG-programmable parts ...

--a

Article: 71362
Subject: RE: Xilinx Virtex-II Configuration in Slave Serial
From: "Jackson Pang" <jacpang@cisco.com>
Date: Thu, 15 Jul 2004 10:36:41 -0700
Links: << >>  << T >>  << A >>
Hi Shehzad

I have used the exact board w/ Multilinx. You don't have to unhook the MPM
in any way. The Jtag chain is built so that whatever you program will
overwrite the MPM image programmed at power-up. You just double check your
leads going into the jtag header from multilinx. I found it easier/quicker
to just use parallel III connector w/ a gender changer (female/male) wire
wrapped to the jtag header on the board.

FYI, I could not get Multilinx to work with the XMD, but ok w/ parallel III.


If you have any luck w/ using the PCI, please let me know also.

-JP




Article: 71363
Subject: Altera FIR compiler 3.1.0, no filter ouput
From: "yyz" <elelab@hotmail.com>
Date: Thu, 15 Jul 2004 17:58:15 GMT
Links: << >>  << T >>  << A >>
I tried to implement a low pass filter and decimtion using Quatus 4.0 and
FIR compiler 3.1.0

Parameterize - FIR Compiler Megacore Function

          Coefficient Specification - (low pass set [1])
                Coefficients Scaling: Auto   Bit Width: 12

          Arichitecture specification:
                Device family: Stratix
                Structure: Distributed Arithmetic: fully serial filter
                Pipeline level: 1
               Data storage: Logic cells
               Coefficients Storage: Logic cells

         Rate Specification:
               Decimation Factor 10

          Input specifcation:
              Number of input channel 1
              Input number system: signed binary
              Input bit width: 12

        Output specification:
             full resolution bit width is 24
             Based on method: Acual Coefficients
            output number system : full resolution


 Coefficients generator dialog

             Floating coefficient set
             Rate specification
                    Decimation factor 10
             filter type: low pass
             window type: Hamming
             coeffients: 37
             Sample rate: 2.0E7
             cutoff freq.1:   1.0e6


After Analysis and synthesis in Quatus 4.0, I got two warninngs

           Warning: Reduced register
fir:inst|fir_st:fir_st_inst|sadd:Uaddl_0_n_2_n|res[14]~reg0 with stuck
data_in port to stuck value GND

            Warning: Reduced register
fir:inst|fir_st:fir_st_inst|sadd:Uaddl_0_n_1_n|res[14]~reg0 with stuck
data_in port to stuck value GND

After simulation in Quatus 4.0, no filter output.

Can anyone help?





Article: 71364
Subject: Re: Spartan3 Dev Boards
From: Eric Crabill <eric.crabill@xilinx.com>
Date: Thu, 15 Jul 2004 11:01:12 -0700
Links: << >>  << T >>  << A >>

Hi,

> I would like to see a real VGA driver on a dev kit but I am
> also interested in what this Digilent 3 bit shoestring VGA can
> do. It seems to simple to believe. Has anybody done anything
> with it?

Well, you get 8 colors, you can certainly do character generators
and simple graphics.  For two "exercises" that are directly
compatible with the D2E/DIO1 combo from Digilient, check out:

http://www.engr.sjsu.edu/crabill

I'm sure these can easily be ported to the new Spartan-3 board.
What kind of stuff did you want to do with it, I'm curious.

Eric

Article: 71365
Subject: Re: Nios reset behavior
From: "Kenneth Land" <kland_not_this@neuralog_not_this.com>
Date: Thu, 15 Jul 2004 13:42:48 -0500
Links: << >>  << T >>  << A >>

In SOPC builder you set the Reset Location in the Nios More tab.

This is where the system will reset to.

I always set this an internal ram that holds either Germs or my program.
That program can load a larger program out of flash and then jump to it.
(or whatever you want it to)

The new NiosII has fancier automatic boot options but I haven't used it for
that yet.

Ken

"tns1" <tns1@cox.net> wrote in message news:hSwJc.974$ml.802@lakeread05...
> I am trying to understand the low level startup sequence on a custom
> Nios board. When the Nios (3.2) resets, what determines where it fetches
> its very first instruction? Is it always from the onchip bootstrap area
> or is this configurable? I don't have the OCI so I assume I can't just
> step thru from reset on my target (with gdb).
>
> As I understand it, SOPC(4.0) compiles my custom bootstrap and Quartus
> (4.0sp1) adds this code to the pof, but not to the application srec. I
> am confused that the objdump for the bootstrap shows it is compiled for
> my SRAM base, not the onchip area. The Nios manuals say the code is not
> generally relocatable so this does not seem right. I don't see how to
> fix this base in the Nios dialog - it appears to be set correctly.
>
> TIA
>



Article: 71366
Subject: Re: Clock generation
From: "Vladislav Muravin" <xfilex2003@hotmail.com>
Date: Thu, 15 Jul 2004 15:09:12 -0400
Links: << >>  << T >>  << A >>
what is your refclk frequency?.

"Patrik Eriksson" <no.spam@netinsight.net> wrote in message
news:40f69fd4$1@fnewsa.telia.net...
> Hi,
>
> I would like to generate a clock from a refclk according to the
> following function:
>
> clk = refclk*(64/66)
>
> I will implement this function in an VirtexII Pro FPGA and my first
> approach is to divide the refclk by 3 in logic and then use a DCM to
> multiply with 32/11.
>
> clk = refclk*(1/3)*(64/22)
> clk = refclk/3*(32/11)
>
> Will this work? The frequencies has to be locked to each other.
>
>
> ------
> Patrik Eriksson
>



Article: 71367
Subject: Re: Nios reset behavior
From: tns1 <tns1@cox.net>
Date: Thu, 15 Jul 2004 12:30:23 -0700
Links: << >>  << T >>  << A >>
Thanks. I see where I can pick the reset location. My configuration is 
just as you describe - a bootstrap routine onchip, and an app that gets 
copied from flash to external sram before execution.

My earlier statement about the bootstrap base address was wrong - the 
base address is correct for this onchip code image.

However, there is a bug in the way either my bootstrap or app gets 
built, that causes the application to jump from sram to flash addresses 
for any function call in main() (ISRs too). The base address for my app 
is correctly set to sram, not flash.

I believe the problem has to do with the initialization code before 
main(), either the routines that set up new stack frames and the CWP 
handler. To track down this bug I have been trying to make use of gdb 
(no jtag port for OCI) for either my hw target or the cpu simulator 
target. I'd like to step thru the init stuff. Using gdb for target hw 
debug does work, but so far I can't step thru the init stuff (it locks 
when stepping into flash - no surprise).

Has anyone gotten the nios cpu simulator to work under gdb? I can load 
an image and source but I can't step. I can't find the sim.ld script 
that is mentioned in the gdb docs.



Kenneth Land wrote:
> In SOPC builder you set the Reset Location in the Nios More tab.
> 
> This is where the system will reset to.
> 
> I always set this an internal ram that holds either Germs or my program.
> That program can load a larger program out of flash and then jump to it.
> (or whatever you want it to)
> 
> The new NiosII has fancier automatic boot options but I haven't used it for
> that yet.
> 
> Ken
> 
> "tns1" <tns1@cox.net> wrote in message news:hSwJc.974$ml.802@lakeread05...
> 
>>I am trying to understand the low level startup sequence on a custom
>>Nios board. When the Nios (3.2) resets, what determines where it fetches
>>its very first instruction? Is it always from the onchip bootstrap area
>>or is this configurable? I don't have the OCI so I assume I can't just
>>step thru from reset on my target (with gdb).
>>
>>As I understand it, SOPC(4.0) compiles my custom bootstrap and Quartus
>>(4.0sp1) adds this code to the pof, but not to the application srec. I
>>am confused that the objdump for the bootstrap shows it is compiled for
>>my SRAM base, not the onchip area. The Nios manuals say the code is not
>>generally relocatable so this does not seem right. I don't see how to
>>fix this base in the Nios dialog - it appears to be set correctly.
>>
>>TIA
>>
> 
> 
> 


Article: 71368
Subject: News, Sydney-X1 FPGA Computer Challenges Commodore, Amiga and Apple
From: "Tony Burch" <tony@burched.com.au>
Date: Fri, 16 Jul 2004 05:42:31 +1000
Links: << >>  << T >>  << A >>
SYDNEY-X1 FPGA COMPUTER
CHALLENGES COMMODORE,
AMIGA AND APPLE

BurchED announces the release of the Sydney-X1 FPGA Computer
for electronics hobbyists, educators and computer architecture researchers

SYDNEY, Australia, July 15, 2004 – BurchED, a provider of Field Programmable
Gate Array (FPGA) development board solutions, today announced the
availability of the new Sydney-X1 FPGA Computer.  Integrating the high
performance B5-X300 FPGA motherboard, the Sydney-X1 addresses electronics
hobbyists’ demand for a new and exciting platform for the design of small
system-on-chip computers, custom or standard architecture CPUs, and
arcade-style gaming machines.

The Sydney-X1 is a complete computer system based on FPGA technology, and is
supplied with everything needed for a working system out-of-the-box,
including keyboard, mouse, VGA extension cable, 5W speaker, 64MB compact
flash card, power supply and FPGA programming cable.  Design for the system
is done using the free Xilinx WebPACK™ design tools, and with VHDL or
Verilog hardware description language code.  System-on-chip designs can be
created from mixes of code including cores available from the web, code from
BurchED demo applications and code designed from scratch.  The FPGA can be
reprogrammed within a matter of seconds, so that different designs can be
developed and shared amongst users.

The Challenge
With the introduction of the Sydney-X1, BurchED claims to attempt to capture
some of the spirit and fun of earlier frontier computing machines such as
the Commodore 64, Amiga Color Personal Computer, and Apple IIe.  The
Sydney-X1 provides the accessibility and hardware control that was
characteristic of those early machines, while providing an easy-to-use
platform for today’s electronics hobbyists.

About FPGA Computers
FPGA computers are a new concept in electronics hobbyist computing.  They
offer the ability to explore the design of new computers and other
system-on-chip hardware.  The main difference between an FPGA computer and a
traditional computer is that there is no fixed-silicon CPU at the heart of
the machine.  Instead, there is a programmable gate array device (the FPGA),
which can directly implement a CPU, or multiple CPUs, and peripheral
interfaces.  CPUs may be custom designed or functionally identical to
popular vendors’ CPUs, such as Microchip PIC, Atmel AVR, Zilog, or Intel
microcontrollers.

About BurchED
Burch Electronic Designs (BurchED), founded in 1997, is a provider of great
value Field Programmable Gate Array (FPGA) development boards, for use by
electronics hobbyists, design engineers and universities.  Additional
information about BurchED is available at www.burched.biz




Article: 71369
Subject: Re: Nios - Ethernet Frame Format
From: csim036@ec.auckland.ac.nz (Colin)
Date: 15 Jul 2004 13:54:12 -0700
Links: << >>  << T >>  << A >>
Thanx guys I really appreciate you help.

Article: 71370
Subject: Network Communication Using Nios Daughter Board
From: csim036@ec.auckland.ac.nz (Colin)
Date: 15 Jul 2004 14:09:27 -0700
Links: << >>  << T >>  << A >>
Hi,

My partner and I are trying to implement a network bridge using the
APEX20KE Nios Development board and Nios Ethernet Daughter Board.  As
part of this network bridge we need to be able to recieve all Ethernet
packets and be able to strip the headers (which we have been able to
do).  And then create new headers, create another Ethernet packet with
the new header and send that (which we couldn't do).

I've gone over the Ethernet User Manual and all available
documentation on the Nios Ethernet Board but there is no functions
available or no means available to create my own packets and send it
(ie. without Nios having to send ARPs, etc).

We need to be able to create our own Ethernet Packets and just send it
as is (at the moment we can only use the "nr_plugs_send()" and
"nr_plugs_send_to()" functions to send, and these functions create the
Ethernet packet for us and we have no control of what goes into the
Ethernet headers).

We really need to know means to create our own Ethernet, IP and TCP or
UDP headers, for an Ethernet packet and then send it.

Anyones' assistance is most welcomed.  Thanx

Article: 71371
Subject: SPARTAN-3 RDS resistor
From: "Amontec, Larry" <laurent.gauch@amon-tec.com>
Date: Thu, 15 Jul 2004 23:37:19 +0200
Links: << >>  << T >>  << A >>
What is the Rds (drain-source resistor) of an SPARTAN-3 IO defined as an 
active open-drain?

Larry
www.amontec.com

Article: 71372
Subject: Re: FPGA with fully asynchronous RAM
From: Ray Andraka <ray@andraka.com>
Date: Thu, 15 Jul 2004 19:37:50 -0400
Links: << >>  << T >>  << A >>

I'm not.  FPGAs are specifically designed for synchronous logic designs.
While an async design can be done if done very carefully, the lack of support
for this by the tools makes it excruciating at best.  Every once in a while
someone comes along with the bright idea to use an FPGA as a platform for
async logic experiments.  A search of the literature should provide a trail of
efforts that al come to the same conclusion: that the tools and FPGAs don't
support it.  There are plenty of academics that have already plowed this
path.  Read their work and be forewarned.

Nicholas Weaver wrote:

> In article <40E3C0E0.5040101@ecs.tuwien.ac.at>,
> Fuchs Gottfried  <fuchs@ecs.tuwien.ac.at> wrote:
> >I know that synchronous RAMs are preferable, but the asynchronous RAMs
> >are needed in my design due to the fact that it is a processor design
> >that is fully asynchronous.
>
> I'm sorry for the pain you are going to suffer making self timing
> circuits in an FPGA.
> --
> Nicholas C. Weaver                                 nweaver@cs.berkeley.edu

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 71373
Subject: Re: Spartan 3 termination question (DCI)
From: rickman <spamgoeshere4@yahoo.com>
Date: Thu, 15 Jul 2004 20:12:54 -0400
Links: << >>  << T >>  << A >>
Austin, 

Where did you get your incredible attitude?  I normally refrain from
posting about your mildly offensive posts, but when you call others on
the carpet like this it is just too much.  

Your sarcasm added *nothing* to your message.  It simply made you look
silly and as you said, "weak".  

"Wow.  Sooooo much current!" 

REALLY!  This makes you sound like a 12 year old in the school yard... 
nothing entertaining about that! 

Your posts are normally useful and informative.  Just leave the attitude
out of it, ok? 


Austin Lesea wrote:
> 
> Brian,
> 
> I would appreciate it if you did detail every single omission,
> distortion, or mis-representation.
> 
> In fact, I demand it, or an apology.  As you know, when I make a
> mistake, I own up to it immediately.  I expect no less from others.
> 
> To say "if you are already drawing no power, then 200 mW is a lot of
> power" is a pretty inane response.
> 
> Obviously.  Your point?
> 
> Peter's comment is perfectly accurate:  series terminations dissipate
> virtually no power in the series termination resistors.
> 
> As for my sarcasm, although sarcasm is known as the "weapon of the
> weak." it does serve a purpose to emphasize a point.  I reserve the
> right to be as entertaining as possible.
> 
> Thanks for the suggestion of turning the reference resistors off.  Not a
> bad idea at all.
> 
> Power estimation tools lag the rest of the tools.  Entering in the
> omissions on the hotline generates corrective action reports, which gets
> them fixed.  I will check to see where we are.
> 
> Austin

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 71374
Subject: Re: Clock generation
From: Allan Herriman <allan.herriman.hates.spam@ctam.com.au.invalid>
Date: Fri, 16 Jul 2004 13:04:57 +1000
Links: << >>  << T >>  << A >>
On Thu, 15 Jul 2004 15:09:12 -0400, "Vladislav Muravin"
<xfilex2003@hotmail.com> wrote:

>what is your refclk frequency?.

64B/66B coding is used in 10G Ethernet.  I guess this is what the OP
is using.
One would assume that the output frequency would be 644.53125MHz or
perhaps 161.1328MHz or so, so refclk would be 625 or 156.25MHz.

Jitter is really important for this sort of design.  I recommend that
the OP uses an external analog PLL to generate the clock.

Regards,
Allan.

>"Patrik Eriksson" <no.spam@netinsight.net> wrote in message
>news:40f69fd4$1@fnewsa.telia.net...
>> Hi,
>>
>> I would like to generate a clock from a refclk according to the
>> following function:
>>
>> clk = refclk*(64/66)
>>
>> I will implement this function in an VirtexII Pro FPGA and my first
>> approach is to divide the refclk by 3 in logic and then use a DCM to
>> multiply with 32/11.
>>
>> clk = refclk*(1/3)*(64/22)
>> clk = refclk/3*(32/11)
>>
>> Will this work? The frequencies has to be locked to each other.
>>
>>
>> ------
>> Patrik Eriksson
>>
>




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