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Messages from 72550

Article: 72550
Subject: Re: SSO and decoupling relationship
From: Austin Lesea <austin@xilinx.com>
Date: Tue, 24 Aug 2004 07:35:06 -0700
Links: << >>  << T >>  << A >>
JF

(aside:  why is it that all hypenated French names are now just two 
letters?  A result of Dallas (the old TV show)?"

Ground bounce is from the series inductance in the pcb, package, etc.

V=-L dI/dt

There is no "C" in the equation (capactance).

Please refer to out power app notes, and:

http://support.xilinx.com/xlnx/xweb/xil_tx_display.jsp?sGlobalNavPick=&sSecondaryNavPick=&category=&iLanguageID=1&multPartNum=1&sTechX_ID=al_vias

(sorry for the long URL)

Bypassing is another issue altogether.  The two are related, as a poor 
choice of bypass capacitors can create resonance effects with the series 
inductance.

Austin

jean-francois hasson wrote:
> Hi,
> 
> As I have asked in a previous post without any answer I ask it again : what
> is the relationship if any between SSO and the proper decoupling of an FPGA
> ? It seems there is one because the xilinx datasheet (the one I read)
> indicate a maximum sso provided decoupling is perfect.
> 
> Best regards,
> 
> JF
> 
> 

Article: 72551
Subject: Re: Maximum allowable ground bounce for xilinx fpgas
From: Austin Lesea <austin@xilinx.com>
Date: Tue, 24 Aug 2004 07:39:45 -0700
Links: << >>  << T >>  << A >>
JF,

It is not in the datasheet.

I was stating what our internal design guidelines are for simulating the 
performance of our circuits when exposed to the real noise that is 
likely to be present.

Information like this is presented in the power distribution system 
design applications notes, however.

Ca va?

Austin



jean-francois hasson wrote:

> Hi,
> 
> I read in a previous post the following by M. Lesea :
> 
> "All design (SSO tables, DCM operation, system jitter, etc) assumes that
> the ground bounce stays below +/- 100 mV peak to peak for proper
> operation."
> 
> Where is this information located in the datasheet ? 
> 
> Thanks,
> 
> JF

Article: 72552
Subject: Re: SSO and decoupling relationship
From: "John Retta" <jretta@rtc-inc.com>
Date: Tue, 24 Aug 2004 14:51:38 GMT
Links: << >>  << T >>  << A >>
One board level design technique for reducing adverse effects of SSO
is what Xilinx refers to as "virtual GND/VCC".  That is driving spare
outputs with 0 and tieing to GND plane, or 1 and tieing to VCC plane.

Check answer record 12692 at Xilinx site.

-- 
Regards,
John Retta
Owner and Designer
Retta Technical Consulting Inc.
Colorado based Xilinx consultant

email : jretta@rtc-inc.com
web :  www.rtc-inc.com


"Robert Sefton" <rsefton@abc.net> wrote in message
news:2ov16iFf02bfU1@uni-berlin.de...
> JF -
>
> From what I've read, board-level decoupling has a 2nd-order effect on
> controlling SSO noise. The problem really needs to be tackled inside the
> FPGA package, which is mostly out of your control. Use a device in a
> flip-chip package if you can. That said, proper board-level decoupling
does
> help (follow Xilinx's guidelines), and there are other things you can do.
> For example, picking pin assignments to spread the drivers out on the
> package (you can control this unless the board has already been fabbed).
And
> use the slowest drivers possible (not always an option). The board stackup
> and how the signals are routed are also important.
>
> As for the specific impact of decoupling and SSO noise, decoupling reduces
> the AC impedance (inductance dominates) between voltage and GND planes.
> Switching currents flow in a loop, and the lower the loop inductance the
> fewer SSO problems you'll have.
>
> Big topic, but there's a lot of information out there. Good luck.
>
> RJS
>
> "jean-francois hasson" <jfhasson@club-internet.fr> wrote in message
> news:412a3f03$0$306$7a628cd7@news.club-internet.fr...
> > Hi,
> >
> > As I have asked in a previous post without any answer I ask it again :
> what
> > is the relationship if any between SSO and the proper decoupling of an
> FPGA
> > ? It seems there is one because the xilinx datasheet (the one I read)
> > indicate a maximum sso provided decoupling is perfect.
> >
> > Best regards,
> >
> > JF
> >
> >
>
>



Article: 72553
Subject: Re: Xilinx in Linux
From: vve@xilinx.com
Date: Tue, 24 Aug 2004 16:13:05 +0100
Links: << >>  << T >>  << A >>


Hi Ted,

Answer record 12384

Vincent.

ted wrote:

> Hi,
>
> Does anyone know if it's possible to run the Xilinx ISE 4.2i software in
> Linux?  I would like to develop VHDL code and then program my FPGA (I use a
> parallel port JTAG programmer).  Being able to do this from Linux would make
> the project easier as I need to develop a Linux device driver at the same
> time.  I was thinking I could use WINE.  Do any websites with instructions
> exist?
>
> Thanks.




Article: 72554
Subject: Re: [Synthesis][VHDL] HowTo prevent Removal of Registers ...
From: vve@xilinx.com
Date: Tue, 24 Aug 2004 16:31:13 +0100
Links: << >>  << T >>  << A >>
Hi,

XST support the keep and keep_hierarchy constraint, you will find them
in the constraint guide. You can also use the save_net_flag (S)
constraint to prevent the synthesis tool to remove your second register.

Vincent.

Markus Meng wrote:

> Hi all,
>
> in order to comply with the timing requirements,
> I did explicitly replicate an output register.
>
> -- Code Snip Below
>
>     I2 : a_reg
>         generic map (
>             n => 20
>         )
>         port map (
>             clk  => clk,
>             din  => addro_i,
>             rst  => rst,
>             dout => addr_a_out);
>
>     I3 : a_reg
>         generic map (
>             n => 20
>         )
>         port map (
>             clk  => clk,
>             din  => addro_i,
>             rst  => rst,
>             dout => addr_b_out);
>
> Register instances are sourced from the very same signal.
> However synthesis tries to be 'clever' and removes one
> register instance, making it impossible to have them in the
> IOB section. Any advice how I can avoid this removal without
> going 'to-deep' and instantiate IOB-Register Primitives as
> 'Black-Box-Instances'.
>
> Thank's
>
> Markus


Article: 72555
Subject: Re: Xilinx in Linux
From: "B. Joshua Rosen" <bjrosen@polybus.com>
Date: Tue, 24 Aug 2004 11:31:25 -0400
Links: << >>  << T >>  << A >>
On Tue, 24 Aug 2004 15:15:53 +0100, ted wrote:

> Hi,
> 
> Does anyone know if it's possible to run the Xilinx ISE 4.2i software in
> Linux?  I would like to develop VHDL code and then program my FPGA (I use a
> parallel port JTAG programmer).  Being able to do this from Linux would make
> the project easier as I need to develop a Linux device driver at the same
> time.  I was thinking I could use WINE.  Do any websites with instructions
> exist?
> 
> Thanks.

The current Xilinx tools are Linux native. I you don't have them then see
my old Xilinx on Linux page for instructions on running the 4.2 tools
under wine,

http://www.polybus.com/xilinx_on_linux.html

Article: 72556
Subject: Re: Edk BMM file problem in ISE
From: vve@xilinx.com
Date: Tue, 24 Aug 2004 16:36:16 +0100
Links: << >>  << T >>  << A >>
Hi Stephane,

this error occurs because the tool is looking for the *.ngc (or *.ngo I
can't remember) file and can't find it. Either you don't have it or it
is in the wrong location.

I hope this help.

Vincent.

Stephane Julhes wrote:

> Hello,
>
> I have developped a System on chip with the EDk tool.
>
> I'm developping a V2P with ISE in with I have to use my SOC.
>
> I have linked the EDK project in my main ISE project and I can make
> changes to it.
>
> Under ISE I am able to launch top level simulations in modelsim, in
> order to validate some PPC test routines written in C.
> It works fine.
>
> Synthesis of the ISE project works too.
>
> But when I launch implementation in ISE, the ngdbuild step makes :
> - readings of design
> - checks timing specification
>
> And then it starts processing bmm file, in which I get errors :
> ERROR:NgdBuild:704 - The BRAM instance
> 'socinst/bram/bram/ramb16_s1_s1_0' could not be found in the netlist.
> Please verify the instance name in the BMM file and the netlist.
>
> I get 64 of them, as my Bram is made of 64 ramb16_s1_s1.
>
> I've turned the problem in every way an I can't get the solution.
>
> If someone has information to solve this problem.
>
> Thank you.
>
> Stephane.


Article: 72557
Subject: Re: Xilinx Spartan3 DCM Procedure
From: vve@xilinx.com
Date: Tue, 24 Aug 2004 16:54:19 +0100
Links: << >>  << T >>  << A >>
Hi,

The vhdl file is just a wrapper file, so your DCM hasn't been implemented. You
have to attach the XAW file to your project. Coregen or the architecture wizard
give you a netlist and not an open VHDL source code most of the time.

Vincent.

Brad Smallridge wrote:

> Not sure what to do here.  I ran the wizard for a Single DCM which generated
> a XAW file.  Although this is a "New Source" it doesn't act like one. One
> can generate VHDL code from this XAW file which I did.  I then tried to add
> the VHDL code as a source and got an error message.  Something about a
> conflict between the two files.  So I deleted the XAW file and now the VHDL
> file, by itself, seems to work, that is, it will synthesize and download.  I
> haven't been able to verify the clock outputs yet. Is the XAW file suppose
> to be part of the project source?


Article: 72558
Subject: FPGA SPARTAN 3 or 2 BOARD SCHEMATIC protel
From: videoremote1@yahoo.com (bob)
Date: 24 Aug 2004 13:56:25 -0700
Links: << >>  << T >>  << A >>
Dear FPGA,

I am looking to find a schematic with FPGA SPARTAN 2 OR 3 
with 256 pin in Protel format 
Thank you in advance,

Bob

E-MAIL : VIDEOREMOTE1@YAHOO.COM

Article: 72559
Subject: Re: Altera MAX II
From: lotruong@yahoo.com (Chris)
Date: 24 Aug 2004 14:01:51 -0700
Links: << >>  << T >>  << A >>
I believe what Altera is trying to say is if you compare the biggest Max CPLD,
512 MCs, with the biggest Max II EPM2210, 1700 MCs, you will get four times
the density and will only cost half the price.

Chris


oen_no_spam@yahoo.com.br (Luiz Carlos) wrote in message news:<3fd8f66b.0408240222.5e6a8b95@posting.google.com>...
> Hi Altera folks,
> 
> What does mean "Four times the density at half the price (compared to
> previous-generation MAX devices)" ?
> 
> For example, the EPM570 that has 440 "Typical Equivalent Macrocells".
> 440/4=110
> Does it means it will priced at half the price of the 128 macrocell
> MAX?
> 
> Why not, eight times the density at same price? Or just, one eighth
> the price?
> 
> Just curious!
> 
> Luiz Carlos

Article: 72560
Subject: Re: DDR SDRAM
From: Marcus Harnisch <marcus.harnisch@gmx.net>
Date: Tue, 24 Aug 2004 23:03:30 +0200
Links: << >>  << T >>  << A >>
ALuPin@web.de (ALuPin) writes:
> My question:
> Why do the addresses on the local interface "local_col_addr" 
> "020","021","022","023","030","031","032","033" 
> turn to the memory addresses
> "0040","0042","0044","0046","0060","0062","0064","0066" on the DDR
> SDRAM Interface ?
>
> It is said later in the User Guide that the controller runs the DQ
> port to the DDR devices at one half the width and twice the rate of
> the DATAIN port (input data at the local interface of the
> controller).
>
> But how are the coherence with the shown example addresses?

Because the internal interface has a data width of sixteen bit while
the the SDRAM interface is only eight bits wide...

--Marcus

Article: 72561
Subject: Re: Edk BMM file problem in ISE
From: Matthew E Rosenthal <mer2@andrew.cmu.edu>
Date: Tue, 24 Aug 2004 17:05:57 -0400 (EDT)
Links: << >>  << T >>  << A >>
I had this exact same error.
My problem was that in the synthesis properties dialoge box under "keep 
hierarchy" it was set to no.  This has to be set to yes or soft.

Matt

On Tue, 24 Aug 2004 vve@xilinx.com wrote:

> Hi Stephane,
>
> this error occurs because the tool is looking for the *.ngc (or *.ngo I
> can't remember) file and can't find it. Either you don't have it or it
> is in the wrong location.
>
> I hope this help.
>
> Vincent.
>
> Stephane Julhes wrote:
>
>> Hello,
>>
>> I have developped a System on chip with the EDk tool.
>>
>> I'm developping a V2P with ISE in with I have to use my SOC.
>>
>> I have linked the EDK project in my main ISE project and I can make
>> changes to it.
>>
>> Under ISE I am able to launch top level simulations in modelsim, in
>> order to validate some PPC test routines written in C.
>> It works fine.
>>
>> Synthesis of the ISE project works too.
>>
>> But when I launch implementation in ISE, the ngdbuild step makes :
>> - readings of design
>> - checks timing specification
>>
>> And then it starts processing bmm file, in which I get errors :
>> ERROR:NgdBuild:704 - The BRAM instance
>> 'socinst/bram/bram/ramb16_s1_s1_0' could not be found in the netlist.
>> Please verify the instance name in the BMM file and the netlist.
>>
>> I get 64 of them, as my Bram is made of 64 ramb16_s1_s1.
>>
>> I've turned the problem in every way an I can't get the solution.
>>
>> If someone has information to solve this problem.
>>
>> Thank you.
>>
>> Stephane.
>
>

Article: 72562
Subject: Re: XC2V250 protoboard
From: dxslyz@lycos.de (Steven)
Date: 24 Aug 2004 14:15:06 -0700
Links: << >>  << T >>  << A >>
> If you can get JBits to work with V2Pro, there's a cheap
> xc2vp4-board from Memec/Insight for $199. 

Can you please post the link to this board, or the name of it ? I can
not find it.  And how long does it take to deliever ? I am in germany
too.


Thanks

Steven Yu

Article: 72563
Subject: Any experience with Actel Flash-FPGAs ?
From: SG <gupt@hotmail.com.NOSPAM>
Date: 24 Aug 2004 15:35:19 -0700
Links: << >>  << T >>  << A >>

Hi all

I am evaluating the Actel ProAsic Flash-based FPGAs and am wondering
if anyone has experience using them.  The claim from Actel is that
they have new products in 0.13u that are smaller in area than
comparative Xilinx/Altera products (Spartan/Cyclone) and offer better
performance.  They claim this is because instead of using 6 SRAM
transistors for the configuration memory, the Actel Pro-Asic 3s use 1
Flash transistor.  This reduces die are for the same number of logic
elements/gates and increases performance due to shorter wires in the
die.

Any experiences with the Pro-Asic line ?  Even better, has anyone used
the new 0.13u FPGAs (engineering samples or something or maybe just
using tools) ?

Thanks
Sumit

Article: 72564
Subject: Re: Altera MAX II
From: Jim Granville <no.spam@designtools.co.nz>
Date: Wed, 25 Aug 2004 10:37:05 +1200
Links: << >>  << T >>  << A >>
Luiz Carlos wrote:
> Hi Altera folks,
> 
> What does mean "Four times the density at half the price (compared to
> previous-generation MAX devices)" ?
> 
> For example, the EPM570 that has 440 "Typical Equivalent Macrocells".
> 440/4=110
> Does it means it will priced at half the price of the 128 macrocell
> MAX?
> 
> Why not, eight times the density at same price? Or just, one eighth
> the price?

  This is market-speak. It is not intended to convey accurate 
information, but is considered successful if the reader thinks the 
information is there.
  Missing from "at half the price" is a key "per resource unit", but if
someone (miss) reads this to think their devices are one eighth the 
price, and rushes off to design them in, that would be called
'successful promotion'.....
-jg

PS Also missing from this spin, is the fact that the cheapest 
previous-generation MAX devices, are actually cheaper than the
cheapest MAX II devices.
  ie the price per resource unit has declined, but the
minimum unit-cost step has actually increased, because they
pruned the two smallest offerings.


Article: 72565
Subject: Re: DSP/FPGA/video board?
From: soar2morrow@yahoo.com (Tom Seim)
Date: 24 Aug 2004 15:39:40 -0700
Links: << >>  << T >>  << A >>
"Georgi Beloev" <gbH8SPAM@beloev.net> wrote in message news:<SYydnTMglL5u-7fcRVn-gw@megapath.net>...
> Hi,
> 
> I'm looking for an inexpensive (up to $1000) development board with the
> following features:
> 
> - Relatively fast DSP, e.g., Blackfin.
> - Mid-range Cyclone II or Spartan-3 FPGA.
> - At least 4 MB SDRAM.
> - Video in (CVBS and Y/C), digital video decoder.
> - Video out (CVBS and Y/C),  digital video encoder.
> - The video decoder and encoder should be able to work simultaneously.
> 
> A combination of boards, e.g., a DSP kit and a plug-in FPGA board can also
> work. Other DSPs and FPGAs than the ones mentioned above can also be
> considered. This is for doing research on video processing and video
> compression; I don't have more precise requirements yet.

You could combine a Spartan-3 board from Digilent ($89) with ADI
ADSP-2199XX EZ-KITE Lite ($595).

Article: 72566
Subject: IP Coregen: FFT v2.1 IP core regd.
From: ping_anand@yahoo.com (anand)
Date: 24 Aug 2004 17:40:54 -0700
Links: << >>  << T >>  << A >>
Hi,

In my design, I am using the FFT v2.1 IP core thats available in the
IP Core generator that comes along with Xilinx ISE 6.2. I want to use
the scaling option (SCALE_SCH). I dont know how to derive the scaling
schedule. I am configuring the IP core to do 64 point FFT with 8-bit
inputs.

Any pointers or suggestions is highly appreciated.

Thanks.

Sincerely,
Anand

Article: 72567
Subject: XST 5 input mux synthesis question
From: Matthew E Rosenthal <mer2@andrew.cmu.edu>
Date: Tue, 24 Aug 2004 20:51:29 -0400 (EDT)
Links: << >>  << T >>  << A >>
Hi all,
2 questions.
I am designing a 5 input mux with the following verilog

assign muxOut = (selectA) ? inputA :
 		(selectB) ? inputB :
 		(selectC) ? inputC :
 		(selectD) ? inputD : E;

will xilinx know to put a 5 input mux there?
How do i know if it did?

If I know that E is the latest arriving input is there a way to insure 
that XST puts it in the fastest path of the mux?
Is there a fastest path in a 5 input mux?

Thanks

Matt


Article: 72568
Subject: Re: XST 5 input mux synthesis question(s)
From: Matthew E Rosenthal <mer2@andrew.cmu.edu>
Date: Tue, 24 Aug 2004 20:52:11 -0400 (EDT)
Links: << >>  << T >>  << A >>
I guess that was more than 2 questions...

On Tue, 24 Aug 2004, Matthew E Rosenthal wrote:

> Hi all,
> 2 questions.
> I am designing a 5 input mux with the following verilog
>
> assign muxOut = (selectA) ? inputA :
> 		(selectB) ? inputB :
> 		(selectC) ? inputC :
> 		(selectD) ? inputD : E;
>
> will xilinx know to put a 5 input mux there?
> How do i know if it did?
>
> If I know that E is the latest arriving input is there a way to insure that 
> XST puts it in the fastest path of the mux?
> Is there a fastest path in a 5 input mux?
>
> Thanks
>
> Matt
>
>

Article: 72569
Subject: Xilinx version ROM with automatic increment
From: "Håkon L" <agurk.haklis@hotmail.com>
Date: Wed, 25 Aug 2004 08:55:20 +0200
Links: << >>  << T >>  << A >>
Hi,
I have usually included a version register in my FPGA designs, but I have to
change/increment it manually in the VHDL code.

Does anybody have an idea for how one can make an auto-incrementing version
ROM which increments with each new routing?
What is the most easy way to manipulate the ROM? Can I manipulate the .bit
file? Run CoreGen automatically?

Regards
Håkon Lislebø



Article: 72570
Subject: Re: DDR SDRAM
From: ALuPin@web.de (ALuPin)
Date: 25 Aug 2004 00:33:06 -0700
Links: << >>  << T >>  << A >>
Marcus Harnisch <marcus.harnisch@gmx.net> wrote in message news:<86k6vow8nx.fsf@dipsy.harnisch.local>...
> ALuPin@web.de (ALuPin) writes:
> > My question:
> > Why do the addresses on the local interface "local_col_addr" 
> > "020","021","022","023","030","031","032","033" 
> > turn to the memory addresses
> > "0040","0042","0044","0046","0060","0062","0064","0066" on the DDR
> > SDRAM Interface ?
> >
> > It is said later in the User Guide that the controller runs the DQ
> > port to the DDR devices at one half the width and twice the rate of
> > the DATAIN port (input data at the local interface of the
> > controller).
> >
> > But how are the coherence with the shown example addresses?
> 
> Because the internal interface has a data width of sixteen bit while
> the the SDRAM interface is only eight bits wide...
> 
> --Marcus

But if it is 8bit wide why is 020 used and not 20 ?
And what about that DQ port to the DDR device is one half the width ?

Rgds
Andre

Article: 72571
Subject: Re: Xilinx version ROM with automatic increment
From: "Pfna" <not_valid@bogus_mail_address.com>
Date: Wed, 25 Aug 2004 09:52:42 +0200
Links: << >>  << T >>  << A >>

"Håkon L" <agurk.haklis@hotmail.com> wrote in message
news:cghcv9$r1v$1@newstree.wise.edt.ericsson.se...
> Hi,
> I have usually included a version register in my FPGA designs, but I have
to
> change/increment it manually in the VHDL code.
>
> Does anybody have an idea for how one can make an auto-incrementing
version
> ROM which increments with each new routing?
> What is the most easy way to manipulate the ROM? Can I manipulate the .bit
> file? Run CoreGen automatically?
>
> Regards
> Håkon Lislebø
>
>

Hi

You could investigate if you can use the Xilinx utility "Data2BRAM". It
changes the bitfile to manipulate data in the BRAMs.

/Pfna



Article: 72572
Subject: Re: Xilinx version ROM with automatic increment
From: "Guy Eschemann" <guy.eschemann@t-online.de>
Date: 25 Aug 2004 01:12:34 -0700
Links: << >>  << T >>  << A >>

You could try to locate the init value for this register in the bit
file, and then use a PERL or whatever script to automatically increment
it after each P&R iteration. I'm not familiar with the details of
Xilinx bitstreams, but I guess you'll have to also update some kind of
CRC after doing this.

Another suggestion would be the USERCODE register ; its value can be
set with the bitgen -userid option, and read out via JTAG.

If you have an external PROM, you may have a look at XAPP694 (Reading
User Data from Configuration PROMs).

Have fun,
Guy.

H=E5kon L wrote:
> Hi,
> I have usually included a version register in my FPGA designs, but I
have to
> change/increment it manually in the VHDL code.
>
> Does anybody have an idea for how one can make an auto-incrementing
version
> ROM which increments with each new routing?
> What is the most easy way to manipulate the ROM? Can I manipulate the
.bit
> file? Run CoreGen automatically?
>=20
> Regards
> H=E5kon Lisleb=F8


Article: 72573
Subject: Configuration : Virtex-E, CLB column
From: "Cyrille Lambert" <eepgcrl@brunel.ac.uk>
Date: Wed, 25 Aug 2004 02:30:27 -0700
Links: << >>  << T >>  << A >>
Dear all, 

Subject: Virtex-E, CLB column. 

Inside a Xilinx Virtex-E FPGA, 5 types of column are present (Centre, 
CLB, Block SelectRAM Interconnect, Block SelectRAM Content, Right-Left 
IOB Columns). Let's take in account the CLB column. Each CLB column 
contains 2 Top IOB blocks, 2 Bottom IOB blocks and a certain number 
of "CLB" blocks. Each "CLB" block contains the information about the 
CLB by itself (Configuration), the routing (SB and CB). 

Firstly, is it correct. And secondly, how are organized these 
information in a frame or better in a "CLB" block. 

Best regards, 
/Cyrille Lambert 



Article: 72574
Subject: Re: XC2V250 protoboard
From: gerd?NO?SPAM@rzaix530.rz.uni-leipzig.de (Gerd)
Date: 25 Aug 2004 11:15:56 GMT
Links: << >>  << T >>  << A >>
Steven <dxslyz@lycos.de> wrote:
> > If you can get JBits to work with V2Pro, there's a cheap
> > xc2vp4-board from Memec/Insight for $199. 

> Can you please post the link to this board, or the name of it ? I can
> not find it.  And how long does it take to deliever ? I am in germany
> too.

I'm not in the office where the board is (not even in Germany ;) ),
but if I remember correctly, the name is DS-KIT-2VP4-LC(-EU). You
can also check the Xilinx website,
  products / development boards / virtex2pro,
it should be listed there.


regards,
-g

-- 
In crustulum beatitas.



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