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Hello All, I have 3 burning, if fundamental questions about FPGA architecture. 1) When the term routing is used, does it include the switch block multiplexers and the interconnections (Long wires, short wires etc.)? 2) When packing it done well, can I say that LUTs are packed close to each other so the amount of routing resources used is less? 3) For Altera FPGAs (eg. Stratix versions), how are the LUTs implemented? For Xilinx, its generally distributed RAM. For Altera which only uses coarse-grain memory, this can't be the case so what is the alternative? tEdArticle: 73226
Hi I've the some problem. In my project the hardware clock connect to DCM was incorrect generate. It think the skew on input clock was bad. 1) Try redesign clock generator for this board. 2) use atrribute for DCM LOCK it give you stable clock. But if you have input clock with too much skew the Lock couldn't be set. The output clock isn't be generate in this case. WZ Użytkownik "Niv" <niv.nospam.goaway@ntlworld.com> napisał w wiadomości news:V3%1d.124$QF4.27@newsfe2-win.ntli.net... > Hi out there; > I'm generating 49.152 MHz from 40MHz osc using 2 DCMs > first does 24/25 & second does 32/25. > > This generally works, but sometimes doesn't! > > I've not used the DCMs' clkfb input as only one clock is used in > the whole FPGA, the 49.152. The clkfb of both is tied to gnd. > > Should I feed the DCM 1 o/p back to its clkfb & similarly > for DCM 2, or what exactly? Will this give better functionality? > > Any commentsd please > > TIA Niv. > >Article: 73227
Hi Gary, We have designed a test-bed with an Altera cyclone to test and upload configuration files to epcs4 of a minipci product. We have developed code to upload .rbf files directly to the epcs4 of the device under test. The flash time for a full epcs4 is around 3 seconds. If this development serves your purpose, we can make it available against a certain royalty payment. Another possibilty is to obtain the "byte jammer" software from Altera, it flashes the epcs via the JTAG chain... best regards ron "Gary Pace" <xxx@yyy.com> schreef in bericht news:Zz62d.1762$Gz.1605@fe2.texas.rr.com... > We have a number of PCB's with Altera Cyclone/Config device systems. > > In R&D we use Quartus to program this. > > For production, we have a bed of nails based ATE system, using LabView. > > We want to program the config. device automatically. > > Has anyone done this ? > > Does Altera produce a .dll or .ocx version of the programming tools ? > Can the programmer be run as a WIN32 console app. (ie from the command line) > ? > Does National Instruments (or a third party) have anything ? > > Any advice much appreciated, > > Gary > >Article: 73228
Looks like Simprim libraries are missing which includes components like x_lut2, x_ff etc. Post Ngdbuild or post PAR back annotated simulation files have these libraries included. Unisim libraries are behavioral models while Simprim libraries are gate level models. Did you compile these libraries? This answer record will guide you on doing backannotated simulations. http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=10177 Regards Vikram Sridhar Hegde wrote: > Hi, > > I am designing a simple ROM in VHDL and following is the code for > it.Xilinx ISE 6.2i doesn't seem to have any issues synthesizing the > design to a Virtex 2 chip(xc2v4000) or translating/mapping/routing the > design(Implementation process). > > When I use the test bench created by HDL bencher to see the results, > in Modelsim, a behavioral simulation shows be proper results but a > post translate simulation or anything beyond that like a Post Map or a > Post place and route simulation show a U on all output pins and > Modelsim gives me a number of warnings about "Unbound components" > shown below.. > > Im stuck at this design phase and would appreciate any help from the > VHDL gurus out there...Heres the code:- > > ----------------------------------------------------------------------- > > library IEEE; > use IEEE.STD_LOGIC_1164.ALL; > use IEEE.STD_LOGIC_ARITH.ALL; > -- Uncomment the following lines to use the declarations that are > -- provided for instantiating Xilinx primitive components. > --library UNISIM; > --use UNISIM.VComponents.all; > > entity inrom is > Port ( en : in std_logic; > clk : in std_logic; > dout : out std_logic_vector( 15 downto 0); > valid : out std_logic; --valid data is present on output when 1 > reset : in std_logic > ); > end inrom; > > architecture rtl of inrom is > > type array_rom is array (15 downto 0) of std_logic_vector( 15 downto > 0); > signal myarray : array_rom; > signal valid_sig:std_logic; > signal dout_sig : std_logic_vector(15 downto 0); > signal clk2: std_logic; > > begin > > myarray(0) <= x"0000"; > myarray(1) <= x"0000"; > myarray(2) <= x"0000"; > myarray(3) <= x"003C"; > myarray(4) <= x"0000"; > myarray(5) <= x"0000"; > myarray(6) <= x"0064"; > myarray(7) <= x"0000"; > myarray(8) <= x"0000"; > myarray(9) <= x"000A"; > myarray(10) <= x"0000"; > myarray(11) <= x"0000"; > myarray(12) <= x"003C"; > myarray(13) <= x"0000"; > myarray(14) <= x"0000"; > myarray(15) <= x"0064"; > > process( reset,clk) > variable romvar:natural range 0 to 15; > > begin > if reset = '1' then > dout_sig <= (others=>'0'); > valid_sig <='0'; > romvar :=0; > > elsif (clk'event and clk='1') then > if en='1' then > dout_sig <= myarray (romvar); > valid_sig<='1'; > romvar :=romvar + 1; > else > dout_sig <= myarray (romvar); > valid_sig<='0'; > end if; > end if; > end process; > > dout <= dout_sig; > valid <=valid_sig; > end rtl; > ------------------------------------------------------------------------- > Warnings given by Modelsim: > > do inromtbw.ndo > # ** Warning: (vlib-34) Library already exists at "work". > ###### inrom_translate.vhd(443): ); > # WARNING[1]: inrom_translate.vhd(443): No default binding for > component: "x_mux2". (No entity named "x_mux2" was found) > ###### inrom_translate.vhd(455): ); > # WARNING[1]: inrom_translate.vhd(455): No default binding for > component: "x_ff". (No entity named "x_ff" was found) > ###### inrom_translate.vhd(468): ); > # WARNING[1]: inrom_translate.vhd(468): No default binding for > component: "x_xor2". (No entity named "x_xor2" was found) > ###### inrom_translate.vhd(472): ); > # WARNING[1]: inrom_translate.vhd(472): No default binding for > component: "x_zero". (No entity named "x_zero" was found) > ###### inrom_translate.vhd(476): ); > # WARNING[1]: inrom_translate.vhd(476): No default binding for > component: "x_one". (No entity named "x_one" was found) > ###### inrom_translate.vhd(714): ); > # WARNING[1]: inrom_translate.vhd(714): No default binding for > component: "x_lut2". (No entity named "x_lut2" was found) > ###### inrom_translate.vhd(2994): ); > # WARNING[1]: inrom_translate.vhd(2994): No default binding for > component: "x_lut3". (No entity named "x_lut3" was found) > ###### inrom_translate.vhd(3128): ); > # WARNING[1]: inrom_translate.vhd(3128): No default binding for > component: "x_lut4". (No entity named "x_lut4" was found) > ###### inrom_translate.vhd(3203): ); > # WARNING[1]: inrom_translate.vhd(3203): No default binding for > component: "x_or2". (No entity named "x_or2" was found) > ###### inrom_translate.vhd(3341): ); > # WARNING[1]: inrom_translate.vhd(3341): No default binding for > component: "x_tri". (No entity named "x_tri" was found) > ###### inrom_translate.vhd(3450): ); > # WARNING[1]: inrom_translate.vhd(3450): No default binding for > component: "x_inv". (No entity named "x_inv" was found) > ###### inrom_translate.vhd(3533): port map (O => GSR); > # WARNING[1]: inrom_translate.vhd(3533): No default binding for > component: "x_roc". (No entity named "x_roc" was found) > ###### inrom_translate.vhd(3535): port map (O => GTS); > # WARNING[1]: inrom_translate.vhd(3535): No default binding for > component: "x_toc". (No entity named "x_toc" was found) > # vsim -lib work -t 1ps inromtbw > # Loading C:/Modeltech_5.7g/win32/../std.standard > # Loading C:/Modeltech_5.7g/win32/../ieee.std_logic_1164(body) > # Loading C:/Modeltech_5.7g/win32/../ieee.std_logic_arith(body) > # Loading C:/Modeltech_5.7g/win32/../std.textio(body) > # Loading C:/Modeltech_5.7g/win32/../ieee.std_logic_textio(body) > # Loading C:/Modeltech_5.7g/win32/../vital2000.vital_timing(body) > # Loading C:\Xilinx6\vhdl\mti_se\simprim.vcomponents > # Loading C:/Modeltech_5.7g/win32/../vital2000.vital_primitives(body) > # Loading C:\Xilinx6\vhdl\mti_se\simprim.vpackage(body) > # Loading work.inromtbw(testbench_arch) > # Loading work.inrom(structure) > # ** Warning: (vsim-3473) Component 'romvar_madd_n0000_inst_cy_5_0' is > not bound. > # Time: 0 ps Iteration: 0 Region: /inromtbw/uut File: > inrom_translate.vhd > # ** Warning: (vsim-3473) Component 'valid_sig_1' is not bound. > # Time: 0 ps Iteration: 0 Region: /inromtbw/uut File: > inrom_translate.vhd > # ** Warning: (vsim-3473) Component 'mmux_n0001_inst_mux_f5_130' is > not bound. > > I can not use a Core generated ROM for this design due to some > restrictions I have in my other codes..Sorry for a rather long mail > and thanks in advance for any help!!Article: 73229
I'll try to put some light here! The problem arises from using the same name for different things. a) Semiconductor CHIPS: FPGAs, CPUs, DSPs, ..., are hardware. Try to eat them and you will understand. But please, don't sue me for your broken teeth. b) Potato CHIPS: software, of course! c) Rest: Well, the rest is ..., restware. Easy, isn't it? PS.: Don't forget CHiPs, California Highway Patrol. If someone remember! Luiz Carlos.Article: 73230
Hello: Anybody knows any prototype board with a Xilinx Virtex II FPGA and a CAN bus controller? RegardsArticle: 73231
Jim Granville wrote: > u722534179@spawnkill.ip-mobilphone.net wrote: > >> I'm using EPM7128S now.Some of the outputs connect to a Darlington >> array which controls some relays. >> So I want to know the exact state of these outputs during the >> Power-up.But the datasheet of max7000s doesnt mention it. Somebody >> tell me the voltage of I/Os is uncertain before the POR completed.Then >> how can I control them before the device running properly? > > > PLDs have internal Power On resets, > IIRC Atmel specify ~3.8V POR release on 5V parts. > (Altera should will be similar). IMO, before the initialization, the pins are inputs in high impedance state. This is especially important because there is a time before the chip is programmed. And it can also be that it takes a few development cycles until the prototype is programmed correctly. Make sure the external hardware is not fried before that. As Jim said, an EEPROM based CPLD such as the EPM7128S is rather quick in booting, once it is programmed. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.netArticle: 73232
greg wrote: > Hello > I'm nev on this group and have following problem. > I need to program EPM7064SLC44 using JTAG cable (ByteBlasterII) and Quartus > 4.1 and it doesn't work > Auto detection does not work either. When i connect EPM7128SLC84 all works, > so cable and software is OK. > I tried different chips (EPM7064SLC44 ones with different speed grades) and > all don't work. > i connected scope and TDI,TMS and TCK signals seems to be ok, but there is > no TDO signal... > Does anybody had similar problem? > maybe there is something wrong with quartus? > I used altera 7000 series chips and never had any problems (but never used > 7064 one) You have the required pullups and pulldowns ? 1k up for TMS, TDI and TDO and 1k down for TCK. Plus there is whealth of pins that require a fixed connection. Documented in the *.RPT file as ASCII. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.netArticle: 73233
Hi FPGA folks, I am trying to get started with the Twister+Lancelot evaluation board. Has somebody played with that boards? I'd like to have some reference so that I could ask questions. Thank you for your help. Best regardsArticle: 73234
Recovery time is the period of time following a clock that an asynchronous input must remain stable. It is similar to hold time, but for async inputs. This warning looks like it came from a flip flop model that is telling you that its asynchronous CLR pin wiggled too soon after the rising edge of CLK for the flip flop to operate properly. Chris "Naimesh" <naimesh.thakkar@gmail.com> wrote in message news:<ci9h45$9dn@odak26.prod.google.com>... > Hello > > I am getting following warning during simulation in ModelSim > > > * Warning: *DFE3C RECOVERY High VIOLATION ON CLR WITH RESPECT TO CLK; > # Expected := 1 ns; Observed := 0 ns; At : 61005 ns > # Time: 61005 ns Iteration: 1 > > Can any one tell what is RECOVERY High VIOLATION. > Thank for any help > > NaimeshArticle: 73235
Dear all: My user reset is connect to all DFF. due to Fan Out limit, XST duplicated several reset signal and cause some output DFFs can not place into IOB. how to do, set a higher fan out value, or drive user reset with BUFG, or any other way? Regards, SeyiorArticle: 73236
"ALuPin" <ALuPin@web.de> wrote in message news:b8a9a7b0.0409160400.35fb5d1e@posting.google.com... > Hi FPGA folks, > > I am trying to get started with the Twister+Lancelot evaluation board. > > Has somebody played with that boards? > I'd like to have some reference so that I could ask questions. > I've got a Lancelot connected to my Nios (Cyclone) development kit board. It works fine, although I ended up writing my own vga firmware which is a lot nicer (IMHO, of course :-) than the original demo code that came with the board (my code is vaguely based on newer Nios II application notes and examples). The hardware is not worth copying either, since the video dac on the card is now considered obselete by TI. However, the board does exactly what it says on the tin - it is an example card with example code to get you started, and worked fine for me in that sense. Somebody started a mailing list for the Lancelot, but apart from a few initial posts, it's been dead quiet. I can't even remember its address offhand, although I'm sure a google groups search would reveal it.Article: 73237
I'm using EPM7128SLC84 now. Since some of the outputs is connected to Darlington arrays controling relays. So I want to know the exact state of these I/Os before power on reset(POR) complete. Also,if the I/O voltage is uncertain ,how can I control it? What should I do? -- Sent by lance.work from gmail subpart from com This is a spam protected message. Please answer with reference header. Posted via http://www.usenet-replayer.comArticle: 73238
Hello all, Does anyone know where I can find documentation on the text output format of the xdl tool (which I believe is what Xilinx calls the Xilinx Design Language)? I have looked on the Xilinx website and on the web, and not found anything useful. Any pointers will be greatly appreciated. Thanks, MahimArticle: 73239
Hi - On 16 Sep 2004 07:35:18 -0700, mahim_usenet@yahoo.com (Mahim Mishra) wrote: >Hello all, > >Does anyone know where I can find documentation on the text output >format of the xdl tool (which I believe is what Xilinx calls the >Xilinx Design Language)? I have looked on the Xilinx website and on >the web, and not found anything useful. Any pointers will be greatly >appreciated. > >Thanks, >Mahim The documentation is part of the install. Look for xdl.html in <xilinx install directory>\help\data\hdl. Bob Perlman Cambrian Design WorksArticle: 73240
"David Brown" <david@no.westcontrol.spam.com> schreef in bericht news:cic2p4$gct$1@news.netpower.no... > > "ALuPin" <ALuPin@web.de> wrote in message > news:b8a9a7b0.0409160400.35fb5d1e@posting.google.com... > > Hi FPGA folks, > > > > I am trying to get started with the Twister+Lancelot evaluation board. > > > > Has somebody played with that boards? > > I'd like to have some reference so that I could ask questions. > > > > I've got a Lancelot connected to my Nios (Cyclone) development kit board. > It works fine, although I ended up writing my own vga firmware which is a > lot nicer (IMHO, of course :-) than the original demo code that came with > the board (my code is vaguely based on newer Nios II application notes and > examples). The hardware is not worth copying either, since the video dac on > the card is now considered obselete by TI. However, the board does exactly > what it says on the tin - it is an example card with example code to get you > started, and worked fine for me in that sense. > > Somebody started a mailing list for the Lancelot, but apart from a few > initial posts, it's been dead quiet. I can't even remember its address > offhand, although I'm sure a google groups search would reveal it. > I happen to know the designer of both boards, when he showed me the Lancelot I was quite impressed with power of dedicated Nios instructions and hardware acceleration for the Mandelbrot demo ;) JeroenArticle: 73241
I need to program a digital PLL in a CPLD. I tryed to use an external Clock Generator @ 24.576 MHZ, but the data signal is not exactly that frequency. So can anyone help me with that problem ???Article: 73242
Your problem may be simpler than you imagine. If you need a result at *every* clock and start from an empty array, you can insert the new values one at a time until you have the 32-bit population, then begin the removal and replacement. If you have 31 comparators for the new value (you can ignore the 24th), your results will look like a thermometer when comparing the new value to the pre-ordered array. The elements 1-23 can shift up 0 or 1 depending on the local comparison bit. The elements 25 to 32 can shift down by 0 or 1 based on the same results. The one caveat is that the initial values before bringing in the first set of 32 numbers need to shift completely off one end with an out-of-range number rather than shifting out position 24. If you want a full sort of 32 unsorted values, I can give you a technique - the bitonic sort - to perform the sort in 15 clock cycles; it's one of the fastest ways to do a full sort but requires time and resources. The one-at-a-time method I outlined above would give you better results. "Kumar Vijay Mishra" <vizziee@yahoo.com> wrote in message news:889cd7c9.0409152205.35aeb3c@posting.google.com... > Hi. > > I am working on inmplementation of order statistics CFAR, where > sorting of a continuous stream of data is required. > > Exactly problem is as under: > I am getting a continuous stream of 16-bit data. In every clock cyle I > have to sort 32-size array. When I have sorted the array in ascending > order, I want to choose 24th number only. In the next clock cycle, I > get a new no added to my array while the first number gets out of the > array. The new array that I get is to be sorted again and he 24th > position number is to be taken out. > So, in every clock cycle, I get a new data (in an array of 32 16-bit > numbers) (with the oldest data getting deleted from this array) and in > the same clock cycle, I need to have the 24th-position data available > to me for further processing. > > Can anybody help me in this? Plus if someone can direct me to any > useful link on VHDL designs of sorting, since I am new to FPGA and > VHDL. > > Thanx in advance.Article: 73243
Ted wrote: > > Hello All, > > I have 3 burning, if fundamental questions about FPGA architecture. > > 1) When the term routing is used, does it include the switch block > multiplexers and the interconnections (Long wires, short wires etc.)? I normally am referring to both the interconnect lines as well as the switches and multiplexors when I use the term routing. > 2) When packing it done well, can I say that LUTs are packed close to > each other so the amount of routing resources used is less? You would thinks so. But I am sure there are mitigating factors. For example, if you have large data busses that need to run on long routes anyway, it is not so important to minimize the length of these nets while other logic such as FSM (finite state machines) will be well served by short routes. So it is a design dependant issue. > 3) For Altera FPGAs (eg. Stratix versions), how are the LUTs > implemented? For Xilinx, its generally distributed RAM. For Altera > which only uses coarse-grain memory, this can't be the case so what is > the alternative? I believe the LUTs are still RAM based in Altera FPGAs. You just can't use the LUT as a small ram block. I expect Xilinx has a patent on that. But patents expire eventually. So it may not be too long before Altera also has distributed ram... likely about the time when no one cares anymore ;) -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 73244
Jimmy zhang wrote: > A 32 bit adder takes two 32 bit inputs. The propogation delay > can be significant. if one of those two 32 bit inputs is a constant > 1, can the add logic be optimized so that the delay for increment > (+1) is reduced? Increment is usually done by setting the carry in to 1. In the case of a ripple carry adder, it can be done with a chain of half adders, instead of full adders. I think that makes it twice as fast, 32 gate delays instead of 64. > The ohter question is that for 32 bit add, can I achieve 100Mhz > on the latest FPGAs? In an FPGA, it doesn't make much difference, assuming you use one with built in carry logic. I believe that the built in carry logic is faster than a carry lookahead adder at 32 bits, maybe not by 64 bits. -- glenArticle: 73245
<seyior> wrote in message news:ee88e17.-1@webx.sUN8CHnE... > Dear all: > My user reset is connect to all DFF. due to Fan Out limit, XST duplicated several reset signal and cause some output DFFs can not place into IOB. > > how to do, set a higher fan out value, or drive user reset with BUFG, or any other way? You may be able to remove the user reset completely. Is your user reset only to guarantee the initial state of the design (a common ASIC practice)? If so, you can eliminate this reset signal, which will potentially make your design significantly smaller. Xilinx FPGAs have an internal Global Set/Reset signal that is asserted at the end of the configuration process, guaranteeing the initial conditions. Also see the following TechXclusive article. Get Smart About Reset (Think Local, Not Global) http://support.xilinx.com/xlnx/xweb/xil_tx_display.jsp?sTechX_ID=kc_smart_reset --------------------------------- Steven K. Knapp Applications Manager, Xilinx Inc. General Products Division Spartan-3/II/IIE FPGAs http://www.xilinx.com/spartan3 --------------------------------- Spartan-3: Make it Your ASICArticle: 73246
Ted wrote: > I have 3 burning, if fundamental questions about FPGA architecture. > 1) When the term routing is used, does it include the switch block > multiplexers and the interconnections (Long wires, short wires etc.)? Different architectures are different, but I would include everything except LUT data bits, carry chain configuration, and IOB configuration. Inputs to LUT's, FF's, and IOB's usually come from mux's, which are, to me, routing. > 2) When packing it done well, can I say that LUTs are packed close to > each other so the amount of routing resources used is less? Maybe. If you use the carry chain that fixes the relative position of many CLBs. That can restrict the routing such that close packing increases the routing problems. Also, as the device gets full and routing resources get low, the router can make some very long routes, including through LUTs. If the device is not very full, there isn't much constraint on the routing and some routers will spread the logic out. > 3) For Altera FPGAs (eg. Stratix versions), how are the LUTs > implemented? For Xilinx, its generally distributed RAM. For Altera > which only uses coarse-grain memory, this can't be the case so what is > the alternative? It is, I believe, a course array of RAM, DSP, and LAB blocks, where the LAB blocks internally contain LUT's and routing resources, and then routing between the different kinds of blocks. http://www.altera.com/literature/hb/stx/ch_2_vol_1.pdf -- glenArticle: 73247
> > Yup. Not his time. Aside, do we have enough BRAM? I always make use of all BRAMs available in a device, but because there is a new primitive IDELAY available in V4 the need for synchronization FIFOs will be reduced. This new feature will be very useful. I do have several questions regarding the usage of ILOGIC primitive. What is the tab resolution delay? I remember a number of 80ps from the presentation, but I'm not sure I heard correctly? I believe this delay depends on the speed-grade of the device, right? In order to use variable IDELAY, IDELAYCTRL has to be instantiated. Lets say I would like to use IDELAY for two groups of data signals, one running at 166MHz and the other at 200MHz. Do I have to instantiate two IDELAYCTRL primitives and connect REFCLK of each IDELAYCTRL to the same reference clock or do I have to connect 166MHz clock to one IDELAYCTRL and 200MHz clock to other IDELAYCTRL. Is there any correlation between the REFCLK and clocks of the incoming data signals at all, or is REFCLK completely unrelated to any other clock? I saw there is a "Fourth-Generation Design Security" build into V4. Is external battery still needed, or have you implemented some sort of non-volatile memory (EEPROM) inside V4 for the keys? What's the size of bitstream file compared to the previous generation of devices? Regards, Igor BizjakArticle: 73248
IgI, See below, Austin IgI wrote: >>>Yup. Not his time. Aside, do we have enough BRAM? > > > I always make use of all BRAMs available in a device, but because there is a > new primitive IDELAY available in V4 the need for synchronization FIFOs will > be reduced. This new feature will be very useful. I do have several > questions regarding the usage of ILOGIC primitive. What is the tab > resolution delay? I remember a number of 80ps from the presentation, but I'm > not sure I heard correctly? Yes, you did. 78 ps. I believe this delay depends on the speed-grade > of the device, right? Nope. It is derived from a feedback loop from the reference clock, so it never changes. > > In order to use variable IDELAY, IDELAYCTRL has to be instantiated. Lets say > I would like to use IDELAY for two groups of data signals, one running at > 166MHz and the other at 200MHz. Do I have to instantiate two IDELAYCTRL > primitives and connect REFCLK of each IDELAYCTRL to the same reference clock > or do I have to connect 166MHz clock to one IDELAYCTRL and 200MHz clock to > other IDELAYCTRL. The reference clock is always 200 MHz for the delay elements, and has nothing at all to do with the speed the interface needs to run at. One ref clock for the delay is all it takes for the whole part. Is there any correlation between the REFCLK and clocks of > the incoming data signals at all, or is REFCLK completely unrelated to any > other clock? Completely unrelated, unless by chance you need a 200 MHz clock to do something else. > > I saw there is a "Fourth-Generation Design Security" build into V4. Is > external battery still needed, or have you implemented some sort of > non-volatile memory (EEPROM) inside V4 for the keys? Triple 56 bit key DES, battery bcked key RAM, just like V2 and V2P. It is the fourth generation/technology part to have this core. Even though single and double key DES is no longer considered secure (by the federal gov't), triple DES with three differing keys is still considered safe for the time being. Next generation will require AES (in two years). > > What's the size of bitstream file compared to the previous generation of > devices? Uh, depends on the device. Generally speaking, an LX25 is ~ 2500 system gates (whatever that means) and is 7,819,520 bits long. A 2VP20 (~2000 system gates) is 8,214,560. V4 has fewer BRAM bits than Virtex II Pro in ratio to CLBs, and the LX family has no PPC or MGTs. Or, to put it another way, we haven't done anything radical to save config bits in V4. > > Regards, > Igor Bizjak > >Article: 73249
That's what I really love about this newsgroup, people recommeding products of their direct competitors. Kudos to you, Tony! I designed the Trenz board. It is layouted in a way that you can cut it in stripes without interrupting the power supply. For a dongle product. At 42mm x 30mm x 3.5mm it will give you 60 FPGA I/O plus configuration and power supply, at 42mm x 20mm x 3.5mm you will have to solder every IO to the board yourself. Are you sure that you can not squeeze it in with these additional 2mm? You can cut away these 2mm but it will interrupt the main power supply, you could fix that with a wire, but this will result in a really ugly looking board afterwards. BTW: Can you tell us what it is that you want to build the board into? Also, does anybody know about a source for generic usb dongle cases? Our quantities are not large enough to have a custom case molded. Kolja Sulimma "Tony Burch" <tony@burched.com.au> wrote in message news:<4149187b$0$23897$afc38c87@news.optusnet.com.au>... > Hi Darien, > > Here is a new board that may meet your needs > http://www.trenz-electronic.de/prod/proden19.htm > > It's dimension is 50.7 x 43.6mm, however if you > took off the USB connector, and then used a dremel > tool, or a small mill, to route off the top egde and > the left edge (no, I'm serious:) ), then I think you > may be able to bring it down to your needed size. > > You could then solder your wires to the bottom > edge connector. > > Best regards, > > Tony Burch > B U R C H E D > Simple FPGA Boards, The Most Free I/O, Easy Prototyping > http://www.burched.biz > > > "Daragoth" <daragoth@kuririnmail.com> wrote in message > news:317379a8.0409151507.68edc201@posting.google.com... > > Hi, I'm a hobbyist, and about a month and a half ago I made a post to > > this newsgroup looking for a compact FPGA board that I could purchase > > online in small quantities for a project I was doing. It seemed that > > no one knew of a board with the specs I needed (and the closest ones I > > was able to find were the ones at www.fpgas4fun.com, but they were > > slighty too large for what I needed), so I decided to try and design > > one myself with PCB design software (EAGLE 4.13). But I have very > > little experience in PCB design and am pretty overwhelmed with created > > a design from scratch. So I was wondering if there was a place I > > could download the design or (in case anyone missed my original post) > > purchase a board with the following specs: > > > > -FPGA device with at least 15,000 usable gates (more would be > > preferable). I only need a small number of user IOs, so that > > shouldn't be an issue at all. > > -clock to run the FPGA with only around 4 MHz frequency range... > > higher isn't a problem however. > > -in-circuit reprogrammable non-volatile memory device for storing the > > FPGA's configuration data, if the FPGA doesn't have one built-in. > > -The board's must be able to fit with a 40 mm x 30 mm x 10 mm or less > > volume (this is important). > > > > I'm planning on just soldering wires directly to the board, so no > > specific connectors are necessary. And I don't mind if the specs > > aren't exactly what I need, just so long as they are relatively easy > > to alter to my specifications. Thanks a lot for any help. > > > > > > -Darien
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