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Messages from 73450

Article: 73450
Subject: Re: Virtex 4 integrated A/Ds? Yes it does.
From: Thomas Reinemann <thomas.reinemann@masch-bau.uni-magdeburg.de>
Date: Wed, 22 Sep 2004 08:38:45 +0200
Links: << >>  << T >>  << A >>
Hi Austin,

Austin Lesea wrote:
> PLLs, Serdes, A/D, all have a similar problem:  they want it quiet!
What is a Serdes?

> Once we have a proven A/D technology that meets all requirements, then 
> we can discuss market needs.  
How will you know the requirements if you don't discuss market needs. 
For example, we use FPGA in mechatronics, that means sample frequencies 
of about 100kHz are sufficient. Therefore we use a Delta-Sigma-ADC, 
which generates other requirements as a Flash ADC for example.


Bye Tom

Article: 73451
Subject: edge reset
From: "Rune Christensen" <rune.christensen@adslhome.dk>
Date: Wed, 22 Sep 2004 08:55:35 +0200
Links: << >>  << T >>  << A >>
Hello

I have created an edge reset on a counter by using two flipflops
http://old.iot.dk/jjm/adsen/VHDL/KnowHow/Edge_Reset/edge_reset.htm

reset : process(e_rst, e_rst_rst)
begin
  if (e_rst_rst = '1') then
    s_rst <= '0';
  elsif (e_rst'event and e_rst = '1') then
    s_rst <= '1';
  end if;
end process reset;

reset_reset : process(clk)
begin
  if (clk'event and clk = '1') then
    if (s_rst = '1') then
      e_rst_rst <= '1';
    else
      e_rst_rst <= '0';
    end if;
  end if;
end process reset_reset;

But is it possible to simplify edge reset?

I have tried this from
http://www-ee.eng.hawaii.edu/~msmith/ASICs/HTML/Book/CH12/CH12.6.htm

counter : process(a_rst, e_rst, clk)
begin
  if (a_rst = '1') then
    cnt <= 0;
  elsif (e_rst'event and e_rst = '1') then
    cnt <= 0;
  elsif(clk'event and clk = '1') then
    cnt <= cnt + 1;
  end if;
end process counter;

But xilinx will not accept the "elsif (e_rst'event and e_rst = '1') then"

Thanks
Rune Christensen



Article: 73452
Subject: Re: XST vhdl adder with carry out : broken carry chain
From: abeaujean@gillam-fei.be (A Beaujean)
Date: 21 Sep 2004 23:55:44 -0700
Links: << >>  << T >>  << A >>
Bret Wade <bret.wade@xilinx.com> wrote in message news:<ciq91k$7ko2@xco-news.xilinx.com>...
> On July 30 I posted:
> 
>  > Hello Bart,
>  >
>  > We've run your code and there is indeed a map packing problem. The MSB
>  > is simply a FF driven by COUT of the previous slice. I see two related
>  > problems with the packing:
>  >
>  > 1. FF "tmp1_16" should be packed into a slice utilizing the CIN pin
>  > through the XORCY BEL as an extension of the carry chain but is not.
>  >
>  > 2. Instead, FF "tmp1_16" is being packed into the FFY BEL of the carry
>  > chain slice that is driving it, displacing "tmp1_15" from its correct
>  > packing location.
>  >
>  > I've logged CR 192265 for these issues. Meanwhile, I don't see a work
>  > around for first issue except to extend the carry chain by one bit as
>  > you mentioned or possibly by instantiating an XORCY and FF to
>  > terminate
>  > the carry chain. The second issue can be controlled with a map packing
>  > constraint such as:
>  >
>  > INST "tmp1_16" XBLKNM = XLNX_WA ;
>  >
>  > I'll post again when we have a fix date scheduled.
>  >
>  > Regards,
>  > Bret Wade
>  > Xilinx Product Applications
> 
> Just to follow up on this issue, it has been fixed for the next service 
> pack, 6.3i SP2 which will become available in mid October.
> 
> Bret

Hello Bart, 

Please find hereafter a piece of code that works for an incrementer. I
had exactly the same problem as you have until I finally coded that
way.
I am not sure that works for A + B as it does for A + 1.

Hope it can help.

A. Beaujean

Library ieee ;
Use ieee.std_logic_1164.all ;
Use ieee.std_logic_unsigned.all ;
Use ieee.std_logic_arith.all ;
--
Package TDC Is   -- Package for Time to Digital Conversion
--
Component TDC_SUM_RE Is -- Builds the sum of all ones and ((all ones -
1) + Tdc_In
                        -- to force the mapper to use the carry chain.
                        -- Outputs of the carry chain are registered
in the same slice
                        -- (Rising Edge)
  Generic(Width          : integer) ; -- Width of Component, nbr of
stages
  Port   (Reset_Not      : in  std_logic ;
          Clock          : in  std_logic ; -- Clock
          Tdc_In         : in  std_logic ;
          Output         : out std_logic_vector((Width-1) downto 0)) ;
--          
End Component ;
--
Component TDC_SUM_FE Is -- Builds the sum of all ones and ((all ones -
1) + Tdc_In
                        -- to force the mapper to use the carry chain.
                        -- Outputs of the carry chain are registered
in the same slice
                        -- (Falling Edge)
  Generic(Width          : integer) ; -- Width of Component, nbr of
stages
  Port   (Reset_Not      : in  std_logic ;
          Clock          : in  std_logic ; -- Clock
          Tdc_In         : in  std_logic ;
          Output         : out std_logic_vector((Width-1) downto 0)) ;
--          
End Component ;
--
End TDC ;                            
--
Library ieee ;
Use ieee.std_logic_1164.all ;
Use ieee.std_logic_unsigned.all ;
Use ieee.std_logic_arith.all ;
--
--
---------------------------------------------------------------------------------------
--
--                         HANDLING THE TDC_SUM_RE COMPONENT
--
---------------------------------------------------------------------------------------
--
Entity TDC_SUM_RE Is    -- Builds the sum of all ones and ((all ones -
1) + Tdc_In
                        -- to force the mapper to use the carry chain.
                        -- Outputs of the carry chain are registered
in the same slice
                        -- (Rising Edge)
  Generic(Width          : integer) ; -- Width of Component, nbr of
stages
  Port   (Reset_Not      : in  std_logic ;
          Clock          : in  std_logic ; -- Clock
          Tdc_In         : in  std_logic ;
          Output         : out std_logic_vector((Width-1) downto 0)) ;
--          
End TDC_SUM_RE ;

Architecture Arch_Of_TDC_SUM_RE Of TDC_SUM_RE Is
--
-- Components declarations
--
Component FDC   -- Rising edge FF 
  Port (D,C,CLR: in std_logic ;
        Q      : out std_logic );
End Component ;
--
-- Signals
--
Signal Chain         : std_logic_vector((Width-1) downto 0);
Signal Regs          : std_logic_vector((Width-1) downto 0);
Signal Reset         : std_logic ;
Signal All_Ones      : std_logic_vector((Width-1) downto 0) ;
Signal All_Zeroes_M1 : std_logic_vector((Width-1) downto 1) ; 
--
-- Attributes
--
Attribute KEEP : string ;
Attribute KEEP of Chain     : signal is "true" ;
--
Begin
--
-- Components instantiation
--
FDC_All:
For I in 0 to (Width-1) Generate
FDC_One:
FDC
  Port Map (C     => Clock,
            D     => Chain(I),
            CLR   => Reset,
            Q     => Regs(I));
End Generate ;
--
--
--------------------------------------------------------------------------------------
--
--                              CONCURRENT STATEMENTS
--
--------------------------------------------------------------------------------------
--
-- The trick used is to generate a sum of all ones and the
concatenation of
-- (all ones minus 1) and the input signal.
--
All_Ones <= (Others => '1') ;
All_Zeroes_M1 <= (Others => '0') ;
Chain <= All_Ones + (All_Zeroes_M1 & Tdc_In ) ;
Reset <= Not Reset_Not ;
Output <= Regs ;
--
End Arch_Of_TDC_SUM_RE ;
--

Article: 73453
Subject: Re: Virtex 4 integrated A/Ds? Yes it does.
From: mkl<kal@delete.dspia.com>
Date: Wed, 22 Sep 2004 07:05:04 GMT
Links: << >>  << T >>  << A >>
On Wed, 22 Sep 2004 08:38:45 +0200, Thomas Reinemann
<thomas.reinemann@masch-bau.uni-magdeburg.de> wrote:

>Hi Austin,
>
>Austin Lesea wrote:
>> PLLs, Serdes, A/D, all have a similar problem:  they want it quiet!
>What is a Serdes?

Serializer/Deserializer; any of the various serial physical layer
transceivers which invariably include a clock recovery circuit ie pci
express, rocket io etc etc. 

Article: 73454
Subject: Re: Tcl script window does not appear
From: ALuPin@web.de (ALuPin)
Date: 22 Sep 2004 00:06:53 -0700
Links: << >>  << T >>  << A >>
In the DDR SDRAM MegaCore Function User Guide it is said on page 2-32

1. Choose Utility Windows > Tcl console (View menu)
I do that and I see the Tcl console

2. Choose Tcl Script (Tools menu)
I do that and I cannot see any tool

3. Choose add_constraints_for_example_controller.tcl and click
Run

As I said I do not see any tool. When I type
add_constraints_for_example_controller.tcl
in the Tcl console and press return I get the error message
"couldn't execute ..."
So in my opinion the tool that is said to have scripts to choose
is missing ...

"Subroto Datta" <sdatta@altera.com> wrote in message news:<rGW3d.11129$eK3.9387@newssvr31.news.prodigy.com>...
> The Tcl console is interactive, so that the user can type in Tcl commands in 
> there, or execute Tcl scripts which they write using the source command.. 
> When you choose Tools->Tcl Scripts it opens a dialog which points to the 
> canned Tcl scripts that ship with Quartus. You can then select the script 
> and run it. The only one of significance there is the dse script which you 
> can also run from your DOS box by typing quartus_sh --dse.The Full version 
> of Quartus fully supports Tcl.
> 
> - Subroto Datta
> Altera Corp.

Article: 73455
Subject: Re: Stratix II vs. Virtex 4 - features and performance
From: mkl<kal@delete.dspia.com>
Date: Wed, 22 Sep 2004 07:10:59 GMT
Links: << >>  << T >>  << A >>
On 21 Sep 2004 03:58:37 -0700, news@sulimma.de (Kolja Sulimma) wrote:

>> Since no known method exists
>> for cracking AES, a brute force attack is the only way to attempt to
>> crack the key. 
>Nope. 
>Ever heard of differential power analysis?

I am completely clueless about this but doesn't filtering your current
consumption with some large metal/metal or any other type of on die
capacitors in addition to hiding the processing with some uniformly
distributed other power events make this very difficult ?


Article: 73456
Subject: Re: Stratix II vs. Virtex 4 - features and performance
From: "Simon Peacock" <nowhere@to.be.found>
Date: Wed, 22 Sep 2004 19:11:27 +1200
Links: << >>  << T >>  << A >>
To throw a spanner in the works.. the code is only as good as the people ...
if you really want to get the insides of the fpga ... go straight to the
source... the money "invested" in cracking the code will probably buy one of
the engineers who designed it :-)... you might even have some cash left
over...

And for those that think this is illegal.... is cracking codes legal ?

Simon



"Kolja Sulimma" <news@sulimma.de> wrote in message
news:b890a7a.0409210258.6490580d@posting.google.com...
> > Since no known method exists
> > for cracking AES, a brute force attack is the only way to attempt to
> > crack the key.
> Nope.
> Ever heard of differential power analysis?
>
> Kolja Sulimma



Article: 73457
Subject: Re: From whence the MAC on an Altera NIOS devel kit board?
From: hmurray@suespammers.org (Hal Murray)
Date: Wed, 22 Sep 2004 02:41:48 -0500
Links: << >>  << T >>  << A >>
>Interesting... is it unique to each board (and if so does it mean that the flash
>image on the CD isn't the "real" flash image)?

I don't know about NIOS, but if you are pinching pennies (or
tight for space), I think it's reasonably common to put the MAC
address in a back corner of a flash or serial EPROM chip.
Those chips often have sector protect schemes that help avoid
bogus erasures.

It can be a pain for the software/systems level.

-- 
The suespammers.org mail server is located in California.  So are all my
other mailboxes.  Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's.  I hate spam.


Article: 73458
Subject: Re: Stratix II vs. Virtex 4 - features and performance
From: hmurray@suespammers.org (Hal Murray)
Date: Wed, 22 Sep 2004 02:55:15 -0500
Links: << >>  << T >>  << A >>
>I am completely clueless about this but doesn't filtering your current
>consumption with some large metal/metal or any other type of on die
>capacitors in addition to hiding the processing with some uniformly
>distributed other power events make this very difficult ?

Probably, but is "very difficult" difficult enough?  How
much is your secret worth?  If it's worth a lot then the
bad guys will be willing to pay somebody a lot to work
on the problem.

Don't forget that the people designing chips have to be able
to debug them.  There are tools and techniques designed for
debugging chips that can be used for "debugging" secrets.


This comes up every year or two.  I pull out these URLs:
  http://www.cl.cam.ac.uk/~mgk25/sc99-tamper.pdf
  http://www.cl.cam.ac.uk/~mgk25/sc99-tamper-slides.pdf
Lots of pictures in the second one.

Those papers are from 1999.  The technology has changed since them.
I doubt if the general ideas are out of date.

-- 
The suespammers.org mail server is located in California.  So are all my
other mailboxes.  Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's.  I hate spam.


Article: 73459
Subject: Re: edge reset
From: "Jeroen" <jayjay.1974@xs4all.nl>
Date: Wed, 22 Sep 2004 09:57:49 +0200
Links: << >>  << T >>  << A >>

"Rune Christensen" <rune.christensen@adslhome.dk> wrote in message
news:415121e2$0$302$edfadb0f@dread12.news.tele.dk...
> Hello
>
> I have created an edge reset on a counter by using two flipflops
> http://old.iot.dk/jjm/adsen/VHDL/KnowHow/Edge_Reset/edge_reset.htm

This is asynchronous design which should be avoided.

> reset : process(e_rst, e_rst_rst)
> begin
>   if (e_rst_rst = '1') then
>     s_rst <= '0';
>   elsif (e_rst'event and e_rst = '1') then
>     s_rst <= '1';
>   end if;
> end process reset;
>
> reset_reset : process(clk)
> begin
>   if (clk'event and clk = '1') then
>     if (s_rst = '1') then
>       e_rst_rst <= '1';
>     else
>       e_rst_rst <= '0';
>     end if;
>   end if;
> end process reset_reset;
>
> But is it possible to simplify edge reset?
>
> I have tried this from
> http://www-ee.eng.hawaii.edu/~msmith/ASICs/HTML/Book/CH12/CH12.6.htm
>
> counter : process(a_rst, e_rst, clk)
> begin
>   if (a_rst = '1') then
>     cnt <= 0;
>   elsif (e_rst'event and e_rst = '1') then
>     cnt <= 0;
>   elsif(clk'event and clk = '1') then
>     cnt <= cnt + 1;
>   end if;
> end process counter;
>
> But xilinx will not accept the "elsif (e_rst'event and e_rst = '1') then"
>
> Thanks
> Rune Christensen
>

No synthesizer will accept it, because there is no way to synthesize it.
Think hardware ;) The clk'event and clk='1' is a indication to the
synthesizer that you want a flipflop on the outputs after the combinatorial
logic you describe in the process. There can only be one such statement.

This is the way:

signal reset_0,reset_1;
signal cnt:integer;
process(clk)
begin
   if a_rst='1' then        --asynchronous reset in
    cnt<=0;
  elsif clk'event and clk='1' then

   reset_0<=s_rst;      -- synchronous reset in
   reset_1<=reset_0;

   -- detect edge on s_rst
   if reset_0='0' and reset_1='1' then
      cnt<=0;
   else
     cnt<=cnt+1;
   end if;
  end if;
end process;

Hope this helps,

Jeroen




Article: 73460
Subject: Re: USER RESET in XILINX FPGA
From: hmurray@suespammers.org (Hal Murray)
Date: Wed, 22 Sep 2004 02:58:35 -0500
Links: << >>  << T >>  << A >>
>Yes, the Verilog-2001 declaration assignment syntax works. For
>example "reg foo = 1;" gets you a foo with an initial value of 1.
>What's more, xst seems to know what to do with this as well. I
>was at first reluctant to use it in my designs, doubting the xst
>support, but I found it works, so I use it, now.

Have you looked at what it's actually doing?

My guess is it's using the global reset line.  Have you seen
the discussions here?  They happen quite frequently.  They might
be a bit complicated until you "get it".

-- 
The suespammers.org mail server is located in California.  So are all my
other mailboxes.  Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's.  I hate spam.


Article: 73461
Subject: Re: USER RESET in XILINX FPGA
From: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Date: Wed, 22 Sep 2004 08:02:27 +0000 (UTC)
Links: << >>  << T >>  << A >>
Stephen Williams <spamtrap@icarus.com> wrote:
...

: Yes, the Verilog-2001 declaration assignment syntax works. For
: example "reg foo = 1;" gets you a foo with an initial value of 1.
: What's more, xst seems to know what to do with this as well. I
: was at first reluctant to use it in my designs, doubting the xst
: support, but I found it works, so I use it, now.

Stephen,

I know that option and use it. But even if I create a register with
reg foo;
XST gives that register a default value (FALSE). For the simulator however
it is unknown (x).  What I ask about is something like

pragma register_default_state FALSE

and then the simulator would come up with all registers in state FALSE if
they are not initializes in an explicit way (either as above "reg foo = 1;"
or in an initial statement)

: However, that really only simulates the power-on case. If you have
: resets at times other then power on, or soft resets for subsystems,
: this feature is obviously no help.

Totally clear!

Bye

-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Article: 73462
Subject: Re: Virtex 4 integrated A/Ds? Yes it does.
From: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Date: Wed, 22 Sep 2004 08:06:37 +0000 (UTC)
Links: << >>  << T >>  << A >>
Thomas Reinemann <thomas.reinemann@masch-bau.uni-magdeburg.de> wrote:
: Hi Austin,

: Austin Lesea wrote:
: > PLLs, Serdes, A/D, all have a similar problem:  they want it quiet!
: What is a Serdes?

: > Once we have a proven A/D technology that meets all requirements, then 
: > we can discuss market needs.  
: How will you know the requirements if you don't discuss market needs. 
: For example, we use FPGA in mechatronics, that means sample frequencies 
: of about 100kHz are sufficient. Therefore we use a Delta-Sigma-ADC, 
: which generates other requirements as a Flash ADC for example.

But most peripherals can be bought with some serial interface. You only need
about 4 FPGA pins to communicate  with these devices. So having an ADC
onchip the FPGA is not worth the effort, beside for monitoring the FPGA
status itself.

And the requirements for the ADC differ in such a big way for different
users.

Bye
-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Article: 73463
Subject: Re: USER RESET in XILINX FPGA
From: Allan Herriman <allan.herriman.hates.spam@ctam.com.au.invalid>
Date: Wed, 22 Sep 2004 18:15:53 +1000
Links: << >>  << T >>  << A >>
On Wed, 22 Sep 2004 02:58:35 -0500, hmurray@suespammers.org (Hal
Murray) wrote:

>>Yes, the Verilog-2001 declaration assignment syntax works. For
>>example "reg foo = 1;" gets you a foo with an initial value of 1.
>>What's more, xst seems to know what to do with this as well. I
>>was at first reluctant to use it in my designs, doubting the xst
>>support, but I found it works, so I use it, now.
>
>Have you looked at what it's actually doing?

It sets the INIT attribute on the flip flop.

Regards,
Allan

Article: 73464
Subject: Re: Spartan-3 DDR Speed
From: Nick Sawyer <nick.sawyer@xilinx.com>
Date: Wed, 22 Sep 2004 10:35:18 +0200
Links: << >>  << T >>  << A >>
Hi,

The 660 is feasible using a DCM. The 622 number in the data sheeet is
more of a guideline. Most of the reasons that a design may not work
at these high speeds are more to do with the package and pcb than the
silicon. Beyond the 660 number, internal speed becomes the limiting
factor, and the Virtex2 or Virtex4 becomes the best solution.

Cheers
Nick

Thomas Rudloff wrote:

> Hi,
>
> the data sheet tells 330MHz for CLKOUT_FREQ_2X_LF what yields into
> 660MBit/s while 620MBit/s are mentioned.
>
> ISE 6.2 compiles a small test with 200MHz clock (1x) constrains yielding
> into 800MBit/s. Will this work?
>
> The device is a XC3S200-4FT256.
>
> Thanks
> Thomas


Article: 73465
Subject: How To Synchronize FPGAs
From: "Leroy Tanner" <ikeepthespiritalive@freenet.de>
Date: Wed, 22 Sep 2004 11:14:39 +0200
Links: << >>  << T >>  << A >>
Hello newsreaders,

For a while I have been confronted with the following task which I find
quite challenging but unfortuantely didn't manage to solve it, yet.
What I want to do is to use 2-4 FPGAs (Xilinx Virtex 2 Pro) together on one
printed circuit board (PCB). They are used to process a large amount of
incoming serial data (data rates of several GHz's). My idea is to handle
that data parallel by the 2-4 FPGAs. But now there arises the problem how to
adequately split the data and how to synchronize the FPGAs among one
another, in particular?
Is it possible or first of all a realistic idea to synchronize multiple
FPGAs in the GHz range? How can this be done without much protocoll
overhead? I would like to do it without applying an extra transfer protocoll
among the FPGAs just for that purpose! Up to this date I didn't find a
proper solution, yet.
Maybe someone can give me a hint? Any ideas how to solve that problem?

Regards,    Leroy Tanner



Article: 73466
Subject: Re: edge reset
From: "Rune Christensen" <rune.christensen@adslhome.dk>
Date: Wed, 22 Sep 2004 11:42:03 +0200
Links: << >>  << T >>  << A >>

"Jeroen" <jayjay.1974@xs4all.nl> skrev i en meddelelse 
news:41513083$0$78738$e4fe514c@news.xs4all.nl...
>
> "Rune Christensen" <rune.christensen@adslhome.dk> wrote in message
> news:415121e2$0$302$edfadb0f@dread12.news.tele.dk...
>> Hello
>>
>> I have created an edge reset on a counter by using two flipflops
>> http://old.iot.dk/jjm/adsen/VHDL/KnowHow/Edge_Reset/edge_reset.htm
>
> This is asynchronous design which should be avoided.
>
>> reset : process(e_rst, e_rst_rst)
>> begin
>>   if (e_rst_rst = '1') then
>>     s_rst <= '0';
>>   elsif (e_rst'event and e_rst = '1') then
>>     s_rst <= '1';
>>   end if;
>> end process reset;
>>
>> reset_reset : process(clk)
>> begin
>>   if (clk'event and clk = '1') then
>>     if (s_rst = '1') then
>>       e_rst_rst <= '1';
>>     else
>>       e_rst_rst <= '0';
>>     end if;
>>   end if;
>> end process reset_reset;
>>
>> But is it possible to simplify edge reset?
>>
>> I have tried this from
>> http://www-ee.eng.hawaii.edu/~msmith/ASICs/HTML/Book/CH12/CH12.6.htm
>>
>> counter : process(a_rst, e_rst, clk)
>> begin
>>   if (a_rst = '1') then
>>     cnt <= 0;
>>   elsif (e_rst'event and e_rst = '1') then
>>     cnt <= 0;
>>   elsif(clk'event and clk = '1') then
>>     cnt <= cnt + 1;
>>   end if;
>> end process counter;
>>
>> But xilinx will not accept the "elsif (e_rst'event and e_rst = '1') then"
>>
>> Thanks
>> Rune Christensen
>>
>
> No synthesizer will accept it, because there is no way to synthesize it.
> Think hardware ;) The clk'event and clk='1' is a indication to the
> synthesizer that you want a flipflop on the outputs after the 
> combinatorial
> logic you describe in the process. There can only be one such statement.
>
> This is the way:
>
> signal reset_0,reset_1;
> signal cnt:integer;
> process(clk)
> begin
>   if a_rst='1' then        --asynchronous reset in
>    cnt<=0;
>  elsif clk'event and clk='1' then
>
>   reset_0<=s_rst;      -- synchronous reset in
>   reset_1<=reset_0;
>
>   -- detect edge on s_rst
>   if reset_0='0' and reset_1='1' then
>      cnt<=0;
>   else
>     cnt<=cnt+1;
>   end if;
>  end if;
> end process;
>
> Hope this helps,
>
> Jeroen
>
>
>

Thanks for the answer.
I have created the following from your description

  p_pps_edge : process(rst, clk)
  begin
    if (rst = '1') then
      pps_edge_old <= '0';
    elsif (clk'event and clk = '1') then
      pps_edge_old <= pps;
    end if;
  end process p_pps_edge;

  pps_edge <= not pps_edge_old and pps;

Hope this is correct :-)
pps is an input pin with a signal comming from a acutime2000 GPS reciever 
(pulse per second).


Cheers
Rune 



Article: 73467
Subject: ISE 6.3 Suse 9.1 installation problem
From: Arthur Sharp <arthur@nospam.com>
Date: Wed, 22 Sep 2004 20:21:29 +1000
Links: << >>  << T >>  << A >>
I have a desktop with Suse 9.1 and I managed to install ISE 6.2 .

I also have a laptop  with Suse 9.1 as well, but I could not
install neither ISE 6.2 nor ISE 6.3 .

The error is the same :
Wind/U Error(294): unable to install Wind/U ini file 
(/tmp/xinstall/cd1/LINISE1G.35.2.0/data/Windu).
See the Wind/U manual on the "WindU" file and the "WINDU" environment 
variable.

WindU X-tookit Error : wudisplay Can't open dispaly

the program teminates

If you have any ideas, please let me know.

Thanks.

Arthur

Article: 73468
Subject: Re: ISE 6.3 Suse 9.1 installation problem
From: Arthur Sharp <arthur@nospam.com>
Date: Wed, 22 Sep 2004 20:23:52 +1000
Links: << >>  << T >>  << A >>
Arthur Sharp wrote:
> I have a desktop with Suse 9.1 and I managed to install ISE 6.2 .
> 
> I also have a laptop  with Suse 9.1 as well, but I could not
> install neither ISE 6.2 nor ISE 6.3 .
> 
> The error is the same :
> Wind/U Error(294): unable to install Wind/U ini file 
> (/tmp/xinstall/cd1/LINISE1G.35.2.0/data/Windu).
> See the Wind/U manual on the "WindU" file and the "WINDU" environment 
> variable.
> 
> WindU X-tookit Error : wudisplay Can't open dispaly
> 
> the program teminates
> 
> If you have any ideas, please let me know.
> 
> Thanks.
> 
> Arthur

I forgot to add that I have followed the procedure described in the 
release note of killing the windu processes and deleting the .wind...
directory, but to no avail.

Arthur

Article: 73469
Subject: Problem with Xilinx Webpack documentation
From: abeaujean@gillam-fei.be (A Beaujean)
Date: 22 Sep 2004 03:28:43 -0700
Links: << >>  << T >>  << A >>
Having problem with Webpack. 

Installed it automatically. 

When trying to get help thru the HELP button and then the "Online
Documentation' button, Adobe Reader starts and shortly displays a
window saying "There was an error opening this document. The path does
not exist", with no other indication whatsoever.

Can someone help by telling me what PATH it is ? What file should be
there ? Is there maybe an environment variable missing ?

Thank for help.

Article: 73470
Subject: Re: ISE 6.3 Suse 9.1 installation problem
From: Arthur Sharp <arthur@nospam.com>
Date: Wed, 22 Sep 2004 20:32:43 +1000
Links: << >>  << T >>  << A >>
Arthur Sharp wrote:
> I have a desktop with Suse 9.1 and I managed to install ISE 6.2 .
> 
> I also have a laptop  with Suse 9.1 as well, but I could not
> install neither ISE 6.2 nor ISE 6.3 .
> 
> The error is the same :
> Wind/U Error(294): unable to install Wind/U ini file 
> (/tmp/xinstall/cd1/LINISE1G.35.2.0/data/Windu).
> See the Wind/U manual on the "WindU" file and the "WINDU" environment 
> variable.
> 
> WindU X-tookit Error : wudisplay Can't open dispaly
> 
> the program teminates
> 
> If you have any ideas, please let me know.
> 
> Thanks.
> 
> Arthur


I found out on Google that I needed to set the DISPLAY variable
export DISPAY=:0

worked in my case

Arthur

Article: 73471
Subject: Re: edge reset
From: "Rune Christensen" <rune.christensen@adslhome.dk>
Date: Wed, 22 Sep 2004 13:06:08 +0200
Links: << >>  << T >>  << A >>

"Rune Christensen" <rune.christensen@adslhome.dk> skrev i en meddelelse 
news:415148e7$0$232$edfadb0f@dread12.news.tele.dk...
>
> "Jeroen" <jayjay.1974@xs4all.nl> skrev i en meddelelse 
> news:41513083$0$78738$e4fe514c@news.xs4all.nl...
>>
>> "Rune Christensen" <rune.christensen@adslhome.dk> wrote in message
>> news:415121e2$0$302$edfadb0f@dread12.news.tele.dk...
>>> Hello
>>>
>>> I have created an edge reset on a counter by using two flipflops
>>> http://old.iot.dk/jjm/adsen/VHDL/KnowHow/Edge_Reset/edge_reset.htm
>>
>> This is asynchronous design which should be avoided.
>>
>>> reset : process(e_rst, e_rst_rst)
>>> begin
>>>   if (e_rst_rst = '1') then
>>>     s_rst <= '0';
>>>   elsif (e_rst'event and e_rst = '1') then
>>>     s_rst <= '1';
>>>   end if;
>>> end process reset;
>>>
>>> reset_reset : process(clk)
>>> begin
>>>   if (clk'event and clk = '1') then
>>>     if (s_rst = '1') then
>>>       e_rst_rst <= '1';
>>>     else
>>>       e_rst_rst <= '0';
>>>     end if;
>>>   end if;
>>> end process reset_reset;
>>>
>>> But is it possible to simplify edge reset?
>>>
>>> I have tried this from
>>> http://www-ee.eng.hawaii.edu/~msmith/ASICs/HTML/Book/CH12/CH12.6.htm
>>>
>>> counter : process(a_rst, e_rst, clk)
>>> begin
>>>   if (a_rst = '1') then
>>>     cnt <= 0;
>>>   elsif (e_rst'event and e_rst = '1') then
>>>     cnt <= 0;
>>>   elsif(clk'event and clk = '1') then
>>>     cnt <= cnt + 1;
>>>   end if;
>>> end process counter;
>>>
>>> But xilinx will not accept the "elsif (e_rst'event and e_rst = '1') 
>>> then"
>>>
>>> Thanks
>>> Rune Christensen
>>>
>>
>> No synthesizer will accept it, because there is no way to synthesize it.
>> Think hardware ;) The clk'event and clk='1' is a indication to the
>> synthesizer that you want a flipflop on the outputs after the 
>> combinatorial
>> logic you describe in the process. There can only be one such statement.
>>
>> This is the way:
>>
>> signal reset_0,reset_1;
>> signal cnt:integer;
>> process(clk)
>> begin
>>   if a_rst='1' then        --asynchronous reset in
>>    cnt<=0;
>>  elsif clk'event and clk='1' then
>>
>>   reset_0<=s_rst;      -- synchronous reset in
>>   reset_1<=reset_0;
>>
>>   -- detect edge on s_rst
>>   if reset_0='0' and reset_1='1' then
>>      cnt<=0;
>>   else
>>     cnt<=cnt+1;
>>   end if;
>>  end if;
>> end process;
>>
>> Hope this helps,
>>
>> Jeroen
>>
>>
>>
>
> Thanks for the answer.
> I have created the following from your description
>
>  p_pps_edge : process(rst, clk)
>  begin
>    if (rst = '1') then
>      pps_edge_old <= '0';
>    elsif (clk'event and clk = '1') then
>      pps_edge_old <= pps;
>    end if;
>  end process p_pps_edge;
>
>  pps_edge <= not pps_edge_old and pps;
>
> Hope this is correct :-)
> pps is an input pin with a signal comming from a acutime2000 GPS reciever 
> (pulse per second).
>
>
> Cheers
> Rune
>

When I used Modelsim Xilinx Special Edition the first attempt didn't work 
and I have changed it to

  p_pps_edge : process(rst, clk)
  begin
    if (rst = '1') then
      pps_edge_new <= '0';
      pps_edge_old <= '0';
    elsif (clk'event and clk = '1') then
      pps_edge_new <= pps;
      pps_edge_old <= pps_edge_new;
    end if;
  end process p_pps_edge;

  pps_edge <= not pps_edge_old and pps_edge_new;



Article: 73472
Subject: Re: ISE 6.3 Suse 9.1 installation problem
From: Simon <news@gornall.net>
Date: Wed, 22 Sep 2004 11:11:55 GMT
Links: << >>  << T >>  << A >>
Arthur Sharp wrote:
> Arthur Sharp wrote:
> 
>> I have a desktop with Suse 9.1 and I managed to install ISE 6.2 .
>>
>> I also have a laptop  with Suse 9.1 as well, but I could not
>> install neither ISE 6.2 nor ISE 6.3 .
>>
>> The error is the same :
>> Wind/U Error(294): unable to install Wind/U ini file 
>> (/tmp/xinstall/cd1/LINISE1G.35.2.0/data/Windu).
>> See the Wind/U manual on the "WindU" file and the "WINDU" environment 
>> variable.
>>
>> WindU X-tookit Error : wudisplay Can't open dispaly
>>
>> the program teminates
>>
>> If you have any ideas, please let me know.
>>
>> Thanks.
>>
>> Arthur
> 
> 
> 
> I found out on Google that I needed to set the DISPLAY variable
> export DISPAY=:0
> 
> worked in my case

I posted about this previously on the group - WindU is the only program 
I've ever encountered in 15 years using unix that doesn't accept :0.0 as 
a DISPLAY (not DISPAY :-) variable....

Simon

Article: 73473
Subject: Re: Mr. Greenfield, spare us the propaganda !
From: info@bostonsemiconductor.com (Chris Alexander)
Date: 22 Sep 2004 05:08:03 -0700
Links: << >>  << T >>  << A >>
Just so!  There is more marketing jive going on here than just from
Altera.  Being new to this group, I thought this was a Xilinx only
area until the "infamous posts" showed up.

I look forward to the technical threads, but the hype from anyone
(including Austin) I skip over.

One more poster to add to the "skip-over-list".

"Pete Fraser" <pete@rgb.com> wrote in message 
> 
> Let's not forget that Austin got things going with the following:
> 
.
.
> 
> Mr Greenfield certainly escalated things, but with Austin's
> "Bring 'em on" invitation, it's not surprising.

Article: 73474
Subject: Re: Stratix II vs. Virtex 4 - availability & fab partnership
From: info@bostonsemiconductor.com (Chris Alexander)
Date: 22 Sep 2004 05:12:51 -0700
Links: << >>  << T >>  << A >>
Um...you are all making good points, but I think the technical folks
in the crowd do not care.  I suggest you organize some sort of mud
wrestling event and see which of you can sell more tickets for
bragging rights.

"Paul Leventis \(at home\)" <paulleventis-news@yahoo.ca> wrote in message news:<nZ44d.35186$RTE1.25248@news01.bloor.is.net.cable.rogers.com>...
> Hi Stifler,
> 
> Well, at least David included his affiliation/credentials.  But let's take a
> quick (admittly fun) poke at your message.
> 
.
.
.
<MORE WORDS HERE>



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