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Tails wrote: > > "Antti Lukats" <antti@case2000.com> wrote in message news:<cjc3ae$ves$01$1@news.t-online.com>... > > "Roman Zeilinger" <Patrick.Bateman23@gmx.at> wrote in message > > news:2rtd9aF1eq2mjU1@uni-berlin.de... > > > Hi > > > > > > And where can I find the download link for the Verilog model? > > > Because I can nowhere on the project site of aeMB! > > > > > > cheers > > > Roman > > > > http://www.opencores.com/pdownloads.cgi/list/aemb > > > > get the archive, the verilog source is inside there, checked :) > > > > Antti > > If you check out the syn directory in that archive it lists the > sythesis results for various FPGA's. What is interesting is the > frequency of operation in a Xilinx device is >3X the Altera device. > > I would be very interested to see the results of a Nios-II core in a > Xilinx Device!! That doesn't suprise me at all. Each vendor has designed their CPU from the ground up knowing exactly how to optimize the design for their architecture. I am sure every little nit was used to optimize the design for speed and size. I expect the xxxxBlaze designs use a lot more LUTs in the Altera parts too! As you say, it will be interesting to see how the Nios-II core fits into a Spartan-3. I will also be interested in seeing how it fits an Altera ACEX which Altera is not supporting with this design. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 73776
There doesn't appear to be any way to put timing constraints on the internal signals of a design. I have a fast clock and a slow clock and it would be best if I could put a timing constraint on the fast signals. When the editor opens up I see GLOBALS, PORTS, ADVANCE and MISC. Where are the signals? And how does Xilinx track signals through the VHDL sysnthesis inferrence process anyway? Seems like a lot of my signals are gone or renamed when I poke around in the layout editor. One thing I have found is that you can double click the boxes in the editor and up pops a nice description of what the constraint does. I found this by accident. I also have GLOBALS that I didn't expect. I have an oscin, OK, my oscillator input, but I also have a devounced switch signal , which granted, goes to a lot of components, but still considered a nearly DC value. What do I put here, 1000ns? >You can put a constraint from anything to anything in the UCF file. You >can also put period constraints on all of your clocks. Read the CGD manual. By the way. The CGD manual is a 900 plus page doc. Best if one zone into the strategy chapter first, I suppose, or else read 137 pages leading up to this chapter. Where is the Getting Started tutorial on this subject? b r a d @ a i v i s i o n . c o mArticle: 73777
You will probably need to instantiate the LUT1 primitive(s) in the design to get the LUT into the netlist. Then you need an attribute attached in the Xilinx constraint file: perhaps a "KEEP" or net "S" constraint will give you what you want - check the constraints guide. As for the DQS... Are you looking at "matching" the delays for the DQS and data? If you're just looking for a delay, realize that the LUT delay can be a very sloppy value. Changes over PVT (process, voltage, temperature) will give you varying delays. A more appropriate method of dealing with DDR memory in the pre-Virtex-4 devices may be to use the main clock and the guaranteed timing relative to that clock for appropriate access. If you use an external route to match the feedback clock delays to the clock/data delays, you have an extremely well-matched system. If you have a DCM available just for clocking in the data, you could phase-shift there instead. "van de Kerkhof" <bvdk@NOSPAMMoce.nl> wrote in message news:1096459252.191676@news-ext.oce.nl... > It is ment for dqs delay in a ddr design. > > synthesis is ok the delay line is still there but ISE is deleting them. > > Bram > > > "Marc Randolph" <mrand@my-deja.com> wrote in message > news:R-idndwld6koPMfcRVn-gQ@comcast.com... > > van de Kerkhof wrote: > > > Hi. > > > > Howdy Bram, > > > > > I made a programmable lut delay. > > > > A LUT delay? How much of a delay, and how did you attempt do this? > > Unless you are using an SRL, you are probably not getting what you are > > wanting. > > > > > Xilinx ise thinks it may optimize some luts away how can i prevent this. > > > > Use FF's or SRL's. > > > > > I use synplicity for synthesis. > > > > > > I already tried: keep keep_architecture syn_noprune syn_keep > syn_preserve. > > > > > > Changing the lut init by making an other design will change the number > of > > > luts it will optimize but it should be possible to say dont touch the > luts?? > > > > Unless you instantiate the LUTs and Fx muxes, I could see it being very > > hard to keep a good synthesis tool from doing its job. After all, 99% > > of the users want the synthesis tool to optimize the LUTs as much as > > possible. It typically leads to faster designs and lower utilization. > > > > Good luck, > > > > Marc > >Article: 73778
"Brian Davis" <brimdavis@aol.com> wrote in message news:a528ffe0.0409280339.31c53619@posting.google.com... > Steven Knapp wrote: > > > > The limitation is if ... > > > > * The VCCO supply ramps faster than the minimum > > data sheet specification (Tcco) > > > One question: is this strictly a power-up issue, or can it be > triggered during operation? No, it can only be triggered during the power-up sequence. > In particular, since the ramp spec. is worse for the leaded > packages, could a large transient on the VCCO supply cause > the same problem? No, not unless the transient drops the VCCO supply down toward ground, in which case the application would violate a variety of specification. --------------------------------- Steven K. Knapp Applications Manager, Xilinx Inc. General Products Division Spartan-3/II/IIE FPGAs http://www.xilinx.com/spartan3 --------------------------------- Spartan-3: Make it Your ASICArticle: 73779
Hi, > For example, when you 'turn on' a PC, the PCI-reset > line is held for some # of cycles, then the PC's > BIOS starts scanning the PCI-bus for devices. After > a reset/powerup, will the FPGA configure itself in time? It depends. The amount of time it takes the FPGA to "get ready" depends on how you are configuring the FPGA with its bitstream, and the size of the bitstream. And if that is "in time" depends on what bus interface you are designing. For example, a 2vp100 configured with slave serial with a CCLK frequency of 1 MHz is going to take a long, long time... Another example, a 2s50 configured with select map (8-bit parallel) with a CCLK frequency of 50 MHz is going to be fairly quick. The next question is, "How much time do I have?" The following assumes a system compliant with the PCI 2.3 and/or PCI-X 2.0 specifications. * PCI 32-bit design -- about 2^25 bus clock cycles * PCI 64-bit design -- about 100 ms * Any PCI-X design -- about 100 ms The reason a 32-bit PCI design has so much more time is that it does not need to be ready to see the busmode/buswidth broadcast which takes place at the rising edge of reset. > And what happens if you want to do 'on the fly' > FPGA re-configuration? Will that lock-up the PC? No, I have seen some designs on hardware from VCC that do this. However, it requires some context saving -- done by the driver, or done by the hardware, so that when the new configuration is loaded, you are able to "restore" the values in the PCI Configuration Space, such as the Base Address Registers, etc. EricArticle: 73780
"rickman" <spamgoeshere4@yahoo.com> wrote in message news:4159BB3B.10CC935B@yahoo.com... > Brian Davis wrote: [snip] > > I don't think this is a problem. The ramp speed issue in only of > concern at a voltage threshold around 0.8~1.0 volts. As it was > explained to me, when the part powers up, there are a lot of transistors > which are turned on initially. Once Vcc gets above about 1.0 volts, > everything is biased and the transistors that need to be off are off. > But the part draws a lot of current in the meantime as the voltage > ramps. If the voltage ramps too fast, the PS can max out on current and > for some reason, this will disturb the part and it will not initialize > correctly to the point that a power down must be done to correct the > problem. > > So the problem is that you must let the part draw as much current as it > needs as the voltage ramps up. The spec is to let you know how much > current you will need for a given ramp rate. Keep the ramp rate slower > than the worst case spec and the part will be happy with the current > spec'd in the data sheet. After the voltage rises above about 1.0 volts > this is no longer an issue regardless of how the spec is written (or > interpreted). The problem that you described is a completely different phenomena from much older FPGA families. This phenomena does not exist on any of the modern FPGA architectures like Virtex-II, Virtex-II Pro, Spartan-3, and Virtex-4. --------------------------------- Steven K. Knapp Applications Manager, Xilinx Inc. General Products Division Spartan-3/II/IIE FPGAs http://www.xilinx.com/spartan3 --------------------------------- Spartan-3: Make it Your ASICArticle: 73781
"Uwe Bonnes" <bon@elektron.ikp.physik.tu-darmstadt.de> wrote in message news:cjcmmt$2ca$1@lnx107.hrz.tu-darmstadt.de... > Austin Lesea <austin@xilinx.com> wrote: > : Rick, > > : This issue is (was) new: the ESD protection of the Vcco pins was firing > : on a high (very fast) dV/dt. Later mask sets got fixed, but some early > : mask sets are still in production with this restriction. > > Any hints for decoding the top marking for that issue? At present, the XC3S50 and the XC3S1000 do not have a minimum VCCO ramp rate restriction. The remaining family members do. The Spartan-3 data sheet lists the appropriate specifications (Tcco). When the restriction is removed for the other devices, we will tie the difference to a top-mark field on the package and indicate the difference in the data sheet. --------------------------------- Steven K. Knapp Applications Manager, Xilinx Inc. General Products Division Spartan-3/II/IIE FPGAs http://www.xilinx.com/spartan3 --------------------------------- Spartan-3: Make it Your ASICArticle: 73782
ALuPin wrote: > > Hi, > > I have a question concerning the following phenomenon: > > I have a signal which is registered by the following way: > > entity xy is > port (... > DQS : inout std_logic_vector(15 downto 0); > ); > end xy; > > architecture zy of xy is > signal l_input_cell : std_logic_vector(15 downto 0); > begin > > process(Reset, Clk) > begin > if Reset='1' then > l_input_cell <= (others => '0'); > elsif rising_edge(Clk) then > l_input_cell <= DQS; > end if; > end process; > end zy; > > When I simulated the design (I had changed a different design to my > own > VHDL style) I got different simulation results (functional simulation > Modelsim) with respect to the signal "l_input_cell". > > Then I changed "rising_edge(Clk)" back to "Clk'event and Clk='1'" and > I got the same result as in the original design. > > So why is there a difference at all? > Does the use of an INOUT port play any role ? I can't say that the INOUT port would make a difference since you never assign a value to DQS. But there is a difference between the two clock edge descriptions. I don't recall how "rising_edge()" is defined, but it is not the same as "Clk'event and Clk='1'". Even so, I would not expect a difference in how the two operate unless CLK has values other than '1' and '0'. I belive "Clk'event and Clk='1'" will detect a transistion from *any* value to '1' as a valid clock edge, while "rising_edge(Clk)" requires the previous state to be '0' or possibly 'L'. Does you simulation allow Clk to be undefined with a 'Z', 'U' or 'X'? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 73783
On Wed, 29 Sep 2004 08:37:25 -0700, Cyrille Lambert wrote: > Hi everybody, > > I cannot find any paper or application note on the Virtex-II architecture. Do you know where could I find it? > In order to know more about the bitstream in the spirit of the xapp151 for example. By the way, if this application note reflects the architecture of the Virtex-II tell me please, I am a bit lost. > > Thanks by advance, > /Cyrille Lambert What precisely are you asking for? The Xilinx website has users manuals and data sheets fro everything they produce.Article: 73784
Hi all [SOPC users], is there a way a can configure the read burst length of the standard SDRAM controller within SOPC 4.1? Best Regards MarkusArticle: 73785
Brad Smallridge wrote: > > There doesn't appear to be any way to put timing constraints on the internal > signals of a design. I have a fast clock and a slow clock and it would be > best if I could put a timing constraint on the fast signals. Timing constraints are applied to paths, not signals. You may well have different timing constraints on different paths that end at the same node or start from the same node. So a timing constraint must be applied to a path (or paths) between a set of starting points and a set of ending points. Clocks can be constrained to a period which will then be the default constraint on all paths ending on the FFs driven by that clock. But still you need to think *paths*. > When the editor opens up I see GLOBALS, PORTS, ADVANCE and MISC. > Where are the signals? And how does Xilinx track signals through the VHDL > sysnthesis > inferrence process anyway? Seems like a lot of my signals are gone or > renamed when I poke > around in the layout editor. > > One thing I have found is that you can double click the boxes in the editor > and up pops > a nice description of what the constraint does. I found this by accident. > > I also have GLOBALS that I didn't expect. I have an oscin, OK, my > oscillator input, but > I also have a devounced switch signal , which granted, goes to a lot of > components, but still > considered a nearly DC value. What do I put here, 1000ns? > > >You can put a constraint from anything to anything in the UCF file. You > >can also put period constraints on all of your clocks. Read the CGD manual. > > By the way. The CGD manual is a 900 plus page doc. Best if one zone into the > strategy chapter first, I suppose, or else read 137 pages leading up to this > chapter. > > Where is the Getting Started tutorial on this subject? Timing constraint design is the one area of FPGA design that is not well taught and is subject to errors with little means of verification. I am surprised that after being used for so many years, timing constraints have not caught up with the logical part of chip design in terms of verification. I can perform simulations on the logic and measure the coverage of my test vectors. But I have no way to verify that my timing constraints are correct and are doing what I want them to do. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 73786
Hi, I'm using OCR processing (optical character recognition) on a 3.2 Ghz PCU. It is not fast enough (10 minutes for each single newspaper page). Do you think that a FPGA solution could increase the speed of the processing? Must the software be programmed in order to be used with FPGA's or do solutions exist regardless of the soft? Thanks for your information. Daniel ParisArticle: 73787
Daniel wrote: > Hi, > > I'm using OCR processing (optical character recognition) > on a 3.2 Ghz PCU. > It is not fast enough (10 minutes for each single > newspaper page). Do you think that a FPGA solution could > increase the speed of the processing? Yes, it could. > Must the software be programmed in order to be used > with FPGA's or do solutions exist regardless of the soft? I don't understand this question. You want a hardware implementation, not a reimplementation of software. Most likely the algorithm will be completely different. I recommend looking at dynamic programming algorithms and systolic array processors. If those work, FPGA's are a good choice. -- glenArticle: 73788
Sadly, FGPA readback is not supported at all. You can, however, perform a verify in which the data is read back from the device and compared against the source bistream. alonzo wrote: >Hello, >I'm trying to readback the configuration file of an FPGA. Does anybody has >ideas about how would be the best way to do it? I'm trying to use iMPACT >command readbackToFile and I get the following error: >// *** BATCH CMD : readbackToFile -p 1 -f remay >ERROR:iMPACT:1353 - ACD entry READBACK_PROGRESS_COUNT not found for >device > family xc2s200e. >EXCEPTION:iMPACT:ConstraintsManager.c:394:1.34.2.1 - Data not found. > > >Any ideas?? > >Thanks! >Alonzo. > > >Article: 73789
Robert S. Grimes wrote: > Yeah, that's sounds right, Glen; it's what I'm assuming. The problem > is that I don't know how to tell it otherwise! I've done fairly > complex designs before, but I've never had to deal with high speed. > This project is fairly simple, but needs to high speed counters to > measure the arrival times of pulses on two signals. So, I have three > signals that enter via pins (counter clock and the two pulse trains of > interest); the rest of the design can be relatively slower, maybe as > much as three orders of magnitude. There was a question here not so long ago about the meaning of static timing analysis. For a synchronous design the tools can compute the time it takes from the output of any FF, through logic to the input of any other FF. That time, plus the setup time of the FF determines the maximum clock rate. It is done without knowing which FF's are enabled on any clock cycle, and so might be overly restrictive. It might be that you can tell the tools what you really mean, or you might just have to ignore the results of that analysis. The frequency you came up with is the frequency if you don't stop the counter. -- glenArticle: 73790
I believe you can use the __attribute__ option to the DWORD variabele. You just need a look in the documentation what type of attribute you have to specify for alignment. I'm sure it works on structs. "Luigi Padovani" <l.padovani@seventech.it> wrote in message news:TyX4d.2010428$6p.344224@news.easynews.com... > Hello, > > I have found a problem with a C++ Code, > > if i have a Buffer of "unsigned char" (for example 00 00 00 00 37 00 00 20 > 00 ecc..ecc.) ,i want to get a DWORD value from the 5 byte they should be > return 00 00 20 00 sequence, instead they give me the result from 37.... (a > 4 bytes pairs)... if i try from 6 or 7 byte , they returned me the same > value , also from the 8 byte give me a new correct value.. the Nios can't > addressing the offset of 4bytes? , the same code compiled on pc work great.. > > > Thank's a lot > > > > > > >Article: 73791
In article <g1r6d.2613$JG2.1445@newssvr14.news.prodigy.com>, don <don@don.com> wrote: > >I've seen a lot of boards that use FPGAs as a PCI I'm farrr from an expert, but I built a PCI target in a CPLD a few weeks ago. I thought it was kind of interesting so I wrote it up: http://www.ben.com/minipci/ That's about $15 worth of parts if you can make it at home. >If I need to use an FPGA as a PCI-controller, are there >any tricks I should know about? For example, when you >'turn on' a PC, the PCI-reset line is held for some ># of cycles, then the PC's BIOS starts scanning the >PCI-bus for devices. First you need to google for the "PCI Local Bus Specification" PDF. You will find bootleg copies. The 2.1 I've found is easier to use than 2.2 because it has a working table of contents. Reset will be low for a long time (for example if you hold down the front panel reset) but it will only be low with a stable CLK for a period defined in the spec. The biggest pitfall I'm aware of is that many PCI bridge chipsets (and their BIOSes) can and will disable CLK on a slot that does not respond to a configuration cycle at boot. If you can get past that point you can experiment a lot more. >And what happens if you want to do 'on the fly' FPGA >re-configuration? Will that lock-up the PC? As long as your IO lines are all tristated during reconfiguration and your part comes out of reconfiguration with everything tristated (without needing a PCI RST# which isn't going to be there). I was working with a CPLD so that meant everything was going to default to zeros. As long as my IDLE state was state=0 it worked fine. If you rely on any config space bits getting set by the BIOS your driver will have to note those and put them back after a reconfiguration. With an FPGA you might be able to modify your bitstream so it comes up with the right settings. -- Ben Jackson <ben@ben.com> http://www.ben.com/Article: 73792
Robert S. Grimes wrote: > Hi, > > According to app not XAPP379, fast counters up to 40 bits long can be > created. I need a 32 bit or so counter, clocked as fast as possible, > so I thought I would start with the technique in the app note. It > claims "basic CoolRunner-II CPLD AND gate...is 40 inputs wide". Maybe > so, but I don't know how to get XST to recognize my intentions to use > it in my VHDL code. Probably I don't know the syntax. Can anybody > help me with a simple example? > > Thanks! > -Bob Do you real need binary counter in your application? If you are searching to speed your design, try a LSFR architecture of your counter -> you will use more Flip-Flops but you will increase the speed ! Regards Laurent www.amontec.comArticle: 73793
"glen herrmannsfeldt" <gah@ugcs.caltech.edu> a écrit dans le message de news: cjes0g$842$1@gnus01.u.washington.edu... > > > Daniel wrote: > > > Hi, > > > > I'm using OCR processing (optical character recognition) > > on a 3.2 Ghz PCU. > > It is not fast enough (10 minutes for each single > > newspaper page). Do you think that a FPGA solution could > > increase the speed of the processing? > > Yes, it could. > > > Must the software be programmed in order to be used > > with FPGA's or do solutions exist regardless of the soft? > > I don't understand this question. You want a hardware > implementation, not a reimplementation of software. Why not a reimplementation of software? Is it more difficult to develop a version for a FPGA solution (if the publisher can do it) than to programme the FPGA in order to adjusted it to the soft?Article: 73794
Użytkownik "Dave" <gretzteam@hotmail.com> napisał w wiadomości news:urSdnShroJyVN8XcRVn-hA@comcast.com... > Hi, > I have a design (basically a FIR filter) that is clocked by the output of a > DCM. I understand that I should not do anything before the locked signal > goes high. However, what is the right way to do this? > > I also have a small state machine that resets the FIR filter, sets some > stuff, and then enable everything. The state machine is also clocked by the > output of the DCM (it is the only clock of the design). Should I use the > locked signal as an asynchronous reset of the state machine so that nothing > happens before locked goes high? I wonder if this is what people do, or if > there is an easier way. > Thanks, > David > > Hi! 1. Delay the lock in the shift register 2. Latch a lock transition to get a clock enable 3. and use clock enable to your master state machine 4. repeat for any clock coming from DCM Rafal J.Article: 73795
All, Neil is right, that the ISE tools do not support readback (only verify). But the silicon can (of course) read back its bitstream to any device that is programmed to provide the necessary commands to the device to do so (otherwise, how would verify work at all?). For example, the Rosetta experiment uses JTAG readback to find soft errors caused by cosmic ray neutron showers. http://tinyurl.com/7xemy (by the way, http://tinyurl.com is a cool way to minimize the pain of long URLs) Austin Neil Glenn Jacobson wrote: > Sadly, FGPA readback is not supported at all. You can, however, perform > a verify in which the data is read back from the device and compared > against the source bistream. > > alonzo wrote: > >> Hello, >> I'm trying to readback the configuration file of an FPGA. Does anybody >> has >> ideas about how would be the best way to do it? I'm trying to use iMPACT >> command readbackToFile and I get the following error: // *** BATCH CMD >> : readbackToFile -p 1 -f remay >> ERROR:iMPACT:1353 - ACD entry READBACK_PROGRESS_COUNT not found for >> device >> family xc2s200e. >> EXCEPTION:iMPACT:ConstraintsManager.c:394:1.34.2.1 - Data not found. >> >> >> Any ideas?? >> >> Thanks! >> Alonzo. >> >> >> >Article: 73796
HI JIM - PLease see below.
thanks.
Jim Granville <no.spam@designtools.co.nz> wrote in message news:<d4k6d.5778$mZ2.508657@news02.tsnz.net>...
> Guy wrote:
>
> > Let me first say thank you for your responses.
> > To address some of the questions / comments:
> > I realize that not everyone will extract the same application or value
> > from the on-chip NV memory, however, since it has the potential to
> > provide or support different applications, general enough value may be
> > justified for inclusion.
>
> Since this is Horizon gazing, what about looking into FPGA+MRAM - then
> you can offer SRAM to all users, and do not have to do a RAM/OTP die
> trade off - plus it is much easier to explain to users.
> [FPGA designers are not always the most hardware literate :) ]
>
One thing we are striving to do, in order to keep cost minimal, is to
stay away from non standard CMOS processes. MRAM although by itself
shows huge promise for density/speed/cost, will add non-linear cost to
SoCs due to non-standard process needed and thus premium for the
entire SoC, not just the MRAM portion. Good idea though. Let's
assume a technology has been identified that does meet this goal for
the assumptions I originally described.
> For an example of MRAM see
> http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=MR2A16A&nodeId=015424
>
> > Answers / Comments for Jim and Hal:
> > a. bad bits: built in ECC would make bad bit transparant to the user
>
> What about a bad row/column select line - or is enough fringe test
> memory included to test all array access lines ?
>
Let's assume the user will not need to be concerned about this as it
will be handled by the fpga vendor both in write-by design, test modes
and testing.
> >
> > b. speed = assume approximately 25ns access time
>
> Any Icc projections ?
> [ROM is usually quite low power]
>
Assume: Icc Standby = ~ 20uA
Icc Active = similar to on-chip/embedded sram (similar sense
amps etc)
> >
> > c. width = flexible, 16/32/64 bit
>
> Why stop at 64 wide ?
> One edge on-chip memory gives is 'free width', and that can
> translate to lower power.
>
There would be a trade-off of standby versus active power reduction
which is dependent on width. Wider = higher standby power but lower
active due to bandwidth.
> > d. secure code storage would come by two assumptions: i) on-chip
> > processor preventing external need to access the memory. ii) readback
> > via JTAG etc of Memory would be programmed as disabled by the user
> >
> > e. on-chip charge pumps require no special external voltage supply
> >
> > f. user application would be able to log/write data to NV memory for
> > storage
>
> Any values/estimates on write times / write energies / Block sizes ?
>
As you allude, NV memory often does have assymettrical write/read
times.
A goal of ours is to support no slower than 50us per write word. At
64bit word, this is 1.28Mkbps. I believe many applications will be
immune from write time consideration since many will preprogram the
data. In circuit logging may consider this but due to OTP and finite
size (~10mbit), I assume 1.28mbps is fine? What do you think? As far
as write power, a goal is <2mW DC per bit. Assume min block sizes of
1 or 2Mbit.
> What about Read-While-Write - which is a common drawback in FLASH.
>
Not sure I understand your read-while-write - does this imply dual
port? IF so, for cost considerations and area optimization, we are
only anticipating single port NV blocks.
> > g. external applications could read NV data too, but you obviously
> > loose security
>
> But selectively, one would hope ?
Security would depend on the data and application?
Of course, the user can implement an DES/AES encryption scheme and use
a NV OTP Key on chip thus enabling quite secure data transfer.
However, if the data is program memory or something that can't be
encryted, then security is less.
>
> >
> > h. OTP = nonerasable
> >
> > i. no tradeoff with NV and Ram like functionality - it would be a
> > standard feature, not swappable block within the silicon family
>
> I was meaning more Software than Hardware - the issue is development,
> and early production, where users need to not have ROM. That may
> mean a bigger device (with the extra SRAM), and a re-compile, or
> external NV memory.
>
> There is also potential here for power saving, as external memory will
> always be width constrained to save pins, plus have all the
> BUS capacitance. Internal ROM can be wider, so use a lower clock
> for the same BUS bandwidth.
>
>
> >
> > j. yes for non secure, it would enable integration into the FPGA of
> > on-board NV data for some applications (mature s/w code for example).
> > Realize that also for some applications, you can create a sense of
> > "virtual" unlimited multiwrite capability. To demonstrate what I mean
> > by Virtual multi-write, I'll use the following example. Let's say
> > that you know you may need to write 10,000 maximum lifetime events at
> > 100 bits data each but do not need to keep history for more than 16
> > events. As a designer, you could buy a tiny block of flash or EEPROM
> > of 1.6kbits and keep writing over the older events. Or, with OTP, you
> > could simply purchase enough OTP memory to store the entire lifetime
> > worth of events. Many applications that store NV data can quantify
> > the lifetime of storage from a practical specification. One example,
> > Televisions need to store user configuration (like: color, tint,
> > favorite channels etc), and need to provide the user with unlimited
> > adjustments of this data. However if you make some assumption, the
> > design can calculate an upper limit of needed storage. For example,
> > lets say 512bits stored, TV life is 20 years. I would venture to
> > guess that if you assumed that data storage would occur Max once a day
> > for each of 20 years, you would be happy to remove the $1 EEPROM from
> > the board as long as the on-chip cost of the NV block was less.
> > 20yr*512b*365days = 7Mbit total
> >
> >
> > Any other creative thoughts on how this could be used would be
> > appreciated.
>
>
> <paste>
> Nicholas Weaver wrote:
> > There is already a more secure mechanism for this: SRAM-based
> > encryption keys used to load encrypted bitfiles. That mechanism can
> > be used to bootstrap a large non-volatile store, with a keystone of
> > the SRAM-based encyption key which is probably significantly harder to
> > reverse/crack than on-chip static bits.
> >
> > Thus the "savings" by putting it on-chip are not security, but the
> > cost savings of not needing a large external Flash PROM.
>
> That's true for bitstreams, but not as easy for external code.
> I can see an application where the user defines a 'Rom BUS Scrambler'
> that is used to load the external memory, and then reverse the scramble
> on read. See the Dallas secure Microcontroller families.
> Boot load code could be 'password zipped', where more time is tolerated
> to unpack, and shift to the external memory.
> So you get medium levels of security, with low cost (?) silicon, and
> not needing too special design flows.
>
> -jg
Article: 73797Nicholas - please see below responses. Thanks. nweaver@soda.csua.berkeley.edu (Nicholas Weaver) wrote in message news:<cjc7cp$qg0$1@agate.berkeley.edu>... > In article <a11322d6.0409271941.e71e499@posting.google.com>, > Guy <guys@altera.com> wrote: > >quick survey... > > > >Would it be of value to provide cheap on-chip one time programmable > >memory in an FPGA like Cyclone II? > >Say 1-10Mbit depending on density. > > Would it slow down the fab or up the cost? See response to Jim - our goal is a standard fab process so cost would simply be driven by it's area. > > >It would be field or user programmable either via a programmer (very > >fast) or by user logic. > > > >It would be very secure (anti-copy) for: > > secure s/w code with on-chip processor > > secure data storage > > configuration data(s) > > etc. > > There is already a more secure mechanism for this: SRAM-based > encryption keys used to load encrypted bitfiles. That mechanism can > be used to bootstrap a large non-volatile store, with a keystone of > the SRAM-based encyption key which is probably significantly harder to > reverse/crack than on-chip static bits. Just to point out, the mechanism you are referring to for SRAM based devices require the programming of NV memory to hold this mentioned security Key. ALthough the encryption is super strong from the data perspective, analyzing the physical NV memory currently being used (EEPROM/EPROM/or FLASH) is not very difficult to extract the Key and thus crack the encrypted data. This NV technology adds manufacturing premium to the whole wafer cost, which is traded off for the value of the feature. We are looking into removing this process premium via the NV technology discussed in the thread. Also, the memory technology being discussed is actually undetectible and thus can not be cracked. Does this sound good to anyone? What applications do users envision needing true anti-piracy/copy of the actual FPGA configuration/functionality? I'll probably start another thread on this. > > Thus the "savings" by putting it on-chip are not security, but the > cost savings of not needing a large external Flash PROM. So, based on above paragraph, savings is realized in both external NV integration onto the chip and ultimate Security of data via encryption and security of the actual Key. Thanks.Article: 73798
I am interested in the compatibility of a VHDL project instantiating a verilog open core, floating point arthmetic block. Is this possible and if it is not is there another way to use a verilog open core inside a VHDL project, a transform of some kind?Article: 73799
How to find a Evaluation board for Xilinx Virtex II Hallo, please can anybody help me? I want to program a Virtex II or Virtex Pro FPGA Chip. Anybody knows an evaluation board to program this chips? I want to make a fast analogue digital converter and I want to make a performance check. Fist I wand to create a program with mathlab and than by hand with VHDL. Please can somebody tell me a good Evalation Board? I have a gadget of 1500$.
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