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"Brad Smallridge" <bradsmallridge@dslextreme.com> wrote in message news:<10og784qui0oc19@corp.supernews.com>... > What does this mean? > > Maximum output required time after clock: 6.060ns > > Is this the time required for the clock edge at the pin > to some register inside the fpga or from the edge to > some signal at an output pin or something else? > > b r a d Howdy Brad, What is the name of the timing parameter that you are referring to, and what vendor/part/speed does it apply to? The name typically looks like Tcksomething. The terms "output" and "required" normally don't go together in timing parameters that I can think of. If you are using Xilinx, the online interactive datasheets usually provide a description of what the parameter means: http://www.xilinx.com/applications/web_ds/index_top.htm Good luck, MarcArticle: 75426
Maybe a more interesting number would be the paid "seats" rather than total including free downloads. I would think this is a fairer representation of actual use of the product. I myself have downloaded many free programs that I rarely or never use. I've also downloaded WebPack even though I use the full Foundation ISE, just so I could run iMPACT on a production computer. Xilinx didn't seem to think about production when they made the install scripts on the ISE CD-ROMs. "Symon" <symon_brewer@hotmail.com> wrote in message news:<2uvnorF2dja35U1@uni-berlin.de>... > "Petter Gustad" <newsmailcomp6@gustad.com> wrote in message > news:87sm7pxov0.fsf@parish.home.gustad.com... > > Well, I did search, but I was searching for number of licenses and > > similar terms. Searching for seats did not occur to me at the time. > > > I was just pulling your leg, Petter! I only knew what to search for because > Austin had posted so recently in a thread I was interested in. I remember > wondering if the other 199,999 designers have as much 'fun' with the > software as I do! ;-) > Good luck with your research, > All the best, Syms.Article: 75427
Eric wrote:
> ERROR:Xst:764 - C:/code.vhd line 22: No default binding for component:
> <SRL16E_1>. Generic <INIT> is not on the entity.
> ERROR: XST failed
>
> If I simply change SRL16E_1 to SRL16E the code passes through with no
> warnings or errors. Anyone know what is going on?
> -- Instantiate the 10 srl16s
> instantiatesrl16s: for i in 0 to 9 generate
> cell : SRL16E_1 port map(
The GENERATE will handle unrolling and labeling
the elaborated processes based on the *single*
label "instantiatesrl16s"
If the instances were outside of a generate,
(they're not) then the designer would supply unique
labels for each one, but cell_1: etc. not SRL16E_1:
The error occurs because SRL16E is in the library
but SRL16E_1 is not.
-- Mike Treseler
Article: 75428Hi, I am doing somethings on a Xilinx FPGA. First, I have a circuit (circuit1) which is quite small than I have some other circuits (circuit2,3,4..) that is very large what I have do is to first implmentat circuit1 on the FPGA after that, I would like to intergrate circuit 1& circuit 2 however, I want the placing of circuit remain the same as if there is no circuit (so that all timing of circuit may preserved) would anyone give me some suggestion on how to achevie it? Thank You Regards GaRYArticle: 75429
Nicolas Matringe wrote:
> Antti Lukats a écrit:
>
>> advice: if you do any serious FPGA verification (with Xilinx silicon) you
>> *MUST* use ChipScope - no way around it. There are other OCI solutions
>> availabe of course also, but I would defenetly consider ChipScope as
>> primary tool.
> I still wonder why Xilinx is *selling* this tool, especially since you
> can't do much serious work without it.
> Altera's SignalTap is free and (IMO) much more user friendly.
It is possible to do serious work without
ChipScope or SignalTap, but it requires synchronous
design and continuous simulation and regression testing.
-- Mike Treseler
Article: 75430"RobJ" <rsefton@abc.net> wrote in message news:<2v0j5kF2goq1sU1@uni-berlin.de>... > I have a design that has compiled fine under ISE for three years. Now ISE > 6.3i sp2 has a problem with the module name "adc". Specifically, it can't > figure out this module's correct place in the design hierarchy. In the > "Sources in Project" window it lists this module at the top of the hierarchy > instead of down under the module in which it is instantiated. > > Adding one character to the module name fixes the problem. Anyone else seen > this? The problem did not exist in ISE 5.2i sp3. That's the last version I > used before 6.3i sp2. > Well I have modules named "cpu" and "alu" under 6.2... I wonder if I should upgrade ;-) Have you tried other three letter combinations? Could it be a reserved word problem rather than a minimum length one?Article: 75431
John wrote: > > I'm the parent poster who started this thread. > > I was over seas this past few days, so I wasn't able to provide the > requested information on power. > > Currently the DSP draws under 130 mA @ 1.25 V (core) and under 80 mA > 3.3V I/O, clocked @ 300 MHz. > > The processing is using less than 15% of the DSP's available horsepower, > which means the functionality should easily fit into an FPGA. Would a > modern FPGA with twelve 6-stage (3 biquad) IIR filters, 32-bit fixed- > point, clocked at 1 MHz be able to significantly beat those power > levels? What about handling a softcore? I would think it would be easier to find power savings by using a lower power DSP than switching to an FPGA. Technology is simply working against you on FPGAs. The newer technologies tend to burn at idle about as much power as you are using running your app. An older FPGA is going to cost more for the amount of logic. Normally DSP moves to FPGAs when you need higher speed than you can get on a single processor. You didn't say which DSP you are using or if it is fixed or floating point. The two cases I would want to distinguish are if you are using one of the very high performance VLIW processors (like the C62xx) or one of the smaller chips like the C5xxx. If using the high end chips you could switch to a lower power chip. Since you are only using 15% of the available DSP processing speed, even if you are already using a low power DSP, you should be able to save power by lowering the clock speed. DSP chips are still CMOS and the dynamic power scales with frequency. If you cut the speed by 4 your power should go down significantly and you will still only be using 60% of the available resources. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 75432
Thomas, The soft FIT rate can be brought down to below 20. Present FPGAs being designed into spacecraft, or already in use (like the Mars Rovers) utilize one of the techniques I alluded to. On Mars, they reconfigure the devices on a scheduled basis to remove any possibility of a soft errors accumulating and upsetting the rovers. If a fault is discovered between reconfigurations, they reconfigure again. For more demanding environments, there is the XTMR tool that we released, which can be used to convert a design to a completely triple modular redundant design. Now no single hard, or soft fault, affects operation (virtually bulletproof). The XTMR tool supports selecting only those areas of the design which are critical to be TMR'd (for example, a critical state machine). Combine the full TMR with scrubbing (which is where you continually reconfigure even while operating), and it becomes bulletproof (highest level of reliability). This is what is considered for low earth orbit applications. So, if the soft error rate is 30 FIT/Mb for the configuration bits (a real number for Virtex II -- includes the SEUPI factor), depending on the size of device, and the techniques chosen, and the goal FIT rate, it becomes a matter of engineering the system to get it down to the desired goal. Contact one of our Mil/Aero FAEs through your local Xilinx representative's office for all of the details. Also please be aware that Xilinx has strong disclaimers regarding any application involving human life. These applications must be reviewed and approved by Xilinx. A good example is someone who wants to use our FPGA in a nuclear power plant better talk to us first. We would not want them to do a simplistic design and not take all possible failure mechanisms into account -- and neither would you! How would like a typical PC to be controlling a nuclear power plant, or the descent of an airplane? Not me! It isn't Intel's or Microsoft's fault if you use a device for an application that it was not intended for (and you have an accident). Austin Thomas Stanka wrote: > Hi, > > Austin Lesea <austin@xilinx.com> wrote: > >>Additionally, there are three known ways to eliminate soft errors as a >>cause of functional failures, so you had better worry about the 'real' >>problem, and not chase red herrings (where in the world does that >>colloquialism come from?). > > > Would you think it is possible to have a design in an Xilinx fpga with > FIT rates below 20 usable in Orbit? > I can't sell my customers a single component with FIT rates of several > hundreds. Even if I could prove, that other failures are dominant over > fpga failures. > > My answer based on the question if an Cpld would be better than an > Fpga in safty critical applications which is not the overall case in > my opinion, because I see no technical advantage of an Cpld, which > might be seen by people thinking Fpgas are always SRAM-based. I would > like to have you proving that even SRAM-based Fpgas are good enough. > > bye ThomasArticle: 75433
Gabor, What you refer to is the number of actual seats of software in use. That is hard for even us to estimate. If we remove all free downloads, that is unfair as many of them are being used to design with our parts. If we remove all software shipped to universities and schools, that is probably fair. I think the point of this is that Xilinx has more seats of software out there than anyone else (in our field). I have heard that at any given moment there are 20,000 or more designs actively being done. If the average number of seats of software to support that is 2 (a conservative number for a million gate design), then that is 40,000 active being used seats of software. Maybe the number is 2.5? 3.5? No one knows. Even the 20,000 is a WAG. Maybe someone here could let us know how many seats of software is typically used per design. It would be an interesting thing to know. There are those that haven't started yet, but are playing with the software, and those that have finished, and have to occasionally go back and fix/add something to the design. Do we count those? I say yes. (Strange to see a thread where I am quoted ... and it really isn't directed to me at all.) Austin Gabor Szakacs wrote: > Maybe a more interesting number would be the paid > "seats" rather than total including free downloads. > I would think this is a fairer representation of > actual use of the product. I myself have downloaded > many free programs that I rarely or never use. > I've also downloaded WebPack even though I use the > full Foundation ISE, just so I could run iMPACT on > a production computer. Xilinx didn't seem to think > about production when they made the install scripts > on the ISE CD-ROMs. > > "Symon" <symon_brewer@hotmail.com> wrote in message news:<2uvnorF2dja35U1@uni-berlin.de>... > >>"Petter Gustad" <newsmailcomp6@gustad.com> wrote in message >>news:87sm7pxov0.fsf@parish.home.gustad.com... >> >>>Well, I did search, but I was searching for number of licenses and >>>similar terms. Searching for seats did not occur to me at the time. >>> >> >>I was just pulling your leg, Petter! I only knew what to search for because >>Austin had posted so recently in a thread I was interested in. I remember >>wondering if the other 199,999 designers have as much 'fun' with the >>software as I do! ;-) >>Good luck with your research, >>All the best, Syms.Article: 75434
John, We have one benchmark which tells us that one of our V4 DSP48 blocks is 5mW/100 MHz. So how many 18X18 + 48 b accumulator blocks do you need to build your filter? If it is 72 (6*12), then we get 72*5 = 360 mW / 100 MHz, or at 1 MHz, 3.6 mW. Looks like a slam dunk win to me. Now, of course there is the static power for the FPGA, and the IO power, but still looks promising. I would do a "what if" using the power prediction spreadsheet on line: http://www.xilinx.com/products/design_resources/design_tool/grouping/power_tools.htm Austin John wrote: > I'm the parent poster who started this thread. > > I was over seas this past few days, so I wasn't able to provide the > requested information on power. > > Currently the DSP draws under 130 mA @ 1.25 V (core) and under 80 mA > 3.3V I/O, clocked @ 300 MHz. > > The processing is using less than 15% of the DSP's available horsepower, > which means the functionality should easily fit into an FPGA. Would a > modern FPGA with twelve 6-stage (3 biquad) IIR filters, 32-bit fixed- > point, clocked at 1 MHz be able to significantly beat those power > levels? What about handling a softcore? > > John.Article: 75435
Hello, I am trying to interface a USB receiver chip with the FPGA. The USB chip can only allow unidirection communications. it just outputs eight bit of data at 12 MHz at each rising edge of the USB clock in brust mode. The scheme I used is simple but my State machine is getting lost and screwing up the count of the counter. some times It works sometimes it does not work! I am using the counter to generate addressess for the Dual port RAM. My VHDL comlplier also ignoring the intialization of the signal Flag1 and I do not know why? The FPGA is running at the clock frequency of 60MHZ. Thanks very much. Regards john signal State : unsigned(7 downto 0); signal nextstate : unsigned(7 downto 0); constant E0 : unsigned(7 downto 0):="00000000"; constant E1 : unsigned(7 downto 0):="00000001"; constant E2 : unsigned(7 downto 0):="00000010"; constant E3 : unsigned(7 downto 0):="00000011"; Signal State1 : unsigned(7 downto 0); Signal nextstate1 : unsigned (7 downto 0); constant F0: unsigned(7 downto 0):="00000000"; constant F1: unsigned(7 downto 0):="00000001"; Signal inc: std_logic:='0'; Signal eq_signal : std_logic:='1'; Signal Reset_A : std_logic; Signal counter_clock : std_logic; Signal USB_port : unsigned ( 7 downto 0); Signal Flag1 : std_logic:='0'; Begin Data_Bus<="00000000000000"; C0: counter port map (Address_bus, Data_in,DPR_CLK,inc,eq_signal,Reset_A); Process(State1,nextstate1) Begin Case State1 is When F0 => Flag1 <='0'; nextstate1 <= F1; When F1 => Flag1 <='1'; nextstate1<=F0; When others => Null; End Case; End Process; ------------------------------------------- Process(USB_CLK,State1,nextstate1) Begin If (USB_CLK'event And USB_CLK='1') Then State1 <= nextstate1; End If; End Process; ------------------------------------------ Process (State,nextstate,SM_DIR,Flag1) Begin Case State is When E0=> Reset_A<='1'; inc<='0'; UBL <='1'; LBL <='1'; CE0 <='1'; CE1 <='0'; Output_Enable<='1'; Read_write <='1'; nextstate<=E1; When E1=> If (Flag1='1')Then Reset_A<='0'; UBL <='1'; LBL <='1'; CE0 <='1'; CE1 <='0'; Output_Enable<='1'; Read_write <='1'; inc<='1'; nextstate<=E2; Else nextstate<=E1; End If; When E2=> Reset_A<='0'; UBL <='0'; LBL <='0'; CE0 <='0'; CE1 <='1'; Output_Enable<='1'; Read_write <='0'; inc<='0'; nextstate<=E3; When E3=> If (Flag1='0')Then Reset_A<='0'; UBL <='0'; LBL <='0'; CE0 <='0'; CE1 <='1'; Output_Enable<='1'; Read_write <='0'; inc<='0'; nextstate<=E1; Else nextstate<=E3; End If; When others => NULL; End case; End Process; Process (DPR_CLK,State,nextstate) Begin If (DPR_CLK'event And DPR_CLK='1') Then State <= nextstate; End If; End Process; End DPR_ARCH;Article: 75436
"Mike Treseler" <mike_treseler@comcast.net> wrote in message news:ktadnfExOLKmERbcRVn-jQ@comcast.com... > Nicolas Matringe wrote: > > Antti Lukats a écrit: > > > >> advice: if you do any serious FPGA verification (with Xilinx silicon) you > >> *MUST* use ChipScope - no way around it. There are other OCI solutions > >> availabe of course also, but I would defenetly consider ChipScope as > >> primary tool. > > > I still wonder why Xilinx is *selling* this tool, especially since you > > can't do much serious work without it. > > Altera's SignalTap is free and (IMO) much more user friendly. > > It is possible to do serious work without > ChipScope or SignalTap, but it requires synchronous > design and continuous simulation and regression testing. > > -- Mike Treseler Hi Mike, I was already wondering who will reply and say that he can do all by simulations only :) Sure it is possible todo it all without the use of any OnChipInstrumentation tools at all. But if you work with external ASIC PHY test chips without even having proper timing specs for those or in case the latency specs for the external phy chips are wrong, then well you just cant simulate what you do not know, you need to see whats happening inside the FPGA. Maybe my experiences are not common and everybody else are very happy with simulations only, but I have found ChipScope and its advanced use of very great value, and it has been able todo many things that would not be possible or would have taken too much time. Like RocketIO has some gotchas, and the simulation models are not good enough, so by doing simulations only you can not get a Serial OOB detect circuitry working. No way. Because rocketio receives random noise with 4 bits repeating pattern when no valid signal is applied to RXP/RXN. This can only be found when catching the actual rocketio recived signal. Attaching ChipScope makes that all visible, you see the problem and you can write ip cores that take care of that, or if you want can write simulation models that the real behavior into account. So I would say my statement says, if you are doing serias FPGA verification for a longer period of time, involving projects with latest technologies (both FPGA and outside components and circuitry) then the "on-chip" instrumentation use is a MUST, this is what I said. Sure there are many very serious project that can be completed very succesfully without ever using OCI. As of CS vs SignalTap vs Identify - all are good tools, but I wish there would be something better. Something that is cross platform and more open in design - ChipScope doesnt not provide option for low clock or clock enable, or and well my wishlist is long. So long it might be easier todo by itself then attempting to use existing tools. AnttiArticle: 75437
Chris Stratton wrote: > > "RobJ" <rsefton@abc.net> wrote in message news:<2v0j5kF2goq1sU1@uni-berlin.de>... > > I have a design that has compiled fine under ISE for three years. Now ISE > > 6.3i sp2 has a problem with the module name "adc". Specifically, it can't > > figure out this module's correct place in the design hierarchy. In the > > "Sources in Project" window it lists this module at the top of the hierarchy > > instead of down under the module in which it is instantiated. > > > > Adding one character to the module name fixes the problem. Anyone else seen > > this? The problem did not exist in ISE 5.2i sp3. That's the last version I > > used before 6.3i sp2. > > > > Well I have modules named "cpu" and "alu" under 6.2... I wonder if I > should upgrade ;-) > > Have you tried other three letter combinations? Could it be a > reserved word problem rather than a minimum length one? That might make some sense. I belive the new Virtex 4 that is supported under 6.3 has an internal ADC. Seems like a bad choice of names to start restricting though. This might be a bug. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 75438
What did your simulation say? Syms. "john" <conphiloso@hotmail.com> wrote in message news:73aa8725.0411050800.1b21084c@posting.google.com... > Hello, > > I am trying to interface a USB receiver chip with the FPGA. The USB > chip can only allow unidirection > communications. it just outputs eight bit of data at 12 MHz at each > rising edge of the USB clock in brust > mode. The scheme I used is simple but my State machine is getting lost > and screwing up the count of the counter. some times It works > sometimes it does not work! > I am using the counter to generate addressess for the Dual port RAM. > My VHDL comlplier also ignoring the intialization > of the signal Flag1 and I do not know why? The FPGA is running at the > clock frequency of 60MHZ. > > Thanks very much. > Regards > john >Article: 75439
that's what i thought ... "Antti Lukats" <antti@case2000.com> wrote in message news:cmdudc$jkf$03$1@news.t-online.com... > "Yttrium" <Yttrium@pandora.be> wrote in message > news:wRuid.11510$Hh1.459812@phobos.telenet-ops.be... > > I'm experimenting with chipscope pro to test it and see if we can use it > in > > our company, so i got the 6.3i demo and am inserting the ILA/ICON and VIO > > and in the PAR report i get: > > > > WARNING:Place - > > The structured logic associated with a shift register could not be > placed > > in > > just dont pay attention to that, it always gives zillion of similar > warnings! > > advice: if you do any serious FPGA verification (with Xilinx silicon) you > *MUST* use ChipScope - no way around it. There are other OCI solutions > availabe of course also, but I would defenetly consider ChipScope as primary > tool. > > Antti > > PS I am using ChipScope to to capture at 3GS/S :) > with rocketIO and custom "analyzer" application, kinda nice to see 3GS/S > Logic analyzer - my primary use was capturing USB HS raw data, V2Pro > rocketio can be directly coupled to USB (receive only)... > >Article: 75440
whizkid wrote: > Hi all, > after syntheising with design Compiler , I manually changed a cell > from the netlist(changed the gate strength)... How can get an SDF file > for this new netlist...using DC > thanks > whizkid Start DC, setup your libraries, read in the verilog netlist file, setup your wireload models (or even the original constraints you used), then you should be able to write out a SDF file. But then, as Petter mentioned, it is better to get SDF output from layout extraction. Output from DC is not very accurate (since wire delay is modeled by wire load model). JoeArticle: 75441
"Chris Stratton" <cs_posting@hotmail.com> wrote in message news:ae2ff5ca.0411050655.5f5c0d91@posting.google.com... > > Have you tried other three letter combinations? Could it be a > reserved word problem rather than a minimum length one? No, I didn't think of that. Changing from 'adc' to 'adc1' fixed it, but I ended up calling it 'adc_if'. I kind of doubt it's a reserved word problem because it did pull the module into the project. It just put it in the wrong place. I'll open a case with Xilinx when I get a minute. RobArticle: 75442
Austin Lesea wrote: > Gabor, > > What you refer to is the number of actual seats of software in use. > > That is hard for even us to estimate. > > If we remove all free downloads, that is unfair as many of them are > being used to design with our parts. > > If we remove all software shipped to universities and schools, that is > probably fair. Not to those at Univ or schools :) > > I think the point of this is that Xilinx has more seats of software out > there than anyone else (in our field). > > I have heard that at any given moment there are 20,000 or more designs > actively being done. If the average number of seats of software to > support that is 2 (a conservative number for a million gate design), or, one designer could be responsible for 100+ designs ( 0.01 x ) ? > then that is 40,000 active being used seats of software. Maybe the > number is 2.5? 3.5? No one knows. Even the 20,000 is a WAG. So what did your comment "We have 200,000+ seats of software out there," actually mean ? Did that mean "over the last 10 years, over 200,000 downloads have been started ", or does this also include a factor, like for Magazine Circulation, where they count sales, then multiply by a re-read factor to get a better sounding number for advertising sales ? What about CPLD vs FPGA users - does that matter ? > > Maybe someone here could let us know how many seats of software is > typically used per design. It would be an interesting thing to know. > > There are those that haven't started yet, but are playing with the > software, and those that have finished, and have to occasionally go back > and fix/add something to the design. Do we count those? I say yes. A better metric might be "Number of Active Customers" [Who have brought one or more devices in the last 12 months]. That could sensible split FPGA and CPLD. That is easy to derive from direct and disti info, and gives a reasonable minimum for Alive SW Seats -jgArticle: 75443
I want to realize an EPP interface using Altera FPGA Cyclone (read and write operation) but I have some synchronization problems. I want to sample datas from a 4 bits chip, storing them in a ZBT SRAM memory (Flow trought) and later acquiring them by parallel port. the chip works at 10MHz but the pll on board can't divide input clock of 20MHz for 2. How can I divide the frequency? thanks. Does anyone do something like that?Article: 75444
rickman wrote: > John wrote: > >>I'm the parent poster who started this thread. >> >>I was over seas this past few days, so I wasn't able to provide the >>requested information on power. >> >>Currently the DSP draws under 130 mA @ 1.25 V (core) and under 80 mA >>3.3V I/O, clocked @ 300 MHz. >> >>The processing is using less than 15% of the DSP's available horsepower, >>which means the functionality should easily fit into an FPGA. Would a >>modern FPGA with twelve 6-stage (3 biquad) IIR filters, 32-bit fixed- >>point, clocked at 1 MHz be able to significantly beat those power >>levels? What about handling a softcore? > > > I would think it would be easier to find power savings by using a lower > power DSP than switching to an FPGA. Technology is simply working > against you on FPGAs. The newer technologies tend to burn at idle about > as much power as you are using running your app. An older FPGA is going > to cost more for the amount of logic. Normally DSP moves to FPGAs when > you need higher speed than you can get on a single processor. > > You didn't say which DSP you are using or if it is fixed or floating > point. <snip> ..and I would add the Usage Duty Cycle. As Rick says, FPGAs static Icc is not good, and trending the wrong way. So if your app has to wait any time between runs, it can change the whole decision path. -jgArticle: 75445
Jim, I do not know the interval, but it is certainly not what we shipped in the last 20 years! I believe it was either shipped in a year, or a quarter, but maybe someone else inside Xilinx will let me know. I was reading press releases as an engineer just like you were. I already gave you the WAG of 20,000 designs happening at the present moment in time, and that WAG is primarily from disti's, rep's, factory, etc. Now how much stock can you put in numbers that you get from people who get paid to report big numbers? Are they being completely honest with us? I have to assume so. Are the customers being honest with their reps? But, all must be taken with a very critical eye. Regardless, we have a lot of folks using our tools and parts (as shown by our quarterly fiscal results). Other folks keep track of overall market share, but the ones that do tell me that our share continues to grow. Others sometimes have a good quarter in growth (get ahead of us by a 1/2% Q-Q), but overall, we are still doing the kind of job that keeps engineers voting with their designs being done with Xilinx parts. That is fine with me, and we always remain open and willing to improve to make the engineer's life and their products even better. Austin Jim Granville wrote: > Austin Lesea wrote: > >> Gabor, >> >> What you refer to is the number of actual seats of software in use. >> >> That is hard for even us to estimate. >> >> If we remove all free downloads, that is unfair as many of them are >> being used to design with our parts. >> >> If we remove all software shipped to universities and schools, that is >> probably fair. > > > Not to those at Univ or schools :) > >> >> I think the point of this is that Xilinx has more seats of software >> out there than anyone else (in our field). >> >> I have heard that at any given moment there are 20,000 or more designs >> actively being done. If the average number of seats of software to >> support that is 2 (a conservative number for a million gate design), > > > or, one designer could be responsible for 100+ designs ( 0.01 x ) ? > >> then that is 40,000 active being used seats of software. Maybe the >> number is 2.5? 3.5? No one knows. Even the 20,000 is a WAG. > > > So what did your comment "We have 200,000+ seats of software out > there," actually mean ? > > Did that mean "over the last 10 years, over 200,000 downloads have been > started ", or does this also include a factor, like for Magazine > Circulation, where they count sales, then multiply by a re-read factor > to get a better sounding number for advertising sales ? > > What about CPLD vs FPGA users - does that matter ? > >> >> Maybe someone here could let us know how many seats of software is >> typically used per design. It would be an interesting thing to know. >> >> There are those that haven't started yet, but are playing with the >> software, and those that have finished, and have to occasionally go >> back and fix/add something to the design. Do we count those? I say yes. > > > A better metric might be "Number of Active Customers" [Who have brought > one or more devices in the last 12 months]. That could sensible split > FPGA and CPLD. > That is easy to derive from direct and disti info, and gives a > reasonable minimum for Alive SW Seats > > -jg >Article: 75446
On the nice nifty architecture-wizard tool, from within Xilinx Foundation's project manager, is it possible to create verilog instantiation templates rather than VHDL? The docs suggest no, but I'm curious if there is something I'm not seeing. -- Nicholas C. Weaver. to reply email to "nweaver" at the domain icsi.berkeley.eduArticle: 75447
I have a board using XC2VP20-6FF896c and two xc18v04 proms, seems Jtag have problem as: 1) Whenever there is a free-runnimg clock, the Jtag config fails. when the free-runnimg clock is turned off, config successfully. 2) Maseter seral mode never work, check cclk, it is alway there. Could clock interference affect Jtag configuration? but I use the same design with virtex E, there is no problem. Appreciate any help on this problem.Article: 75448
> As of CS vs SignalTap vs Identify - all are good tools, but I wish there > would be something better. Something that is cross platform and more open in > design - ChipScope doesnt not provide option for low clock or clock enable, > or and well my wishlist is long. So long it might be easier todo by itself > then attempting to use existing tools. > > Antti Did you check out DiaLite from Temento Systems (www.temento.com)? /danielArticle: 75449
Naimesh wrote: > Hello, > > I am doing a project in Xilinx CPLD XC9572 usign Xilix ISE 6.2i. > > I am observing a illogical problem. > > All my flip flops are negative edge triggered but some how even if the > edge on the clock comes cpld doesnt recognize it. > > So I made a simple flip flop where at Power On Reset I am clearing it > and at the edge of the clock I am setting it to 1. > > Even then I was not able to see that test signal as 1. > > When I converted the test flip flop from -ve edge to +ve edge I was > getting proper result. > > After that I converted all other signals to +ve edge triggered and I > observed same problem as was in -ve edge trigerred.even in test Flip > Flop. > > Again I converted just the Test flip flop to -ve edge and kept all > other +ve edge and again proper results. > > Now I want to buffer the clock as I think this is a problem of loading > of clock. > > but as if I write > > Clock1 <= Clock; > > xst removes it so how can I tell xst to not remove that. > any other suggestions for problem I m observing. You might write Clock1: out std_logic; Clock: in std_loigc; New_clock: in std_logic; ... Clock1 <= not (clock); ... then use New_clock to drive your Flip-flops, and connect Clock1 to New_clock on your development board. VAX, 9000 > > Thank u > Naimesh
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