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Messages from 76950

Article: 76950
Subject: Re: Xilinx speed grading
From: Austin Lesea <austin@xilinx.com>
Date: Thu, 16 Dec 2004 07:45:23 -0800
Links: << >>  << T >>  << A >>
B,

Your analogies are so much fun!

Sounds like we are in "violent agreement."

Austin

B. Joshua Rosen wrote:
> On Wed, 15 Dec 2004 11:11:26 -0800, Austin Lesea wrote:
> 
> 
>>"everything except the squeal"?
> 
> The expression "everything except the squeal" comes from Upton Sinclair's
> book The Jungle about the Chicago Stockyards. The Jungle caused Congress
> to pass the 1906 Clean Food and Drug act that created the FDA.
> 
> 
>>Now that is pretty graphic.
>>
>>
>>EasyPath(tm) is no different that selling an FPGA that has a laser fuse
>>blown to replace a defective column of logic.
>>
>>Gee, I wonder who does that with every part they sell?
>>
>>Get over it:  a few bad memory bits (out of 20 million) is not a
>>"slightly defective" part -- it is >99.99985% perfect.
>>
>>Austin
> 
> 
> I didn't say there was anything wrong with EasyPath it's a good idea. I
> was just making the point that no chip company is going to throw out a
> part if there is a way to sell it. EasyPath allow you to sell parts that
> work with specific bit streams but not with every bit stream. The customer
> benefits by getting a much lower price at the cost of giving up the
> flexibility of being able to drop in a different bit stream. The OP was
> asking about parts that are slower than the slowest speed grade, I was
> saying if there were any significant number of parts that were failing
> to meet the lowest speed grade you would simply add a lower grade. It
> would be bad business to do anything else. The farmstand on my corner does
> the same thing. At the end of August they sell cases of Tomatoe seconds
> for $6 a case. The tomatoes are fine for sauces, but they are ugly enough
> that you don't want to put them in a salad. I buy a case of EasyPath
> tomatoes every year and use them to make a years supply of spaghetti sauce.

Article: 76951
Subject: Re: Xilinx speed grading
From: Austin Lesea <austin@xilinx.com>
Date: Thu, 16 Dec 2004 08:04:06 -0800
Links: << >>  << T >>  << A >>
Symon,

Why are fuses so much better?  They cost in area (redundant circuits 
which drive down yield), and they cost in test (have to blow them).

So the customer pays twice on every part for perfection more than they 
would for a non-redundant part, and certainly they pay more for an 
EasyPath(tm) part.

The fact that EasyPath parts pass a full qualification program proves 
their reliability, so that is not an issue either.

We do test 100% of the LUTs, IOs, clock resources, and some other 
features on every EasyPath part.  That is how we just introduced the 
'ECO feature'.  If you need to change IO strength (very common), or 
change the logic in a LUT (that darned inversion you forgot), you can do 
so without any changes or worries to the test program.

If worst comes to worst, and you need to change something not tested, it 
turns out the probabilities that the new pattern will work are amazingly 
high.  We will work with you to make the change, and tell you what your 
exposure is for parts already shipped (to operate with the new pattern).

Can't do that with an ASIC -- they are all garbage immediately for the 
smallest error!

That is why 'HardtoCopy' is what we abandoned ('Hardwire') years ago: 
no profit, no margins, sucks engineering resources dry, immense costs, 
tremendous headaches, unhappy customers -- hey that sounds just like the 
ASIC business!

The structured ASIC business has turned out to be a big yawn - so small 
$ and units that it is hard to see it on any charts.  Who cares? 
Non-story.  The finance folks have already written it off, and moved on 
to the next shell and pea game.

Getting back to EP, it turns out that most failing parts (restricted 
info for exact number) are bad because of one or two config bits.  Also, 
if the volume is high enough for the EasyPath customer, we start wafers 
for just that customer, and test to their pattern.  We would never know 
if these are perfect parts, or not, and we wouldn't care either (as we 
saved the requisite amount of money to offer the parts at the price we 
do).  Just like an ASIC, except it has a higher test coverage, and lower 
PPM failure number!

"Dodgy" makes it sound like we are dumpster diving.

In reality, it is a very clever, very efficient, very useful, very cost 
effective product flow.

I think that certain frustrated competitors have promoted the 'EasyPath 
=  Flawed Goods' FUD story out of desparation.

When one can introduce a whole new and useful product (profitable, too) 
line with $0 of IC design engineering (no tapeouts, no design), that has 
got to hurt!

Austin



Symon wrote:

> Hi Austin,
> It would seem to me that the laser fuse method is a much better idea than 
> EasyPath(tm). As you say in another post, we live in an errored world! With 
> the laser fuse, yield is higher, price is lower. With EasyPath(tm), you 
> scrabble around in the defect bin to find dodgy parts which fit the user's 
> design. The design then must remain unchanged, because a recompile might hit 
> a bad bit in your installed base. Maybe you should rename it 
> DifficultPath(tm)? Or am I missing something? No worse than an ASIC, I 
> guess.
> Syms.
> "Austin Lesea" <austin@xilinx.com> wrote in message 
> news:cpq28u$9kt2@cliff.xsj.xilinx.com...
> 
>>EasyPath(tm) is no different that selling an FPGA that has a laser fuse 
>>blown to replace a defective column of logic.
>>
>>Gee, I wonder who does that with every part they sell?
> 
> 
> 

Article: 76952
Subject: Re: Digital clock synthesis
From: glen herrmannsfeldt <gah@ugcs.caltech.edu>
Date: Thu, 16 Dec 2004 10:07:18 -0800
Links: << >>  << T >>  << A >>


Hal Murray wrote:

(someone wrote)
>>Make the accumulator overflow at 100,000,000 rather than at 134217728.

(snip)
> I still don't see how to easily implement "overflow" at an
> arbitrary value.  Time to sleep on it.

On overflow load 34117728 into the counter instead of 0.

-- glen


Article: 76953
Subject: New HDLmaker release
From: "B. Joshua Rosen" <bjrosen@polybus.com>
Date: Thu, 16 Dec 2004 15:04:16 -0500
Links: << >>  << T >>  << A >>
I've uploaded a new release of HDLmaker, revision 7.3.3. HDLmaker is an
open source Verilog hierarchy builder for building FPGAs (especially
Xilinx) and ASICs. It creates projects files and scripts for all of the
popular simulation and synthesis tools including XST, Synplify, Precision,
NCsim, VCS, ModelSim. VHDL support has be deprecated in HDLmaker. VHDL
components may be instantiated in Verilog designs but it is no longer
recommended that you use VHDL as the target language as many of the new
features are Verilog only.

http://www.polybus.com/hdlmaker/users_guide/index.htm



Article: 76954
Subject: Re: Exportability of EDA industry from North America?
From: EDA wannabe <No@Email.Address.com>
Date: Thu, 16 Dec 2004 16:37:38 -0500
Links: << >>  << T >>  << A >>
Phil Tomson wrote:
>
> Probably the best bet if you want an EDA job in the US is to get a PhD,
> but even some of the highlevel research is starting to move over.
>
> It's not a pretty picture.  The standard of living will likely have to
> fall a good bit in the US before you see these kinds of jobs move back.


I understand that there must be some level of parity before the jobs start
flowing back.  Regarding the comment about a Ph.D., I am actually speaking
about the outlook for someone  completing an advance degree.  Typically,
though, the relevance of even R&D tends to follow the prevalence of the
associated application, so if the industry practice moves elsewhere, the
relevance and value of the R&D is likely to follow (I surmise).  So I'm
wondering how much the R&D in this area will likely be eroded in North
America.

As well, the angle I'm interested in is that of combinatoric algorithms in
mapping applications to prefabricated systems-on-chip, or configurable
platforms.  That might be nonstandard enough to maintain a presence in
North America.  It all depends on the experience and grounding of
alternative, more economic countries in this knowledge area. Especially in
terms of university activity.

I would also imagine that the more niche-like the area, the less attractive
it is for developing countries.  It seems like the road to development
typically tries to capitalize on large anticipated markets for a particular
skill set or technology.  I wonder how much this will protect against
erosion of R&D in North America.  Of course, any opinions will necessarily
be highly speculative, but it would be interesting to hear rationales for
them.

Aside from the doom and gloom of predicting the potential decline of an
industry and area of R&D, I wonder about the likely challenges in transferring
the associated experience into other areas.  Combinatoric problems are a
very general label, and I'm sure there is much crucial, domain-specific knowledge
to make such a skill set valuable.


Article: 76955
Subject: Re: Inferring SRLs with INIT value
From: Kevin Neilson <kevin_neilson@removethiscomcast.net>
Date: Thu, 16 Dec 2004 17:07:45 -0700
Links: << >>  << T >>  << A >>
Ray Andraka wrote:
> Kevin Neilson wrote:
> 
>> Kevin Neilson wrote:
>>
>>> Synplify now reads the defparam 'INIT' used for instantiated SRLs, so 
>>> you can initialize the value of the SRL16 for both simulation and 
>>> synthesis with a single defparam.  However, I'm wondering if there is 
>>> a way to infer SRL16 Johnson rings or shift registers with an initial 
>>> value.  This can be done with registers by setting the 'reset' value 
>>> of the register to the desired value, but you can't have a reset 
>>> clause with SRLs or they won't get inferred as SRLs.  It would be 
>>> nice to be able to infer a Johnson ring because if you want to 
>>> instantiate SRLs you need to instantiate one for each 16 bits of the 
>>> register which makes it hard to parameterize it.
>>
>>
> No, you pretty much have to instance the SRLs to take advantage of 
> putting the inits on them.  You might be able to do it from the UCF (I 
> never tried that), but that makes the simulation not match the 
> hardware.  That said, be careful using just the SRL as a johnson  
> counter, because there is no way to reset it other than 
> reconfiguration...ie, it won't recover from an upset.  Ken Chapman kind 
> of glosses over that fact in his dissertation on SRL16's.
> 
>> I also have another question:  I put a register on the output of the 
>> SRL to register the output.  I assumed that the register would be 
>> placed in the same slice as the SRL, but the placer puts them in 
>> different CLBs. Why would it do that?  -Kevin
> 
> 
> 
> Probably doing that because you're using the reset on the register.  The 
> reset pin is not available if you are using the SRL in the same half-slice.
> 
I didn't know that about the SRL--I guess I can leave the reset off of 
the flop.  It seems weird to do so but I guess it won't hurt anything. 
How does the synthesizer know what the initial state is if there is no 
reset clause?
-Kevin

Article: 76956
Subject: PCI doubt
From: "Shreyas Kulkarni" <shyran@gmail.com>
Date: 16 Dec 2004 17:17:57 -0800
Links: << >>  << T >>  << A >>
hi there,

i have a (probably very fundamental) doubt regarding PCI -
what is the difference between a PCI master, arbiter and initiator?
they all look same to me.

TIA,
Shreyas


Article: 76957
Subject: Re: JTAG vs. Passive Serial Config speed
From: "Jeroen" <jayjay.1974@xs4all.nl>
Date: Fri, 17 Dec 2004 03:16:19 +0100
Links: << >>  << T >>  << A >>

"Kolja Waschk" <kawk@20.12.2004.telos.info> wrote in message
news:pan.2004.12.15.16.00.52.620341@20.12.2004.telos.info...
> Hi
>
> Is there a significant difference in the time it takes to download a
> configuration to an Altera Cyclone (EP1C6) using JTAG, vs. the Passive
> Serial Configuration method?
>
> In January, Greg Steinke here mentioned a program to program a Serial
> Configuration Device (e.g. EPCS1) _through_ a Cyclone, with the
> programmer attached only to the Cyclone's JTAG port. It was beta, then.
> Is this option available in e.g. Quartus today, or even available as
> source code (a "combined" Jrunner + Srunner?).
>
> Thanks for info
> Kolja
>

yes, the new Quartus can now program an EPCS1/4 through the FPGA. You have
to convert the SOF file by using the 'Convert Programming Files' in the
Files Menu. Select JTAG Indirect (*.JIC). Then add the necessary SOF file.
Open the programmer and use the generated JIC file. Works excellent, and
quite speedy. It's takes around one minute depending on the size of the SOF
file. It even works with multiple devices. Don't forget to check the
checkbox for EPCS in the programmer, it defaults to off.

This was previously done using the ByteJammer software, which is extremely
slow and cumbersome. Basically because the JAM file is some kind of simple
BASIC looking language (STAPL) that's being interpreted runtime.

Configuring a device over JTAG at full speed (10MHz) takes only half a
second or so. That's with hardware assisted JRunner software running on a
NIOS.

Jeroen



Article: 76958
Subject: Re: Xilinx FIFO
From: "Peter" <peter@xilinx.com>
Date: 16 Dec 2004 21:34:12 -0800
Links: << >>  << T >>  << A >>
Symon wrote:
> I just read the V4 user guide, UG070. It seems the really tricky bit
is
> making sure the FULL signal goes high when the FIFO is full. Not one
write
> clock cycle later. ;-)
> Cheers, Syms.
>
That's unfortunately true. Came too late for me to catch...
The user should select the almost FULL output instead.
FULL is not as critical a signal as EMPTY. A well-designed FIFO system
should never go FULL, and the exact "full-ness" level is not so
important. Hardly anybody cares whether the FIFO can hold 1024, 1023 or
1020 entries.
But the user often really wants to empty the FIFO content completely.
That's why reliable EMPTY decoding is more important than exact FULL
decoding.
Nevertheless, it's a cosmetic flaw that will be fixed next time around.
Peter Alfke   (FIFO is my middle name)


Article: 76959
Subject: Re: altera cyclone and fifo synchronisation
From: Ben Twijnstra <btwijnstra@gmail.com>
Date: Fri, 17 Dec 2004 09:58:07 GMT
Links: << >>  << T >>  << A >>
Hi Peter,

> Otherwise: Welcome to the end of the alphabet...

Hmmm... interesting... so you joined Zilog during the past week? ;-)

Ben


Article: 76960
Subject: Re: Inferring SRLs with INIT value
From: Ray Andraka <ray@andraka.com>
Date: Fri, 17 Dec 2004 08:01:07 -0500
Links: << >>  << T >>  << A >>
Kevin Neilson wrote:

>>
>> Probably doing that because you're using the reset on the register.  
>> The reset pin is not available if you are using the SRL in the same 
>> half-slice.
>>
> I didn't know that about the SRL--I guess I can leave the reset off of 
> the flop.  It seems weird to do so but I guess it won't hurt anything. 
> How does the synthesizer know what the initial state is if there is no 
> reset clause?
> -Kevin

The synthesizer doesn't 'know' the initial state.  The initial state 
defaults to '0' in Xilinx.  In order to change that to a '1' you either 
need an explicit (pre)set on the flip-flop (which you can't do if  it is 
to share a slice half with an SRL16), or you need to put an INIT=S 
attribute on the flip-flop.  That, I think, still requires the ff to be 
instantiated rather than inferred.

-- 
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  

 "They that give up essential liberty to obtain a little 
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 76961
Subject: Re: Digital clock synthesis
From: Ray Andraka <ray@andraka.com>
Date: Fri, 17 Dec 2004 08:09:43 -0500
Links: << >>  << T >>  << A >>
Hal Murray wrote:

>>With a 27-bit accumulator clocked at 100 MHz, you can generate any
>>integer Hz frequency, but with 5 ns jitter.
>>    
>>
>
>Thanks, but that looks like a variation on what I was asking about.
>
>I can't see how to make a 1 Hz output with a 27 bit phase accumulator
>running at 100 MHz.  Works great if I have a 134.217728 MHz clock.
>
>If I have a 27 bit accumulator and I add 1 each cycle with a
>100 MHz clock, I get 0.745 Hz.  Adding 2 makes 1.490 Hz.
>
>Is there some variation of the simple phase accumulator that I
>haven't stumbled into yet?  If so, what's the magic word?
>
>  
>
You need more than 27 bits.  With 27 bits, the resolution is 0.745 Hz.  
If you extend it to 32 bits, then you have a frequency resolution of 
0.02 Hz and can therefore get much closer to your 1Hz setting.  In that 
case, setting the increment value to 43 will yield 1.002 Hz.  Increasing 
the width of the accumulator improves the frequency resolution.  Note 
that the jitter is still one cycle of your master clock, so although the 
frequency resolution is improved, your jitter is constant.

-- 
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  

 "They that give up essential liberty to obtain a little 
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 76962
Subject: Re: Inferring SRLs with INIT value
From: "Marc Randolph" <mrand@my-deja.com>
Date: 17 Dec 2004 05:10:10 -0800
Links: << >>  << T >>  << A >>

Kevin Neilson wrote:
> Ray Andraka wrote:
> >> Kevin Neilson wrote:
> >>
> >>> Synplify now reads the defparam 'INIT' used for instantiated
SRLs, so
> >>> you can initialize the value of the SRL16 for both simulation and

> >>> synthesis with a single defparam.  However, I'm wondering if
there is
> >>> a way to infer SRL16 Johnson rings or shift registers with an
initial
> >>> value.  This can be done with registers by setting the 'reset'
value
> >>> of the register to the desired value, but you can't have a reset
> >>> clause with SRLs or they won't get inferred as SRLs.  It would be

> >>> nice to be able to infer a Johnson ring because if you want to
> >>> instantiate SRLs you need to instantiate one for each 16 bits of
the
> >>> register which makes it hard to parameterize it.
> >>
> >>
> > No, you pretty much have to instance the SRLs to take advantage of
> > putting the inits on them.  You might be able to do it from the UCF
(I
> > never tried that), but that makes the simulation not match the
> > hardware.  That said, be careful using just the SRL as a johnson
> > counter, because there is no way to reset it other than
> > reconfiguration...ie, it won't recover from an upset.  Ken Chapman
kind
> > of glosses over that fact in his dissertation on SRL16's.
> >[...]
> > Probably doing that because you're using the reset on the register.
The
> > reset pin is not available if you are using the SRL in the same
half-slice.
>
> I didn't know that about the SRL--I guess I can leave the reset off
of
> the flop.  It seems weird to do so but I guess it won't hurt
anything.
> How does the synthesizer know what the initial state is if there is
no
> reset clause?

Howdy Kevin,

To summarize what Ray said: the tools will see and use the INIT clause,
but you may have to instantiate the SRL in order to use the INIT.  And
after the FPGA is loaded and running, there is no way to re-initialize
the SRL without reloading the whole part - UNLESS you put a special
reset circuit in front of your SRL to shift in a known value... which
might take up more resources than keeping the shift register in flops
to begin with.

Have fun,

   Marc


Article: 76963
Subject: Re: Digital clock synthesis
From: Ray Andraka <ray@andraka.com>
Date: Fri, 17 Dec 2004 08:11:57 -0500
Links: << >>  << T >>  << A >>
Symon wrote:

>Hal,
>Make the accumulator overflow at 100,000,000 rather than at 134217728.
>HTH, Syms.
>  
>
No, that doesn't work.  The phase accumulator depends on modularity of 
the number system, and by truncating the count like that you destroy the 
modularity.  The way to get there is to extend the width of the 
accumulator and select the appropriate constant based on the accumulator 
width.

-- 
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  

 "They that give up essential liberty to obtain a little 
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 76964
Subject: Re: Open source FPGA EDA Tools
From: Marius Vollmer <marius.vollmer@uni-dortmund.de>
Date: Fri, 17 Dec 2004 14:48:08 +0100
Links: << >>  << T >>  << A >>
pant_nagar@tatanagar.com writes:

> i attended gospl forum recently. It was mentioned that Complete
> software toolset is open along with h/w architecture. All device
> information required for different software subsystems will be
> available.

That would be very nice indeed, especially when there are devices
available that comply with that architecture.

What I am quite annoyed at right now is that ST starts sooo cautiously
with the GOSPL project.  You have to apply for a license and they
don't let you read the license document before being approved to be
allowed to sign it.

They should just put up all the stuff they have for download, with
mainstream Free licenses for the software and documentation.  No
restrictions should be placed on independent devices that comply with
the architecture.

Article: 76965
Subject: Re: Digital clock synthesis
From: "Symon" <symon_brewer@hotmail.com>
Date: Fri, 17 Dec 2004 05:48:56 -0800
Links: << >>  << T >>  << A >>
Hi Ray,
That's what I meant. Make the accumulator modulo 100,000,000. I didn't 
mention truncation, I wrote overflow. In fact, I'm struggling to understand 
what you think I meant that would mean truncation. What did you mean?
Extending the width of the accumulator doesn't help you get *exactly* the 
right frequency if you want 1Hz steps from a 100MHz clock, which is what Hal 
was talking about. You just get closer and closer approximations as the 
accumulator gets wider. The maximum jitter over the frequency output range 
is determined by the clock rate.
Cheers, Syms.

"Ray Andraka" <ray@andraka.com> wrote in message 
news:dUAwd.1205$Tf5.139@lakeread03...
> Symon wrote:
>
>>Hal,
>>Make the accumulator overflow at 100,000,000 rather than at 134217728.
>>HTH, Syms.
>>
> No, that doesn't work.  The phase accumulator depends on modularity of the 
> number system, and by truncating the count like that you destroy the 
> modularity.  The way to get there is to extend the width of the 
> accumulator and select the appropriate constant based on the accumulator 
> width.
>



Article: 76966
Subject: Re: Digital clock synthesis
From: "Symon" <symon_brewer@hotmail.com>
Date: Fri, 17 Dec 2004 05:52:23 -0800
Links: << >>  << T >>  << A >>
Why not make the accumulator work modulo 100,000,000? You get exactly 1Hz 
and 1Hz steps. Who wants 1.002 when you can easily have 1.0000000000 with a 
smaller solution?
Cheers, Syms.
"Ray Andraka" <ray@andraka.com> wrote in message 
news:aSAwd.1203$Tf5.1052@lakeread03...
> You need more than 27 bits.  With 27 bits, the resolution is 0.745 Hz.  If 
> you extend it to 32 bits, then you have a frequency resolution of 0.02 Hz 
> and can therefore get much closer to your 1Hz setting.  In that case, 
> setting the increment value to 43 will yield 1.002 Hz.  Increasing the 
> width of the accumulator improves the frequency resolution.  Note that the 
> jitter is still one cycle of your master clock, so although the frequency 
> resolution is improved, your jitter is constant.
>



Article: 76967
Subject: Re: Digital clock synthesis
From: "Symon" <symon_brewer@hotmail.com>
Date: Fri, 17 Dec 2004 05:57:14 -0800
Links: << >>  << T >>  << A >>
Hmmm, maybe not smaller as you need a subtraction as well as an 
accumulation. I need to think about that when I get time. But certainly more 
accurate....
"Symon" <symon_brewer@hotmail.com> wrote in message 
news:32g6k6F3ltb5iU1@individual.net...
> Why not make the accumulator work modulo 100,000,000? You get exactly 1Hz 
> and 1Hz steps. Who wants 1.002 when you can easily have 1.0000000000 with 
> a smaller solution?
> Cheers, Syms.
> "Ray Andraka" <ray@andraka.com> wrote in message 
> news:aSAwd.1203$Tf5.1052@lakeread03...
>> You need more than 27 bits.  With 27 bits, the resolution is 0.745 Hz. 
>> If you extend it to 32 bits, then you have a frequency resolution of 0.02 
>> Hz and can therefore get much closer to your 1Hz setting.  In that case, 
>> setting the increment value to 43 will yield 1.002 Hz.  Increasing the 
>> width of the accumulator improves the frequency resolution.  Note that 
>> the jitter is still one cycle of your master clock, so although the 
>> frequency resolution is improved, your jitter is constant.
>>
>
> 



Article: 76968
Subject: Re: PCI doubt
From: Kolja Sulimma <news@sulimma.de>
Date: Fri, 17 Dec 2004 15:00:41 +0100
Links: << >>  << T >>  << A >>
That is a very good question, because at least my PCI standard Rev 2.1 
has none of these in the index, and only lists master in the Glossary.
master = an agent that initiates a bus transaction
agent  = an entity that operates on a computer bus
Entity and bus are not defined, but an entity is apparently a bus device
bus device = A bus device can be either a master or a target
I love standards ;-)

Seriously,
Master and Initiator are the same.
An arbiter is something completely different. It exists once per bus and 
resolves confliicts if multiple masters request acces to the bus.
See the REQ# and GNT# signals of each master are connected to the arbiter.

Kolja Sulimma




Shreyas Kulkarni wrote:
> hi there,
> 
> i have a (probably very fundamental) doubt regarding PCI -
> what is the difference between a PCI master, arbiter and initiator?
> they all look same to me.
> 
> TIA,
> Shreyas
> 

Article: 76969
Subject: Re: Exportability of EDA industry from North America?
From: ptkwt@aracnet.com (Phil Tomson)
Date: 17 Dec 2004 14:28:43 GMT
Links: << >>  << T >>  << A >>
In article <41C20022.7338460C@Email.Address.com>,
EDA wannabe  <No@Email.Address.com> wrote:
>
>Aside from the doom and gloom of predicting the potential decline of an
>industry and area of R&D, I wonder about the likely challenges in transferring
>the associated experience into other areas.  Combinatoric problems are a
>very general label, and I'm sure there is much crucial, domain-specific
>knowledge
>to make such a skill set valuable.

I am beginning to think along these lines as well.  Areas like datamining 
or bioinformatics will likely dwarf EDA in terms of revenue (and thus 
more jobs will be available in those areas).  It might be 
better to think of Google instead of [Synopsys|Mentor|Cadence|etc] as a 
potential employer. I also am a grad student (with a lot of years of 
'real-world' experience) and whereas I was aiming toward EDA in my 
studies, now I'm starting to think about branching out into a different 
area that might be growing faster... but I'm still very interested in EDA.

Phil 


Article: 76970
Subject: Re: Digital clock synthesis
From: "John_H" <johnhandwork@mail.com>
Date: Fri, 17 Dec 2004 16:29:25 GMT
Links: << >>  << T >>  << A >>
The modulo 100M is just adding either the phase step to the accumulator
(most of the time) or 2^27-100M plus the phase step to the accumulator (each
time the accumulator overflows).  Adding a selected one of two values can be
done within the Xilinx carry chain at no cost.

"Symon" <symon_brewer@hotmail.com> wrote in message
news:32g6taF3kks5aU1@individual.net...
> Hmmm, maybe not smaller as you need a subtraction as well as an
> accumulation. I need to think about that when I get time. But certainly
more
> accurate....

> "Symon" <symon_brewer@hotmail.com> wrote in message
> news:32g6k6F3ltb5iU1@individual.net...
> > Why not make the accumulator work modulo 100,000,000? You get exactly
1Hz
> > and 1Hz steps. Who wants 1.002 when you can easily have 1.0000000000
with
> > a smaller solution?
> > Cheers, Syms.

> > "Ray Andraka" <ray@andraka.com> wrote in message
> > news:aSAwd.1203$Tf5.1052@lakeread03...
> >> You need more than 27 bits.  With 27 bits, the resolution is 0.745 Hz.
> >> If you extend it to 32 bits, then you have a frequency resolution of
0.02
> >> Hz and can therefore get much closer to your 1Hz setting.  In that
case,
> >> setting the increment value to 43 will yield 1.002 Hz.  Increasing the
> >> width of the accumulator improves the frequency resolution.  Note that
> >> the jitter is still one cycle of your master clock, so although the
> >> frequency resolution is improved, your jitter is constant.



Article: 76971
Subject: Re: Exportability of EDA industry from North America?
From: Mike Treseler <mike_treseler@comcast.net>
Date: Fri, 17 Dec 2004 08:42:59 -0800
Links: << >>  << T >>  << A >>
Phil Tomson wrote:

> I also am a grad student (with a lot of years of 
> 'real-world' experience) and whereas I was aiming toward EDA in my 
> studies, now I'm starting to think about branching out into a different 
> area that might be growing faster... but I'm still very interested in EDA.

Then stick with EDA.
There is a very good chance that your future
job will not be directly related to your
course of study in any case.
The important thing is to enjoy what you are doing.

        -- Mike Treseler

Article: 76972
Subject: Re: how to start with development of eda tools
From: Stephen Williams <spamtrap@icarus.com>
Date: Fri, 17 Dec 2004 09:16:46 -0800
Links: << >>  << T >>  << A >>
kevin wrote:
 > how to start with development of eda tools(e.g simulation tools and
 > synthesizing tools): what knowledge should i know and where i can find
 > the
 > informations(tutorial, guides or something else)

People have already given you the hardware experiences you'll need.
Add to that list at least one graduate level course in compiler
construction, and/or equivilent experience.

The techniques for how simulation engines work come from operations
research (discrete event simulations) with a dose of queuing theory.
Most digital simulators are to some degree simle discreet event
simulations underneath. This sort of information should be relatively
easy to find. (I had coursework and work experience to draw on here.)

The techniques for synthesis are deeply hidded from the public. It's
probably easier to get documentation for building an atomic bomb:-)
There are all kinds of books on combinational logic synthesis, but
for synthesis of algorithms (i.e. sequential, behavioral code) the
only book I can find is:

Logic Synthesis for Control Automata
Samary Baranov
Kluwer Acedemic Publishers

Of course, it makes no mention of behavioral, sequential code. You
have to make the mental connections yourself.

-- 
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."


Article: 76973
Subject: Re: Digital clock synthesis
From: "Symon" <symon_brewer@hotmail.com>
Date: Fri, 17 Dec 2004 09:32:16 -0800
Links: << >>  << T >>  << A >>
Hi John,
What I'm thinking is, if the input to the circuit is the phase step, 
effectively frequency in this case, you have to calculate "2^27-100M plus 
the phase step" somewhere in the circuit each time the frequency changes. 
This needs another adder, yes? Can you fit all the stuff into 1 lut per bit?
Cheers, Syms.
"John_H" <johnhandwork@mail.com> wrote in message 
news:FPDwd.19$2w4.857@news-west.eli.net...
> The modulo 100M is just adding either the phase step to the accumulator
> (most of the time) or 2^27-100M plus the phase step to the accumulator 
> (each
> time the accumulator overflows).  Adding a selected one of two values can 
> be
> done within the Xilinx carry chain at no cost.
>
> "Symon" <symon_brewer@hotmail.com> wrote in message
> news:32g6taF3kks5aU1@individual.net...
>> Hmmm, maybe not smaller as you need a subtraction as well as an
>> accumulation. I need to think about that when I get time. But certainly
> more
>> accurate....
>
>> "Symon" <symon_brewer@hotmail.com> wrote in message
>> news:32g6k6F3ltb5iU1@individual.net...
>> > Why not make the accumulator work modulo 100,000,000? You get exactly
> 1Hz
>> > and 1Hz steps. Who wants 1.002 when you can easily have 1.0000000000
> with
>> > a smaller solution?
>> > Cheers, Syms.



Article: 76974
Subject: FIFO WREN RDEN and missing clock cycle
From: "Brad Smallridge" <bradsmallridge@dslextreme.com>
Date: Fri, 17 Dec 2004 11:43:52 -0800
Links: << >>  << T >>  << A >>
Hi folks,

I have run into this problem before, and I just can't put a handle on it.  I 
use the code before to generate read and write enable to store bit image 
information into a fifo.  The idea is that the read enable comes on one line 
after the write enable no mater what line length is used.  Works great 
except, as far as I can tell, there is a skew in the image fifo.  Seems on 
the first line, the write enable comes on n cycles before the read enable, 
as it should, but what is needed is the the read enable come on n-1 cycles 
on only the first row, so that the fifo outputs the first bit of the first 
row, at the same time the first bit of the second row is going into the 
fifo.

This probably won't make any sense to anybody unless they have done image 
processing. Does anyone have a clean explanation and solution?

Most of the meat is in the v2 process:

 -- video signal synching
 v1: process(clk,reset)
 begin
 if(reset='1') then
   vline_1  <= '0';
   vline_2  <= '0';
   vframe_1 <= '0';
   vframe_2 <= '0';
   vin_1    <= (others=>'0');
 elsif(clk'event and clk='1') then
   vline_1  <= vline;
   vline_2  <= vline_1;
   vframe_1 <= vframe;
   vframe_2 <= vframe_1;
   vin_1    <= vin;
   vin_2    <= vin_1;
   vin_3    <= vin_2;
 end if;
 end process;

 -- fifo read and write enable setup
 v2: process(clk,reset)
 begin
 if(reset='1') then
   fifowren <= '0';
   fiforden <= '0';
 elsif(clk'event and clk='1') then
   if( vframe_2='0') then
     fifowren <= '0';
     fiforden <= '0';
   elsif( vline_1='1' and vline_2='0') then
     fifowren <='1';
     if( fifowren='1') then
       fiforden <= '1'; -- one line later
     end if;
   end if;
 end if;
 end process;

 v3: process(clk,reset)
 begin
 if(reset='1') then
   video_threshold <= '0';
 elsif(clk'event and clk='1') then
   if( vin_1 > 175 ) then
     video_threshold <= '1';
   else
     video_threshold <= '0';
   end if;
 end if;
 end process;

 v4: process(clk,reset)
 begin
 if(reset='1') then
   video_bits_1 <= (others=>'0');
   video_bits_2 <= (others=>'0');
 elsif(clk'event and clk='1') then
   video_bits_1 <= fifodout;
   video_bits_2 <= video_bits_1;
 end if;
 end process;

   -- shift lines done here
   fifodin(2 downto 1) <= fifodout(1 downto 0);
   fifodin(0) <= video_threshold;

 v5: process(clk,reset)
 begin
 if(reset='1') then
   vout <= (others=>'0');
 elsif(clk'event and clk='1') then
   if( video_bits_2(1)='1' and video_bits_2(2)='1') then
     vout <= "10101010";
   else
     vout <= vin_3;
   end if;
 end if;
 end process;
 





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