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Thank you very much for your post. I didn' t want to discredit the importance of the FPGA in the market, my question derived by my low experience and i'm very interested in the FPGA world. I'm buying a Xilinx Spartan3 FPGA based board for doing practice. On Sat, 08 Jan 2005 19:52:31 +0000, kubik wrote: > I'm a beginner in this field so forgive me if what seems interesting > for me can seem stupid for others. > I'm approaching the fpga field cause i' ve read many times that the > fpga can reduce the time to market and reduce the costs of the system > for low volume applications. > Surfing on the web i can find easily PC-104 platform for more or less > 100$ that have a 300MHz cpu clock etc etc. > If i search for an fpga board with the same price i will never reach > comparable performance, or quantity of hardware. > So i would like to know which are the markets or the applications where > an fpga can represent a real gain or be necessary.? > > Are there useful only for that application where the performance is > not a goal? > > Are there useful only for research and prototyping?Article: 77526
Jason Berringer wrote: > Attention all gurus, > > I have a general question regarding constraints and asynchronous interfaces. > How do you specify details like "offset in before" when you really have no > idea when the signals will be arriving. I ask only because I have an > asynchronous interface that I need to get working at a higher frequency and > I feel that the only problem lies in the fact that I can't tell the tools > that I need this block to meet certain speeds using constraints. I'm new at > the constraints aspect of things other than using the basic "period" > constraint. If the input signal is not synchronous to the clock, no constraint will effectively handle the sampling for you. You need to assume that the input can create setup or hold time violations at some transitions. The important thing is to design your logic to handle cases where the signal falls in the forbidden window. The first rule to observe when you sample an asynchronous signal is to sample it in only one place. This means, for example using an IOB input flip-flop to sample the signal once, and to only use the Q of that flip flop for any internal decision. If you don't do this, some parts of your logic may see the input signal high on a particular clock edge while others see it low on the same edge. I suspect this is what is happening when writes don't work. Note again that no constraint will fix this, you need to design for it. For example: reg in_ff; ref in_dly; always @ (posedge clk) in_ff <= uP_signal_pin; always @ (posedge clk) begin in_dly <= in_ff; if (in_dly & !in_ff) begin ... ; // some action on falling edge of input end end In the above case if you use uP_signal_pin instead of in_ff, you may miss some falling edges of the input signal when the flip-flop that implements in_dly and the flip-flop that implements the action of the if statement don't see uP_signal_pin fall on the same edge. Depending on the clock rate and the parameters of the flip-flop doing the sampling, you may want to actually go through 2 flip-flops before using the signal in any synchronous state machine. This allows for the case where the first flip-flop goes metastable for a time nearing the clock period. At 100 MHz in a -5 xc2s150 I would think this is unnecessary unless you are looking for a very high degree of reliability. As far as constraints go, I think the period constraint should be all you need unless you are also sampling some signals close to the clock edge or require a maximum pin-to-pin latency for some cases. You can have a lot more reading on this if you Google for "metastability". God Luck, Gabor > > Details are: Asynchronous device is a uP running at 40 MHz, I have a set of > read/write 32 registers (32 bits wide) that are setup in the FPGA (Spartan > II xc2s150 device speed rating is a 5) running at 100 MHz. All transfers > where the uP reads from the registers are working perfectly, however the > occasional write transfer is not (maybe 1 out of 50 on average). Chip > select, write, read, address, and data lines are all the lines that I have > available. > > Thanks > > Jason > > jberringer at the domain sympatico dot caArticle: 77527
Hi I am designing a system which uses a small embedded processor(8052) to do general house keeping tasks,drive LCDs,read keyboard inputs etc and an Altera ACEX fpga to perform signal processing.The problem I have is that the customer wishes to be able to perform periodic updates to the fpga over tcp/ip which is do-able using a simple tcp/ip stack in the 8052 however where i am a little overwelmed by choices about is wether I should use jam byte code player in the 8052 with the original configuration data in code rom and reload new configuartion data into flash or put all the configuration data into flash and use a cpld to read the flash and configure the fpga in PS mode,or put the configuration data into flash and use the 8052 to configure the fpga in PPA mode. If anyone has any experiance of implementing this type of system or has any advice/comments all will be gratefuly received.Article: 77528
Hi all, my question is not really related to FPGAs (so let me know if there is a more appropriate forum), but I think it is of some relevance. Anyway, I have a design that contains a 75 MHz clock, and a PLL that multiplies it up to 300 MHz. These two clocks will be in sync except for the jitter the PLL introduces. Also, the 75 MHz clock is FM modulated to spread its power spectrum out, but the PLL should track this. I'm wondering about the best way to synchronise signals between the two clock domains; I have two state machines that need to do a small amount of communication. I could simply place some flip flops to sync the signals, but I get the feeling that the chance of metastability will be much higher, since the two clock domains are related by the PLL. Is there any particular method that works well in this situation? Thanks in advance, Michael Chan.Article: 77529
HI You should divide 300MHZ to 75 MHZ and try synchronise this clock domains. For devider use simple counter , it should works. WZ U¿ytkownik "Michael Chan" <mchan@itee.uq.edu.au> napisa³ w wiadomo¶ci news:newscache$xab3ai$oml$1@lbox.itee.uq.edu.au... > Hi all, my question is not really related to FPGAs (so let me know if there > is a more appropriate forum), but I think it is of some relevance. > > Anyway, I have a design that contains a 75 MHz clock, and a PLL that > multiplies it up to 300 MHz. These two clocks will be in sync except for > the jitter the PLL introduces. Also, the 75 MHz clock is FM modulated to > spread its power spectrum out, but the PLL should track this. I'm wondering > about the best way to synchronise signals between the two clock domains; I > have two state machines that need to do a small amount of communication. I > could simply place some flip flops to sync the signals, but I get the > feeling that the chance of metastability will be much higher, since the two > clock domains are related by the PLL. Is there any particular method that > works well in this situation? > > Thanks in advance, > > Michael Chan. > >Article: 77530
On Fri, 07 Jan 2005 22:07:04 +0100, newsmailcomp5 wrote: > David <david.nospam@westcontrol.removethis.com> writes: > >> I don't know about Sweden, but in Norway the tax rate isn't actually as >> bad as that - only about 40% or so. It varies widely according to your > > I'm (in Norway) close to 50% income tax, sales tax (VAT) is 25%, a > gallon of gasoline is US$ 6. Then there are road tax, toll, lots of > extra taxes on certain gods, if you buy a high range Mercedes you can > pay more than 1 million NOK (160,000 US$) in taxes alone on that > single purchase. 0.5L beer costs 5+ US$ in the store and usually US$ > 10+ in a resturant. > Certainly alchohol is ridiculously priced, and petrol costs more than in virtually any other country, despite Norway being a major producer. An American living in Norway would find driving a different experiance - cars and petrol are far more expensive, and people generally have older cars with far better fuel economy than SUVs, and it's more common for families to have one car rather than two (personally, I cycle about 4 km to work). We don't have the same relationship to cars as is common in the USA, so for most people the price of a Mercedes is irrelevant when a Toyota will do just as good a job. >> the cost of living here (in Norway - Sweden is similar), some things are >> relatively cheap (like housing, and electricity), and others expensive >> (like petrol). Salaries have much less spread here - high-paying jobs are >> lower-paying than the UK or the US, but low-paying jobs are better paid. >> And as an indication, my four-bedroom house cost about twice my salary, >> although admittedly that was an unusually good deal. > > You can't be living in a major city. In Oslo a four bedroom house cost > at least 5x my annual income (or 10x after income tax). > I'm living in a small town - prices are a lot higher in Oslo. But for much of the country, it is not hard to be in a fairly low property-price area while still within an hours commute to work (I am a half-hour ferry ride from the nearest city). However, I expect that a 4x or 5x income house price is far more common. But it's also worth taking into account that mortgages are cheap (I always find these "cheap mortgage" spam mails amusing - they quote rents fare above what I already pay) and easy to get, and tax-deductable. > I've lived in California and the only think I can think of which is > more expensive there than in Norway is lift tickets at ski resorts... It's difficult for me to give a true comparison (having moved to Norway from Scotland straight after university), but my impression is that Norway is not nearly as expensive a place to live as it is rumoured to be. David > > PetterArticle: 77531
Hello, we want to start with xilinix on our linuxboxes (SuSE). We're new to xilinix -tools. I've seen, that the ISE tools might run with wine under linux. My Q: Does it work with the usb-download or perhaps is there a site to look at? Thanks MichaelArticle: 77532
Hi, I have some recent comparison on this subject. I moved back to Sweden from San Jose last year after living there for 3 years. Taxes are higher in Sweden but not that much higher. In California I paid around 35%-40%, it depends on how many deductibles you have. In Sweden I pay around 50% in taxes. Kids health and dental is free. Adult has to pay a copay for each health care visit. Dental for adults is subsidized and not free and can be expensive. Schools and universities are free in Sweden. I don't need to start saving to my kids college fees. Even if we have 25% sales tax in Sweden, some stuff is actually cheaper here even if most of the part is more expensive. But the difference is not that much despite the 25% sales tax. The house I rent in US cost $2100 which was a good price there. In Sweden I bought a house which would had cost at least $1.000.000 in San Jose for 1/4 of the price. I live in Gothenburg which is the second largest city in Sweden. Cars are slightly more expensive. It depends on the brand and type. Gas is way more expensive (2.5x) here but I don't need to drive that much here. In US, when you had to do some shopping, you needed to use your car to drive around to all the stores or shopping centers. Here I can go down to the down town and park the car and walk to all the stores. That kind of downtown doesn't really exist in silicon valley. The US salary was much higher than my Swedish salary. So in all, I had slightly more money in US after all the bills was paid. But here I have my own house. The infrastructure is much better and the social security is also much better plus all my relatives and friends are here. Comparison with US is also dependent on the current currency rate on dollar. When I moved to US, one dollar was at most 11 Swedish kronor, now it's down to 6.7 Swedish kronor. That is a 40% difference. So now the prices in US are 40% cheaper to Sweden compared to year 2000.!!! Göran Bilski Kevin Neilson wrote: > vadim wrote: > >> I have received a job offer from a company in San Jose, California. >> The position title is: Test Development >> Engineering. The salary offered is 67k/year with Relocation Assistance >> and a Benefits package. I already have a 60k/year job in Toronto, >> Canada as Applications Engineer. >> >> The San Jose job is closer to circuit-design which is an area I would >> like to get into. >> >> I was told that the housing prices of Bay Area will make this salary >> into a 50k equivalent of Toronto. So practically my "buying power" is >> reduced. >> >> I have a dillema whether: -Professional advantages of this position, >> closer to ciruit design. -Working in Silicon Valley, the Mecca of >> HighTech. >> outweigh the offered salary ? >> >> Thanks in advance. > > > I would guess you'd be financially better off in Toronto. I don't know > how expensive Toronto is, but I know it will be fairly expensive to live > in San Jose. And while the position may be closer to design, it's not > terribly close. > > I'm surprised about the comments from the guy from Sweden. He must have > moved someplace very expensive, because Sweden isn't cheap. And their > tax rate is like 98%.Article: 77533
On 2005-01-10, Michael Schuster <schusterSoccer@enertex.de> wrote: > we want to start with xilinix on our linuxboxes (SuSE). We're new to xilinix > -tools. I've seen, that the ISE tools might run with wine under linux. My > Q: Does it work with the usb-download or perhaps is there a site to look > at? If you can pay for the tools, a Linux version of ISE is available. It should support parallel cable. I don't know about USB. If you're talking about WebPack, you're right, it's not natively for Linux. I don't know if it works with Wine, maybe.Article: 77534
Lots of tracks, lots of complication If you are stuck with the board (ACEX * 8052) then you have a kindof rough time ahead. You might use the LWIP stack (availablle on the internet) and some code available from Altera to do the JAM thing but it is going to be risky, slow and irritating. Here is a plug for NIOS and the newer FPGAs. Consider this. Use a Cyclone (e.g. 1C6 -already bigger and faster than the largest ACEX) with NIOS (1 or 2). TCP/IP stacks already sorted out. Built-in CPU (very fast), enough FPGA area (for the rest of your FPGA requirements), cheaper config device (will probably save a lot comparing and EPC2 to an EPCS1 (when you prefer prom configuration)), NIOS comes with ASMI programming features that easily reprograms your config IC..... I can go on and on. You will be looking at one FPGA, one config PROM, one RAM chip (running at e.g. 16 bit width) and one Flashchip (but you might get away using a single EPCS1/4 IC to do all !!), the LAN chip and transformer you already require (+maybe a WDT). Much simpler PCB layout (everything now stars away from the FPGA), in-circuit programming, much easier in circuit debugging, more than one serial port and lots lots more (for about the same cost you are going to pay anyway) I have just finished yet another NIOS based board that used to take 3 boards full of 8051s. 8051 CPUs are cute, but they can only go so far. PLUS.... Impress you client but also have a bigger hold over him. The reason why I write all this is because I did a similar design reconfiguring an older APEX20k FPGA from a configuration such as the one you are describing. Not worth it unless you have already spent all the money on the boards and/or you client has his heart set on the slowest system problematic system ever. Another thing, visualize how you are going to hold the entire config block in an 8051's memory, calculate a CRC + doing TCP/IP + extras. Wow. Like chewing you own leg off. My 22.56cents worth Victor Schutte Zertec Engineering http://www.zertec.co.za <edad3000@yahoo.co.uk> wrote in message news:1105341233.433559.52050@c13g2000cwb.googlegroups.com... > Hi > I am designing a system which uses a small embedded processor(8052) to > do general house keeping tasks,drive LCDs,read keyboard inputs etc and > an Altera ACEX fpga to perform signal processing.The problem I have is > that the customer wishes to be able to perform periodic updates to the > fpga over tcp/ip which is do-able using a simple tcp/ip stack in the > 8052 however where i am a little overwelmed by choices about is wether > I should use jam byte code player in the 8052 with the original > configuration data in code rom and reload new configuartion data into > flash or put all the configuration data into flash and use a cpld to > read the flash and configure the fpga in PS mode,or put the > configuration data into flash and use the 8052 to configure the fpga in > PPA mode. > If anyone has any experiance of implementing this type of system or > has any advice/comments all will be gratefuly received. >Article: 77535
Tuukka Toivonen <tuukkat@killspam.ee.oulu.finland.invalid> wrote: > On 2005-01-10, Michael Schuster <schusterSoccer@enertex.de> wrote: > > we want to start with xilinix on our linuxboxes (SuSE). We're new > > to xilinix > > -tools. I've seen, that the ISE tools might run with wine under linux. My > > Q: Does it work with the usb-download or perhaps is there a site to look > > at? > If you can pay for the tools, a Linux version of ISE is available. > It should support parallel cable. I don't know about USB. > If you're talking about WebPack, you're right, it's not > natively for Linux. I don't know if it works with Wine, maybe. On a well configured and recent wine, Ise works quite a long way. Calling XST from ISE is dead slow, due to a Linux kernel bug. However you can't use the programming tools talking to the hardware. Is was told, that Ise 7.1 Webpack will come with a Linux version however. Until then, talk to your distributor for the Linux 60 day evaluation suite. Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 77536
> Hi > I am designing a system which uses a small embedded processor(8052) to > do general house keeping tasks,drive LCDs,read keyboard inputs etc and > an Altera ACEX fpga to perform signal processing.The problem I have is > that the customer wishes to be able to perform periodic updates to the > fpga over tcp/ip which is do-able using a simple tcp/ip stack in the > 8052 however where i am a little overwelmed by choices about is wether > I should use jam byte code player in the 8052 with the original > configuration data in code rom and reload new configuartion data into > flash or put all the configuration data into flash and use a cpld to > read the flash and configure the fpga in PS mode,or put the > configuration data into flash and use the 8052 to configure the fpga in > PPA mode. > If anyone has any experiance of implementing this type of system or > has any advice/comments all will be gratefuly received. Hi Maybe You should use some hardware stack or at least Ethernet to serial device. Look at Tibbo homepage. And for configuring APEX FPGA I would use Atmel configuration memory. You can program that memory through I2C :) J.PawelczykArticle: 77537
Hello,
(first of all sorry for continuing in a new thread, but google
wouldn't let me reply for several days now: "unable to retrieve
message ..")
@BO:
As i'v already mentioned i tried a lot of combinations of datatypes
and (xil_)printf formatting-strings, including "%d".
But nothing is beeing displayed.
I've tried using putnum, too. It works but merely submits the
hex-values.
Seeing putnum working irritates me even more, in the end everything is
just a call to outbyte().
@JON:
It is not my intention to submit long longs. I'm using Xuint32 or
unsigned long, what is the same.
(When looking at my example i saw that i was pasting the wrong
xil_printfs, but in the real code they are alright (using the
according variables), just a sign of the many, many combinations i've
tried...)
Regards
Patrick
>The xil_printf documentation states:
>This function is similar to printf but much smaller in size (only
1KB). It
>does not have support for floating point numbers. xil_printf also
does not
>support printing of long long (i.e 64 bit numbers"This func is
similar to
>printf but much smaller. It does not have support for floating pt
numbers or
>long long. "
>Try using %d instead of %l and see if you get *something*...
>>"Patrick" <mai99drh@studserv.uni-leipzig.de> wrote in message
>>news:9bb2b1a1.0501060813.78b7a669@posting.google.com...
>> Hello,
>>
>> i know this is a rather stupid question, but i'm somewhat
irritated.
>>
>> I'm triing to send some data per Uartlite. For normal
>> characters/strings everything works fine, but if i try to send some
>> integers or long integers they aren't displayed.
>>
>> (Short) example:
>>
>> ...
>>
>> /* global definitions, no pointers */
>> Xuint32 interrupt_count = 0;
>> volatile Xuint32 jiffies = 0;
>>
>> ...
>>
>>/* values incrementd during pit-isr, pit works, pit running at 100HZ
>> */
>> void pit_timer_int_handler(void * baseaddr_p)
>> {
>> jiffies++;
>> interrupt_count++;
>>
>> XTime_TSRClearStatusBits(XREG_TSR_PIT_INTERRUPT_STATUS);
>> }
>>
>> ...
>>
>> main(){
>>
>> /* string displayed correctly */
>> xil_printf("\r\nRunning Mainloop");
>>
>> while(1){
>> sleep(2);
>> xil_printf("\nLoop");
>>
>> /* here the values aren't displayed,but the "a"s and "b"s are
displayd
>> */
>> xil_printf("\n %l a", i_interrupt_count);
>> xil_printf("\n %l b", l_interrupt_count);
>> /* giving the arguments as pointers won't help either */
>> xil_printf("\n %l a", &i_interrupt_count);
>> xil_printf("\n %l b", &l_interrupt_count);
>> }
>> }
>>
>>
>> i have tried different compinations with "%d","%D","%l","%ul" or
"%c"#
>> as format-strings and different datatypes for the two variables
>> (unisgned, int, long, unsigned long).
>>
>> i was looking at the xil_printf sources, too, to see what
characters
>> after "%" are supported.
>>
>> I'm using an uartlite at 9600 baud, 8 databits, no parity.
>>
>> So, does someone might have an idea or hint what my mistake is?
>>
>> Regards
>> Patrick
Article: 77538Hi all! I am currently looking for an application note, a tech report or anything else that deals with Xilinx Spartan2 bitstream structure in order to edit bitstreams for this FPGA. Someone has ever tried to do that ? Cheers, GrégoryArticle: 77539
Gregory, you have to be more specific about what you want to edit: BlockRAM content: easy LUTs: not too difficult Interconnect structure: forget it Peter AlfkeArticle: 77540
vadim wrote: > I have received a job offer from a company > in San Jose, California. The position title is: Test Development > Engineering. The salary offered is 67k/year with Relocation Assistance > and a Benefits package. I already have a 60k/year job in Toronto, > Canada as Applications Engineer. > > The San Jose job is closer to circuit-design which is an area I would > like to get into. > > I was told that the housing prices of Bay Area will make this salary > into a 50k equivalent of Toronto. So practically my "buying power" is > reduced. > > I have a dillema whether: > -Professional advantages of this position, closer to ciruit design. > -Working in Silicon Valley, the Mecca of HighTech. > > outweigh the offered salary ? > > Thanks in advance. This has been a very insightful thread! What I say is nothing new considering some of the other replies, but none the less here is my experience & opinion: First, I would not take a position based upon salary alone... or upon salary at all (assuming it pays the bills) -- By now you have seen that living in the bay area is costly, and home ownership (if that is important to you at this time) is very difficult on one salary. Thus, if you decide to take the opportunity consider the other benefits and potential pitfalls that await. I lived/worked in the silicon valley for a while and it is something I'm glad to have experienced. As the other posters note, there is something special about being surrounded by talent, and not merely at the work-place. The personal networking opportunities are priceless, as demonstrated by the many successful ventures that have sprung from the valley over the years. However, it is not the place for everyone; things are expensive, the public transport isn't great (I was glad to have a good bike-commute path with good bike lanes... flying past the internet-bubble-induced traffic melt-downs in 2000 was great), and there is a definite materialistic streak no doubt inspired by the good salaries. Its also a very diverse area ethnically, but there are areas where this diversity doesn't equate to an interesting social experience (social diversity) as you'll find in San Francisco, Berkeley, or Santa Cruz for example; the valley can be somewhat sterile. Perhaps the biggest draw of the bay area, though, is the fact that you have such communities and natural beauty within an hour's drive of each other. If you don't find one area to your liking, there is almost certainly another that doesn't require moving across the country to find. After San Jose I relocated to a community not far away and have enjoyed it immensely as it offers things to my liking. JesseArticle: 77541
Hello,
while searching the EDK-docs for a way to generate partial bitstreams
with bitgen i read about the PartialMaskX-option, X={0|1|2}.
This bitgen switch sounds very interesting to me but the docs only
mention that the mask is a hex value.
I couldn't find any further documentation about that.
So if someone could kindly point me to some deeper description of that
option and the format of the mask/hexvalue?
I understand the mask in that way:
Given a xilinx fpga with a fixed number of clb-columns (blocktype 0 ->
PartialMask0 ), i choose the ones i'd like to include in the bitstream.
So the mask would look somewhat like 001000100100011100 expressed as
hex-value (0x891c for this example).
The problem is: for a given device how do i know the number of bits in
the mask? all i know is the number of major frames/columns of a given
blocktype.
Is there a one-to-one-mapping (having 24 selected major-frames would
look somewhat like 00000000111111111111111111111111 = 0x3fffffff?
A further question was if all minor-frames of the selected major-frames
are then embedded in the bitstream?
Best Regards
Patrick
Article: 77542In article <1105379893.785166.222330@c13g2000cwb.googlegroups.com>, Peter Alfke <peter@xilinx.com> wrote: >Gregory, you have to be more specific about what you want to edit: >BlockRAM content: easy >LUTs: not too difficult >Interconnect structure: forget it If you REALLY want to edit interconnect structure on a Xilinx FPGA, use one supported by JBits. But you really, REALLY don't want to. -- Nicholas C. Weaver. to reply email to "nweaver" at the domain icsi.berkeley.eduArticle: 77543
"Nicholas Weaver" <nweaver@soda.csua.berkeley.edu> schrieb im Newsbeitrag news:cruiv3$2n6e$1@agate.berkeley.edu... > If you REALLY want to edit interconnect structure on a Xilinx FPGA, > use one supported by JBits. But you really, REALLY don't want to. Is there a practical reason to do so?? Cant think of such a reason. Regards FalkArticle: 77544
Thanks for the comments guys,a couple of interesting idea to look into there,however I might be stuck with the 8052 as the customer is a very big fan of them and look s at you strangly if you mention to him that there are newer ones available ;)Article: 77545
Uwe Bonnes wrote: >Brian Dam Pedersen <brian.pedersen@mail.danbbs.dk> wrote: > > > >>Got the hint - there was a typo in my command line. However fixing this >>did not fix my problems: >>$ ./naxjp -port digilent.txt -auto >>"xc9536xl_pc44:/home/brian/projects/extensionboard/cpld/wiring.jed" >>Device position 1. Command 'auto'. Partname 'xc9536xl_pc44'. File >>'pc44:/home/brian/projects/extensionboard/cpld/wiring.jed' >>Plug-in file 'algxc95xl' not found. >>Device error:ISP algorithm is unknown for device 'xc9536xl_pc44' >>Elapsed time: 43 ms >> >> > >What is the Jtag ID of your chip? Perhaps there is some mismatch between >what naxjp knowns and how your chips identifies itself. If you look around >for naxjp-079, when source was still available, you may compile a debug >version and look with gdb what is going wrong! I can sen you the 79.tgz >version on request. > > Oh, yeah! There was a change in the device ID sometime like 1997 that totally screwed up all the JTAG programming tools. The utility you are using may be expecting the old dev ID, or maybe the parts you have are the old ones, and the program is expecting the NEW ID. There is a cleverly hidden knowledge base article on this problem. At least with the Xilinx tools, there was no workaround for it. I ran into this on the XC9572 (NON-XL) part, but I think this change affected many of the 95xx parts. JonArticle: 77546
Peter Alfke wrote: > Gregory, you have to be more specific about what you want to edit: > BlockRAM content: easy > LUTs: not too difficult > Interconnect structure: forget it > > Peter Alfke > LUTs. But thanks, xapp151 came and told me the truth about it :) But it does not seem to be "not too difficult" as you say. I need to make it completely automatic through a C program. Maybe do you know any tutorial or further paper or application note concerning this problem ?Article: 77547
edad3000@yahoo.co.uk wrote: > Hi > I am designing a system which uses a small embedded processor(8052) to > do general house keeping tasks,drive LCDs,read keyboard inputs etc and > an Altera ACEX fpga to perform signal processing.The problem I have is > that the customer wishes to be able to perform periodic updates to the > fpga over tcp/ip which is do-able using a simple tcp/ip stack in the > 8052 however where i am a little overwelmed by choices about is wether > I should use jam byte code player in the 8052 with the original > configuration data in code rom and reload new configuartion data into > flash or put all the configuration data into flash and use a cpld to > read the flash and configure the fpga in PS mode,or put the > configuration data into flash and use the 8052 to configure the fpga in > PPA mode. > If anyone has any experiance of implementing this type of system or > has any advice/comments all will be gratefuly received. Part of this decision will be based on headroom. If the 89C5x device has plenty of room, and the ACEX is small, then you can store config in on chip Flash. If you want to allow the most headroom, then you will save on chip flash for Code, and use a SPI memory for FPGA storage. If you choose a 89C5x with HW SPI, then you will be able to load the FPGA faster. -jgArticle: 77548
"Jezwold" <edad3000@yahoo.co.uk> wrote in message news:1105392118.498651.9700@c13g2000cwb.googlegroups.com... > Thanks for the comments guys,a couple of interesting idea to look into > there,however I might be stuck with the 8052 as the customer is a very > big fan of them and look s at you strangly if you mention to him that > there are newer ones available ;) > figure out what cost savings you can make, and take everything in account... struggling with 8051 code for maybe months, that's not even guaranteed to work; or a modern design which is finished in no time. Managers are always sensitive to money saving and meeting deadlines in time ;) If you can finish this in half the time for half the money, the 8052 sentiment will be gone. A Jam player in 8052 will be slow and eat lots of code space, together with a TCP/IP stack I'm wondering if it would even fit in 64K of code space. Going to bankswitching is very complicated and expensive and ever slower. You're pushing the humble 8052 far too far, I'm afraid... Cyclone's are cheap, config devices are cheap, NIOSII is easy to use. For $995 you have a complete design kit. Seems like a lot of money, but writing software that's not going to work is far more expensive. JeroenArticle: 77549
I have a customer for whom I have designed an FPGA-based board as well
as the FPGA code. The FPGA on this board implements a controller for a
device with a proprietary interface. I have an NDA with the device
manufacturer which gives me access to the proprietary interface specs,
so that I can implement the controller for my customer.
The FPGA code can be divided into the following two categories.
1. Blocks which contain information or details of the proprietary interface.
2. The rest of the code.
I am free to deliver the full code to the customer, as long as no
proprietary information is divulged.
It is the intent of the agreement with the device manufacturer for my
customer to be able to modify their design as long as they can't modify
or see any of the details of the IP code which implements the
proprietary interface.
I am using Xilinx ISE 6.3i and XST for my design flow.
QUESTIONS
1. Does XST provide any way to generate a secure netlist?
2. Is there any way to generate a secure netlist in the Xilinx
implementation flow, then provide the interface definition and this
secure netlist to my customer?
3. Are there other synthesis tools (Synplicity, Exemplar, etc.) that
will generate encrypted netlists?
4. Are there general-purpose, third-party, tools for encrypting
FPGA-based designs at the source or netlist level?
5. Any other suggestions?
TIA
Urb
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