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Messages from 77725

Article: 77725
Subject: No respect of external pins (xilinx)
From: =?ISO-8859-1?Q?Gr=E9gory_Mermoud?= <gregory.mermoud@epfl.ch>
Date: Sat, 15 Jan 2005 17:25:27 +0100
Links: << >>  << T >>  << A >>
Hi all!

I encounter a strange problem. I wrote a macro and tried to use it in a 
design. The problem is, the xilinx tools modify the external pins of my 
macro. Indeed, my macro is build of LUTs and then, I want to use partial 
reconfiguration to change their equations. The problem is that the tools 
modify the entries of these LUTs and my equations are not ok any more.

Someone has ever experienced such a problem ? Does it exist any option 
for tools to force them to respect the external pins ?

Grégory

Article: 77726
Subject: maximum DDS clocking frequency on an Xilinx FPGA
From: robin.tsang@gmail.com
Date: 15 Jan 2005 09:08:41 -0800
Links: << >>  << T >>  << A >>
Hello,

Does anyone know what is the maximum clocking frequency achievable on
any Xilinx FPGA using the ISE's auto generated DDS core?

I need a cost effective way to test a high-speed DAC (>=500 MSPS) and
need a digital pattern generator to drive my DAC input. So far the best
solution I found is using an FPGA, but don't know how fast it can be.

The DDS needs to have performance better than 80dB SFDR, but doesn't
need much frequency resolution (10 Hz is plenty).
An pointers are welcome, thanks in advance.

Robin


Article: 77727
Subject: Re: I2C --> SPI or Parallel Port Concentrator
From: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Date: Sat, 15 Jan 2005 18:48:32 +0000 (UTC)
Links: << >>  << T >>  << A >>
Chris Graham <chrisgr@shaw.ca> wrote:
> I'm new to FPGAs & PLDs, but hoping you can help me with the following:

> I need to  build a data concentrator that would take 8 to 16 I2C channels 
> and concentrate them into one high speed SPI or 8-bit parallel channel.  The 
> I2C channels would be masters, each with usually no more than one slave, 
> with the slave transmitting as it requires - at intervals as short as about 
> 1ms.  The channels may be at different clock rates depending on their length 
> to accomodate long lines that need a low clock rate.

> The concentrator would receive all this data, keeping up with the rate, 
> combine it, tagged by port and device number, and relay it to a 
> microcontroller.   Also the microcontroller could direct commands through 
> the concentrator to selected I2C channels & device numbers.

>  The microcontroller would also be able to download configuration 
> information to the concentrator to set clock rates, etc.

> Does this sound like a good job for an FPGA or PLD?  How large an device in 
> terms of number of gates, etc am I likely to need?

> Any recommendations for a chip or manufacturer?

What about a FT2232 in host emulation mode, an address decoder and a
handfull of PCF8584 8 bit to I2C controllers as USB solution?


-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Article: 77728
Subject: Re: XST vs. Verilog Libraries
From: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Date: Sat, 15 Jan 2005 18:52:54 +0000 (UTC)
Links: << >>  << T >>  << A >>
Stephen Williams <spamtrap@icarus.com> wrote:

> I'm working with ISE 6.2i on a project, and I'm trying to organize
> the source into libraries. In fact, I'm using a couple Opencores
> cores for this task as well. The libraries are in the format that
> Icarus Verilog handles just fine. That is, the library is a directory
> of verilog files, with each file named after the module it contains.

> I cannot for the life of me figure out how to get XST to do the
> same thing. I can list all the files in a file list, but I really
> just want to point it at the library directory and be done with it.
> I can see that the -vlgincdir flag to the run subcommand works for
> includes, but what (if anything) does the job for modules?

Well, XST programmers managed to screw up -vlgincdir for use in conjunction
with ISE in many releases. The knowledge base is unclear about if it
should work at all with a present release or if there are plans to fix that
mode. What a pity...

-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Article: 77729
Subject: No device found in Boundary Scan Chain, for Xilinx PC4 Cable
From: zihu88@hotmail.com
Date: 15 Jan 2005 10:58:06 -0800
Links: << >>  << T >>  << A >>
Hi All,

I am learning how to program Xilinx CPLD, starting with XPLA3
(XCR3032XL)and Parallel Cable IV. I consistently encounted the problem
from iMPACT - "No device detected in Boundary Scan Chain" when I tried
to initialize the Boundary Scan Chain. The error no. is 585 and I am in
JTAG mode. I am not using developing board since I'd like to build an
embedded system afterwards.

I followed the hint given by ISE6.3i for checking - The pin layout, The
connection, The Power level. But no problem found there.

.I have read from this group saying Port-En pin should be put high when
init, I tried this but failed. I put Port-En back to low.

.I am using battery cells and resister network as the power supply for
the XCR3032XL. The Voltage is 3.3-3.6V and the Current is 1.8mA.

.I am using PS2 mouse port as the power supply for the PC4 Cable. The
voltage is 5.04V and the Current is changing around 10mA, far lower
than the recommended but this is one of the standard config for PC4
cable.

.The cable is connected and Parallel port is in ECP mode.

.I have added the .jed file into iMPACT before initializing the cable.
And I get the same problem.

.As I debugged the chain, I found the TDO sticked to be "1" whatever
the TDI was.

So what's the issue? Is it to say PC4 doesn't support XCR3032XL?
Appreciation for any idea!

-Zimmer


Article: 77730
Subject: Re: No respect of external pins (xilinx)
From: Bret Wade <bret.wade@xilinx.com>
Date: Sat, 15 Jan 2005 11:59:54 -0700
Links: << >>  << T >>  << A >>
Grégory Mermoud wrote:
> Hi all!
> 
> I encounter a strange problem. I wrote a macro and tried to use it in a 
> design. The problem is, the xilinx tools modify the external pins of my 
> macro. Indeed, my macro is build of LUTs and then, I want to use partial 
> reconfiguration to change their equations. The problem is that the tools 
> modify the entries of these LUTs and my equations are not ok any more.
> 
> Someone has ever experienced such a problem ? Does it exist any option 
> for tools to force them to respect the external pins ?
> 
> Grégory

Hi Gregory,

The change in the equation is due to pin swapping. You can prevent the 
pin swapping by using the LOCK_PINS constraint.

I am assuming that your macro is an RPM macro. If it were a hard macro, 
I wouldn't expect the pin swapping to have occurred in the first place. 
But your use of the term "external pins" does imply a hard macro.

More details about the LOCK_PINS constraint:
http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=15845

Regards,
Bret

Article: 77731
Subject: print(hello world) vs printf(hello world) / system wizard vs platform studio vs command prompt
From: "Hur" <jaeyoung_hur@yahoo.com>
Date: Sat, 15 Jan 2005 21:23:19 +0100
Links: << >>  << T >>  << A >>
Hi,,,,,

Let me raise one problem on "undefined reference" error message.

In XPS (EDK 6.3) simple microblaze TestApp ....
(with only 64 KB BRAM and RS232_uart)

----------------------------------------------------------
#include "xparameters.h"
#include "xutil.h"
#include <stdio.h>

int main (void) {
print("-- Hello World --\r\n");

printf("-- Hello World --\n");   // this is sometimes problem
return 0;
}
---------------------------------------------------------- 

Interesting observations....

- When I make system using Base System Wizard,
   both of "print" and "printf"  of "Hello_World.c" are ok.....

- When we manually create system using Platform Studio (and/or Command
Prompt),
    only "print" is ok...
    The error message of "printf" statement is

---------------------------------------------------------
./microblaze_0/lib//libc.a(print.o): In function
`print':
print.o(.text+0x1c): undefined reference to `outbyte'
make: *** [TestApp/executable.elf] Error 1
---------------------------------------------------------


What I did (in platform studio) was
- create project with mh MHS file
- netlist generation -> bitstream generation : this is ok
- add software project (simple C code above)
- generate linker script
- generate library and BSP : seems ok
- build all user applications : not ok, the error message above found

I guess this problem is related to the "libgen",
If yes or not, Let me know how i can solve this problem :) !!...

Thankyou
regards



Article: 77732
Subject: Re: Programming and copyright
From: nweaver@soda.csua.berkeley.edu (Nicholas Weaver)
Date: Sat, 15 Jan 2005 20:31:25 +0000 (UTC)
Links: << >>  << T >>  << A >>
In article <zt0Gd.556$7C4.122@newsfe2-gui.ntli.net>,
Kryten <kryten_droid_obfusticator@ntlworld.com> wrote:
>Since cryptographic processing is becoming increasingly useful in 
>applications, is the crypto hardware available for use after loading? I 
>suspect it isn't something that the chip makers thought of at the time, but 
>I'd guess it would not be a huge job to multiplex the signals to the rest of 
>the FPGA and say "finished using this for loading, now available to the FPGA 
>application"

Except that as hard-cores go, AES doesn't save much.  Its only 10
BlockRAMs and ~600 slices for a key agile, >1.5 Gbps AES core.

-- 
Nicholas C. Weaver.  to reply email to "nweaver" at the domain
icsi.berkeley.edu

Article: 77733
Subject: Re: I2C --> SPI or Parallel Port Concentrator
From: "Chris Graham" <chrisgr@shaw.ca>
Date: Sat, 15 Jan 2005 20:50:58 GMT
Links: << >>  << T >>  << A >>
> Some options:
> a) Use tiny uC as i2c-spi bridges, and chain them.
> Advantage is easy to add more channels, & testing is very simple.

I'd like to have a single fast serial serial link to the host with no need 
for select lines, so this would not work for my appplication.  A dedicated 
concentrator chip with support for up to say 8  I2C ports would be better.

>  So that puts you into the smaller FPGA area - and there,
> neither speed nor logic are likely to be an issue.

Sound good. I'll look into a low end FPGA.

>  You can time-share dual port ram, to make it appear
> more-ported.
>  Do you need instant-on ?

While the system was in use, all the channels would be on all the time.

>  What is MAX i2c speed ?

Up to 400 kbps on each channel but some channels might be less - as little 
as 20kbps.




Article: 77734
Subject: Re: No respect of exernal pins [xilinx]
From: "Peter Alfke" <alfke@sbcglobal.net>
Date: 15 Jan 2005 13:09:52 -0800
Links: << >>  << T >>  << A >>
Gregory, tis is not a direct answer to your question, but:
Have you looked at SRL16 to change the content of your LUT(s)?
I think that is much more convenient than partial configuration (for
your particular purpose).
Peter Alfke


Article: 77735
Subject: Re: maximum DDS clocking frequency on an Xilinx FPGA
From: "Peter Alfke" <alfke@sbcglobal.net>
Date: 15 Jan 2005 13:22:01 -0800
Links: << >>  << T >>  << A >>
In Spartan-3 I am running a 32-bit DDS accumulator  at 160 MHz.
In Virtex-4 the "DSP Slice", which is a muliplier-accumulator with some
extra hooks, runs guaranteed at 500 MHz, and involves zero external
logic.
If you want to go faster, you can use multiple accumulators and funnel
them out through the parallel-to-serial converter that exists on every
Virtex-4 output pin, and run 1 Gbps.
If you want to go even faster, use the 3 Gbps multi-gigabit transceiver
in Virtex-IIPro, or the up to 10 Gbps MGT in Virtex-IIProX.

You see, there are lots of options, all depending on the amount of
mental effort you want to expend. But 10 Gbps is today's upper limit.
Peter Alfke


Article: 77736
Subject: Re: Looking for low-cost protoboards.
From: Erik Walthinsen <omega@pdxcolo.net>
Date: Sat, 15 Jan 2005 13:40:49 -0800
Links: << >>  << T >>  << A >>
Lukasz Salwinski wrote:
> However, anyone knows
> whats the status of the USBhigh-speed drivers for Linux ?
> XEM3001's apparently using Cypress CY68013 FX2 - is it
> supported under Linux ?

That would depend on how you program it.  Class drivers for all the
major types of devices exist, so if you program the FX2 to look like a
serial port, or a hard drive, and you properly set the class ID in
[r]enumeration, it'll just work.

If you program it differently, there's libusb which allows you to write
"drivers" in user space, built into your app.  libusb lets you fiddle
with the low-level USB communications straight from your app,
elimininating the need for a kernel-mode driver, but restricting
operation to your application (or library, if you write your "driver" as
one).

I haven't played with the FX2 personally yet, my devel board hasn't
arrived from Bulgaria(!) (http://www.elrasoft.com/) yet, probably next
week.  I've done a fair bit of research in advance of getting it though
(and I've written Linux kernel drivers before)... ;-)

The interesting thing about the FX2 in conjunction with an FPGA is its
AUTO mode, which is used by http://oscar.dcarr.org/ssrp/index.php, the
project that alerted me to the ELRAsoft board.  His firmware literally
consists of setting up a bunch of registers, then executing an inifinite
loop flashing an LED.  The FX2's FIFO handles everything else, clocked
from the external device.

TTYL,
     Omega
     aka Erik Walthinsen

Article: 77737
Subject: Re: No respect of external pins (xilinx)
From: =?ISO-8859-1?Q?Gr=E9gory_Mermoud?= <gregory.mermoud@epfl.ch>
Date: Sun, 16 Jan 2005 00:16:46 +0100
Links: << >>  << T >>  << A >>

> 
> Hi Gregory,
> 
> The change in the equation is due to pin swapping. You can prevent the 
> pin swapping by using the LOCK_PINS constraint.
> 
> I am assuming that your macro is an RPM macro. If it were a hard macro, 
> I wouldn't expect the pin swapping to have occurred in the first place. 
> But your use of the term "external pins" does imply a hard macro.
> 
> More details about the LOCK_PINS constraint:
> http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=15845 
> 
> 
> Regards,
> Bret

You're great. Preciseness, conciseness. All what I love. :) Thx

Article: 77738
Subject: Re: No respect of external pins (xilinx)
From: =?ISO-8859-1?Q?Gr=E9gory_Mermoud?= <gregory.mermoud@epfl.ch>
Date: Sun, 16 Jan 2005 00:52:02 +0100
Links: << >>  << T >>  << A >>

> 
> Hi Gregory,
> 
> The change in the equation is due to pin swapping. You can prevent the 
> pin swapping by using the LOCK_PINS constraint.
> 
> I am assuming that your macro is an RPM macro. If it were a hard macro, 
> I wouldn't expect the pin swapping to have occurred in the first place. 
> But your use of the term "external pins" does imply a hard macro.
> 
> More details about the LOCK_PINS constraint:
> http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=15845 
> 
> 
> Regards,
> Bret

I does not work. I do not understand why. In fact, what is the 
fundamental difference between an RPM macro and a hard macro ? Should 
the LOCK_PINS constraint not work by using one of them  ?

Article: 77739
Subject: Re: No respect of exernal pins [xilinx]
From: =?ISO-8859-1?Q?Gr=E9gory_Mermoud?= <gregory.mermoud@epfl.ch>
Date: Sun, 16 Jan 2005 00:52:39 +0100
Links: << >>  << T >>  << A >>
Peter Alfke wrote:
> Gregory, tis is not a direct answer to your question, but:
> Have you looked at SRL16 to change the content of your LUT(s)?
> I think that is much more convenient than partial configuration (for
> your particular purpose).
> Peter Alfke
> 
No, what is it  ?

Article: 77740
Subject: Re: No respect of external pins (xilinx)
From: =?ISO-8859-1?Q?Gr=E9gory_Mermoud?= <gregory.mermoud@epfl.ch>
Date: Sun, 16 Jan 2005 01:23:33 +0100
Links: << >>  << T >>  << A >>

> The change in the equation is due to pin swapping. You can prevent the 
> pin swapping by using the LOCK_PINS constraint.
> 
> I am assuming that your macro is an RPM macro. If it were a hard macro, 
> I wouldn't expect the pin swapping to have occurred in the first place. 
> But your use of the term "external pins" does imply a hard macro.
> 
> More details about the LOCK_PINS constraint:
> http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=15845 
> 
> 
> Regards,
> Bret

Another question in the same field : does it exist any way to insert a 
macro while keeping exactly the same routing than the one proposed by 
the macro ?

Grégory

Article: 77741
Subject: Re: No respect of exernal pins [xilinx]
From: "Peter Alfke" <alfke@sbcglobal.net>
Date: 15 Jan 2005 16:27:54 -0800
Links: << >>  << T >>  << A >>
If you declare the 4-input LUT an SRL16, it becomes a 16-bit shift
register. You shift in the 16 bits, and can then use it as the normal
LUT that implements the logic you need.
Remember that the LUT really is defined by 16 bits stored in 16
latches. And Xilinx was smart enough to interconnect the 16 latches in
such a way that they can function as a 16-bit shift register.
The explanation how a latch can be transformed into a master-slave
register would go too far here. Just trust me, it works, and is one of
the big advantages Xilinx has over its competitor...
Peter Alfke


Article: 77742
Subject: What is the difference between ASIC and FPGA?.
From: tvnaidu@yahoo.com
Date: 15 Jan 2005 17:02:39 -0800
Links: << >>  << T >>  << A >>
Hello, I have two questions about Electronic circuit board design.
These are the questions:

1st question:
What is the main difference between FPGA and ASIC, recently I went to
some exhibition, there I heard from somebody, he says "we are designing
a prototype handset based on FPGA, which was used between DSP chip and
main processor, later on we will go wityh ASIC", I didn't understand
quite well, what was the main difference, also whereever FPGA was used,
can that be replaced by ASIC?.

2nd question:
What are the main stepps involved in circuit board design?. Suppose if
I want some board to be designed, what are the steps I have to do (like
a fabless design), how can I contact the fab to get my prottype board
as well as production baord?.

Thanks in advance, appreciated.


Article: 77743
Subject: Re: What is the difference between ASIC and FPGA?.
From: "Tam/WB2TT" <t-tammaru@c0mca$t.net>
Date: Sat, 15 Jan 2005 20:46:52 -0500
Links: << >>  << T >>  << A >>

<tvnaidu@yahoo.com> wrote in message 
news:1105837359.911078.236150@z14g2000cwz.googlegroups.com...
> Hello, I have two questions about Electronic circuit board design.
> These are the questions:
>
> 1st question:
> What is the main difference between FPGA and ASIC, recently I went to
> some exhibition, there I heard from somebody, he says "we are designing
> a prototype handset based on FPGA, which was used between DSP chip and
> main processor, later on we will go wityh ASIC", I didn't understand
> quite well, what was the main difference, also whereever FPGA was used,
> can that be replaced by ASIC?.
>
> 2nd question:
> What are the main stepps involved in circuit board design?. Suppose if
> I want some board to be designed, what are the steps I have to do (like
> a fabless design), how can I contact the fab to get my prottype board
> as well as production baord?.
>
> Thanks in advance, appreciated.
>
An FPGA is a Field Programmable Logic array. As the name implies, it can be 
programmed to be anything within its capability. ASIC stands for Application 
Specific IC. In his context, he means a custom IC. So, the FPGA is a 
prototype for the final version. You don't make one ASIC, you  make 
tens/hundreds of thousands.

Tam 



Article: 77744
Subject: Re: What is the difference between ASIC and FPGA?.
From: Guy Macon <_see.web.page_@_www.guymacon.com_>
Date: Sun, 16 Jan 2005 01:55:51 +0000
Links: << >>  << T >>  << A >>

Tam/WB2TT wrote:

>An FPGA is a Field Programmable Logic array.

Minor correction: An FPGA is a Field Programmable Gate Array.
                       ^                          ^^^^



Article: 77745
Subject: Re: What is the difference between ASIC and FPGA?.
From: kensmith@green.rahul.net (Ken Smith)
Date: Sun, 16 Jan 2005 02:09:42 +0000 (UTC)
Links: << >>  << T >>  << A >>
In article <1105837359.911078.236150@z14g2000cwz.googlegroups.com>,
 <tvnaidu@yahoo.com> wrote:
>Hello, I have two questions about Electronic circuit board design.
>These are the questions:
>
>1st question:
>What is the main difference between FPGA and ASIC, recently I went to

Field Programable Gate Array:  a bunch of logic cells that you can program
to do lots of different things.  One of these things would may be the
thing you want done.

Application Specific Integrated Circuit: a chip designed to do a certain 
job or a small group of jobs.  If you want to do something else get a 
different chip.


>some exhibition, there I heard from somebody, he says "we are designing
>a prototype handset based on FPGA, which was used between DSP chip and
>main processor, later on we will go wityh ASIC", I didn't understand
>quite well, what was the main difference, also whereever FPGA was used,
>can that be replaced by ASIC?.

Basically it like this:

You can make the prototype with very costly general purpose FPGAs, some 
DSPs, and have a cable running off to a big battery.  This version costs a 
billion dollars each.  Our target cost is 3 dollars so we will have to 
spend 10 Million on making a custom chip and sell about 4 million units to 
make it pay.

>2nd question:
>What are the main stepps involved in circuit board design?.

1)  Decide what the bourd should do.
2)  Make a schematic that does that.
3)  Decide the mounting issues.
4)  Select the component packages.
5)  Buy board layout software if you intend to do it yourself
6)  Start placing the parts
7)  Discover that they won't fit and loop back to 3
8)  Finish placing
9)  Start running the traces
10) Discover that you can't route as placed and loop back to 8
11) Finish routing
11) Check the proposed layout
12) Rip out large sections and loop back to 8
13) Check the improved version  
14) Check it again
15) Make Gerber plots and an NC drill file
16) Check the Gerbers and drill file
17) Compose a README.TXT
18) Zip together the Gerber, NC drill and README.TXT
19) Get bids on making the board
20) Select a vendor and send off the files
21) Get a phone call from the vendor pointing out an error
22) Loop back to 11 and increase the ring on the vias etc
23) Get the boards from the FAB house.
24) Gather the parts needed
25) Discover that you can't get the MOSFET in a DPAK loop back to 4
26) Stuff the board
27) Apply power
28) Scrape the burning parts off your face
29) Replace the burned parts
30) Apply the right power the right way around this time
31) Begin debugging the board
32) Discover the errors that are not just part values
33) Loop back to 1
34) Prepair BOMs etc for the production build.
35) Fight off the accounting guy who wants to lower cost.
36) Make the pre-pre-production units
37) Correct the BOM and assembly drawings
38) Start testing the pre-pre-production units
39) Build the pre-production units
40) Do major testing
41) Discover that the specifications from marketing have changed
42) Loop back to 1

 
-- 
--
kensmith@rahul.net   forging knowledge


Article: 77746
Subject: Re: I2C --> SPI or Parallel Port Concentrator
From: Jim Granville <no.spam@designtools.co.nz>
Date: Sun, 16 Jan 2005 16:41:33 +1300
Links: << >>  << T >>  << A >>
Chris Graham wrote:
>>Some options:
>>a) Use tiny uC as i2c-spi bridges, and chain them.
>>Advantage is easy to add more channels, & testing is very simple.
> 
> 
> I'd like to have a single fast serial serial link to the host with no need 
> for select lines, so this would not work for my appplication.  A dedicated 
> concentrator chip with support for up to say 8  I2C ports would be better.

You do not have to use chip selects, you can also daisy-chain SPI 
devices, esp if they are all identical. Then the SPI runs at >> 16x the 
i2c speed.

> 
>> So that puts you into the smaller FPGA area - and there,
>>neither speed nor logic are likely to be an issue.
> 
> 
> Sound good. I'll look into a low end FPGA.
> 
> 
>> You can time-share dual port ram, to make it appear
>>more-ported.
>> Do you need instant-on ?
> 
> 
> While the system was in use, all the channels would be on all the time.

Instant-on refers to the response from power up. Some FPGAs serial load,
and some are faster to start. If that matters, it can influence the
FPGA selection. - ie if a remote master, expects the slave to be
alive/awake, and does not retry, then this may be an issue.

-jg


Article: 77747
Subject: Re: No respect of external pins (xilinx)
From: Bret Wade <bret.wade@xilinx.com>
Date: Sat, 15 Jan 2005 21:44:23 -0700
Links: << >>  << T >>  << A >>
Grégory Mermoud wrote:
> 
>>
>> Hi Gregory,
>>
>> The change in the equation is due to pin swapping. You can prevent the 
>> pin swapping by using the LOCK_PINS constraint.
>>
>> I am assuming that your macro is an RPM macro. If it were a hard 
>> macro, I wouldn't expect the pin swapping to have occurred in the 
>> first place. But your use of the term "external pins" does imply a 
>> hard macro.
>>
>> More details about the LOCK_PINS constraint:
>> http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=15845 
>>
>>
>> Regards,
>> Bret
> 
> 
> I does not work. I do not understand why. In fact, what is the 
> fundamental difference between an RPM macro and a hard macro ? Should 
> the LOCK_PINS constraint not work by using one of them  ?

An RPM macro is defined in the logical design using RLOC constraints or 
indirectly, the flooprplanner. A hard macro is defined in the physical 
design using FPGA Editor and exists in the logical design only as a 
black box.  Which are you using?

Bret

Article: 77748
Subject: Re: Exportability of EDA industry from North America?
From: "Ales Hvezda" <ahvezda@seul.org>
Date: 15 Jan 2005 20:46:16 -0800
Links: << >>  << T >>  << A >>
Hi,

I usually like spending my free time working on the code rather than
posting to USENET, but I want to address some of the points from the
previous poster in this thread.


[snip]
>> * Linux distro & revision level
>> * Installation flavor (i.e. RedHat comes in "personal",
"workstation",
>>    "server", and so on.  SuSE comes in "personal" and
"professional").
>
> RedHat 9, Workstation, upgraded to the latest fixes on FreshRPM's
apt-get
> repository.


When I first read your response, I was quite curious to see for myself
if a stock RedHat 9 system really does have so much trouble installing
gEDA/gaf or running Stuart's gEDA Suite CD installer, so I ran a little
experiment: I installed stock RedHat 9.0 (Shrike) into a completely new
system (using vmware):

# cat /etc/issue
Red Hat Linux release 9 (Shrike)

and then installed gEDA/gaf and the Suite CD.  Both installed
almost out-of-the-box.  I followed the INSTALLs and READMEs that
can be found at:

http://geda.seul.org/download.html

The only change I made was to add /usr/local/lib into ld.so.conf
(and re-ran ldconfig).  I have the build typescript to the gEDA/gaf
build/install if you want to see the evidence.

I'm guessing that those rpms from FreshRPM that you installed, changed
the standard packages (like gtk+) in a way that they are no longer
standard or similar to the upstream source packages.  See below.


[snip]
>> : other distributions use differing names for some of the normal
system
>> : libraries. (GTK+ 2 comes to mind)
>
> Redhat 9 calls GTK+ 2.0 GTK2, but your configuration scripts are
looking for
> GTK+-2.0 So they don't find GTK2, and back down to GTK+ 1.2


Hmmm, on my newly installed RedHat 9.0 system, gtk+ 2.0 is in
fact called gtk+-2.0, i.e. the following works:

$ pkg-config gtk+-2.0 --cflags --libs
-I/usr/include/gtk-2.0 -I/usr/lib/gtk-2.0/include
-I/usr/include/atk-1.0 -I/usr/include/pango-1.0 -I/usr/X11R6/include
-I/usr/include/freetype2 -I/usr/include/glib-2.0
-I/usr/lib/glib-2.0/include  -Wl,--export-dynamic -lgtk-x11-2.0
-lgdk-x11-2.0 -latk-1.0 -lgdk_pixbuf-2.0 -lm -lpangoxft-1.0
-lpangox-1.0 -lpango-1.0 -lgobject-2.0 -lgmodule-2.0 -ldl -lglib-2.0

Also on my all of my Debian systems (both testing and unstable)
the above pkg-config gtk+-2.0 also works fine.

I don't think I have personally seen a Linux (or other OS)
distribution (and I routinely test gEDA/gaf on common distributions and
configurations) that has renamed gtk+'s pkg name to GTK2.


> Your scripts on the latest version of gSchem cannot find the dynamic
links
> for libstroke, or libgdg* , even though they are in /usr/local/lib
(with
> all the other libraries it did find):
>
> $ ls /usr/local/lib/libst*
>
>        /usr/local/lib/libstroke.a /usr/local/lib/libstroke.so.0
[snip]
> $ ls /usr/local/lib/libgdg*
>        /usr/local/lib/libgdgeda.a /usr/local/lib/libgdgeda.so.6
[snip]
>
> $ ldd `which gschem`
>
>        libstroke.so.0 => not found
[snip]
>        libgdgeda.so.6 => not found
[snip]

Yeah, these libraries are in /usr/local/lib, but you need to
tell ld.so (dynamic linker/loader) where to look for them.  You need to
either 1) set LD_LIBRARY_PATH to point there or 2) add /usr/local/lib
to ld.so.conf.  The final alternative is to use rpath (not recommended
by various people, but that's a whole different debate), but you would
have to add that to the Makefiles yourself.


[snip]
> In the past, using source and ./configure, make, and make install, it
did
> do the right thing, but this latest 2004 release behaves differently.

I haven't really changed how gEDA/gaf is configured or compiled
in a quite some time, so if you had success with previous releases,
something else has changed.


[snip]
>> systems which will and won't work. Did you read the README?
>
> Absolutely! And I am running RedHat 9, a system that should work...
All
> the versions of my various tools are at or above the rev levels
required.
>

Yeah, sounds like you are running a RedHat 9 system which has
been upgraded and somehow the upgraded pieces are not what the gEDA/gaf
./configure scripts expect.


> The first time I ran the CDROM install, it built and installed the
symbols
> libraries at least 20 times before I killed the process. (I was
getting
> curious as to why it was taking so long, and why every hour or so I
would
> look at it and it was building the symbols yet again.)


Yes, I observed this as well and it is a bug.   However, if you
let it run, it will eventually finish (it did for me).  I have a pretty
good idea why this is happening.  Stuart and I will fix this for the
next rev of the suite CD.


[snip]
> I have a definite desire for gEDA to succeed, as I think
> GPL'd software is the future. But at this stage, gEDA 20041228
> shouldn't have been released to the public. If a guy like me who
[snip]


Interestingly enough, 20041228 has been out for ~18 days and
I haven't heard of anybody else having build problems (using gtk+
2.2.x/2.4.x; trying to compile with gtk+ 2.6.x is another matter
because of a function name clash in my code, already fixed in CVS :-).

Thanks for the feedback.

-Ales
-- 
Ales Hvezda
ahvezda 0x40 seul.org
http://geda.seul.org/


Article: 77749
Subject: Re: Lattice DDR Interface
From: "cas7406@yahoo.com" <cas7406@yahoo.com>
Date: 15 Jan 2005 22:59:29 -0800
Links: << >>  << T >>  << A >>
Andre,

I do agree with Luc. But, I'd also like you know I have used IP Manager
to generate both the DDR Memory and DDR Generic modules. I have
implemented them without problems.
(ispLEVER 4.2 updated with SP1, W2000 SP4)

Rgds,
cristian

Luc wrote:
> Hi Andr=E9
>
> Your first source would be one of the Lattice FAE's. They will
> certainly help you in isolating the problem and finding a solution.
>
> Regards,
> Luc
> On 12 Jan 2005 04:11:02 -0800, ALuPin@web.de (ALuPin) wrote:
>
> >Hi newsgroup folks,
> >
> >I am trying to use the new EC/ECP - DDR interface which can be
instantiated
> >in the IP-Manager of ispLEVER4.2
> >
> >When trying to map it I get a memory error and the mapping
> >is aborted.
> >
> >I am using WINDOWS2000 SP4
> >
> >
> >Has someone tried to use this new interface ? Have you experienced
> >such errors? What other experiences did you have with that new
> >interface?
> >
> >Thank you for you opinion.
> >
> >Rgds
> >Andr=E9




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