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Messages from 78300

Article: 78300
Subject: Re: Xilinx ISE 6.3i compxlib freeze
From: "Gabor" <gabor@alacron.com>
Date: 28 Jan 2005 11:02:13 -0800
Links: << >>  << T >>  << A >>
Dan wrote:
> I'm trying to compile the simulation libraries and I have a big
> problem: compxlib causes my computer to freeze in the middle of the
> compilation. Some background:
>
> Windows XP service pack 2
> Xilinx ISE 6.3.03i
> Xilinx EDK 6.3.02i
> ModelSim SE 6.0b
>
> The problem occurs both when I try to compile the simulation
libraries
> from the command line (compxlib -s mti_se -f all -l all) and from the
> ISE interface.
>
> Has anyone else encountered this problem? I haven't been able to find
> any good answers on the Xilinx support site and before I open a tech
> support call, I was curious if any of you have seen this problem --
and
> fixed it -- before.
>
> Regards,
> Dan
>
> --
> Daniel Alex Finkelstein
> Graduate Research Fellow
> Computer & Information Science
> Polytechnic University
> 5 MetroTech Center
> Brooklyn, NY 11201
> tel: 718-260-3378
> fax: 718-260-3609
> url: http://pages.poly.edu/~dfinke01


See Xilinx answer record 19712:
"Currently, ISE 6.3i and all previous versions of ISE are not supported
on Windows XP Service Pack 2. Xilinx will be fixing incompatibilities
that have been found to date in ISE 6.3i Service Pack 1, scheduled for
release in September 2004. Xilinx is committed to fixing other
incompatibilities as they are found, but will not be able to provide
official support for this specific version of Windows until ISE 7.1i,
to be released in early 2005."


Article: 78301
Subject: Re: Microscope examination of a PLD
From: "logjam" <grant@cmosxray.com>
Date: 28 Jan 2005 11:31:22 -0800
Links: << >>  << T >>  << A >>
Here are the results of decapping my IC...
http://www.stockly.com/forums/showthread.php?p=6#post6


Article: 78302
Subject: Re: LVDS without termination
From: "Symon" <symon_brewer@hotmail.com>
Date: Fri, 28 Jan 2005 11:46:11 -0800
Links: << >>  << T >>  << A >>
Kolja,
Oh dear, what claptrap you've had so far in response to your query. IMHO of
course! I guess you get what you pay for! Anyway, here's my guff.
The data rate is somewhat unimportant. What's the rise time of the signals
into your spartan3? Can you tell us what the driving part is?
Also, you should be aware that the trace length on the PCB is only part of
the signal path. There's also the leadframe/BGA package to consider. A rule
of thumb from that Howard Johnson chap, if the total signal path is less
than a sixth of the rise time, you're OK! Electric goes at about 160ps/inch.
Cheers, Syms.
BTW, LVDS/PECL/CML etc. can work without a termination resistor, and the DCI
thing has 'issues'. Browse the Xilinx answers thingy.



Article: 78303
Subject: Re: PCI X MSI Capability (XILINX Core)
From: Eric Crabill <eric.crabill@xilinx.com>
Date: Fri, 28 Jan 2005 11:47:00 -0800
Links: << >>  << T >>  << A >>

Hi,

The PCI-X core will not generate the writes for MSI.
You will need to watch the extended status from the
core to see if MSI is enabled -- and if so, you will
need to have your user application generate the write.

Eric

"Kedar P. Apte" wrote:
> 
> Hi All,
> 
> I am simulating a design with PCI X support (XILINX PCI X Core)
> to test MSI function of the PCI x device
> I am doing the following things at initialisation stage of the pci x
> device
> 
> 1. read capability pointers for MSI ID
> 2. initialise PCI high and low addresses (64 bit)
> 3. initialise 16 bit message.
> 4. enable MSI in the MSI control register specifying no. of messages
> in bit [6:4] of MSI control register.
> 
> I am facing following porblems
> 1. The INTA line is not getting asserted. as I am enabling MSI.
> 2. but no transaction is happening from the device for sending MSI
> when internally the interrupt is getting asserted.
> 
> can anybody tell me if anything I am missing or anything is wrong.
> 
> Thanks in advance
> Rgds
> kedar

Article: 78304
Subject: Re: LVDS through connectors
From: "Symon" <symon_brewer@hotmail.com>
Date: Fri, 28 Jan 2005 11:50:34 -0800
Links: << >>  << T >>  << A >>
Ian,
Good post, thanks.
Syms.



Article: 78305
Subject: Re: Rocket I/O + Optical Fiber
From: Quiet Desperation <nospam@nospam.com>
Date: Fri, 28 Jan 2005 12:00:01 -0800
Links: << >>  << T >>  << A >>
In article <1106931566.670306.136580@f14g2000cwb.googlegroups.com>, tom
<tnbiggs@yahoo.com> wrote:

> Where are you buying your cables? I find it hard to believe that the
> cost of the optics + fiber is cheaper than a cable. 

Compared to *a* cable, but I'm coming from a situation where we have
custom built, electrically timed/trimmed bundles of differential
cables. A harness like that can run well into five figures. And, like I
said, given fiber we might want to no longer colocate units that
previously were in the same rack simply to deal with the massive data
transfer between them. It's a comm system, and there's powerful
arguments for putting one of the units as close to the dish as
possible, and having the other tucked away in the receive shack. That
could be hundreds of feet.

> In my experience
> the cost is very much cheaper when you stay electrical, when your
> distances are not very far. Why not use standard cables like those made
> for Infiniband (meant for 3.125GHz)? There's also a standard for 10G
> Ethernet over copper cable. There's a reason it exists: cost!

If I can stay electrical, fine. That's why I'm looking for information.
I can't get a feel on the Xilinx site as to how much cable a Rocket I/O
port can drive. Cripes, it took me all day to discover it's CML. All
the datashets and app notes are focused on backplane applications. I'll
probably just buy a couple Pro X demo boards and connect them with
various lengths of cable, and I guess I need to get a field engineer
involved.

Article: 78306
Subject: Re: LVDS through connectors
From: Georgi Beloev <gbH8SPAM@beloev.net>
Date: Fri, 28 Jan 2005 12:04:11 -0800
Links: << >>  << T >>  << A >>
Ian Dedic wrote:
> We've also used standard dual-row 0.1" pitch headers/plugs with no
> problem at over 1Gb/s with 100ps risetime signals (from an Agilent
> 81250 ParBERT); so long as you use a pin arrangement like this
> 
> GND GND
> D0  D0B
> GND GND
> D1  D1B
> GND GND
> 
> the differential impedance is close to 100ohms with negligible
> crosstalk or reflections -- there's a virtual ground plane down the
> centreline.

Ian,

Thanks for the reply. I think this arrangement will also work well with 
standard flat cables that plug into the dual-row connectors. The wires 
in the cable will be ordered like that:

GND
GND
D0
D0B
GND
GND
D1
D1B
GND
GND

The crosstalk between adjacent LVDS pairs will be reduced by the two 
ground wires between them. Have you worked with such a connection? Does 
it perform well given that there are now two cheap and non-SI-optimized 
connectors at both ends of the cable?

Thanks,
-- Georgi

Article: 78307
Subject: New code FLASH memory
From: Jim Granville <no.spam@designtools.co.nz>
Date: Sat, 29 Jan 2005 09:40:23 +1300
Links: << >>  << T >>  << A >>
For those working on SoftCPU, this looks interesting...

http://www.st.com/stonline/press/news/year2005/p1563m.htm

32MBit, $6 (vol?), Automotive, 75MHz burst modes, 32 bit access,
various protection schemes... 80 pin qfp and BGA packages.

since most of the larger soft CPUs need a code storage device,
this would be a good candidate, with perhaps some cache locking
for really fast code?.
-jg




Article: 78308
Subject: Re: How do I get the contents in FPGA
From: "Jezwold" <edad3000@yahoo.co.uk>
Date: 28 Jan 2005 13:07:37 -0800
Links: << >>  << T >>  << A >>
The ACEX is a static ram based device which means that its confuration
data is loaded into it each time it is powered up>it depends on what
type of system you have as to how that configuration data is loaded
into the fpga.Most commonly there is a dedicated  configuration memory
which automaticaly load the data at startup,sometimes an embedded micro
loads the data,so you need to know what type of system you are dealling
with.


Article: 78309
Subject: Altera Quartus 4.2 Service Pack 1 fails to install
From: Jedi <me@aol.com>
Date: Fri, 28 Jan 2005 22:34:21 GMT
Links: << >>  << T >>  << A >>
Apparently Altera was too quick in releasing SP1.

It is just too stupid to find any previous 4.2 installation.



rick


Article: 78310
Subject: Sensitive List Question
From: "James" <james_h@hotmail.com>
Date: Sat, 29 Jan 2005 01:02:23 +0100
Links: << >>  << T >>  << A >>
Hello

I have got a statemachine which is sensitive on current_state and a start
Signal. Everything is working fine but when I synthesize my design the tool
gives me a warning that signals in the sensitive list are missing. In detail
it is a counter signal and a intern register of the state machine.

So my question is: Do I have to add these signals to my sensitive list,
although if the change there has no effect at all? Or can I also leave them
out and ignore this warning from the synthesizer?

Thanks
James




Article: 78311
Subject: Re: Copying/Reverse Engineering PAL
From: Eric Smith <eric-no-spam-for-me@brouhaha.com>
Date: 28 Jan 2005 17:20:37 -0800
Links: << >>  << T >>  << A >>
"Kryten" <kryten_droid_obfusticator@ntlworld.com> writes:
> Okay. The master clock source (16 MHz) seems unclear from the schematic.
> I can't see an oscillator module or even a quartz crystal.
> Easily produced though.

If we're still talking about the original Macintosh (or Plus, SE),
the main oscillator is 15.6672 MHz.

Article: 78312
Subject: Re: EDK 6.3 Eval with Spartan 3 Starter Kit
From: Eric Smith <eric-no-spam-for-me@brouhaha.com>
Date: 28 Jan 2005 17:22:04 -0800
Links: << >>  << T >>  << A >>
"newman5382" <newman5382@yahoo.com> writes:
> Does anybody know what the limitations are with the EDK 6.3 Evaluations 
> software that comes with the Xilinx Spartan III Starter Kit DO-SPAR3-DK.

And is there a way for those of us that bought the S3 Starter Kit before
the EDK 6.3 Evaluation was bundled can get one?

Article: 78313
Subject: Re: lowest-cost FPGA and CPLD
From: Eric Smith <eric-no-spam-for-me@brouhaha.com>
Date: 28 Jan 2005 17:31:30 -0800
Links: << >>  << T >>  << A >>
"Johnson Liuis" <gpsabove@yahoo.com> writes:
> I heard that Lattice Semiconductor Corporation boasted they were providing
> the lowest-cost FPGA and CPLD solutions, not sure if the news was true.
> Could anybody confirm it? If so could anybody give me a price range for
> their lowest-cost solution?

I don't know about the Lattice parts, but some of the Xilinx CPLDs are
*very* inexpensive.  For example, the XC9536XL is under $1.07 in
quantity 100 from Digikey.  I haven't been able to buy 22V10 or even
16V8 style CPLDs for less.

The Spartan 3 FPGAs also seem to have amazingly good pricing.

I haven't compared Altera pricing, but I imagine that they must be
competitive.

Article: 78314
Subject: Re: Altera Quartus 4.2 Service Pack 1 fails to install
From: "Subroto Datta" <sdatta@altera.com>
Date: Sat, 29 Jan 2005 05:53:07 GMT
Links: << >>  << T >>  << A >>
Hello Jedi,
    Quartus II 4.2 allows for multiple installations to co-exist on a 
computer. Prior versions of Quartus II i.e 4.1 and earlier allowed only a 
single installation to exist on a computer at any one time. When you install 
multiple versions of Quartus II 4.2 you are prompted to give each 
installation a name for identification purposes. The default name for the 
second copy is Quartus II 4.2 (2nd Copy) and this is echoed for the user to 
change if desired.

At the time of installing Quartus II 4.2 SP1 (Subscription Version) you will 
be prompted to select which of the different installations of Quartus 4.2, 
the Service Pack should be installed in.

This process is checked out as part of the QII 4.2 Software release 
verification process, and just to be sure once more I tried it once more 
using the download from www.altera.com. Therefore if you have a specific 
problem, please describe whether you had given your installations diffrent 
names, and whether you were prompted to choose between the different Quartus 
II 4.2 installations when the Quartus II 4.2 SP1 executable was run.

Subroto Datta
Altera Corp.


"Jedi" <me@aol.com> wrote in message news:N5zKd.574$Xu6.302@read3.inet.fi...
> Apparently Altera was too quick in releasing SP1.
>
> It is just too stupid to find any previous 4.2 installation.
>
>
>
> rick
> 



Article: 78315
Subject: Re: What's new in MicroBlaze 3.00a?
From: "AdamS" <sutongqi@gmail.com>
Date: 28 Jan 2005 22:03:47 -0800
Links: << >>  << T >>  << A >>
thanks
It seems that EDK 6.3i has updated a lot


Article: 78316
Subject: Quartus II megafunction
From: ahmato_abdo@hotmail.com (Ahmad)
Date: 28 Jan 2005 22:26:39 -0800
Links: << >>  << T >>  << A >>
Dear,

I am trying to create a Single Port Ram, using MegaWizard Plug in
Manager in Quartus II 4.0. So I choose the Storage section: LPM_RAM_IO
(which should have only one port for read/write), after typing the
name, and clicking next, the function return to LPM_RAM_DQ (which has
one port input and one output). Did anyone has this bug before??

I even checked the entity of the LPM_RAM_IO and there is dio[] inout
port...LPM_RAM_DQ and LPM_RAM_IO are completely different modules!!!

Any help is much appreciated,
regards,
Ahmad.

Article: 78317
Subject: Re: Sensitive List Question
From: "Jezwold" <edad3000@yahoo.co.uk>
Date: 29 Jan 2005 00:25:26 -0800
Links: << >>  << T >>  << A >>
Firstly its called a sensitivity list :)
and secondly its really only used by simulators the synthesis tools
don't actualy take any notice of what is and what isnt on the
sensitivity list when synthesising logic.


Article: 78318
Subject: Re: Sensitive List Question
From: "Jezwold" <edad3000@yahoo.co.uk>
Date: 29 Jan 2005 00:39:08 -0800
Links: << >>  << T >>  << A >>
I should add that if you have simulated something with an item missing
from the sensitivity list,then the reason you get a warning from the
synthesis tool is that the behaviour of the synthesised logic may
differ from what you simulated because sensitivity list items do have a
profound effect on how your simulation will behave.


Article: 78319
Subject: How to change the font in EDK's text editor?
From: "AdamS" <sutongqi@gmail.com>
Date: 29 Jan 2005 00:41:22 -0800
Links: << >>  << T >>  << A >>
the font in ISE's text editor could be changed and how about EDK's?
I couldn't find the entry.

I saw the font in Xilinx's demo video are comfortable, but not in my
EDK.

Anyone knows how to change the font? thx^_^


Article: 78320
Subject: Re: Altera Quartus 4.2 Service Pack 1 fails to install
From: Jedi <me@aol.com>
Date: Sat, 29 Jan 2005 08:42:53 GMT
Links: << >>  << T >>  << A >>
Subroto Datta wrote:
> Hello Jedi,
>     Quartus II 4.2 allows for multiple installations to co-exist on a 
> computer. Prior versions of Quartus II i.e 4.1 and earlier allowed only a 
> single installation to exist on a computer at any one time. When you install 
> multiple versions of Quartus II 4.2 you are prompted to give each 
> installation a name for identification purposes. The default name for the 
> second copy is Quartus II 4.2 (2nd Copy) and this is echoed for the user to 
> change if desired.
> 
> At the time of installing Quartus II 4.2 SP1 (Subscription Version) you will 
> be prompted to select which of the different installations of Quartus 4.2, 
> the Service Pack should be installed in.

Installed a 2nd copy of Quartus 4.2 but it still fails to find any
installation. Just keeps telling:

"Quartus 4.2 Full Version is not isntalled on this machine."

> 
> This process is checked out as part of the QII 4.2 Software release 
> verification process, and just to be sure once more I tried it once more 
> using the download from www.altera.com. Therefore if you have a specific 
> problem, please describe whether you had given your installations diffrent 
> names, and whether you were prompted to choose between the different Quartus 
> II 4.2 installations when the Quartus II 4.2 SP1 executable was run.

I haven't given a different name during Quartus installation.
And the directories are located as normal in c:\altera\quartus42.

So what does it look for exactly? Environment settings?


rick


> 
> Subroto Datta
> Altera Corp.
> 
> 
> "Jedi" <me@aol.com> wrote in message news:N5zKd.574$Xu6.302@read3.inet.fi...
> 
>>Apparently Altera was too quick in releasing SP1.
>>
>>It is just too stupid to find any previous 4.2 installation.
>>
>>
>>
>>rick
>>
> 
> 
> 

Article: 78321
Subject: Re: Quartus II megafunction
From: "Jezwold" <edad3000@yahoo.co.uk>
Date: 29 Jan 2005 00:47:38 -0800
Links: << >>  << T >>  << A >>
I havent seen this bug but wouldn't it be better to directly
instantiate the single port ram in your code rather than using the
wizard function?From what i have seen all they do is generate a
standard instatiation with all the correct values plugged in. I don't
use them myself because most of the time they seem more trouble then
they are worth.


Article: 78322
Subject: Altera subscriptions deleted?
From: Jedi <me@aol.com>
Date: Sat, 29 Jan 2005 08:55:02 GMT
Links: << >>  << T >>  << A >>
What happended to the susbcription information
if you log into your "mySupport" page at Altera?


Altera_ID and software subscription informations are gone!


rick

Article: 78323
Subject: Re: Altera subscriptions deleted?
From: "Leon Heller" <leon_heller@hotmail.com>
Date: Sat, 29 Jan 2005 09:21:09 -0000
Links: << >>  << T >>  << A >>
"Jedi" <me@aol.com> wrote in message news:GbIKd.68$2p.27@read3.inet.fi...
> What happended to the susbcription information
> if you log into your "mySupport" page at Altera?
>
>
> Altera_ID and software subscription informations are gone!

I just checked, and the Altera web site was down. Perhaps they are fixing 
the problem.

Leon
-- 
Leon Heller, G1HSM
http://www.geocities.com/leon_heller 



Article: 78324
Subject: Re: Sensitive List Question
From: "James" <james_h@hotmail.com>
Date: Sat, 29 Jan 2005 12:42:54 +0100
Links: << >>  << T >>  << A >>

"Jezwold" <edad3000@yahoo.co.uk> schrieb im Newsbeitrag 
news:1106987948.225608.116210@c13g2000cwb.googlegroups.com...
>I should add that if you have simulated something with an item missing
> from the sensitivity list,then the reason you get a warning from the
> synthesis tool is that the behaviour of the synthesised logic may
> differ from what you simulated because sensitivity list items do have a
> profound effect on how your simulation will behave.

in the end I should just add all my values to the sensitivity list, so that 
the synthese tool is happy? 





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