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"Tobias Weihmann" <listen@fomalhaut.de> schrieb im Newsbeitrag news:1123462503.096899.87040@g47g2000cwa.googlegroups.com... > Hello. > > I'm new to Spartan-3, before I only worked on the legacy XC6216 FPGA. I > am trying to port a university project over to a modern FPGA platform. > > I assume that the full details of the Spartan-3 bitstream are not > published beyond what is described in XApp452 (XC6216 bitstream was > fully published). > > Also I assume that it is possible to damage the FPGA using invalid > bitstreams (as opposed to the XC6216). > > I want to generate a placed & routed design using my own custom > algorithms and then upload it to the Spartan-3, without resorting to > PAR tools and such. > > At what point would I have to enter the workflow? Convert my design to > NCD files? (Most likely, the NCD format is closed as well?) > > Thank you, Tobias > Hallo Tobias, could you contact me in private? I see you like science fiction, but fomalhout star system seems not to have internet connection yet. AnttiArticle: 88051
Hi Andy, your answer does not really answer my question. Independently of whether I use the redudant assignment in my VHDL or not the holding of the D-flip flop is the problem. Is it possible to fit it into an output register ? Rgds Andr=E9Article: 88052
Hi there, i am trying to run the modular designflow with multiple instances of one module. NGDBuild says Error:NGDBuild:560 Found 4 sctive blocks of module ... The reference Guide tells me that I will have to use -use_pim for each instance of my module, but only when I do my final assembly. So what do I have to do in the active module phase to tell ngdbuild that I want to use multiple instances? Thanks for your help... C.LauerArticle: 88053
Hello Eric Thanks for the psuedo code.It does help to understand the concept of evolutionary algorithms.Now can you also give the code.I am very eager to implement it. Thanks again AnkitArticle: 88054
hi could somebody help me with this error message i get from model sim se? i'm trying to simulate (post place and route) my design and get the following error message: "error code: Failure: (vsim-3807) Types do not match between component and entity for port key_input" My signal key_input is a integer right now (normally it is my own data type but i changed it because i thought perhaps models sim can't handel that). if i change it to std_logic i can simulate. the behavioral simulation works just fine even with my datatype. i checked my design module and the test bench and the datatypes are the same in the entity and the component declaration. if it helps i can post the source. any ideas somebody? thanks UrbanArticle: 88055
Hello Urban,
i have also had problems like you. if you have look into the
translated model =F3f your code you will be able to understand it
better.
I would always suggest that yout top level entity should be with the
std_logic or vector types. This should be the best solution. once your
are into the architecture, if you want to change the types, you can use
other possible converting types. Then you will not face any problems
while simuting through all the phases.
Regards,
J=2EAnil Kumar.
u_stadler@yahoo.de wrote:
> hi
>
> could somebody help me with this error message i get from model sim se?
> i'm trying to simulate (post place and route) my design and get the
> following error message:
> "error code: Failure: (vsim-3807) Types do not match between component
> and entity for port key_input"
>
> My signal key_input is a integer right now (normally it is my own data
> type but i changed it because i thought perhaps models sim can't handel
> that). if i change it to std_logic i can simulate.
> the behavioral simulation works just fine even with my datatype.
> i checked my design module and the test bench and the datatypes are the
> same in the entity and the component declaration.
> if it helps i can post the source.
> any ideas somebody?
>=20
> thanks
> Urban
Article: 88056
ravindra kalla wrote:
> hi,
>
> i m doing project on image processing.For that i need to store pixel
> value of any frame in memory. I read from one journal that there is
> one circular read address generator which is used to generate physical
> address from logical address this help to reduce the size of memory.
>
> I have to store 30*32 pixel in memory.NOW for that i have to generate
> physical address for those memory location.THey suggest circular read
> address generator for this.
>
> But i never read about circular read address generato.So please
> anybody tell me about this generator.
> Is it possible to reduce memory size using this method.
>
I don't know what you mean by "logical address" and "physical address"
in your context.
But a circular address generator for me would count
0 1 2 ... (30*32)-1 0 1 2 ...
so
-------< CUT >----------
signal rst:std_logic;
signal clk:std_logic;
signal cnt:std_logic_vector(9 downto 0);
process(clk)
begin
if rising_edge(clk) then
if rst='1' then
cnt <= (others => '0');
else
if (cnt = "1110111111") then
cnt <= (others => '0');
else
cnt <= cnt + 1;
end if;
end if;
end if;
end process;
-------< CUT >----------
Note that if you don't need it to count upwards (i.e. just for a FIFO
without direct access), the downwards version might be smaller.
-------< CUT >----------
signal rst:std_logic;
signal clk:std_logic;
signal cnt:std_logic_vector(9 downto 0);
signal cnt_n:std_logic_vector(10 downto 0);
cnt_n <= ("0" & cnt) - 1;
process(clk)
begin
if rising_edge(clk) then
if rst='1' or cnt_n(10)='1' then
cnt <= "1110111111"
else
cnt <= cnt_n(cnt'range);
end if;
end if;
end process;
-------< CUT >----------
I'm not sure that's what you're looking for but for me that's what a
circular address generator is.
Sylvain
Article: 88057The problem is not with Quartus but with the component you will use, of which you don't tell us anything. NicolasArticle: 88058
Hello, I am working on cryptographic application over VirtexII FPGAs. I need to store a simmetric key inside a reg of the FPGA, but I dont want that someboy could read it analizyng the bitstream. The bitstream could not be encrypted. Has anybody experience about hide data inside a FPGA?. Anyone knows some papers about this topic? Regards JavierArticle: 88059
Nicolas Matringe schrieb: > The problem is not with Quartus but with the component you will use, of > which you don't tell us anything. > > Nicolas CycloneI EP1C12Article: 88060
Hi, I want to design a sequence detector circuit, there are two approaches . The first approach is the traditional state m/c approach The second is shift register approach for ex: for detecting sequence "10101011" i put a simple 8 bit shift register and look for the pattern "10101011" .I check the shft register value in each cycle whenever the shift register value is "10101011" the output is set to "1". Which method is better the traditional state m/c approach or the shift register approach for sequence detection. Regards, PraveenArticle: 88061
Javier Castillo wrote: > Hello, > > I am working on cryptographic application over VirtexII FPGAs. I > need to store a simmetric key inside a reg of the FPGA, but I dont > want that someboy could read it analizyng the bitstream. The bitstream > could not be encrypted. Has anybody experience about hide data inside > a FPGA?. Anyone knows some papers about this topic? > > Regards > > Javier Hiding a key should be easy if your "reg of the FPGA" is formed by a non-contiguous set of flip-flops. Unless the person reading the bitstream understands the register's usage within the FPGA, they could not determine which of the bitstream bits make up the "reg" and in what order. Try to avoid regular structures (like relational place macros) for your register and either place the flip-flops randomly by hand, or set the placement switches to ignore register ordering when you place and route.Article: 88062
praveen.kantharajapura@gmail.com wrote: > Hi, > I want to design a sequence detector circuit, there are two approaches > . > > The first approach is the traditional state m/c approach > > The second is shift register approach > for ex: for detecting sequence "10101011" i put a simple 8 bit shift > register and look for the pattern "10101011" .I check the shft register > value in each cycle whenever the shift register value is "10101011" the > output is set to "1". > > Which method is better the traditional state m/c approach or the shift > register approach for sequence detection. > > Regards, > Praveen You'll need to define "better" in this case. If you need to run faster, the state machine may do better because it only handles one bit at a time. If you need to change the pattern you're detecting, the shift register and comparator will make life much easier. Also the shift register approach gets slower and bigger as the size of your pattern increases. Either approach can be optimised for a fixed pattern (the comparator turns into an AND gate for the fixed case). The state machine can be further optimised if the pattern is "regular" (symmetric or repeating). I guess the answer is "it depends..."Article: 88063
Javier Castillo wrote: > Hello, > > I am working on cryptographic application over VirtexII FPGAs. I > need to store a simmetric key inside a reg of the FPGA, but I dont > want that someboy could read it analizyng the bitstream. The bitstream > could not be encrypted. Has anybody experience about hide data inside > a FPGA?. Anyone knows some papers about this topic? > > Regards > > Javier I'd say force the placement of theses regs around. And you can also make a small logic block that "calculates" the key from apparently random data. SylvainArticle: 88064
On 8 Aug 2005 06:16:01 -0700, "Gabor" <gabor@alacron.com> wrote: > >Javier Castillo wrote: >> Hello, >> >> I am working on cryptographic application over VirtexII FPGAs. I >> need to store a simmetric key inside a reg of the FPGA, but I dont >> want that someboy could read it analizyng the bitstream. The bitstream >> could not be encrypted. Has anybody experience about hide data inside >> a FPGA?. Anyone knows some papers about this topic? >> >> Regards >> >> Javier > >Hiding a key should be easy if your "reg of the FPGA" is formed by a >non-contiguous set of flip-flops. Unless the person reading the >bitstream >understands the register's usage within the FPGA, they could not >determine >which of the bitstream bits make up the "reg" and in what order. Try >to avoid regular structures (like relational place macros) for your >register and either place the flip-flops randomly by hand, or set >the placement switches to ignore register ordering when you place and >route. A problem arises if you are making more than one device though if they need different keys, as an attacker could compare the bitstreams to find where the key is stored. Adding a significant amount of extra random data would make it harder. Another thing you could do is store a large block of data in a RAM element, with multiple levels of indirection, i.e. some bits determine the location of other bits, which determine the location of other bits etc., with the rest filled with random data.Article: 88065
//-------Creates Initial Population
-------------------------------------------------
for (int k=0; k < Popsize; k++)
{
for(int h=0; h < max; h++)
{
Population[k].SingleVector[h]=rand() % 2;
}
StoreCover[k]=evaluate(Faults, Population[k].SingleVector);
}
//--- Genetic Algorithm Iterations
-------------------------------------------------------
for (int y=0; y < 10; y++) //---- 10 itertions
{
total=0;
//------Repopulation Based on Coverage Criterian
-------------------------------------
posistion=1;
value1=0;
value2=0;
value3=0;
for (k=0; k < max; k++)
Population[0].repopulation[k]=Population[0].SingleVector[k];
// ---- Makes sure non of the values repeat in repopulation
for (k=1; k < Popsize; k++)
{
for (int h=0; h<k ;h++)
{
value1=0; value2=0;
for (int L=0; L < max; L++) if (Population[h].repopulation[L]==1)
value1=value1+ pow(2,L);
for (L=0; L < max; L++) if (Population[k].SingleVector[L]==1)
value2=value2+ pow(2,L);
if (value1 != value2)
{
value3=0;
}else{ value3=1; h=k;}
}
if (value3==0)
{
for (int j=0; j < max; j++)
Population[posistion].repopulation[j]=Population[k].SingleVector[j];
posistion++;
}
}
// cout << "Fixed population \n";
for (k=0; k < posistion; k++)
{
// for (int n=0; n< max; n++)
// {
// cout <<Population[k].repopulation[n];
// }
StoreCover[k]=evaluate(Faults, Population[k].repopulation);
// cout << " " << StoreCover[k] << "\n";
}
// cout << "\n\n\n";
for (k=0; k < posistion; k++)
{
total=total+ StoreCover[k];
}
// cout << "\n\n total=" <<total;
for (int p=0; p<Popsize; p++)
{
random=rand() % 101; //Generates random populations
// cout << "\n";
int start=0, end=0;
for (k=0; k < Popsize; k++)
{
start=end;
end=end+(StoreCover[k]*100/total);
if ((random>=start) && (random<end))
{
for (int n=0; n< max; n++)
{
Population[p].NewVector[n]=Population[k].repopulation[n];
// cout <<Population[k].SingleVector[n];
}
}
}
}
// cout <<"\n";
for (k=0; k < Popsize; k++) //--Swaps NewVector with SingleVector
{
for (int n=0; n< max; n++)
{
Population[k].SingleVector[n]=Population[k].NewVector[n];
// cout <<Population[k].SingleVector[n];
}
StoreCover[k]=evaluate(Faults, Population[k].SingleVector);
// cout << " " << StoreCover[k] << "\n";
}
//------------------------------------------------------------------------------------
// ------ Cross Overs
----------------------------------------------------------------
int random1=rand() % Popsize; //Find 1st vector to swap
int random2=rand() % Popsize; //Find second Vector to swap
int random3=rand() % max; //Finds place to cut
int temp=0;
// cout << "Cross Over " << random1 << " " << random2 << " " <<
random3 <<"\n";
for (int n=0; n< random3; n++)
{
temp=Population[random1].SingleVector[n];
Population[random1].SingleVector[n]=Population[random2].SingleVector[n];
Population[random2].SingleVector[n]=temp;
}
for (k=0; k < Popsize; k++)
{
// for (n=0; n< max; n++)
// {
// cout <<Population[k].SingleVector[n];
// }
StoreCover[k]=evaluate(Faults, Population[k].SingleVector);
// cout << " " << StoreCover[k] << "\n";
}
//------------------------------------------------------------------------------------
// ------ Mutation
----------------------------------------------------------------
random1=rand() % Popsize; //Find 1st vector to swap
random3=rand() % max; //Finds place to swap
// cout << "Mutation " << random1 << " " << random3 <<"\n";
if (Population[random1].SingleVector[random3]==0)
Population[random1].SingleVector[random3]=1;
else Population[random1].SingleVector[random3]=0;
for (k=0; k < Popsize; k++)
{
// for (n=0; n< max; n++)
// {
// cout <<Population[k].SingleVector[n];
// }
StoreCover[k]=evaluate(Faults, Population[k].SingleVector);
// cout << " " << StoreCover[k] << "\n";
}
//------------------------------------------------------------------------------------
}
//-------------Displays final population
---------------------------------------------------
// cout << "Final Set of Vectors\n";
for (k=0; k < posistion; k++) //posistion = number of elements
{
for (int n=0; n< max; n++)
{
// cout <<Population[k].repopulation[n]; //final nonrepeating
elements
}
StoreCover[k]=evaluate(Faults, Population[k].SingleVector);
// cout << " " << StoreCover[k] << "\n";
}
}
Article: 88066Anyone worked on a ZLIB implementation? I am solely interested in the RLC only version. Cheers, IrishArticle: 88067
Hey, i get this warning from the bitgen log and i was wondering if this is a problem or just a warning i can ignore? WARNING:PhysDesignRules:812 - Dangling pin <REV> on block:<DD_2_OUT_9_OBUF/dvi/oddr_dvi_out29/FF2>:<OLOGIC_OFF3>. thanks in advance, kind regards, timArticle: 88068
Hi in the PACE tool you can select "Show Clock Regions". Or you look in the FPGA editor and search the BUFR buffers ans select an output of this. florianArticle: 88069
Pratip Mukherjee wrote: > Can anybody please tell me where can I find the documentation on the list > of functions included in the Small version of NIOS C library (newlib)? > Altera's documentation really not helping me. > Thanks. not sure if you are directly looking for newlib http://sources.redhat.com/newlib/ HeinzArticle: 88070
vssumesh wrote:
> Thanks for the suggestion. I am experimenting with the generate key
> word.
> But while doing that some problem observed. the following code gave
> error.
> "index out of range".
>
> for(i = 0; i<= 7;i=i+1)
> begin
> assign A[i] = (i!=0)?B[i]&C[i-1]:1;
> end
This may only be a warning, since the behavior is perfectly well
defined in Verilog. And since the C[i-1] part is thrown away when i
was zero, it really doesn't matter. However, perhaps your tool is
being extra strict.
> because of this error i am forced to split the loop. Is there any way
> to do this in a single loop???
Well, you could keep the index in range in the i==0 case also, even
though you are throwing it away, with something like
assign A[i] = (i!=0)?B[i]&C[(i!=0)?(i-1):0]:1;
Or you could put a generate-if inside the generate-for-loop:
for(i=0; i<=7; i=i+1)
begin
if (i!=0)
assign A[i] = B[i]&C[i-1];
else
assign A[i] = 1;
end
BTW, if A, B and C are vectors, then this is a very inefficient way to
do this. Why use 8 continuous assignments of 1 bit at a time, when you
could do a single vector continuous assignment? This code only makes
sense if these are arrays of multi-bit vectors.
Article: 88071Sean Durkin (smd@despammed.com) wrote: : Hi Austin, : austin wrote on 04/08/05 21:11: : > 'DONE does not go high' is the #1 complaint we get : What's #2? :) : For me the biggest complaint is the drivers for the Parallel Cable IV. : The same cable works fine on one PC, but is detected as a Parallel Cable Probably a silly/redundant question, but the parallel port is set to ECP mode in the BIOS of the PCs where the IV cable falls back to a III? It's got me before... --- cds : III on another, no matter what settings you use for the parallel port, : and no matter what kind of board you hook it up to. Most of the time : it's slow as hell, taking a minute or so to program a bigger V2P, which : makes rapid prototyping not so rapid anymore... After spending a few : days trying out different cables with different PCs and all ISE-releases : and Service Packs I could get a hand on, and doing a *LOT* of research, : I found that the problem is definitely that Jungo : windriver-parallel-port-thingie you ship with ISE. On their website it : just says that with "some parallel port chips" it simply doesn't work : well, mostly "Intel based chips" (and these are so rare to come by these : days...), and that's that... : We're starting to switch to USB platform cables, but there's still a : whole bunch of parallel cables in use which would be okay if only that : driver worked on more machines... : cu, : SeanArticle: 88072
Hi Tim, It's always a good practice to determine the cause of any warning in FPGA design. Otherwise you can spend a lot of time searching why a design doesn't work as you expected. Regards, Luc On 8 Aug 2005 07:25:43 -0700, "Tim Verstraete" <tim.verstraete@barco.com> wrote: >Hey, > >i get this warning from the bitgen log and i was wondering if this is a >problem or just a warning i can ignore? > >WARNING:PhysDesignRules:812 - Dangling pin <REV> on > block:<DD_2_OUT_9_OBUF/dvi/oddr_dvi_out29/FF2>:<OLOGIC_OFF3>. > >thanks in advance, > >kind regards, > >timArticle: 88073
I found this Masters Thesis on how one person use Genetic Algorithms to create a FPGA netlist. http://www.ce.chalmers.se/~mekman/MasterThesis.pdf Pretty Good Masters project.Article: 88074
Hello, Because I am working with a prototype system and don't care about temp, voltage and process variation. I am using buffers to insert the delay. I am using the "KEEP" synthesis attribute on the inputs and outputs of the buffers to prevent them from being optimized away. I then use a scope to measure the delay. You can also do post PAR timing simulation, but is not as exact. Finally, I use FPGA Editor to check to see that the singals exist and buffers are mapped to the CLB's. Cheers, JOhn On Wed, 20 Jul 2005, John D. Davis wrote: > Hello, > > I am interfacing a XCV1000 to an old MIPS R3000. I am generating a 50 MHz > clock using a DLL with an input clock of 25 MHz. The spec for the R3000 > requires certain timing for 4 output clocks based on the 50 MHz clock. > One clock is the reference 50MHZ clock. Two of the output clocks need to > be delayed by 6 ns and the fourth clock by 12 ns. I can use a second DLL > to generate 90 and 180 degree phase shifted clocks, but that gives me 5 ns > and 10 ns and not 6 ns and 12 ns, respectively. There are some other > delayed signals that I need to generate as well. One signal has to lag > the 50 MHz clock by 3 ns. Is there a way to easily generate specified > signal delays? For registered values, the OFFSET keyword seems to be > appropriate, but I am just using output buffers on the clock signals now. > This is for a research project using a custom PCB with 4 processor tiles. > Each processor tile has 2 XCV1000s, 1 MIPS R3000 and R3010 and SRAMs for > the cache. There are also 2 XC2V6000s to control processor communication > and a second level of SRAMs. The other approach is inserting buffers and > forcing XST to not optimize them away. Are there easier approaches that > have worked for others? I am using ISEE 6.3i. I also have access to > Modelsim and an oscilloscope. > > Thanks for the suggestions, > John Davis > > John D. Davis PhD Candidate Computer Systems Lab Office # 1.650.723.6891 Stanford University Fax # 1.650.725.6949
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z