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"GaLaKtIkUsT" <taileb.mehdi@gmail.com> schrieb im Newsbeitrag news:1129553268.672939.220110@g49g2000cwa.googlegroups.com... > Is there a way to use chipscope with a card which works with an old > XChecker cable? > 1 NO. 2 NO, unless you reverse engineer both XCechker protocol and ChipScope server protocol and write your own Chipscope server (that takes requests from chipscope and forwards to xcecker). AnttiArticle: 90576
I was porting a code form a friend who was working with Altera Quartus. That is where i saw the use of logic operations and concatenation within port mapping statements. Perhaps Quartus is not so strict with the syntax. Thanks very much.Article: 90577
Thanks! Yeah the problem is im a chemical engineer doing research with very basic electronic engineering knowledge. I need a kick in the right direction. There is alot of stuff out there, i just need to figure out the right path. Current help and more is very much appreciated! Cheers! -- ---------------------------------------------- Posted with NewsLeecher v3.0 Final * Binary Usenet Leeching Made Easy * http://www.newsleecher.com/?usenet ----------------------------------------------Article: 90578
On 17 Oct 2005 14:18:54 GMT, kd (pingboypulsar<spamoff>@hotmail.com) wrote: >Yeah the problem is im a chemical engineer doing research with very >basic electronic engineering knowledge. > >I need a kick in the right direction. There is alot of stuff out >there, i just need to figure out the right path. Current help and >more is very much appreciated! ouch... I have a nasty feeling that this is a bit the same as me asking you "please explain how I can build a plant to manufacture 10 tons of ammonia per week" - it's very well-established technology, very easy when you know how, but not something that you should try unless you have a clear idea of what you are doing :-) When I said "almost trivial", I meant "almost trivial for a reasonably well trained digital designer". I don't think it's a very productive use of your or our time to provide you with all the necessary background via Usenet. Get yourself a competent design contractor, watch what he/she does very closely, take their results and modify it as needed to suit your next project... it'll be a few thousand dollars well spent. If you're building industrial instrumentation, or planning to build it, then you have *some* budget surely? This post sounds a bit negative. Apologies... but I strongly suspect that you are a bit too far away from success just yet for Usenet to be your rescue. Please forgive me if I've misjudged. -- Jonathan Bromley, Consultant < oh, and speaking of competent contractors... > DOULOS - Developing Design Know-how VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK Tel: +44 (0)1425 471223 mail:jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 90579
In the Leonardo spectrum there is a Device under the ASIC tab "SCL05U" whats that means ??. I thought it is some kind of device like FPGA in which we can implement the transistor kind of thing. I have searched through net for asic etc and saw an article desribing the structured asic and the platform asic whats the difference between that. The problem with me i am implementing a large design. But due to the inefficiency of the LUT based design of the FPGA i am only verifying a subset of the orginal design (in the Virtex2 XC8000). So how can i test the entire design before moving into the FAB and costly things ???Article: 90580
Xilinx's asynchronous fifos have a depth of (power of 2) -1 bytes. According to my analysis, using Xilinx's application notes, the reason of it is that full flag can be really generated 1 writing clock period after it is really expected. To overcome overflowing, the fifo depth is decreased by 1. AlexArticle: 90581
hi, im trying to use i2c open source core available from opensorces.org and having problems with cofiguring the "scl" and "sda" from the top level design with the use of IO buffers. if anyone got experience on how to correctly configure these two ports from a top level hierachy, pls let me know. thank you. CMOSArticle: 90582
Hi, Thanks everybody for the help. Ok, here's what I have figured out so far which I am planning to use. 1) I will generate the data in a text file using Python scripts. 2) Will probably write another script or use Matlab to convert this to a .mem format which is readable by Xilinx. 3) Will use data2mem from command line to convert .mem file to either a .bit file or .v file. I will first try with verilog file, which I will then include into the project. The verilog file will contain the initialization for the RAM. Later on, I am planning to just use data2mem to generate .bit file, so that I can directly download it to the FPGA. (The different web-pages on Xilinx talk about .elf file, but as I don't have any code to write on the FPGA, but rather just some data, I don't know whether I should be concerned about this or not) Now, if I understand it correctly, these are the only steps required. Is it necessary to do something about the RAM in the hardware design? Like specifying where to store, the memory design etc? Robert.Article: 90583
> Get yourself a competent design contractor, watch what > he/she does very closely, take their results and modify > it as needed to suit your next project... it'll be a > few thousand dollars well spent. If you're building > industrial instrumentation, or planning to build it, > then you have *some* budget surely? If you are building industrial instrumentation, you might want to spend the money the next time as well. Electronic design (not just the FPGAs) has lots of ways to produce less than ideal results. Ground loops, proper power bypassing, signal integrity, and a list of other issues can give you a circuit that doesn't work, or even worse works most of the time. >< oh, and speaking of competent contractors... > Can I do that here as well? -- Phil Hays to reply solve: phil_hays at not(coldmail) dot com If not cold then hotArticle: 90584
All, http://tinyurl.com/clzqh Details the latest readouts for actual single event upsets for Virtex 4, and Spartan 3. The improvements (6 times fewer upsets for Virtex 4, and 2.4 times fewer upsets for Spartan 3 as compared to Virtex II) shows our commitment to making this a non-issue for our customers. Make sure you demand from you ASIC/ASSP/FPGA vendor reports on their SEU susceptibility! This is not an area where you should take this for granted. Reducing SEU susceptibility is not something the foundry builds in to their process; it is something that takes time and effort on the part of IC designers to implement, and more time and effort to verify. For a vendor to claim "oh, we do what Xilinx does..." is completely insufficient. We certainly are not telling anyone how we did this (6X improvement): just that we have done this. The only other company that we are aware of with a "Rosetta"-like program (work with foundry on process; design, simulation, and analysis by IC designers; measurements in neutron and proton beams; actual atmospheric testing in multiple locations at multiple altitudes) is Cypress. Imitation is the sincerest form of flattery. Additionally, Cypress has a good book on the effects of cosmic ray neutrons and protons on memories. http://tinyurl.com/72mvw For more details, contact your FAE. They have materials accessible to them for customer presentations on this issue. AustinArticle: 90585
Let me correct this: The addressing depth of Virtex-4 FIFOs is 512, 1024, 2048, or 4096 locations. The word "byte" is meaningful only for the 2048 x 9 configuration. The FULL flag goes active one write clock cycle after the FIFO has been filled. That means, in a continuous write situation, the last written entry will be lost. That's why I recommend using the ALMOST FULL flag instead of the FULL flag. EMPTY does not have this problem. It goes active on the same read clock edge that is reading the last piece of data out of the FIFO. EMPTY then goes inactive again after a data entry has been written into the FIFO and the internal signal hes been re-synchronized to the read clock, which takes a few read clock cycles. This asymmetric behavior assures that the EMPTY flag is appropriately extremely fast in stopping any further erroneous reads, but is more "relaxed" in allowing the reading to restart again. Note that this read latency only occurs after the FIFO had gone empty. If anybody has questions about the Virtex-4 FIFO, I am the right person to ask. I have designed FIFOs, on and off, for over 35 years... Peter Alfke, Xilinx ApplicationsArticle: 90586
Thanks Sylvain. I am not having much luck myself and am also a bit miffed!! What Linux Kernel are you running? Thanks, ChrisArticle: 90587
"Jerry" <nospam@nowhere.com> wrote in message news:xLC4f.226$0G6.46@fe06.lga... > Greetings, > I posted this in comp.cad.synthesis. That group doesn't have much traffic. > > We are looking into doing a rapidchip with LSI. I would like to hear from > anyone who has done > a rapidchip. I'm interested in all aspects of the process with emphasis on > hidden cost, "Oh you > wanted timing analyses done? Well that's another 5 grand". Also how many > iterations did you > have to go thru with them doing the detail layout? Did they met the device > delivery schedule? > It looks like thier toolset does a prelimanary place and route on the > customer's platform then > the database is handled over to LSI for detail place and route. How long did > LSI spend on > detail place and toute in order to get to tape out? I understand that the > time spent is dependent > on the quality of the RTL, clock frequency, margin in the design, IP > quality, and how many > clocks. Also what was the test scan coverage obtained? > > > I've done ASICs in the past with LSI and found them to be real stickers for > process which > is good. Also we have had a quote in the past with cost associated with the > distributor. Did > you have to pay engineering fees to the distributor? > > Also since we haven't done an ASIC in a few years here our synthesis license > has expired. I > am considering Amplify RapidChip physical synthesis from Synplicity. Anybody > have a > comment on that? > > Are these question more appropriate for John Cooley's DeepChip web site? I > did a search there > but came up pretty empty. > > Thanks in advance for any information you may share. > > Regards > Jerry Hi, The default toolchain for LSI Rapidchip is Synplify ASIC from Synplicity, If I'm correct. Perhaps, you can ask them for input. My experience with with Synplify Pro and Amplify was quite good. The only uncertainty would be the quality of the timing extraction and convergence between the tools (if separate). Time to prepare some figures (area, clocks, speed, RAM, ROM) and check with their sales representatives. Regards, Alvin.Article: 90588
Hi Brad, I re-read you earlier post and could not figure out if you want help with EDK/ISE in general or the driving the VGA port in particular. For now I will assume the latter and explain: XAPP717 has a XPS project under xapp717\hw\apu_idct\. Don't worry about the IDCT portion of it. To drive the VGA port you neeed the plb_tft_cntrl_ref_0 pcore and associated driver which is xapp717/sw/standalone/apu_idct/src/bootload_basicgraphics.* . If you look under bootload_basicgraphics.c, you'll lots of useful function like XTft_DrawLine etc. My 2 cents on how the plb_tft_cntrl_ref_0 works: A portion of the DDR memory is placed aside for the video memory. The powerPC writes to this area to draw on the VGA port. The pcore(plb_tft_cntrl_ref_0) is a master on the PLB bus and grabs the data out of the video memory and buffers it using a single BRAM primitive. It then drives the VGA port in a 640x480 config only. The DCR is used to set the start address of the video memory in the pcore (so it knows wher to grab it from), but you can remove the DCR and specify the start address as a parameter in the MHS file. Hope this helps. If not, tell me exactly what you want to know about. KunalArticle: 90589
Update: Ok, I tried to do this. I defined a simple mem file like this: @0000 2A 3B 4C 5D I saved this as example.mem. Now, I tried data2mem -bd example.mem -o v outputverilog.v I was expecting a verilog file at the output. However, nothing happens. There is no error, but no output file either. Any help would be appreciated. Thanks, Robert.Article: 90590
"Jim Granville" <no.spam@designtools.co.nz> wrote in message news:434ee49c$1@clear.net.nz... > kha59@student.canterbury.ac.nz wrote: > > Thanks Alvin, > > > > The problem is to assign one of 5 colours for each of the integers from > > 1 upwards such that if any two integers have the same colour the > > integer that they sum to must have a different colour: > > > > eg. > > If we have > > 1-green 2-blue 3-green > > > > then 4 cannot be green or blue as 1+3 = 4 and 2+2 = 4. > > I can follow <> green, but <> blue seems to extend your rule ? > > > > > A correct sequence of 160 digits for 5 colours is known. I wish to find > > a sequence of 162 digits. > > So that's a string of ~160 characters, where each character can be one > of 5 values ? > > > > > I'm doing an exhaustive search on a severely restricted subset of all > > the possible sequences. The sequence is built up one colour at a time > > until you get to the point where you know that somewhere down the track > > there will be no possible colour, then you go back one in the sequence > > and try a different colour etc. > > > > This is quite easy to split up each chip at a time should only increase > > the sequence by a few digits (due to memory constraints) and report > > each possible final sequence back to the coordinating chip which dishes > > each of these out to other chips when they request more work. Of course > > there needs to be a prioritisation of sequences such that the sequence > > queue doesn't get too big (ie. always dish out the longest sequences > > which will be exhaustively searched and therefore removed quickest). > > All of this stuff isn't too hard. > > > > To the points you made, > > 1) efficient communication. Each chip needs to get a sequence per unit > > of work which is no biggy, but it will need to report back each > > sequence it ends up at..... This could in fact be quite a few - maximum > > 5^(#of digits sequence was increased by) but usually a lot less. For > > each of these it needs to return (sequence length)/2 bytes. I think I > > will need to consider this point in some more detail... > > 2) fault tolerance. I wish to find a single correct sequence and > > believe (hope!) that there are many of these (expected running time is > > time to first sequence not completion time for exhaustive search which > > would in fact take 100s of years!!!), whilst missing one sequence due > > to a faulty device/communications would be very bad this wouldn't be > > disastrous. I'm not trying to say that no sequence of 162 digits > > exists. > > This reads a little like sorting primes. > The data set would certainly fit into a (very) small microcontroller > = you can even pack into nibbles, and consume just 80 bytes, but > the problem with many small uC will be ensuring there are no overlaps, > or holes, in their scan coverage. > > ie the task is simple enough, but multi-uC management is likely to > be a nightmare. > > Something like i2c for the backplane is also likely to be a serious > bottleneck. > > > > I don't know anything about FPGAs or how these would apply, do you > > happen to have some useful links? > > Look at Altera, Lattice, Xilinx - there are many demo/eval boards and > tool sets. > Also look at the Soft CPUs : Xilinx PicoBlaze, and Lattice Mico8 > > FPGAs can do hugely parallel tasks, and on a small data set like this, > you have no memory bandswidth issues. > > With a FPGA, you could do exclusion mapping - that is, do not store the > Colour@integer, but instead have an array of N x 5 booleans, which are > excluded colours. [ALL 5 => Whoops, go back! ] > An FPGA could scan for all ahead exclusions, very efficently indeed. > One of the small soft CPUs could manage the re-seed process. > > <paste> > > I've got a pure math problem implemented in C that will take about 3 > > years to solve using all 5pcs available to me (the algorithm is about > > as efficient as it will get without some major mathematical insights). > > The algorithm is always where the biggest speed gains can be made, > especially in efficently mapping the algorithm to the hardware it runs > on. > > In a FPGA you could set up 'algorithm races', where (eg) you code > 4 algorithms in ~1/4 of the chip each, and run it for a couple of days, > and compare their Attained String Lengths. > > If the present best is a langth of 160, don't just think about 162, look > to smash it ! :) > > I've added comp.arch.fpga, as this really sounds more like a FPGA+smart > algorithm, than a "sea of uC" problem. > > > -jg Hi, The blue rule seems ok: 2 + 2 == 4. I'd certainly favour FPGAs for this. The biggest issue would still be the memory bandwidth: each time you split some work over different processing nodes, you need to communicate the present N charactrs, while testing for an expansion could easily take less than O(N) time (depends on how the algorithm behaves), possibly leaving processing nodes starved for data and while others might be spening more time on communicating than on processing. My first guess is that a single dual-ported RAM per processing node should suffice. That allows many processing nodes on a modern FPGA. Maybe if I change the memory architecture that I have in mind, some communication overhead could be eliminated. Oops ... I'm trying to solve it! Can I? :-) Alvin.Article: 90591
THIS IS IN CONTINUATION TO THE THREAD I MADE A COUPLE OF DAYS AGO. I WANTED TO ISOLATE THIS FROM THE OTHER STUFF, HENCE THE NEW THREAD: Refer here for the older thread: http://groups.google.com/group/comp.arch.fpga/browse_thread/thread/ca8c05acec5703b3/a2502f9b088ecdea?lnk=raot&hl=en#a2502f9b088ecdea Hi, Here's what I need to do. 1) I will generate the data in a text file using Python scripts. 2) Will probably write another script or use Matlab to convert this to a .mem format which is readable by Xilinx. 3) Will use data2mem from command line to convert .mem file to either a .bit file or .v file. I will first try with verilog file, which I will then include into the project. The verilog file will contain the initialization for the RAM. Later on, I am planning to just use data2mem to generate .bit file, so that I can directly download it to the FPGA. (The different web-pages on Xilinx talk about .elf file, but as I don't have any code to write on the FPGA, but rather just some data, I don't know whether I should be concerned about this or not) Now, if I understand it correctly, these are the only steps required. Is it necessary to do something about the RAM in the hardware design? Like specifying where to store, the memory design etc? Update: Ok, I tried to do this. I defined a simple mem file like this: @0000 2A 3B 4C 5D I saved this as example.mem. Now, I tried data2mem -bd example.mem -o v outputverilog.v I was expecting a verilog file at the output. However, nothing happens. There is no error, but no output file either. Any help would be appreciated. Thanks, Robert.Article: 90592
Answer record #22179 is now on-line (http://www.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=22179) - Peter Peter Ryser wrote: > Please open a case with the Xilinx hotline if you encounter an > intermittent problem while booting the PowerPC after initial power-on in > Virtex-4 FX FPGAs. The hotline engineers will assist you to identify the > problem and once isolated provide you with an appropriate design parameter. > > - Peter >Article: 90593
Hi All,
The specific error here was resolved by including the altera_mf
library into my test bench VHDL code. I also needed to include the USE
altara_mf.altera_mf_components.all into the VHDL code.
Unfortunately when it does compile, there is another error that
appears which is bizarre. The Modelsim error is 3473 as follows:
# ** Warning: (vsim-3473) Component 'a_graycounter2' is not bound.
# Time: 0 ns Iteration: 0 Region:
/tb_sopc_memory_rw_vhdl/write_fifo_vosq0/vosq0_prestore_fifo_dcfifo_dsu_component
File: D:/My
Documents/University/Masters_Project/VHDL_Coding/Prestore_FIFO/vosq0_prestore_fifo.vhd
The error by Modelsim is described as follows:
# The specified component has not been explicitly bound and no default
# binding has been found for it. This means that your VHDL design does
# not include a component configuration for the specified component
that
# indicates which entity/architecture to use for that component. It
also
# means that no entity of the specified name containing ports and
generics
# matching those in the component declaration was found when searching
all
# visible libraries for a default binding. Simulation will continue,
but
# no VHDL code will be executed for the unbound component.
#
# To fix this problem, either put a component configuration in your
VHDL
# design that specifies which entity/architecture to use for this
component
# or compile an entity of the same name as the component and containing
# ports and generics matching those in the component declaration along
# with at least one architecture for the entity into a library that is
# visible at the time the component is being elaborated. You may need
# to add a library use clause before the entity containing the unbound
# component in order to make the library and component visible.
When I go and view the VHDL code that was generated by the Quartus
megawizard for the FIFO, it seems that the VHDL code for my FIFO
appears to have the instantiation of all the libraries including the
one that I described above, which dictates that the entity/architecture
code should be detectable by Modelsim during the compile process. I'm
confused to why this is not happening? Is there another library that
I missed?
Just so it's clear my VHDL testbench also includes the following:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE std.textio.ALL;
USE ieee.std_logic_unsigned.ALL;
USE ieee.std_logic_arith.ALL;
LIBRARY lpm;
USE lpm.lpm_components.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
Regards
Pino
Subroto Datta wrote:
> The lpm_widthu parameter need sto be calculated & set by MegaWizard based on
> the size
> of FIFO chosen by the user.
>
> > C:/altera/modeltech_ae/altera/vhdl/altera_mf.scfifo(behavior)
> > # ** Fatal: (vsim-3350) Generic 'lpm_widthu' has not been given a
> > value.
>
> The design should be modified through the scfifo MegaWizard and should not
> changed manually.
>
> Hope this helps,
> Subroto Datta
> Altera Corp.
>
> <pinod01@sympatico.ca> wrote in message
> news:1129005330.788003.36580@g47g2000cwa.googlegroups.com...
> > To all,
> >
> > I have been attempting to load a lpm component into a Modelsim
> > project and when I get my test bench compiled and I try to simulate, I
> > get the following error. Note that vosq0_prestore_fifo (my own name)
> > is an instantiated VHDL LPM component from Altera Quartus software
> > using their scfifo function. Below shows the log window. The fatal
> > error is shown below and is detailed because for some reaoson I don't
> > know where to declare a value for the LPM_WIDTHU variable? I had
> > thought that this was already defined? Your help would be appreciated.
> >
> > Cheers
> > Pino
> >
> > # Loading work.vosq0_prestore_fifo(rtl)
> > # Refreshing
> > C:/altera/modeltech_ae/altera/vhdl/altera_mf.altera_mf_components
> > # Loading
> > C:/altera/modeltech_ae/altera/vhdl/altera_mf.altera_mf_components
> > # Loading work.vosq0_prestore_fifo_dcfifo_dsu(rtl)
> > # Loading work.vosq0_prestore_fifo_a_gray2bin_fl6(rtl)
> > # Refreshing
> > C:/altera/modeltech_ae/altera/vhdl/altera_mf.a_graycounter(behavior)
> > # Loading
> > C:/altera/modeltech_ae/altera/vhdl/altera_mf.a_graycounter(behavior)
> > # Refreshing
> > C:/altera/modeltech_ae/altera/vhdl/altera_mf.altera_common_conversion(body)
> > # Loading
> > C:/altera/modeltech_ae/altera/vhdl/altera_mf.altera_common_conversion(body)
> > # Refreshing
> > C:/altera/modeltech_ae/altera/vhdl/altera_mf.altera_device_families(body)
> > # Loading
> > C:/altera/modeltech_ae/altera/vhdl/altera_mf.altera_device_families(body)
> > # Refreshing
> > C:/altera/modeltech_ae/altera/vhdl/altera_mf.altsyncram(translated)
> > # Loading
> > C:/altera/modeltech_ae/altera/vhdl/altera_mf.altsyncram(translated)
> > # Loading work.vosq0_prestore_fifo_alt_synch_pipe_lb5(rtl)
> > # Loading work.vosq0_prestore_fifo_dffpipe_lb5(rtl)
> > # Loading
> > C:/altera/modeltech_ae/altera/vhdl/220model.lpm_common_conversion(body)
> > # Loading
> > C:/altera/modeltech_ae/altera/vhdl/220model.lpm_counter(lpm_syn)
> > # Refreshing
> > C:/altera/modeltech_ae/altera/vhdl/altera_mf.scfifo(behavior)
> > # Loading C:/altera/modeltech_ae/altera/vhdl/altera_mf.scfifo(behavior)
> > # ** Fatal: (vsim-3350) Generic 'lpm_widthu' has not been given a
> > value.
> > # Time: 0 ns Iteration: 0 Instance:
> > /tb_sopc_memory_rw_vhdl/write_fifo_vosq0/vosq0_prestore_fifo_dcfifo_dsu_component/scfifo14
> > File:
> > QuartusIIVersion4.0(C:/Modeltech_6.0/win32/../altera/Vhdl/src/altera_mf/altera_mf.vhd)
> > # FATAL ERROR while loading design
> >
> >
Article: 90594pingboypulsar@hotmail.com wrote: > thanks for that info. > > So what is the best approach to learning how to do this? > > Is it possible to elaborate a bit more on this "..so 2Gsps@8bits > fans-out to 500Msps@32bits, where it can (just) feed into a FPGA..." It's outside your Sensor reference area, but I included it as a limiting case, as an example. You can get ADCs ($$) that have 2 G samples/second, and that is above FPGA abilties - but FPGAs have lots of pins, so the solution is to create a wider, slower datapath out of the ADCs. [the opposite of a SPI interface, if you like ] <paste> > I wish to be able to connect industrial sensor(s) to an adc, and > then acquire the value to the fpga for further processing. Maybe its > better to use an asic or something else for interfacing an adc. I > need to find out these things. Physical connection is simple. 'Further processing' sounds like some software, ie a SoftCPU. There are truckloads of examples, of ADC <-> uC connections, and the software needed to initialise the registers in the ADC, and then pump the data out. That software is portable to your FPGA CPU. You have chosen an ADC partnumber, and FPGA SoftCPU ? -jgArticle: 90595
Peter Alfke wrote: > Let me correct this: > The addressing depth of Virtex-4 FIFOs is 512, 1024, 2048, or 4096 > locations. The word "byte" is meaningful only for the 2048 x 9 > configuration. > The FULL flag goes active one write clock cycle after the FIFO has been > filled. That means, in a continuous write situation, the last written > entry will be lost. That's why I recommend using the ALMOST FULL flag > instead of the FULL flag. > EMPTY does not have this problem. It goes active on the same read clock > edge that is reading the last piece of data out of the FIFO. EMPTY > then goes inactive again after a data entry has been written into the > FIFO and the internal signal hes been re-synchronized to the read > clock, which takes a few read clock cycles. Interesting - so for sustained thru-put on these, you are best to avoid going empty, which probably means two operating modes : fastest, and clean-out-the-last-byte(s) I see some uarts have WDOGs in their fifos, that allow simpler streaming code, and they generate a time-content interrupt, as well as the normal threshold one. Timeout is normally some multiple CHAR times, so the end of message chars are dealt to without needing polling. -jgArticle: 90596
Jim Granville wrote: <Peter's stuff snipped> > Interesting - so for sustained thru-put on these, you are best to avoid > going empty, which probably means two operating modes : fastest, and > clean-out-the-last-byte(s) > I see some uarts have WDOGs in their fifos, that allow simpler streaming > code, and they generate a time-content interrupt, as well as the normal > threshold one. > Timeout is normally some multiple CHAR times, so the end of message > chars are dealt to without needing polling. > > -jg We upgraded a Zilog Z8530 serial port to a Z85230 serial port, because the Z85230 has deeper FIFOs. The 85230's recv port has an 8-byte FIFO vs the 8530's 3-byte FIFO. I had hoped that the CPU would be interrupted a lot less using the 85230. The 85230 can be set-up to interrupt when 1 char is recv'd or when there are 4 bytes in the recv FIFO (half full). This sounded really great and even worked quite well, until I discovered that when there _3_ bytes in the FIFO and the chip is set-up to interrupt when half-full, that the chip does not interrupt until another byte is received, even if that's minutes later. ARGH, WIPA! BTW what's a "WDOG"? -DaveArticle: 90597
Peter Alfke wrote: > Let me correct this: > The addressing depth of Virtex-4 FIFOs is 512, 1024, 2048, or 4096 > locations. The word "byte" is meaningful only for the 2048 x 9 > configuration. > The FULL flag goes active one write clock cycle after the FIFO has been > filled. That means, in a continuous write situation, the last written > entry will be lost. That's why I recommend using the ALMOST FULL flag > instead of the FULL flag. > EMPTY does not have this problem. It goes active on the same read clock > edge that is reading the last piece of data out of the FIFO. EMPTY > then goes inactive again after a data entry has been written into the > FIFO and the internal signal hes been re-synchronized to the read > clock, which takes a few read clock cycles. > This asymmetric behavior assures that the EMPTY flag is appropriately > extremely fast in stopping any further erroneous reads, but is more > "relaxed" in allowing the reading to restart again. Note that this read > latency only occurs after the FIFO had gone empty. > If anybody has questions about the Virtex-4 FIFO, I am the right person > to ask. I have designed FIFOs, on and off, for over 35 years... > Peter Alfke, Xilinx Applications So Peter, what do those of us with lowly Spartan-II FPGA's do if we want say, a 16x9 FIFO? -DaveArticle: 90598
Does anyone know of a good reference for timing concepts in synchronous FPGA designs. I know what false and multi-cycle paths are, but need some examples to understand how they occur in real designs.Article: 90599
Dave Pollum wrote: > Jim Granville wrote: > <Peter's stuff snipped> > >>Interesting - so for sustained thru-put on these, you are best to avoid >>going empty, which probably means two operating modes : fastest, and >>clean-out-the-last-byte(s) >>I see some uarts have WDOGs in their fifos, that allow simpler streaming >>code, and they generate a time-content interrupt, as well as the normal >>threshold one. >> Timeout is normally some multiple CHAR times, so the end of message >>chars are dealt to without needing polling. >> >>-jg > > We upgraded a Zilog Z8530 serial port to a Z85230 serial port, because > the Z85230 has deeper FIFOs. The 85230's recv port has an 8-byte FIFO > vs the 8530's 3-byte FIFO. I had hoped that the CPU would be > interrupted a lot less using the 85230. The 85230 can be set-up to > interrupt when 1 char is recv'd or when there are 4 bytes in the recv > FIFO (half full). This sounded really great and even worked quite > well, until I discovered that when there _3_ bytes in the FIFO and the > chip is set-up to interrupt when half-full, that the chip does not > interrupt until another byte is received, even if that's minutes later. > ARGH, WIPA! > > BTW what's a "WDOG"? Sorry, cryptic mode... WDOG = WatchDog = monostable timer, that retriggers on every incomming CHAR, and times-out after some user defined CHAR pauses. Purpose is to catch exactly the PITA you describe :) -jg
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