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Messages from 91025

Article: 91025
Subject: Re: crc on only data or including the address
From: "chris_ivan" <chris.ivan@gmail.com>
Date: 27 Oct 2005 08:35:22 -0700
Links: << >>  << T >>  << A >>
Hi, ashwin.

>2) Is CRC implemented on only data or on whole frame?

>3) Can anyone guide me on how  crc  is computed?
as far as I know, CRC is applied from destination field to data field.
exclude the opening flag, preamble, etc. but include the addresses.

>4) If CRC is wrong, will the PHY still transmit the data onto the PC.
If I'm not mistaken, CRC is calculated by dividing the whole number by
certain polynomial, which is different for each kind of CRC (there are
CRC-32, CRC-16, etc). As you have 4 bytes FCS field, I guess it use
CRC-32, and the polynomial is:

g(x)=x32+x26+x23+x22+x16+x12+x11+x10+x8+x7+x5+x4+x2+x1+1.

the remainder of the division is considered as CRC. the checksum has to
be unique for each data.

please refer to Ross Williams' article for better explanation.. or the
book of Stalling (Data communication).. or just hit the google! you'll
find plenty of them.

if CRC is false, the frame is assumed to be corrupted. thus the sender
have to send it again.  error control, that's what CRC's for.


-ivan-


Article: 91026
Subject: Coregen Memory Initialization issue
From: "Robert" <robertsolanki@gmail.com>
Date: 27 Oct 2005 08:38:05 -0700
Links: << >>  << T >>  << A >>
Hi,
I am using Coregen (update 3) from within ISE (7.1 update 4). I added a
new source from IP, and defined a RAM. This opens the Coregen window,
where I can customizet the RAM. I defined the width and depth and added
a .coe file for the initial values.

I am sure the format of .coe if perfect, since I can see the
coefficients using the button "See coefficients".

However, when I use this RAM in my design (.xco), and try to read the
contents, it doesn't seem like they're actually present. At first, I
kept reading don't cares and now, somehow, it shows zero initial
values.

I use the ISE simulator and I checked the signals down to the memory.
Its the memory output which is 0, whereas I was expecting the initial
values.

Is the initial value information included only during synthesis or is
it used during simulation as well??

Thanks in advance,

Robert.


Article: 91027
Subject: Re: Single Event Upset
From: Austin Lesea <austin@xilinx.com>
Date: Thu, 27 Oct 2005 08:39:23 -0700
Links: << >>  << T >>  << A >>
Nebojsa,

Configuration memory:

Virtex II
40.8 FIT/Mb
Spartan 3
39.5 FIT/Mb

XC2C, XPLA3 CPLDs are tested by our areospace/defense business unit, and 
you would have to contact them.  I do not have their data.  They do not 
use FIT rates, they use cross section.  The FIT rate is so low for these 
devices, when combined with the number of memory cells, the per chip 
soft fail rate is almost none.  It only is of concern in high altitude 
aircraft, or space applications where the neutron flux is as much as 200 
times larger.

1 FIT is defined as one failure per one billion hours.  Multiply the 
FIT/Mb by the Mb of memory in the device to get the soft fail rate for 
the device itself.

Commercial SRAMs are somewhere from 1200 FIT Mb to 6,000 FIT/Mb at the 
90 nm technology node.

There are some newer devices that are claiming better (see Cypress, for 
example).

An ASIC SRAM block from a standard library is 5,000 FIT/Mb from a well 
know foundry.

As for "should I worry", please read:

http://www.xilinx.com/xlnx/xweb/xil_tx_display.jsp?sGlobalNavPick=&sSecondaryNavPick=&category=&iLanguageID=1&multPartNum=1&sTechX_ID=al_soft_vs_hard

or

http://tinyurl.com/9y72u

For a 3S50, as an example, take 39.5 * .37 Mb = 14.6 FIT, or 7,818 years 
mean time between soft failures.

There are ways to mitigate the soft errors, and reduce the FIT rate to 
nearly 0 by design.  Contact your Xilinx FAE for more information.

Austin

PS:  for those sharp eyed readers out there, you may notice that the 
most recent FIT/Mb numbers are slightly higher than ones you may have 
seen before.  Recent work with the standard committee on JEDEC89 (v.4) 
has led to a number of changes in estimating neutron flux, which we have 
endorsed by XIlinx, as it makes our data that we have been taking since 
August 5, 2002, match more closely to all accepted theories and practices.



Nebojsa wrote:

> I read about SEU characteristics of Xilinx FPGA. I'm interested in
> comparation of  MTBF data between Spartan3, Virtex-II and especially
> XC2C and XPLA3 PLDs and
> commercial sRAM of small capacity (max 512kBy). Do you know something
> about
> this issue?
> 
> If I didn't worry about SEU in my recent embedded designs with XPLA3,
> should I worry now when I want to use Spartan3?
> 
> 
> Regards,
> Nebojsa
> 

Article: 91028
Subject: Re: Coregen Memory Initialization issue
From: "Stephen Craven" <scraven@vt.edu>
Date: 27 Oct 2005 08:44:35 -0700
Links: << >>  << T >>  << A >>
Robert,

I have had a similar issue with CoreGen in the past.  You can check the
*.edn file to see if it actually initialized.  If all of your property
INIT strings are zero, it didn't.

The solution for me was to directly edit the *.xco file.  CoreGen was
setting the load_init_file attribute to false and may have been listing
the wrong init file as well.  You can directly edit this file and then
rerun CoreGen in batch mode.

coregen -b file.xco

Hope this helps,
Stephen


Article: 91029
Subject: Re: Optimizing a State Machine
From: "Newman" <newman5382@yahoo.com>
Date: 27 Oct 2005 08:46:12 -0700
Links: << >>  << T >>  << A >>

Mike Treseler wrote:
> backhus wrote:
>
> >   when thisstate => if something then
> >                        someoutput<= someoutput + 1;
> >                     end if;
> >
> > Synthesis tools often create an adder for this assignment in each state
> > it is used, even if you add to the same signal.
>
> I have seen no evidence of this using either Quartus or Mentor
> Synthesis. A clock enable is properly inferred.
>
>          -- Mike Treseler

I've had this happen to me using Altera's MaxPlusII Verilog (I remember
cause I got yelled at).  This was a while back, and the Quartus version
may have improved since then.  I think that a separate counter with an
explicit counter enable makes more intuitive sense to me, with the
possibility of better results across different synthesys tools. Just my
two sense:)

-Newman


Article: 91030
Subject: Re: Coregen Memory Initialization issue
From: "Robert" <robertsolanki@gmail.com>
Date: 27 Oct 2005 08:59:38 -0700
Links: << >>  << T >>  << A >>
Thanks Stephen.

I checked the .xco file and it looks like the coe file is linked
properly.

---------------------.xco file ----------------------
# BEGIN Project Options
SET flowvendor = Foundation_iSE
SET vhdlsim = True
SET verilogsim = True
SET workingdirectory =
c:\robert_project\other_codes\memory_read_from_ram\tmp
SET speedgrade = -4
SET simulationfiles = Behavioral
SET asysymbol = True
SET addpads = False
SET device = xc3s400
SET implementationfiletype = Edif
SET busformat = BusFormatAngleBracketNotRipped
SET foundationsym = False
SET package = pq208
SET createndf = False
SET designentry = VHDL
SET devicefamily = spartan3
SET formalverification = False
SET removerpms = False
# END Project Options
# BEGIN Select
SELECT Single_Port_Block_Memory family Xilinx,_Inc. 6.2
# END Select
# BEGIN Parameters
CSET handshaking_pins=false
CSET init_value=0
CSET
coefficient_file=C:\Robert_Project\Other_Codes\memory_read_from_ram\initialize.coe
CSET select_primitive=16kx1
CSET initialization_pin_polarity=Active_High
CSET global_init_value=0
CSET depth=16
CSET write_enable_polarity=Active_High
CSET port_configuration=Read_And_Write
CSET enable_pin_polarity=Active_High
CSET component_name=my_memory
CSET active_clock_edge=Rising_Edge_Triggered
CSET disable_warning_messages=true
CSET additional_output_pipe_stages=0
CSET limit_data_pitch=18
CSET primitive_selection=Optimize_For_Area
CSET enable_pin=true
CSET init_pin=false
CSET write_mode=Read_After_Write
CSET has_limit_data_pitch=false
CSET load_init_file=true
CSET width=30
CSET register_inputs=false
# END Parameters
GENERATE

--------------------------------------

So I am not sure what's wrong. Is there anything else that need to be
checked?

Robert.


Article: 91031
Subject: Re: ASIC HDL coding styles
From: "johnp" <johnp3+nospam@probo.com>
Date: 27 Oct 2005 09:01:13 -0700
Links: << >>  << T >>  << A >>
Vladimir -

The coding style probably makes it hard for the synthesizer to perform
reasonable optimization of the logic.  For example, it may not be able
to realize that you're creating a counter.  A cleaner coding style
would
make it more readable for humans as well as for synthesis tools.  For
example:
 // psceq0 :: Prescale Counter Equal to Zero
assign psceq0 = ( psc == 5'h0 );


always @ (posedge wclk or posedge rst)
    begin
    if ( rst )
        psc[4:0] <= #TP 5'h1;
    else if ( psceq0 )
        case ( p_clk )
        3'h7    : psc[4:0] <= #TP 5'hd;
        3'h6    : psc[4:0] <= #TP 5'h9;
        3'h5    : psc[4:0] <= #TP 5'h6;
        default : psc[4:0] <= #TP 5'bx;
        endcase
    else
      psc[4:0] <= #TP psc[4:0] - 1'b1;
end

This style screams 'I'm a counter' to everyone and makes clear the
values that are being reloaded.

I hope this helps!

John Providenza


Article: 91032
Subject: Re: Coregen Memory Initialization issue
From: "Robert" <robertsolanki@gmail.com>
Date: 27 Oct 2005 09:09:30 -0700
Links: << >>  << T >>  << A >>
I also checked the .edn file and looks like the string is initialized.
It does show my initial data in there.


Article: 91033
Subject: Re: ASIC HDL coding styles
From: "Robert" <robertsolanki@gmail.com>
Date: 27 Oct 2005 09:11:53 -0700
Links: << >>  << T >>  << A >>
I was always told not to use complicated C-style coding techniques.
Simpler styles generally results into better designs. Atleast, this is
what my instructor used to say. And he's one of the best in this field!

- Robert.


Article: 91034
Subject: re:Optimizing a State Machine
From: geokirilov@yahoo-dot-com.no-spam.invalid (gkirilov)
Date: Thu, 27 Oct 2005 11:16:24 -0500
Links: << >>  << T >>  << A >>
- As for the Block RAM - the SM can not fit in it as the device I am
using does not have enough of it:
synthesis report from XST: (not enough BRAM in this device).
But even then the SM is not fast enough.

- I have only 2 inferred Adders/Subtractors - I will see how i can
change them.

- Another thing -i have the following concurrent statement
sig1 <= '1' WHEN a=b else '0';
sig2 <= '1' WHEN c=d else '0';
sig1/2 are input of the SM. a,b,c,d are 13 bit values. Is this a
problem for 100Mhz (my target freq.).

- I thing that the high number of IF-ELSIF-ELSIF...-ELSE within a
single WHEN xxx => 
can be the reason.


Article: 91035
Subject: Re: Optimizing a State Machine
From: "Peter Alfke" <peter@xilinx.com>
Date: 27 Oct 2005 09:44:12 -0700
Links: << >>  << T >>  << A >>
Can you send me an e-mail, so we can discuss this privately?
Peter Alfke  (peter@xilinx.com )


Article: 91036
Subject: Re: Microblaze & Memory DMA operation
From: "Terry Fowler" <terry.fowler@sbcglobal.net>
Date: Thu, 27 Oct 2005 10:33:29 -0700
Links: << >>  << T >>  << A >>
Macro problem resolved thanks to Deepesh Shakya. It seems that the assembler syntax changed slightly in going from version 6 to 7 and using the version 7 mb_interface.h fixed my problem.

Article: 91037
Subject: another FPGA/asic vendor dead :(
From: "Antti Lukats" <antti@openchip.org>
Date: Thu, 27 Oct 2005 20:25:19 +0200
Links: << >>  << T >>  << A >>
NEWS: LeopardLogic has ceased operations. It wasnt directly FPGA but rather 
asic with part of it as configurable fpga fabric.

Cypress is also out of PLD business silently, well that was to be expected.

humm, who is next?

antti



Article: 91038
Subject: locking hdl to a particular fpga
From: "Matthew Plante" <maplante@iol.unh.edu>
Date: Thu, 27 Oct 2005 14:27:17 -0400
Links: << >>  << T >>  << A >>
Does anyone know if there is a way to lock code to work only on a particular 
fpga?  I know the device has a jtag identifier, which identifies the fpga 
family, but I don't know if part of that idcode reflects a unique serial 
number associated to only 1 fpga.  I'm looking to write some code that 
checks if the id of that fpga is valid, otherwise the code won't run.

Thanks,

-- Matt 



Article: 91039
Subject: Re: locking hdl to a particular fpga
From: "Antti Lukats" <antti@openchip.org>
Date: Thu, 27 Oct 2005 20:53:11 +0200
Links: << >>  << T >>  << A >>
"Matthew Plante" <maplante@iol.unh.edu> schrieb im Newsbeitrag 
news:djr665$as2$1@tabloid.unh.edu...
> Does anyone know if there is a way to lock code to work only on a 
> particular fpga?  I know the device has a jtag identifier, which 
> identifies the fpga family, but I don't know if part of that idcode 
> reflects a unique serial number associated to only 1 fpga.  I'm looking to 
> write some code that checks if the id of that fpga is valid, otherwise the 
> code won't run.
>
> Thanks,
>
> -- Matt

only doable with flash FPGA or external nonvolatile memory on PCB is 
required.

RAM based FPGA have no serial number.

the jtagid is vendor and part type identifier only

antti



Article: 91040
Subject: Re: locking hdl to a particular fpga
From: Phil Hays <Spampostmaster@comcast.net>
Date: Thu, 27 Oct 2005 12:04:14 -0700
Links: << >>  << T >>  << A >>
"Matthew Plante" wrote:

>Does anyone know if there is a way to lock code to work only on a particular 
>fpga?

Encrypted bit stream.  Key is put into battery backed up register in
FPGA, and unless the encryption and decryption keys match, the FPGA
doesn't configure.

See:

http://www.xilinx.com/bvdocs/userguides/ug071.pdf


-- 
Phil Hays to reply solve: phil_hays at not(coldmail) dot com  
 If not cold then hot


Article: 91041
Subject: Re: another FPGA/asic vendor dead :(
From: Jim Granville <no.spam@designtools.co.nz>
Date: Fri, 28 Oct 2005 08:05:24 +1300
Links: << >>  << T >>  << A >>
Antti Lukats wrote:
> NEWS: LeopardLogic has ceased operations. It wasnt directly FPGA but rather 
> asic with part of it as configurable fpga fabric.
> 
> Cypress is also out of PLD business silently, well that was to be expected.
> 
> humm, who is next?

  Yes, but ST has entered the fray, with new partial FPGA offerings, 
that seem well thought out.
  I did smile when I read one press release, that said they have two 
versions of their eval boards, one that allowed an external FPGA to
develop, and then use their internal one.
  A good idea, and usefull to the developer, but perhaps more indicative
of a Tool Flow that's just a little green, perhaps ?
  Those issues improve over time.

-jg


Article: 91042
Subject: Re: Cost to go from FPGA to ASIC
From: "Paul Marciano" <pm940@yahoo.com>
Date: 27 Oct 2005 12:24:49 -0700
Links: << >>  << T >>  << A >>

Austin Lesea wrote:
> But "partially faulty" yet 99.999% tested (much better than an ASIC is
> able to be tested) means that any faults which are not being used, don't
> matter.

I've read criticisms of this "faulty, but tested" thing a number of
times in this newsgroup and it surprises me that smart people don't get
it.

You provide a final, golden bitstream and Xilinx provide tested,
cheaper devices.  The parts of the FPGA that are not could be coated in
jam for all it matters.  The parts that are used are tested.

I'm just a software guy and I get it.  How hard can it be?

;-)


Article: 91043
Subject: Re: System ACE equivalent for CPLDs
From: Neil Glenn Jacobson <n.e.i.l.j.a.c.o.b.s.o.n@x.i.l.i.n.x.c.o.m>
Date: Thu, 27 Oct 2005 12:46:28 -0700
Links: << >>  << T >>  << A >>
OK. Fair enough.  And you could use SystemACE to do all that except for 
programming the CPLD.  Why use a CPLD and not just a small, cheap FPGA 
like a Spartan3 or a variant?


Benjamin Todd wrote:
>>As also indicated, an interesting question to ask is why do you want to 
>>configure your CPLD every time you power up?  Is your design pattern 
>>changing all the time?  Is this some sort of demo board?
> 
> 
> Not exactly, maybe i'm being a little ambitious...
> 
> I'm just doing some research into making a test apparatus for some designs 
> using various CPLDs.  The idea was to make a discrete piece of hardware that 
> the UUT would be plugged into, and then a little report saying whether it 
> passes or fails - this needs to be rugged, and industrialised.
> 
> Using boundary scan I can only verify about half the board, and the less 
> critical half at that, so i'm wondering whether I could use one bit file to 
> run a sequence of test vectors in conjunction with the external tester, and 
> then once all the interconnects are established as correct, load the proper 
> bit file.
> 
> I guess you're wondering why I don't just go for a PC running impact... well 
> i'm trying to avoid having to maintain a PC with the manufacturer, including 
> the OS, the test software etc etc.
> 
> Ben
> 
> 
> 
> 
> 

Article: 91044
Subject: Re: another FPGA/asic vendor dead :(
From: "Antti Lukats" <antti@openchip.org>
Date: Thu, 27 Oct 2005 22:06:47 +0200
Links: << >>  << T >>  << A >>

"Jim Granville" <no.spam@designtools.co.nz> schrieb im Newsbeitrag 
news:436124b3$1@clear.net.nz...
> Antti Lukats wrote:
>> NEWS: LeopardLogic has ceased operations. It wasnt directly FPGA but 
>> rather asic with part of it as configurable fpga fabric.
>>
>> Cypress is also out of PLD business silently, well that was to be 
>> expected.
>>
>> humm, who is next?
>
>  Yes, but ST has entered the fray, with new partial FPGA offerings, that 
> seem well thought out.
>  I did smile when I read one press release, that said they have two 
> versions of their eval boards, one that allowed an external FPGA to
> develop, and then use their internal one.
>  A good idea, and usefull to the developer, but perhaps more indicative
> of a Tool Flow that's just a little green, perhaps ?
>  Those issues improve over time.
>
> -jg
>
hum, where did you find this?
i am also looking at STW22000 news all the time, but its seems kinda 
vaporware or at least not obtainable ?

antti 



Article: 91045
Subject: Re: Cost to go from FPGA to ASIC
From: Austin Lesea <austin@xilinx.com>
Date: Thu, 27 Oct 2005 13:07:55 -0700
Links: << >>  << T >>  << A >>
Paul,

In all fairness to the people who bring this up (over and over again), 
is the "fear" that a defect will "develop" or "migrate" or somehow cause 
a further problem.

That is what process qualification testing is all about.  You take the 
parts that you claim are good for 10, 15, or 20 years, and you test them 
  under commonly accepted conditions to see if you are right.

Every IC manufacturer out there does this.

If we pass XXXX? temp cycles, at YYYY? higher Vcc's, then there are 
formuals which predict what the worst case failure rate will be.  If you 
have even one failure, the process is reset, corrective actions are 
made, and you start the test again on the new corrected process parts.

This is not new at all, but something we have all done for years.

Yet, the fear, although irrational (as it applies to every device made 
in silicon, ever), seems to resonate with people who really don't know 
"what goes on under the hood."

For some, it is like making sausage, you really don't want to know how 
it is done.

For others, once you know how it is done, you know the right questions 
to ask:  "Did your EasyPath program go through a standard qual process?"

Answer: "Yes, it did."

Austin


Article: 91046
Subject: Re: another FPGA/asic vendor dead :(
From: hmurray@suespammers.org (Hal Murray)
Date: Thu, 27 Oct 2005 15:26:40 -0500
Links: << >>  << T >>  << A >>
>Cypress is also out of PLD business silently, well that was to be expected.

Who is in the PLD business these days?  Anybody still making 22V10s as
compared to CPLDs?

How about smaller parts?  Are things like 20R8s pad limited now?

-- 
The suespammers.org mail server is located in California.  So are all my
other mailboxes.  Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's.  I hate spam.


Article: 91047
Subject: Re: another FPGA/asic vendor dead :(
From: Jim Granville <no.spam@designtools.co.nz>
Date: Fri, 28 Oct 2005 09:34:58 +1300
Links: << >>  << T >>  << A >>
Hal Murray wrote:
>>Cypress is also out of PLD business silently, well that was to be expected.
> 
> 
> Who is in the PLD business these days?  Anybody still making 22V10s as
> compared to CPLDs?

Yes, Atmel and ICT ( now Anachip ), and also Lattice and in phase-out 
Cypress. Lattice do an ISP version of the venerable 22V10.
We still use 16V8s, which are actually the lowest cost PLDs
( in spite of the marketdroid claims from Altera...)

> 
> How about smaller parts?  Are things like 20R8s pad limited now?

Nope, they have not changed the die design on the smaller parts in
a long time.

To try and cover a little of the SPLD area, Xilinx did add MLF packages
to the coolrunner, [ but that is dual-voltage, and low Vcc only, so
there are some areas it cannot be applied to].

These pacakges also do not show yet on the Xilinx store....
-jg


Article: 91048
Subject: Re: another FPGA/asic vendor dead :(
From: Jim Granville <no.spam@designtools.co.nz>
Date: Fri, 28 Oct 2005 09:39:09 +1300
Links: << >>  << T >>  << A >>
Antti Lukats wrote:

> "Jim Granville" <no.spam@designtools.co.nz> schrieb im Newsbeitrag 
> news:436124b3$1@clear.net.nz...
> 
>>Antti Lukats wrote:
>>
>>>NEWS: LeopardLogic has ceased operations. It wasnt directly FPGA but 
>>>rather asic with part of it as configurable fpga fabric.
>>>
>>>Cypress is also out of PLD business silently, well that was to be 
>>>expected.
>>>
>>>humm, who is next?
>>
>> Yes, but ST has entered the fray, with new partial FPGA offerings, that 
>>seem well thought out.
>> I did smile when I read one press release, that said they have two 
>>versions of their eval boards, one that allowed an external FPGA to
>>develop, and then use their internal one.
>> A good idea, and usefull to the developer, but perhaps more indicative
>>of a Tool Flow that's just a little green, perhaps ?
>> Those issues improve over time.
>>
>>-jg
>>
> 
> hum, where did you find this?
> i am also looking at STW22000 news all the time, but its seems kinda 
> vaporware or at least not obtainable ?
> 
> antti 

Antti,
  Here is the link
http://www.st.com/stonline/press/news/year2005/p1711p.htm

ST seem to have two branches of ARM+FPGA, this one they call SPEAr,
and they claim samples now, Eval PCBs in Dec....
Price of $12/Volume, 200K FPGA, ADC, 3 x HS-USB(!), Ethernet,
SDRAM and I think SPI-SerialFlash boot ?

-jg



Article: 91049
Subject: Re: another FPGA/asic vendor dead :(
From: "Antti Lukats" <antti@openchip.org>
Date: Thu, 27 Oct 2005 22:48:12 +0200
Links: << >>  << T >>  << A >>
"Jim Granville" <no.spam@designtools.co.nz> schrieb im Newsbeitrag 
news:43613aad@clear.net.nz...
> Antti Lukats wrote:
>
>> "Jim Granville" <no.spam@designtools.co.nz> schrieb im Newsbeitrag 
>> news:436124b3$1@clear.net.nz...
>>
>>>Antti Lukats wrote:
>>>
>>>>NEWS: LeopardLogic has ceased operations. It wasnt directly FPGA but 
>>>>rather asic with part of it as configurable fpga fabric.
>>>>
>>>>Cypress is also out of PLD business silently, well that was to be 
>>>>expected.
>>>>
>>>>humm, who is next?
>>>
>>> Yes, but ST has entered the fray, with new partial FPGA offerings, that 
>>> seem well thought out.
>>> I did smile when I read one press release, that said they have two 
>>> versions of their eval boards, one that allowed an external FPGA to
>>>develop, and then use their internal one.
>>> A good idea, and usefull to the developer, but perhaps more indicative
>>>of a Tool Flow that's just a little green, perhaps ?
>>> Those issues improve over time.
>>>
>>>-jg
>>>
>>
>> hum, where did you find this?
>> i am also looking at STW22000 news all the time, but its seems kinda 
>> vaporware or at least not obtainable ?
>>
>> antti
>
> Antti,
>  Here is the link
> http://www.st.com/stonline/press/news/year2005/p1711p.htm
>
> ST seem to have two branches of ARM+FPGA, this one they call SPEAr,
> and they claim samples now, Eval PCBs in Dec....
> Price of $12/Volume, 200K FPGA, ADC, 3 x HS-USB(!), Ethernet,
> SDRAM and I think SPI-SerialFlash boot ?
>
> -jg
>
read carefully - the SPEAr is customized eAsic.
the fabric is e-beam programmed.

antti








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