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I have been looking at C like development tools and have seen a number of products mature. I tried to get in touch with Celoxia but never got any furthure than the UK representative saying he past my contact information on to the sales representative at the US office. Have you considered Impluse CoDeveloper? Getting a 30 day trial license was very painless. The demo looks like it is the same as if you bought the full version just limited to 30 days. It seems to be very able but a work in progress. Since I have downloaded the demo there has been a couple of updates but I might have caught them in the middle of a release process. The tutorials seem to illustrate features of their environment but the discussion could be more insightful. Their is also a book entitled "Practical Fpga Programming In C" by David Pellerin. I've ordered a copy of the book and I'm hoping that it will help me understand how to take advantage of their libraries with larger designs. On the small it seems like the VHDL code generated is very readable and easy to understand. I was wondering what kind of experiences other designers have had with Impulse's CoDeveloper? DerekArticle: 91151
Marco wrote: > Hallo, > How may I realize an integrator into a FPGA? > > Many Thanks > Marco > > It's written for C programmers, but http://www.wescottdesign.com/articles/pidwophd.html has an integrator implementation in it. For an "integrator" you just add the input to an accumulator once each sample of your DSP algorithm. Note that it doesn't really integrate; the closest you can come in sampled time is to sum the samples. Note also that you must establish a sampling time for your digital signal processing -- if you're sampling some external signal with an ADC and sampling it out with a DAC at the same speed you'll probably want to run the internal algorithm at that speed as well, just watch your integrator depths. -- Tim Wescott Wescott Design Services http://www.wescottdesign.comArticle: 91152
.. When you have to pay a bill by a certain day, or when you have to turn .. in a paper in school, it always means "before the end of the specified .. period". So "Monday" means, before 23:59:59 on Monday.... :-) I'm sorry. Somebody had to do it.Article: 91153
New Zealand is ahead of the rest of the world, as usual... PeterArticle: 91154
My intent was not to offend but merely to inform. You indicated that you had a solution for the CoolRunner devices but he stated that he had used a 9500 device. Since the programming operation of these devices are radically different and you made no indication of having a more general purpose solution I thought I would raise the issue. I am sorry if you found that insulting in any way. Please accept my apologies. dp wrote: >>What you have the CoolRunner will not work for the xc9500 family because >>the configuration algorithms are radically different. > > > Having written the tools from scratch starting with > the logic compiler and ending with the JTAG > access hardware & software, thus my design chain being 100% > self supplied - I would have thought I knew that. > I wonder based on what experience you thought > I did not know. > I offered the guy my help simply because I do have > knowledge way above average on the subject and I might be of > some help at some stage - he would probably know if and > when. > > Dimiter > > ------------------------------------------------------ > Dimiter Popoff Transgalactic Instruments > > http://www.tgi-sci.com > ------------------------------------------------------ >Article: 91155
I always use this(fifo_data <= X"AA4F") kind of HEX representation(assignment) for std_logic_vector and it works. The 16#AA4F# is for variables I think.Article: 91156
DerekSimmons@FrontierNet.net wrote:
> Have you considered Impluse CoDeveloper? Getting a 30 day trial license
> was very painless.
I don't know of a CAE tool that doesn't
provide a full-up 30 day trial.
> It seems to be very able but
> a work in progress.
Thanks for the tip.
> On the small it seems like the VHDL code generated is very
> readable and easy to understand.
Most readers of comp.lang.vhdl can already
write such code without a middle man.
> I was wondering what kind of experiences other designers have had with
> Impulse's CoDeveloper?
Why not try it out on a real design
and tell us how it goes.
-- Mike Treseler
Article: 91157These functions are accomplished by a "trick". The hardware can only perform mathematical operation, with carry. But by grounding every odd input, and ignoring every odd output, the carry does not propagate. Essentially, this divides the adder/subtractor into "watertight one-bit compartments". Peter Alfke, Xilinx ApplicationsArticle: 91158
"Marco" <marcotoschi@nospam.it> wrote in message news:dk5abq$7la$1@nnrp.ngi.it... > Hallo, > How may I realize an integrator into a FPGA? > > Many Thanks > Marco Just know that you can't realize an ANALOG integrator into an FPGA which is what you would need for your Sigma Delta converter pursuit.Article: 91159
"Hans" <hans64@ht-lab.com> wrote in message news:Ovo9f.19467$Ce5.14286@newsfe1-gui.ntli.net... > Hi All, > > I am trying to P&R an XC2V8000 with a large number of MCP constraints on a > 2GB (+2GB swap, /3GB switch in boot.ini) Win2K machine and I am running out > of memory. If I take the constraints out then ISE only consumes 1GB. > > # ERROR:Portability:3 - This Xilinx application has run out of memory or has > # encountered a memory conflict. Current memory usage is 1969212 kb. > Memory > # problems may require a simple increase in available system memory, or > # possibly a fix to the software or a special workaround. To > troubleshoot or > # remedy the problem, first: Try increasing your system's RAM. > > Before I buy some extra memory, are there any switches or tips to reduce the > memory requirements? I tried removing some of the MCP's to see if I could > still meet timing but unfortunately I need them all. > > I also tried installing ISE on my Gentoo64 machine but after some hacking of > libraries, portmap etc I got a "6031 Segmentation fault" during installation > :-( > > Thanks, > Hans. > www.ht-lab.com > Hi, Unless you use 64-bit software, the O/S won't be able to give you more RAM. Having said this, Synopsys distributes a Linux kernel patch to increase the user space to 3.2 GB. Also, ISE might be checking for real RAM (you don't want to P&R on your HD), so adding memory might help (a bit). The "safest" option would be to partition your design in physically separate parts so you can merge the partial results. The ISE supports this, but I haven't used it. Main issues to expect are: - hard to split design - one part uses more BRAMs, MULTs, ... than the other and would cause an overlap (last time I've checked, this could not be solved). Regards, Alvin.Article: 91160
Marco wrote: > sorry for my terrible scheme. > > Please watch the picture at the link: > > http://www.maxim-ic.com/images/appnotes/1870/A237Fig04.gif > > That should be more clear. > > I thought that I could replace the 1-bit dac using a LVCMOS25 out pin > (without dac because it is only 1 bit) and connecting it to the negative > input of LVDS25. > > What do you think about it? > > Is it possible? You need to do some simple maths: 16 bits on 3.3V, is a LSB of ~50uV, so if you want to achieve 16 bit ADC performance, your system must be able to resolve to <50uV, and generate voltage to better than 50uV, in stability/noise. Now, look in the data sheets, for any units uV ? FPGAs are NOT designed as voltage-domain devices, they are time-domain devices. You need these voltage-domain components, added to a FPGA ** Precision Voltage reference ** Analog Switch - GND-VREF toggling ** Precision resistors - Min of 2 ** Integrator = Performance OpAmp + Correct Capacitor ** Stable Clock source ++ Comparitor The last item, you just MIGHT be able to use LVDS, if you are carefull with common mode range, and integrator amplitude. Build it first with an external one, then try and remove when it is ALL working to > 16 bits. In operation, think of a SD-ADC as simply a charge balancing system, that makes a heap of Go-Up / Go-Down decisions ( one every clock) and then totals (average) those over a great many clocks. It relies on the integrator being good enough, that it really does charge balance. -jgArticle: 91161
Peter Alfke wrote: > New Zealand is ahead of the rest of the world, as usual... > Peter > So when will the Spartan 3e actually be available?????? I can't even get my hands on a few chips. This is somewhat upsetting because the same thing happening with the Spartan 3. Even though I love the Xilinx stuff, it seems really damn hard to get the parts! -EliArticle: 91162
Antti Lukats wrote: > "Jon Beniston" <jon@beniston.com> schrieb im Newsbeitrag > news:1130753284.143142.3010@g44g2000cwa.googlegroups.com... > >>Hi, >> >>Does anyone have any SystemACE parts for sale (upto 15 pieces) or know >>any distributor who has some in stock? >> >>Cheers, >>Jon >> > > > I have never found any disti selling them in small quantity. > > its on my DONOTUSE list anyway. > And will be obsoleted soon. (Antti's guess) > There are no plans to discontinue the System ACE CF (XCCACE-TQ144) device. In fact we will be introducing the lead free version early next year to meet ROHS design needs. There are no Xilinx imposed min order quantities (MOQs) on this device and you are able to order these through any of our distributors. Lead times should be on the order of 5-7 weeks after placing the order, putting delivery in early December at this point. EdArticle: 91163
Trying to smoothe the waves. Spartan3e does NOT use a new, unproven manufacturing technology. That means there should not be big surprises like they were with the previous generation. The sequence of availability will be : 500e, and 100e first, 1600e then, 250e and 1200 ater that. I am looking for the evalboard later today. PeterArticle: 91164
"Ed McGettigan" <ed.mcgettigan@xilinx.com> schrieb im Newsbeitrag news:dk5qm5$a2s1@cliff.xsj.xilinx.com... > Antti Lukats wrote: >> "Jon Beniston" <jon@beniston.com> schrieb im Newsbeitrag >> news:1130753284.143142.3010@g44g2000cwa.googlegroups.com... >> >>>Hi, >>> >>>Does anyone have any SystemACE parts for sale (upto 15 pieces) or know >>>any distributor who has some in stock? >>> >>>Cheers, >>>Jon >>> >> >> >> I have never found any disti selling them in small quantity. >> >> its on my DONOTUSE list anyway. >> And will be obsoleted soon. (Antti's guess) >> > > There are no plans to discontinue the System ACE CF (XCCACE-TQ144) > device. In fact we will be introducing the lead free version early > next year to meet ROHS design needs. > > There are no Xilinx imposed min order quantities (MOQs) on this > device and you are able to order these through any of our > distributors. Lead times should be on the order of 5-7 weeks after > placing the order, putting delivery in early December at this point. > > Ed good to know. but the distributors min quantities are 90 pcs ASFAIK. ..and the sysace is still on my DO NOT use list, because 1 WAY too expensive 2 WAY too hard to get 3 WAY too 'prop' the ACE file format is still 'secret' 4 W AY too 'limited' in terms of flexibility 5 WAY not enough media devices supported 6 WAY too large footprint on PCB AnttiArticle: 91165
"Peter Alfke" <peter@xilinx.com> schrieb im Newsbeitrag news:1130788825.037813.299300@g43g2000cwa.googlegroups.com... > Trying to smoothe the waves. > Spartan3e does NOT use a new, unproven manufacturing technology. That > means there should not be big surprises like they were with the > previous generation. > The sequence of availability will be : 500e, and 100e first, 1600e > then, 250e and 1200 ater that. > > I am looking for the evalboard later today. > Peter > haha - S3e 'GENERAL AVAILABILITY' was mid august 2005 according to Xilinx postings on c.a.f. somehow I feel the people are not witnesssing this general availability ? its few hours til NOV 2005. (or it already is in NZ). but mid august is way past. be it NZ or US westcoast timezone. as of today the s3e 'introduction' looks, well 'a little less disaster' then the s3 introduction. Antti's 3e centsArticle: 91166
Hello, I am trying to use .vwf files to simulate some designs (I'm not doing this out of choice...being forced to do it). Anyways, I am using ModelSim-Altera as mu simulation tool. The problem is that I am unable to run the simulation for more than 100 us. When I go to Assignments-Settings-Simulation-Time Scale, the max is 100 us. Plus when I go to Assignments-Settings-Simulator-Simulation Period, I choose "Run Simulation till all stimuli are used", the simulation still runs till 100us. I need to run the simulation for a period greater than that. Any input would be helpful _m_Article: 91167
Antti: Any Pre-release information on your solution??? :-) Antti Lukats wrote: > "Ed McGettigan" <ed.mcgettigan@xilinx.com> schrieb im Newsbeitrag > news:dk5qm5$a2s1@cliff.xsj.xilinx.com... > >>Antti Lukats wrote: >> >>>"Jon Beniston" <jon@beniston.com> schrieb im Newsbeitrag >>>news:1130753284.143142.3010@g44g2000cwa.googlegroups.com... >>> >>> >>>>Hi, >>>> >>>>Does anyone have any SystemACE parts for sale (upto 15 pieces) or know >>>>any distributor who has some in stock? >>>> >>>>Cheers, >>>>Jon >>>> >>> >>> >>>I have never found any disti selling them in small quantity. >>> >>>its on my DONOTUSE list anyway. >>>And will be obsoleted soon. (Antti's guess) >>> >> >>There are no plans to discontinue the System ACE CF (XCCACE-TQ144) >>device. In fact we will be introducing the lead free version early >>next year to meet ROHS design needs. >> >>There are no Xilinx imposed min order quantities (MOQs) on this >>device and you are able to order these through any of our >>distributors. Lead times should be on the order of 5-7 weeks after >>placing the order, putting delivery in early December at this point. >> >>Ed > > > good to know. > > but the distributors min quantities are 90 pcs ASFAIK. > ..and the sysace is still on my DO NOT use list, because > > 1 WAY too expensive > 2 WAY too hard to get > 3 WAY too 'prop' the ACE file format is still 'secret' > 4 W AY too 'limited' in terms of flexibility > 5 WAY not enough media devices supported > 6 WAY too large footprint on PCB > > Antti > >Article: 91168
morpheus wrote: > Hello, > I am trying to use .vwf files to simulate some designs (I'm not doing > this out of choice...being forced to do it). Anyways, I am using > ModelSim-Altera as mu simulation tool. The problem is that I am unable > to run the simulation for more than 100 us. > When I go to Assignments-Settings-Simulation-Time Scale, the max is 100 > us. Plus when I go to Assignments-Settings-Simulator-Simulation Period, > I choose "Run Simulation till all stimuli are used", the simulation > still runs till 100us. > I need to run the simulation for a period greater than that. > Any input would be helpful > _m_ > With the .vwf file the focus, go to Edit-End Time...Article: 91169
Jim Granville <no.spam@designtools.co.nz> writes: > The marketdroid that wrote the link above, decided eBEAM > might scare off some customers, so better to use words > like "configurable logic" & "unprecedented flexibility and time to market". By the way, am I the only one who finds 90% of the material that companies publish on their products to be utterly content-free and useless? It seems like the problem is much worse in the FPGA space than other parts of the computing world. That's extremely surprising, especially because the marketing certainly isn't aimed at average end-users. - aArticle: 91170
I do not understand what joy people get out of bitching and moaning. I am not in Marketing, I just try to help with some factual information. If I can get it... Peter AlfkeArticle: 91171
Peter Alfke wrote: > I do not understand what joy people get out of bitching and moaning. > I am not in Marketing, I just try to help with some factual > information. > If I can get it... > Peter Alfke > I for one welcome whatever information you can provide Peter. I guess its just frustrating to be told that a product will be avaiable a few months from now and it actually turns out to be many months of more than a year. I am always try to 'look-ahead' for the next design. I just hate being teased with things that I cannot have! For experience with previous employment, Marketing always advertised product that couldn't be delivered in the timeframe they stated. Sigh.... Too bad the engineers weren't in charge of everything. Thanks for all the information (even if we bitch)! -EliArticle: 91172
Jim Granville skrev:
> Marco wrote:
> > sorry for my terrible scheme.
> >
> > Please watch the picture at the link:
> >
> > http://www.maxim-ic.com/images/appnotes/1870/A237Fig04.gif
> >
> > That should be more clear.
> >
> > I thought that I could replace the 1-bit dac using a LVCMOS25 out pin
> > (without dac because it is only 1 bit) and connecting it to the negative
> > input of LVDS25.
> >
> > What do you think about it?
> >
> > Is it possible?
>
> You need to do some simple maths:
> 16 bits on 3.3V, is a LSB of ~50uV, so if you want to
> achieve 16 bit ADC performance, your system must be
> able to resolve to <50uV, and generate voltage to better
> than 50uV, in stability/noise.
>
> Now, look in the data sheets, for any units uV ?
>
> FPGAs are NOT designed as voltage-domain devices, they
> are time-domain devices.
>
> You need these voltage-domain components, added to a FPGA
>
> ** Precision Voltage reference
> ** Analog Switch - GND-VREF toggling
> ** Precision resistors - Min of 2
> ** Integrator = Performance OpAmp + Correct Capacitor
> ** Stable Clock source
> ++ Comparitor
>
> The last item, you just MIGHT be able to use LVDS, if you
> are carefull with common mode range, and integrator amplitude.
>
> Build it first with an external one, then try and remove when
> it is ALL working to > 16 bits.
>
> In operation, think of a SD-ADC as simply a charge balancing system,
> that makes a heap of Go-Up / Go-Down decisions ( one every clock)
> and then totals (average) those over a great many clocks.
>
> It relies on the integrator being good enough, that it really does
> charge balance.
>
> -jg
Assuming the threshhold for LVCMOS inputs are close to Vcco/2 with
little hysteresis and LVCMOS outputs are close to 0-Vcco outputs. I
wonder how
well something like this would work?
| FPGA
R R | /|
Vin >--/\/\/--+--/\/\/--|-| |--
| | \|
| |
| | |\
+---------|-| |--
| | |/
=== |
|C
_|_
If the Vcco for the bank is from a seperate source, how well will it be
isolated from the rest?
-Lasse
Article: 91173In article <dk5p1q$1c90$1@f04n12.cac.psu.edu>, emh203@psu.edu says... > Peter Alfke wrote: > > New Zealand is ahead of the rest of the world, as usual... > > Peter > > So when will the Spartan 3e actually be available?????? I can't even > get my hands on a few chips. This is somewhat upsetting because the > same thing happening with the Spartan 3. > > Even though I love the Xilinx stuff, it seems really damn hard to get > the parts! > > -Eli I just received 8 XC3S500-4PQ208CES's (engineering samples) from AvNet a week or so ago. I'm wishing I would have used a Spartan 2E now because I can't seem to get a 8bit BLVDS working. It receives but it does not transmit. Same circuit works on VertexII and Spartan2E no problem... -- Greg Deuerling Fermi National Accelerator Laboratory P.O.Box 500 MS368 Batavia, IL 60510 (630)840-4629 FAX (630)840-5406 Electronic Systems Engineering Group Work: egads_AT_fnal.gov, remove '_AT_'Article: 91174
"Peter Alfke" <peter@xilinx.com> schrieb im Newsbeitrag news:1130792932.840675.310370@f14g2000cwb.googlegroups.com... >I do not understand what joy people get out of bitching and moaning. > I am not in Marketing, I just try to help with some factual > information. > If I can get it... > Peter Alfke > Peter, I just want to have an S3e to play with. thats it. simple as that. I CAN NOT talk about s3e at work- believe me I tried. I will get a weird a look only. I did think that I can not eat my pride to make another attempt (to talki in favor of s3e) but, I did I did eat the pride and did try again to promote S3e - with the same weird look as result. People on the field do not trust to deal with S3e yet. Thats the situation as of today. Sorry. I could ask some friend from some other company to place on order on my behalf, but - that I think is too much troublesome. I can not buy from Xilinx (Xilinx is not selling..) and I am not going to beg either. I do have other toys to play with. I personally DO still think that S3e is the BEST low cost FPGA around - specially the MBT feature, etc. - but it is also likely that I will be looking into alternatives. Peter, its the marketing - Xilinx is big, we all know that, but that is no excuse to bullshit big time. If S3e is available as of today, WHY is it not available from Xilinx online store? Altera has pretty much all the product line in their online shop. I dont have to tell you what is orderable in Xiíinx online store. The fact that s3e is orderable by disties with their usueal 6-8 week delivery (maybe), is not good enough. You know, I am Xilinx user. But as of the S3e delay, I looked 2nd time at Altera Cyclone II, and BIG SURPRISE I found DCI like features there - with no external components. I dont have direct application for this, but I have this on my mind - Cyclone II, orderable now, low cost, supports standard SPI, has on chip termination. If I would have been busy playing with S3e I may not have discovered this feature of Cyclone II. Sorry I have not made full comparison of C-II vs S3e, but chances are C-2 wins. ok, maybe not, the Xilinx SRL16 are really nice, specially when used the way Ken likes it. I hope the missing config readback function of S3 is now being fixed in S3e silicon. Cheapest C-2 available today in online shop is around 12 USD. If I can not buy S3e, I will be buying C-2 ? Could be. For Peter Alfke - I was about to say that I am able to design and manufacture an S3e eval board in 1 WEEK - from design start GO til orders shipped (sure large NRE applies) -, but there is no silicon. hence no eval boards. Xilinx is "targetting" DEC 2005, heavens sake, if there is working silicon of s3e why delay the eval boards til December???? Any delay is lost business, lost money - GOGO, many people are eager to design in S3e, if they get real assurance on availabiliy. The people in the field are no longer buying the marketing bullshit. You can either by the stuff or not. Saying it is available means nothing. Take a look at S3 intro the actual availability was more than a year later from what Xilinx claimed it. A lot of people are looking at 'Xilinx latest' - and they want to get hands dirty with S3e, so why delay? Only explanation I can think of is that there is no silicon working enough to the degree of being allowed to be used in evaluation boards. Really - day before yesterday I spend some time thinking if I should make an s3e eval board - and I figured out that as I am not able to get authorative trustworthy answer on silicon availability it makes no sense to invest extra time at this moment - so I am doing something else instead. Steven Knapp as example hasnt cared to answer my emails. Just plain ignorance. Ok, agreed maybe I am too PITA and thats why he hasnt responded. Antti, Peter relax - I know you are not in the marketing, Maybe one day the marketing will understand that not everything goes. And I dont have much joy in moaning, I do have A LOT OF JOY playing with latest and greates technologies. I really do. And I do play with what I get hands on. Sometimes spending my (or even my families) food money on it. I do not have have any s3e yet, but I have spent some of my private money to obtain some programmable devices lately (not xilinx silicon) and considering buying some more stuff (again not xilinx silicon). hmm,.. actually my last buy was some Xilinx XC4000 on ebay :) - still having ideas to support old FPGAs that are abondoned by their creators. sneak preview: on my harddisk I have a tool I call 'Logic Assembler' it can serve as front end for almost any FPGA/PLD for what the vendor fitter/mapper exists. Tested in silicon with Atmel FPSLIC and Xilinx V4, also works for Xilinx XC4K(bitgen OK no silicon test yet), and pretty much everything. I am looking into adding support for XC2K, XC3K as well but as I have lost my 5 Inch disks with XACT unfortunatly the XC2/3K support is under questionmark :( oh well maybe I can buy it (old XACT) one day on ebay, you never know. --- sorry for long buff.
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