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Hi all, I wander how to find the IEEE package VHDL reference manual in Internet, can you pls give me a link? Thanks a lot. ABAIArticle: 93601
<wtxwtx@gmail.com> schrieb im Newsbeitrag news:1135593905.451170.291220@f14g2000cwb.googlegroups.com... > Hi, > I have implemented a I2C bus core by myself. > > When reading, a multiple source 'error' would happen if your code > assertes the acknowledge bit slightly earlier than the target deasserts > the bus from the last read data bit or when writing, if your code > deasserts the acknowledge bit slightly later than the target asserts > the acknowledge bit on the bus. > > You may ignore them totally without any problem. > > Weng > http://xilant.com/content/view/31/55/ Weng, the multipy source error is usually fatal synthesis error and prevents the bitstream generation until fixed. the OP has problem wiring up the processor data bus, not the SDA/SCL lines IMHO AnttiArticle: 93602
Hi Antti, Thank you for indicating my wrong answer. I misunderstood the problem. One of errors is multi-source data_bus(7 downto 0) are assigned in more than one processes! It is easy to correct it: Use search key to search signal 'data_bus' through the module source file and see how many times the data_bus are assigned. Put all assignments in one process only. WengArticle: 93603
<wtxwtx@gmail.com> schrieb im Newsbeitrag news:1135599779.396787.40140@g14g2000cwa.googlegroups.com... > Hi Antti, > Thank you for indicating my wrong answer. > > I misunderstood the problem. > > One of errors is multi-source data_bus(7 downto 0) are assigned in more > than one processes! > > It is easy to correct it: > Use search key to search signal 'data_bus' through the module source > file and see how many times the data_bus are assigned. Put all > assignments in one process only. > > Weng > Weng you are a bit mistaken again the data_bus is assigned once outside process data_bus <= data_out when (r_w = '1' and dtack_oe = '1') else (others => 'Z'); in the uc_interface.vhd so the ip-core is 100% proper for its intended function - controller for external microcontroller. for on-chip soc bus, the uc_interface module should be replaced, or modified. anttiArticle: 93604
Hello, With Xilinx ISE, I have create a small project. I have a .bit file that I can download into the fpga with Impact. It works well ! But now, I want to download the corresponding configuration file into the flash. Impact asks me to select a .mcs file, and I have no .mcs file. What can I do create such a file ? Thanks. OlivierArticle: 93605
"Olivier Scalbert" <olivier.scalbert@algosyn.com> schrieb im Newsbeitrag news:43aff2c2$0$10968$ba620e4c@news.skynet.be... > Hello, > > With Xilinx ISE, I have create a small project. I have a .bit file that I > can download into the fpga with Impact. It works well ! > But now, I want to download the corresponding configuration file into the > flash. Impact asks me to select a .mcs file, and I have no .mcs file. What > can I do create such a file ? > Thanks. > > Olivier ISE Generate Programming File Generate PROM, ACE or JTAG File then select proper setting and generate .MCS then switcg impact to programming mode and configure the flash device AnttiArticle: 93606
Antti Lukats wrote: > ISE > Generate Programming File > Generate PROM, ACE or JTAG File > > then select proper setting and generate .MCS > > then switcg impact to programming mode and configure the flash device > > Antti > > Thanks for your help ! It works. Now, I can put my blinking starter kit board onto the Christmas tree with no connected pc ! ;) OlivierArticle: 93607
In U.S. patent law there are at least two sections that are applicable in this situation: 35 USC 102: A person shall be entitled to a patent unless - (a) the invention was known or used by others in this country, or patented or described in a printed publication in this or a foreign country, before the invention thereof by the applicant for patent, or (b) the invention was patented or described in a printed publication in this or a foreign country or in public use or on sale in this country, more than one year prior to the date of the application or patent in the United States, or ... To invalidate a patent a patent under 102(a) requires comparing the date that the applicant [Lucent] invented the circuit to the date that John's circuit became publicly known. In this case we don't know when Lucent invented the circuit unless the Lucent chooses to divulge the information or they are forced to do so in court. So the patent may be invalid under 102(a), but we have no way of knowing at this point. To invalidate a patent under 102(b) we would need to show that John's circuit became publicly known more than a year before Lucent's application. Since we know the date of Lucent's application, that is an easier task. In either 102(a) or 102(b) the date that John's invention became publicly known is important, not the date he invented the circuit. - RichArticle: 93608
>Part of the leakage is through the ultra-thin gate dielectric, part is >through transistors that are not perfectly turned off (sub-threshold >leakage). It's the price you pay for high performance and high density >(small size, low cost). >This is perhaps the most frustrating aspect of the newer technology... How big is the low power end of the FPGA market? Does it need high speed? I'm not a silicon wizard. I think it was common to do a die-shrink on existing designs and move them to a new fab line. You don't take full advantage of the new line, but you get some/much of the benefit without much engineering time. Is it feasable to go in the other direction? Can you take a current design and (roughly) make all the rectangles bigger and then run it on an old fab line with low leakage? You would have to figure out how fast it goes, but you wouldn't have to do much engineering on either the chip design or the tools. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 93609
Hi Rich, Thank you for your response. Can you please give me a date example to explain the 102(b). I really have difficulty understanding the item. After I joined this discussion, I re-read the patent 6,760,737 again and found the following several new points that conflict with my previous views posted in this discussion. 1. The patent 6,760,737 has not repeated what John had written in his paper. In other words, my point of view is the patent 6,760,737 has nothing to do with John's paper. 2. It deals with how to find a median data among N data; where N is any odd number greater than 1. Its implementation and its claims are described as more a software operations than a hardware operations. For example, N data is divided into 3 groups and each group should be sorted before doing any further operations. 3. For N = 9 situation, its implementation is slightly different from what John had done. John did it in the minimum comparison operation, but patent 6,760,737 does it like a software operation that is less optimized than John method, but it can be best done by a software. Any further comments are welcome. WengArticle: 93610
The Jiang patent (6,760,737) is based on application 09/760,923, filed on 16 January 2001. Application 09/760,923 claims priority to provisional application 60/192,294, filed 27 March 2000. Any claims in 6,760,737 that are supported by the provisional application may take advantage of the 27 March 2000 priority date. 35 USC 102(b) states that "A person shall be entitled to a patent UNLESS the invention was patented or described in a printed publication in this or a foreign country or in public use or on sale in this country, more than one year prior to the date of the application for patent in the United States..." Now - inserting the specifics of the Jiang patent, 102(b) is essentially: "Jiang is entitled to a patent UNLESS the invention was publicly disclosed prior to 27 March 1999." I'm not going to try to compare John's disclosure to the claims in 6,760,737. My point is simply that if John published his paper on or after 27 March 1999, it is probably not relevant to the validity of 6,760,737. RichArticle: 93611
Hello, Having trouble with some LVDS signals coming from a Camera Link interface. I expect to see from steady signals coming from this line camera. DVAL=1. But it's not there. And the LVAL, line valid, only comes on for maybe one clock, and I expect it to come on for 2K clocks. I am using IBUFDS as inputs. The UCF file loc the pins but that is all. Do I need something more to drop the 100 ohm termination resitance? Brad Smallridge aivision.comArticle: 93612
Hal Murray wrote: > How big is the low power end of the FPGA market? Does it need > high speed? > > Can you take a current > design and (roughly) make all the rectangles bigger and then run > it on an old fab line with low leakage? You would have to figure > out how fast it goes, but you wouldn't have to do much engineering > on either the chip design or the tools. Hal, many things can be done. But the outcome would be circuits that are slower and bigger = more expensive. Some users would gladly pay the price and accept the slower performance, for the low-power benefit. But how big is that market? Presently, the main manufacturers do not think it's worthwhile. This is Capitalism 101, which seems to work, and has given you superb circuits at a low price. If low current is so important, demonstrate it with your pocketbook... And don't forget, you can still buy the low-current circuits introduced almost 10 years ago. Peter AlfkeArticle: 93613
Hello I am starting FPGA with a V4MB, without any download cable, but a RS-232 cable. I am wondering how to download my bit stream file to my board. Could anyone help me ? FrankArticle: 93614
I meant: "demonstrate it with your wallet". English as a second language, especially during holidays... PeterArticle: 93615
I know on Altera parts you have to tell the tool to turn on the on-chip termination resistors: it may be the same with Xilinx. Also, I know on V2PRO parts the banks running differenital I/O must be operated with a 2.5V VCCIO. Also, I would look at the inputs at the connector to make sure that they are acting as expected. If you don't have a differential probe you can get a reasonable look with a single ended one. This is just to make sure that you're not chasing the wrong problem. I've done many designs with Camera Link so let me know if you need anything else. Let us know what you find. "Brad Smallridge" <bradsmallridge@dslextreme.com> wrote in message news:11r0jedsghr3me0@corp.supernews.com... > Hello, > > Having trouble with some LVDS signals coming from a Camera Link interface. > I expect to see from steady signals coming from this line camera. DVAL=1. > But it's not there. And the LVAL, line valid, only comes on for maybe one > clock, and I expect it to come on for 2K clocks. > > I am using IBUFDS as inputs. The UCF file loc the pins but that is all. > Do I need something more to drop the 100 ohm termination resitance? > > Brad Smallridge > aivision.com > > > >Article: 93616
Hi Rich, What you said is causing my confusion the most way: " if John published his paper on or after 27 March 1999, it is probably not relevant to the validity of 6,760,737. " If you posted a paper on website today, tomorrow I used your paper contents to file a patent. Then 102(b) says that your paper is probably not relevant to the validity of mine??? WengArticle: 93617
Taking a quick look at the picture of the board I would suggest perhaps the programming is done via the USB connector and Xilinx's Platform Cable USB. "Frank Schreiber" <frankschr@googlemail.com> wrote in message news:dopoa5$mlo$1@anderson.hrz.tu-chemnitz.de... > Hello > I am starting FPGA with a V4MB, without any download cable, but a RS-232 > cable. I am wondering how to download my bit stream file to my board. > Could anyone help me ? > Frank > >Article: 93618
Hi Antti, I don't have his source code and made a judgement based on the following warnings: Unit i2c_tb: 8 multi-source signals are replaced by logic (pull-up yes): data_bus<0>, data_bus<1>, data_bus<2>, data_bus<3>, data_bus<4>, data_bus<5>, data_bus<6>, data_bus<7>. 1. data_bus are multi-source signals; 2. data_bus is in the module: i2c_tb. It may be in his test bench code to make the multi-source error. I never claimed that it was the IP code error. Any IP code never makes such basic and fundamental error. WengArticle: 93619
There are two different concepts: "First to invent" or "First to file". Europe uses the simpler "first to file". The US uses "First to invent" and gives the inventor a one-year grace period to prove that he/she invented it first. This method is obviously more profitable for the lawyers... If you file a US patent application after reading the idea, you would face the difficult task of proving that you had invented this before the article was published. Fertile field for endless lawsuits... Peter AlfkeArticle: 93620
Hi Peter, Now I understand 102(b) better than before: gives the inventor a one-year grace period to prove that he/she invented it first. With DDP (Document Disclosure Program) program introduced into law, it gives the DDP holder 2 years grace period to prove. Does it contract with the one-year grace period claimed in 102(b)? What is the DDP benefit or disadvantage? Thank you. WengArticle: 93621
Peter Alfke wrote: > There are two different concepts: "First to invent" or "First to file". > Europe uses the simpler "first to file". The US uses "First to invent" > and gives the inventor a one-year grace period to prove that he/she > invented it first. This method is obviously more profitable for the > lawyers... > If you file a US patent application after reading the idea, you would > face the difficult task of proving that you had invented this before > the article was published. Fertile field for endless lawsuits... > Peter Alfke > IOW the 1 year that you have after your invention is described publicly is one year after _you_ publish -- not after _I_ publish. -- Tim Wescott Wescott Design Services http://www.wescottdesign.comArticle: 93622
Do you know the story about J/Phy particle in physics? One scientist published the discovery first, another claimed that they had discover it earlier. Finally a compromise was reached that the particle got a dual name: J/Phy particle. The 102(b) is applied just to the same scenario. Thank you, Peter, you let me understand the complex sentences of 102(b). WengArticle: 93623
Tim Wescott wrote: > > IOW the 1 year that you have after your invention is described publicly > is one year after _you_ publish -- not after _I_ publish. Let me get away from I and You: The inventor filing for a US patent can publish and talk about his idea for a full year before filing the patent application, and anybody else (who learned from this and tries to file before the legitimate inventor) has to prove that he invented it first. In Europe, you better be completely quiet about your idea until you file. Remember, I learned this only by osmosis. I am not a patent lawyer, heaven forbid... Peter AlfkeArticle: 93624
There are some examples in this link. http://www.altera.com.cn/products/devkits/kit-dev_platforms.jsp Binary wrote: > Hi all, > > I want to buy some chips of Altera Cyclone to do some experiments, but > before I proceed, I can't find any reference desing/smallest system > available on Altera's website. For example, the datasheet doesn't > include the smallest system for me to run with! > > Anyone can tell me how to find it? > > Thanks in advance. > > ABAI
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z