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Wouter Coene wrote: > On Tue, 21 Feb 2006 14:37:43 -0800, Dave Pollum wrote: > > > My VHDL project has out grown a XC95108 CPLD, so I'll be using a > > XC95144 instead. After running the ISE synthesizer and fitter, all of > > the XC95144's Function Block Inputs are used. Using exhaustive fit > > mode, 92% of the function block inputs are used. This still doesn't > > leave much room for additional features. I then told ISE to use a > > XC95144XL, instead. Only 64% of the function block inputs are used, and > > the other resources look good, too. [...] The odd thing is that > > the XL version uses _8 more_ flip flops than the standard version, and > > the timing report shows that the XL is faster than the std part, even > > though I selected 10 ns speed grade for both parts. I haven't > > simulated both chips yet. > > The difference in flip-flop count could be due to the synthesiser using > another kind of implementation for some feature for your older CPLD. For > example, there are a couple of ways to encode a FSM, some being smaller and > others being a bit bigger but faster. > > Secondly, the 10 ns speed grade only says something about the pad-to-pad > delay. If I recall correctly, this is the cumulative delay of a typical > signal path. Since the -XL is a whole different chip (3,3V instead of 5V > logic) the component delays making up the total delay are bound to > be different. > > Hope that helps. > > Wouter > -- > Replace "spamtrap" with first name for email address. Thanks! Your comments do make me feel a bit better, but I'm still curious about the different results. I guess I'll re-read the XC9500 and XC9500XL docs. -Dave PollumArticle: 97451
Hi I'm looking for possibilities for migrating project/design from FPGA(XC2V3000) to any asic. What companies, have you ever had experience in this field? Kind regards. Jerzy GburArticle: 97452
Jerzy, Have you considered the immediate cost savings and no risk that you would gain with EasyPath? http://www.xilinx.com/products/silicon_solutions/fpgas/easypath/ Austin Jerzy Gbur wrote: > Hi > I'm looking for possibilities for migrating project/design from > FPGA(XC2V3000) to any asic. > What companies, have you ever had experience in this field? > > Kind regards. > Jerzy GburArticle: 97453
Hi, another option is to develop a FSL coprocessor with OPB Master interface (or an OPB Master IP with FSL interface) , isn't it? Regards, Ivan Antti wrote: > FSL links are connected to MB core and can not access the OPB > the OPB_MCH_SDRAM IP core has slave FSL ports so external FSL (XCL) > master can access the SDRAM over FSL (but not the rest of OPB bus) > > so you have options > 1) MB software will read FSL and translate it to OPB transaction in > software > 2) you write your own FSL 2 OPB (master) bridge > 3) if you want to access BRAM then you can access the second port of > the BRAMs but its rew BRAM port not FSL > > Antti >Article: 97454
Hi, yes of course... when you use a well-supported board (like Xilinx boards), but if you have a board that it is not specific developed for SoC designs, that assertion is not true :( Ivan P.S.: I have also got a LEON3/MB/PPC system working from first attempt... but using an appropiate board (and some months of experience) :D Antti wrote: > The speaker at Xilinx presentation at Embedded World asked the crowd: > "Has anyone managed to create an FPGA System On Chip design - with > first time success?" > > "I have", was my reply: "... using LEON3 GRLIB!" > > to be fully honest my response wasnt exactly true. > > I did manage to get LEON3 system working in FPGA within a few > hours, but I dont really recall if first FPGA configuration > loaded was actually working or not. Maybe not. > > But as of today, I could answer the same question with: > "Yes I have" - and be really correct this time. > > Some 20 minutes ago, I started XPS (EDK 8.1 SP1), new project, > V4FX-12, click, click, done, changing 3 PIN location constraints > (sys_clk, rxd, txd).. save .ucf file, then menu > > Device->Download > > and I got a prompt on serial console connected to FPGA board! > First time synthesis, first FPGA download, system working. > > So the first time success is possible! :) > > Antti >Article: 97455
Gabor wrote: > At our company we call FPGA configuration code "software" if it > is stored on the hard drive and uploaded at run time by a user > application. When it is stored in a serial PROM or flash memory > on the board we call it firmware. > > I don't think the terms "firmware" or "software" have as much to do > with the programming paradigm as with the delivery of the bits to > make the actual hardware run. At my current and previous jobs, FPGA "loads" are/were considered firmware, for the same reason that processor boot code and the lowest-level debug monitor was considered firmware: the images are stored on board in some kind of non-volatile memory. -aArticle: 97456
When I try to connect to my homemade FPGA board (xilinx spartan3) using iMPACT. It finds one chip but names it UNKNOWN. I can't read the ID code. It reads only 0000000000000000000 I can't upload the .bit file. What can course this problem? Tanks Andreas BeierArticle: 97457
You may want to look at Atmel's offering at: http://www.atmel.com/products/ULC/ They do turnkey conversions from most FPGA or CPLD designs. Austin Lesea wrote: > Jerzy, > > Have you considered the immediate cost savings and no risk that you > would gain with EasyPath? > > http://www.xilinx.com/products/silicon_solutions/fpgas/easypath/ > > Austin > > Jerzy Gbur wrote: > > > Hi > > I'm looking for possibilities for migrating project/design from > > FPGA(XC2V3000) to any asic. > > What companies, have you ever had experience in this field? > > > > Kind regards. > > Jerzy GburArticle: 97458
mughat wrote: > When I try to connect to my homemade FPGA board (xilinx spartan3) using > iMPACT. It finds one chip but names it UNKNOWN. > > I can't read the ID code. It reads only 0000000000000000000 > I can't upload the .bit file. > > What can course this problem? > > Tanks > Andreas Beier > > If you are only seeing zeroes on TDO, how about checking all of your connections from the cable to the target system? Don't forget to power the cable, tooArticle: 97459
Thanks to all! I simulated my design indeed using Micron memory models (I use mt8vddt1664a memory model for simulation - it's not exactly my model but seems to be closed enough for me) and as I wrote before it worked just fine. But I did not use the FPGA netlist in my simulation. So as ALuPin@web.de said I'd simulated the VHDL description but not the synthesis result. I am going to simulate the synthesis results (I'll do it tomorrow because first I have to find out how to do it. I've never done it before). Does somebody have a good link about it? So I'm googling around. I'll write about results tomorrow. I am open to any other ideas. Best, AdaArticle: 97460
Hi Venki, If you open the assignent editor (Ctrl-Shift-A) after running the script, you should see the equivalent assignments in a more readable format. To see the relationship between the clock domains clk and dclk, go to Assignments->Settings->Timing Settings. Best regards, BenArticle: 97461
I want my coprocessor can access the BRAM diretly because there is a lot data transfer between them. It will be very unefficient to send these data back to MB through FSL and then put them into OPB RAM or vise verso. I don't want to put connected my coprocessor to the sceond port of the BRAM either because the BRAM(64K) is shared between the MB and my coprocessor and I want the OPB arbitrator to solve the contension problem for me. Then I needn't program my own. For the second choice, write my own FSL2OPB bridge, or as said by ivan: "develop a FSL coprocessor with OPB Master interface" will be quite time consuming because I need to take care of my customized circuit to the OPB bus signals? But it seems the only choice I have. Did I understand this correct? Thank you very much for all the replies.Article: 97462
Brannon wrote: > I hate to break it to you buddy, but partial configuration has crashed > in every version, every service pack, I've ever attempted it on. I have > yet to try it on 8.1, but on all other versions of ISE you can safely > assume that it is busted. It was a sales pitch, not an engineering > priority for Xilinx. Your best chance of getting it to work is for the > case of additional logic only -- change any net names or instance names > and it will certainly crash. It seems like my errors all looked like > the one you posted. I've received the errors on Win2k and WinXP with > both Xeon hardware and AthlonXP hardware. Wow, someone with an even more negative opinion on partial reconfiguration than myself! It's bad, but maybe not quite *that* bad. There's a bunch of people on the partial-reconfig mailing list who've got this stuff to work, but it takes patience, a willingness to hack, and a willingness to accept a big gap between what you would like to do, vs what you actually can do. Mailing details here, including searchable archive: http://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux/Mailing_List/index.html#partial-reconfig JohnArticle: 97463
Hello, I have set-up checkpointing in ModelSim 6.0b (also using EDK 7.1 SP2). ModelSim complains that "two foreign architectures are missing save and restore callbacks" when I checkpoint. These "foreign architectures" happen to be the PPC swift models. When I restore the checkpoints, the waveforms are fully restored. However, I cannot continue the simulation because it makes the following complaint: # ** Fatal (SmartModel): # SWIFT protocol: # The first call to lsm_Model_DCEvaluate must occur at time 0. # Time: 424875000 ps Instance:/system/ppc405_0/ppc405_0/ppc405_i/ippc405_swift/ppc405_swift_inst # ** Fatal: Foreign module requested halt. # Time: 424875 ns Iteration: 0 Foreign Process: /system/ppc405_0/ppc405_0/ppc405_i/ippc405_swift/ppc405_swift_inst/SmartModel File: Foreign # Fatal error at an unknown location # Anyone encountered this issue? Thanks, NNArticle: 97464
hansp wrote: > Check out this link for some ideas: > http://www.fpga4fun.com/10BASE-T.html Yes, I've built the transmitter twice (in both altera and xilinx) parts and it more or less worked. In one case I had to send it through a switch before an embedded ethernet board could understand it. Haven't tried the receiver. Getting it to do anything usefull is a bit different though. BTW you probably need to be local amin on a win XP box to receive UDP packets... There are really a bunch of options: - A serial to ethernet converter module, which may handle a TCP/IP protocol for you (LANCHIP, etc) - An ethernet chip or card intended for PC-ISA - lots of embeded guys have used these (avoid PCI though) - using an ethernet "PHY" chip to interface to the cable (with transformer of course) and then implementing the "MAC" function along with all the protocol stuff in the FPGA - implementing everything in the FPGA except for the transforer (yes, some people cheat with capacitor coupling). This is what the FPGA4FUN project does.Article: 97465
The other day I found myself needing a short gate time ~200 mhz frequency counter for an automated test, and since I had an FPGA board on hand I whipped one up quickly. Getting it reading and reporting to my computer was the easy part. Ah, the input stage.... I've got about 4dBm of RF into 50 ohms to play with - about a volt p-p or a little more if it's high-Z. The output of the device under test has a transformer and then a series cap to create an unbalanced output. I did something ugly with a 3.3v cmos 7406 varient and a feedback resistor, which works well enough to get an accurate reading on one version of the device under test, but not on the other (both have been verified with real test equipment) It also tends to self-oscillate with no input... What would be the right way to do this using on hand parts, such as abused logic, little 1:1 or 2:1 RF transformers, etc? One idea is to use another gate with a feedback resistor and cap to ground in the hope of establishing the threshold level, and then using a transformer to swing another input above and below this. Most parts on hand are SMD - which means dead bug construction in SOIC scale under the maginifier - discourages extensive experimentation. Why do most abuse-of-logic RF applications seem to use NAND gates rather than inverters? From a digital perspective NAND gates are a universal element, but once you tie their inputs together, is there something to be gained from having two inputs in parallel? Is there a way to use a differential input configuration on an FPGA to input a balanced RF signal directly? Theoretically this should be an FPGA clock input... The device in use currently is an Altera Stratix II, but a Xilinx S3 kit is available. If ordering things, what would be a good default low supply voltage HF/VHF gain component to have on hand? I seem to recall lots of last-millenium ham designs using the MC1350P video IF amp, but what would make sense today?Article: 97466
cs_posting@hotmail.com wrote: > The other day I found myself needing a short gate time ~200 mhz > frequency counter for an automated test, and since I had an FPGA board > on hand I whipped one up quickly. Getting it reading and reporting to > my computer was the easy part. > > Ah, the input stage.... Does the FPGA have LVDS option inputs ? If it is new enough to have those, they are differential amplifiers, designed for current mode signals, and will work with thresholds << 1V. IIRC the LVDS spec has +100mV and -100mV levels. Normally, they need a common mode bias of just over 1V, and the better ones will also tolerate rail-rail drive (on ONE ip), but at reduced speed specs. -jgArticle: 97467
For gain, have a look at MMICs. Minicircuits sell them in kits that give you a good range of performance. They're easy to use, and run on a single supply. I think the idea of using the LVDS inputs on the FPGA is a good one, if you can get that into the clock lines you need to use. Otherwise, you only need a little gain to get to levels you need for logic input. Do your clock input lines have a bit of hysterisis? Do they have high enough input impedance to be used with a step-up transformer? Can you reliably bias the transformer DC return to a point between the hysterisis trip-points. I suspect you can do a better job with your logic-gate amplifier, too. Or you could make a fancier input using one of the very fast comparators. Cheers, TomArticle: 97468
On 21 Feb 2006 03:08:26 +0100, "Symon" <symon_brewer@hotmail.com> wrote: >Hi Metal, >Thanks for a good thought provoking post. I added a few 'in my humble >opinion' thoughts to it! I'd be interested in what you think of them! >"metal" <nospam@spaam.edu> wrote in message >No. For both methods, HDL or schematic, the key to understanding something >you've just come across, is to read the comments. In text. The signal names >should be meaningful. Text, text text!! >> >ENTITY DSP_core_for_FFTs IS >PORT( > CLOCK : in std_logic; > DATA_IN : in std_logic_vector(127 downto 0); > DATA_OUT : out std_logic_vector(127 downto 0) > ); >END DSP_core_for_FFTs; > >Pretty clear to me. >> Symon, note that the above textual spec (albeit clear in itself) has ZERO information about what's feeding data in, where the output is going, etc.. What a schem/block gives one is the -connectivity-, and at a -glance-. I think that's what I was trying to get at....the ease of seeing -interrelationsips- in a graphical format. >I'm unconvinced that with today's multi-million gate designs that schematics >have much of a role. The designs are so complex that a language based >description is the way the design must be specified. I agree totally that >the FPGA designer should have a 'view' of the basic hardware they're trying >to fit their design into, I don't think that has to be a bunch of rectangles >with legs on! Some well placed block diagrams can do wonders to illustrate >connectivity and function, but well written text is better! >Finally, if anyone wants to refute any of the points I've made in this post, >I'd appreciate it if they could express their points in a viewlogic >schematic. Thanks. :-) >Cheers, Syms. > >p.s. OK, that whole post was deliberately provocative, I know YMMV. I don't >want to tell others how they should design, everyone has their own way of >doing stuff, this is just my POV! > I might find it hard to argue in the case of the multi-million gate chip....but then I again think that even the mega-chip is generally wired as -blocks- of logic, is it not? I.e. functional blocks. At -any- size, there can always be a hierarchy; just as there is with textual description. Nevertheless; your mention of a mega-chip did cause me to sit back and wonder if there is the "optimum" approach might be size-related?? I.e., those who are repeatedly doing desgins of a few hundred registers (like myself) may benefit more from a graphical approach than the designer who is tackling the million-gate monster. I have to say though, that when it comes time to troubleshoot the -product- that your monster-chip is embedded in, I will -still- want a block-diagram of your chip! LOL ----== Posted via Newsfeeds.Com - Unlimited-Unrestricted-Secure Usenet News==---- http://www.newsfeeds.com The #1 Newsgroup Service in the World! >100,000 Newsgroups ---= East/West-Coast Server Farms - Total Privacy via Encryption =---Article: 97469
In my bad old days in a power authority.. we used opto isolators.. the cabinet holding them was varnished wood.. and the cabinet had its own floor .. wood of course.. and held 4 inches above the main flor by nylon supports. Of course you could only get to one side of the opto from there, each side of the optocouple came out in the other side of the cabinet (thru the wood wall). Do you think they were paranoid? or working to worse case scenario? Simon "Hal Murray" <hmurray@suespammers.org> wrote in message news:lbWdnZ9Z1OHG22HenZ2dnUVZ_sGdnZ2d@megapath.net... > >Is that the famous one about the X-ray machine that irradiated people > >with 100X dose? > > Yup. > > >That case you could call imaging, but the consequences of the particular > >failure (lethal radiation doses) are a little different from, for > >instance, the failure of a blood pressure machine. > > Is your blood pressure machine plugged into the wall? Very sick > people often have electrodes attached at critical places. > > > A friend was jack-of-all-trades involving electronics at Mass General > Hospital. He reported that one of the really nasty things that happens > all too often to gear he worked on is that saline solution would get > dumped down the air vents. When he told me that story, I was thinking > of long term problems. > > Short term might be interesting too. How much isolation does your > magic opto-isolator chip provide when covered with salt water? > > Are we being paranoid enough? > > -- > The suespammers.org mail server is located in California. So are all my > other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited > commercial e-mail to my suespammers.org address or any of my other addresses. > These are my opinions, not necessarily my employer's. I hate spam. >Article: 97470
As Jim has said LVDS is a good way. Just watch the common mode input range. You can use a RF transformer to rebias the DC level to get arround any issues. Another way is to use a single ended standard like SSTL and DC bias the input to the reference voltage used for the SSTL. You do need to have access to Vref pins on the Spartan-3 to use this technique. We have support for LVDS and SSTL in our boards but I am not sure about the Spartan-3 starter kit. John Adair Enterpoint Ltd. - Home of Raggedstone1. The low Cost Spartan-3 Development Board. http://www.enterpoint.co.uk <cs_posting@hotmail.com> wrote in message news:1140663703.875988.162830@g14g2000cwa.googlegroups.com... > The other day I found myself needing a short gate time ~200 mhz > frequency counter for an automated test, and since I had an FPGA board > on hand I whipped one up quickly. Getting it reading and reporting to > my computer was the easy part. > > Ah, the input stage.... > > I've got about 4dBm of RF into 50 ohms to play with - about a volt p-p > or a little more if it's high-Z. The output of the device under test > has a transformer and then a series cap to create an unbalanced output. > > > I did something ugly with a 3.3v cmos 7406 varient and a feedback > resistor, which works well enough to get an accurate reading on one > version of the device under test, but not on the other (both have been > verified with real test equipment) It also tends to self-oscillate > with no input... > > What would be the right way to do this using on hand parts, such as > abused logic, little 1:1 or 2:1 RF transformers, etc? One idea is to > use another gate with a feedback resistor and cap to ground in the hope > of establishing the threshold level, and then using a transformer to > swing another input above and below this. Most parts on hand are SMD - > which means dead bug construction in SOIC scale under the maginifier - > discourages extensive experimentation. > > Why do most abuse-of-logic RF applications seem to use NAND gates > rather than inverters? From a digital perspective NAND gates are a > universal element, but once you tie their inputs together, is there > something to be gained from having two inputs in parallel? > > Is there a way to use a differential input configuration on an FPGA to > input a balanced RF signal directly? Theoretically this should be an > FPGA clock input... The device in use currently is an Altera Stratix > II, but a Xilinx S3 kit is available. > > If ordering things, what would be a good default low supply voltage > HF/VHF gain component to have on hand? I seem to recall lots of > last-millenium ham designs using the MC1350P video IF amp, but what > would make sense today? >Article: 97471
JTAG chains are notoriously problem areas so let start with some basics. Try and keep the TMS, TDI, TCK runs together. If get a big difference between particularly TCK and the others you can get into setup and hold issues. If you programming cable is home grown watch out for the edge rates coming out of the cable. They may be very fast and causing reflections. Add series resistors if this is the problem. Different devices have different JTAG voltages for operation. Driving at 2.5V may be marginal on a 3.3V JTAG. Driving at 3.3V may put too much current, through protection diode, into a 2.5V JTAG device. To help in all this IMPACT has a debug mode where you can waggle signals at will and follow operation with an oscilloscpe. What cable are you using? John Adair Enterpoint Ltd. - Home of Raggesdtone1. The Cheap Spartan-3 Development Board. http://www.enterpoint.co.uk "mughat" <mughat@gmail.com> wrote in message news:dtiit3$bd2$1@news.net.uni-c.dk... > When I try to connect to my homemade FPGA board (xilinx spartan3) using > iMPACT. It finds one chip but names it UNKNOWN. > > I can't read the ID code. It reads only 0000000000000000000 > I can't upload the .bit file. > > What can course this problem? > > Tanks > Andreas Beier >Article: 97472
yes. if you want to use EDK OPB arbiter then you need your own IP that has OPB master port, and that may be time consumint to develop/troubleshoot AnttiArticle: 97473
Yes/No I was using custom board for the PPC design mentioned, not anything even remotly similar to any supported Xilinx boards, so I created a full custom system, and that worked. But agree, I only used uart lite for simple hello greeting. At next step adding a DCM I had to use 2 synthese attempts to get it working again (the DCM runs from 12MHz external clock so its little difficult to setup properly). And with LEON3 I wasnt using supported board either (with supported board it most likely would have worked from first config attempt) - and all of that getting working on first attempt (or within hours) is only possible with lots of experience ;) AnttiArticle: 97474
hi,
am Pavan working on a project in India. I am stuck with a problem. i
hope one of u can clear it. before continuing ill tell u my project in
brief. I am basically a fresh graduate. i love working on
microcontrollers. but i would like to know which one would be better
for my application. my application goes this way.
i need to collect analog inputs convert into a digital format
using a A/D convertor and use the digital data to do some calculations
and based on the value send a signal to the output which changes state
from one to the other. also i need to interface display and some
keypad. so i thought a microcontroller with internal A/D convertor and
memory is sufficient. But now i ve heard about this FPGA concepts and i
would like to know which would be better. And also please mention some
of the advantages of using FPGA over the microcontroller.
hoping to get an answer soon.
Thanking you
yours truly
Pavan.
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Compare FPGA features and resources
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