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Roger Bourne wrote: > I am looking for the equations used in the calculations of the > coeffcients of chebychev IIR (2nd order) low pass filters for biquad > sections (w.r.t passband ripple, stopband attenuation ...). I have been > googling for the past hour, but alas no cigar (I suspect my search > criteria may be too narrow...) . I would appreciate any help, > particularly links and such. i think it might be here: http://www.mathcad.com/library/LibraryContent/MathML/Shrtstep.htm rots-o-ruk decoding it. r b-jArticle: 100101
alright, the reference is too bitchy to decode, here it is for
normalized analog s:
|H(jw)|^2 = 1/(1 + (e*T(w))^2)
when w = 1, you are at the edge of the passband ripple just before the
gain takes a dive.
T(x) is abreviated from T_N(w), the Nth order Tchebyshev polynomial
{ cos(N*arccos(x)) |x| <= 1
T_N(x) = {
{ cosh(N*arccosh(x)) |x| >= 1
"epsilon" = e = sqrt( 10^(dBripple/10) - 1 )
-3 dB frequency: w1 = cosh((1/N)*arccosh(1/e))
no analog zeros, the analog poles are at:
p = -cos(theta)*sinh(phi) +/- j*sin(theta)*cosh(phi)
where phi = (1/N)*arcsinh(1/e)
{ pi/N*(n + 1/2) 0 <= n < N/2 N even
and theta = {
{ pi/N*(n) 0 <= n < N/2 N odd
for normalized s:
H(s) = 1/( (1 - s/p1)(1 - s/p2) ... )
to apply bilinear transform refer to the biquad EQ cookbook at
http://www.musicdsp.org/files/Audio-EQ-Cookbook.txt
can't get more explicit than that.
r b-j
Article: 100102I am trying to perform readback of the configuration for a Virtex-4. I followed the steps in the configuration guide, but have had little luck. The ICAP syncs up (output is 0xDF) and never enters ABORT when I give it commands; however, when I disable the ICAP, switch to read mode, and then re-enable the ICAP, the BUSY signal goes high, I do not recieve any configuration data, and the ICAP output remains 0xDF. Has anyone experienced this problem and know a correction or had success with readback and can inform me of their process? Thanks.Article: 100103
Hi all, Iam trying to develop an embedded mp3 player. I compiled...and installed in linux(FC4) + pentium platform. Now I want to prototype in xilinx development board. There are doubts like, 1)How can I estimate the processing power, fpu, memory, clock frequency, RTOS, cache requirements, like whether they are required or not, if so, how much. 2)Im thinking to use the leon processor (open source) instead of power pc (hardcore) in the xilinx chip. If I port my own processor in xilinx, could I be able to use the resources like ethernet transciever, audio codec etc which are built in the board, connected to power pc processor (like the software, device driver everything is designed with a view of power PC.) 3)In the development boards, there is a flash prom for storing configurations is available. Is it possible to use it as a place for storing my boot code portion so that I can download the image from pc and put it in RAM and run from the same. soft processor: leon chip : xc2vp30 (xilinx virtex-II pro development system Guide me in those areas, where I want to learn & work, PrakashArticle: 100104
"Duane Clark" <junkmail@junkmail.com> wrote in message news:2dyXf.50475$2O6.8995@newssvr12.news.prodigy.com... > faraz.khan@nssi.us wrote: >> Can anybuddy tell me what are the most common methods of grabing >> discrete from out side world. These signals have no vaid and are >> asynchronous > > Hmm... from http://www.nssi.us/about.htm > > "NSS is an engineering company specializing in the development, > modeling, verification, certification, and production testing, of safety > critical Avionics Systems." > > Interesting... Hi Duane, ...and apparently their "SOLE FOCUS IS ON SAFETY, INNOVATIVE ENGINEERING, and PERFORMANCE EFFICIENCY". Wow, I make that three shouted sole foci. Well done indeed. Cheers, Syms.Article: 100105
"Brian Davis" <brimdavis@aol.com> wrote: >Nico Coesel wrote: >> >> I can't find any references to these limitations in the datasheet. A >> DDR memory interface application note makes a short notice of some >> limitations on placement, but thats all there is. >> > > Try XAPP609 and Answer Record 17697 for a description of local clock >placement and routing restrictions (although I think XAPP609 only >describes V2, the structure is similar but not identical in S3). Thanks! I'll give it a thourough reading. -- Reply to nico@nctdevpuntnl (punt=.) Bedrijven en winkels vindt U op www.adresboekje.nlArticle: 100106
John Larkin wrote: > I've highlighted a number of howlers in Black Magic. Half his stuff is > right and half is silly. If you know enough to tell the difference, > you don't need the book. Don't keep us in suspense! Where are the funny parts in Howard Johnson's book? > His opinions on "return currents" are hilarious. Could you expand on this? As far as I can tell, his opinion on return currents is that you have to be as careful about the return current as you are for the, uh, forward current. Is this incorrect? (or is it an incorrect characterization of his opinion?) Alan NishiokaArticle: 100107
Hi! I unsuccessfully tried to find information about Direct Memory Access trough EDK. I would like to start by creating a simple custom OPB peripheral capable of writing Data to a memory accessible by a power PC on my Virtex 2P. Unfortunately, among other things, none of the signals provided trough user_logic.vhd (when DMA is enable by the IPIF) allows the peripheral to specify the address (where the peripheral could write data) leading me to think I got whole DMA thing wrong. However, I red in an other thread that IPIF is suppose to create a simple state machine accessing the bus when the DMA option is enable (I saw no state machine in user_logic.vhd) leading me to think that the issue might also be related to the EDK version I'm using (v8.1). Anybody knows where I could find pertinent information on the subject? ThanksArticle: 100108
Hi! I was investigating incremental synthesis to reduce synthesis time. Bad surprise was that incremental synthesis doesn't reduce the synthesis time at all. I have like 10 components and it takes 3 minutes to compile them without incremental synthesis. I changed the synthesis to incremental and made a little change in a very small component - then it took 4 minutes to compile!!! At some point in the synthesis report XST prints that all unchanged components are "up to date" but the rest of the report shows that all compilation and optimizations are done just like everything was compiled first time. I tried with Xilinx ISE versions 7.1 and 8.1 - both gave the same results... Has anyone managed to reduce the synthesis time signifficantly with XST incremantal synthesis? Or is there any other synthesis tools which are able to do this? Thanks LauriArticle: 100109
Thank you rbj But I am looking for a set of equations for a CASCADED structure of biquad filters. I.E. If the biquad 2nd order (chebychev) IIR filters form a cascaded higher order IIR filter structure, as to obtain a very sharp & immediate response at the cutoff frequency, how would the filter coeffcients of one filter be related to the other filters? I know from online applets that for a 4x2nd order filter, that all 4 filters are different. Can you advise me? -RogerArticle: 100110
I'll look into 6.1E. Is it free? I have been working with the Workspace and Objects windows. Not sure what Workspace means although I need to click on parts of this for certain signals to appear in the Objects list. The Workspace has names of my processes and sometimes line__numbers indicating an immediate assignment. Too bad I can't see what assignment is made on those lines without double clicking the line number and bringing up a source window. Perhpas I can assign labels to these somehow? "Hans" <hans64@ht-lab.com> wrote in message news:bDqXf.294$Rm1.182@newsfe6-gui.ntli.net... >I believe that is the sim tab in your workspace. If you change versions I >would go for 6.1e since 6.0 has some annoying GUI bugs (like not >remembering your window layout). > > Hans > www.ht-lab.com > > "Brad Smallridge" <bradsmallridge@dslextreme.com> wrote in message > news:122qto1lb19mrb8@corp.supernews.com... >> In ModelSim 5.7 I would drag or right click items from a pane called >> Structure and drag them or add them to the Wave. Where is this or what >> is the new procedure for 6.0? >> >> Brad Smallridge >> Ai Vision >> >> > >Article: 100111
1- why the best code are the random codes ? 2- what is the difference between LDPC codes and other linear codes ?Article: 100112
mughat wrote: > I have installed a XCF08P EEPROM in my fpga board. > The first time i wrote a program to it, it worked fine. But I can not erase > the EEPROM. > When i write to it now verify fails, I suspect i have to erase it before > writing a new program. > > Using: Impact 8.1.03i > JTAG programmer: JTAG 3 i belive (Parallel port), came with a digilent > starter board. > > Thanks > Andreas Beier I had a similar problem with IMPACT refusing to go past 51% when programming my XCF02S in the JTAG chain. A simple upgrade from 8.1 ISE to SP1 fixed it (strangely). I did recall it working perfectly with the ISE 7.Article: 100113
Roger Bourne wrote:
> Thank you rbj
> But I am looking for a set of equations for a CASCADED structure of
> biquad filters.
Roger, the information provided is for exactly that.
> I.E.
> If the biquad 2nd order (chebychev) IIR filters form a cascaded higher
> order IIR filter structure, as to obtain a very sharp & immediate
> response at the cutoff frequency, how would the filter coeffcients of
> one filter be related to the other filters? I know from online applets
> that for a 4x2nd order filter, that all 4 filters are different.
>
> Can you advise me?
OK, "4x2nd order" means N = 8.
perhaps i should have subscripted each pole pair:
p_n = -cos(theta)*sinh(phi) +/- j*sin(theta)*cosh(phi)
where phi = (1/N)*arcsinh(1/e)
{ pi/N*(n + 1/2) 0 <= n < N/2 N even
and theta = {
{ pi/N*(n) 0 <= n < N/2 N odd
note that for N odd, p_0 represents a single purely real and negative
number. (no conjugate.)
a pole at
p_n = -cos(theta)*sinh(phi) + j*sin(theta)*cosh(phi)
will have a counterpart reflected on the negative real axis on the
s-plane:
p_n* = -cos(theta)*sinh(phi) - j*sin(theta)*cosh(phi)
which is the complex conjugate. so for one 2nd order stage:
H(s) = 1 / (1 - s/p_n)(1 - s/p_n*)
= |p_n|^2 / (s - p_n)(s - p_n*)
= |p_n|^2 / (s^2 - 2*Re{p_n}*s + |p_n|^2)
this is for normalized s where the "significant frequency" (which is
normalized to w=1) is the bandedge of the passband where the ripple
ends and the gain just begins to dive toward 0.
you can easily work out what 2*Re{p_n} and |p_n|^2 is. that's your
first "assignment."
then use the BLT substitution explicitly provided in the audio EQ
cookbook (at the bottom of the page), and you'll get the biquad stage
in the z-plane.
that's advice. i ain't gonna design if for you, but i'm sure there is
someone listening in that would be happy to take your money to do it.
:-)
r b-j
Article: 100114This new device from Philips claims USB 480MBd (+PHY), 1MB FLASH, and an ARM7 core - for $7.99/10K http://www.standardics.philips.com/news/lpc2800/ So you could add HiSpeed USB, and use the spare flash for your config data ...(or use the MMC/SD interface). - and I'm sure the free ARM7 core would find a use.... :) -jgArticle: 100115
Anyone know if there is an alternative to Impact? that can erase and write mcs files?Article: 100116
I have tried different versions of impact 6.3 and 8.1 but not 7. I think I will try that. "Isaac Bosompem" <x86asm@gmail.com> wrote in message news:1144099399.978999.197900@g10g2000cwb.googlegroups.com... > > mughat wrote: >> I have installed a XCF08P EEPROM in my fpga board. >> The first time i wrote a program to it, it worked fine. But I can not >> erase >> the EEPROM. >> When i write to it now verify fails, I suspect i have to erase it before >> writing a new program. >> >> Using: Impact 8.1.03i >> JTAG programmer: JTAG 3 i belive (Parallel port), came with a digilent >> starter board. >> >> Thanks >> Andreas Beier > > I had a similar problem with IMPACT refusing to go past 51% when > programming my XCF02S in the JTAG chain. > > A simple upgrade from 8.1 ISE to SP1 fixed it (strangely). I did recall > it working perfectly with the ISE 7. >Article: 100117
John Williams' "Partial Reconfiguration on Xilinx Devices" email list is another resource: http://www.cs.uq.edu.au/~jwilliams/mblaze-uclinux/Mailing_List/ The archive is available here: http://www.itee.uq.edu.au/~listarch/partial-reconfig/ Brac wrote: > > I am trying to perform readback of the configuration for a Virtex-4. I > followed the steps in the configuration guide, but have had little > luck. The ICAP syncs up (output is 0xDF) and never enters ABORT when I > give it commands; however, when I disable the ICAP, switch to read > mode, and then re-enable the ICAP, the BUSY signal goes high, I do not > recieve any configuration data, and the ICAP output remains 0xDF. > > Has anyone experienced this problem and know a correction or had > success with readback and can inform me of their process? > > Thanks.Article: 100118
John Williams' "Partial Reconfiguration on Xilinx Devices" email list is another resource: http://www.cs.uq.edu.au/~jwilliams/mblaze-uclinux/Mailing_List/ The archive is available here: http://www.itee.uq.edu.au/~listarch/partial-reconfig/ Denaice wrote: > > Does someone have a working design using an ICAP in Virtex-4 ? We are > trying to send a difference-based partial bitstream to it by using > GPIOs but it doesn't seem to work. (The bitstream is ok, it works in > iMPACT by JTAG)Article: 100119
KJ, Now we're on the same page. Thanks for clearing up my misunderstanding. You're add on this thread is very valid. Take care, Rob "KJ" <kkjennings@sbcglobal.net> wrote in message news:ZOXXf.51244$2O6.29599@newssvr12.news.prodigy.com... > Rob, > >> Of course the FPGA doesn't have any knowledge of the bit stream; which is >> why you have to tell it where the data is in relation to the rising edge >> of the clock. In the case of a receiver, the MegaWizard function gives >> you the option of choosing 0, 45, 90, 135, 180, 225, 270, & 315 degrees. >> This is possible because the Wizard funcion uses a PLL to strip the data >> from the serialized stream. > > What you're talking about here has to do with what Altera calls 'DPA' . > What the data book has to say about DPA is the following (page 51 of 68) > http://www.altera.com/literature/hb/stx2/stx2_sii5v2_03.pdf: > > The DPA block aligns the incoming data to one of eight clock > phases to maximize the receiver's skew margin. The DPA circuit can be > bypassed on a channel-by-channel basis if it is not needed. Set the DPA > bypass statically in the Quartus II MegaWizard Plug-In or dynamically > by using the optional RX_DPLL_ENABLE port. > > DPA has to do with skewing the SERDES clock a bit (with one of 8 settings) > relative to a particular bit position in order to improve receiver skew > margin in order to correct for known skew that may exist in your system > but can be accounted for ahead of time (i.e. at design time when you're > picking one of those 8 settings). This is not the same thing that I was > talking about though. What I was talking about was along the lines of > what is on the next page in the section titled "Receiver Data Realignment > Circuit" where they say... > > The data realignment circuit aligns the word boundary of the incoming > data by inserting bit latencies into the serial stream. An optional > RX_CHANNEL_DATA_ALIGN port controls the bit insertion of each > receiver independently controlled from the internal logic. The data slips > one bit for every pulse on the RX_CHANNEL_DATA_ALIGN port. > > If you scroll a bit further to page 58 under the section titled > "Differential I/O Bit Position" is a nice description showing the bit > order of differential data that basically shows that the nominal rising > edge of the SERDES clock occurs roughly at the transition between when > data bits 2 and 1 are being transmitted. What they don't say is that you > have to use the above mentioned "Receiver Data Realignment" feature first > in order to get the bits in the proper position. > > I ran across this one first in simulation since the receiver was not > performing per the 'Figure 5-14' diagram where I suspected that it was > just Altera's simulation model that was in error. After opening a service > request and subsequent escalations since the problems wasn't resolved and > actually talking to someone at Altera who is very familiar with the SERDES > circuitry the end result was that the simulation model is correct the > diagrams they agreed are somewhat misleading and that the 'Receiver Data > Realignment' feature really does need to be used in order to guarantee > that your design is working correctly at every power up. > > Typically everything seems to power up in the same fashion but I've also > seen the actual hardware have to get 're-aligned' after having already > been aligned. > >> Most discrete SERDES type chips, like National's 90CR types, align the >> data with the rising edge of the PLL clock. In this case > > And this was my mistake when I thought this to be true with Stratix SERDES > also...thanks to Figure 5-14 > > KJ > >Article: 100120
Jim Granville wrote: > This new device from Philips claims USB 480MBd (+PHY), 1MB FLASH, and > [...] > - and I'm sure the free ARM7 core would find a use.... :) yeah ... compressing the bit stream to fit in the flash :)Article: 100121
"John_H" <johnhandwork@mail.com> wrote in message news:vIbYf.4674$kg.343@news02.roc.ny... > The newest version (3.0) of the Spartan3E complete data sheet came out a > week or two ago. I just wanted to give my Kudos to the Xilinx folks for > adding the DESIGN NOTE boxes complete with bright yellow attention symbol > to address the design issues that wouldn't be apparent to the casual data > sheet reader. > > I've noted before that designers would appreciate full attention to detail > in the data sheet as opposed to relying on the answer records or help line > calls. The notes don't appear to detract from the technical "confidence" > in the devices at all, at least for this engineer. It's fantastic to see > the full disclosure. > > Once the device tables specify "logic cells" as opposed to "equivalent > logic cells" I won't have anything to complain about! > > - John_H I second the kudos. I've seen up close the process of creating datasheets and humongous hardware and software reference manuals for a couple of large ASICs projects I've worked on. I've also designed the reference design/development kit boards that were sold to customers. The process was painful, and a real eye-opener for me. It is extremely difficult to do this stuff well, especially when you're fabless and work with a foundry, which means the detailed characteristics for I/O, PLLs, and other major blocks come from the foundry and/or from IP vendors. At the same time, being through this taught me to not assume that data sheets and app notes are always correct. Never forget that human beings write these things, and not always the super-savvy human beings that some may assume. RobArticle: 100122
On 3 Apr 2006 11:31:07 -0700, "Alan Nishioka" <alan@nishioka.com> wrote: >John Larkin wrote: >> I've highlighted a number of howlers in Black Magic. Half his stuff is >> right and half is silly. If you know enough to tell the difference, >> you don't need the book. > >Don't keep us in suspense! Where are the funny parts in Howard >Johnson's book? > It's at work. I'll post some tomorrow. > >> His opinions on "return currents" are hilarious. > >Could you expand on this? > >As far as I can tell, his opinion on return currents is that you have >to be as careful about the return current as you are for the, uh, >forward current. Is this incorrect? (or is it an incorrect >characterization of his opinion?) That is indeed his opinion, and it's goofy. He gives one example somewhere of a board with two ground planes, with a signal trace going from one surface layer to the opposite one through a via. He now suggests that the "return current" can't get from one ground plane to the other and gets confused or something. So he says to add *two* ground-ground vias, straddling the signal via, to let the return current find its way home. Has anybody actually, ever, done anything this silly? The power and ground planes of a multilayer board are massively coupled by the dielectric capacitance. There's typically thousands of times more plane-plane capacitance than the C of an entire signal trace. The whole mess is equipotential as far as any tiny trace-capacitance currents can influence things. The trace doesn't care if it's "referenced to" its "original" ground, to another ground, to a power pour, whatever. It's all just one big AC ground. HoJo also recently showed a picture of some spark gap corona that supposedly illustrated return currents, and Phil Hobbs pointed out (in s.e.d) that the sparks were in the wrong places. Phil and I were competing to lowball-bid to anybody willing to buy our copies of Black Magic. Phil's book, on the other hand, is astonishing. JohnArticle: 100123
Hi Joseph, Thanks again for your help. Alas, I'm still not having consistent results with my setup. Sometimes place-and-route will give me a system that passes the producer-consumer tests, and sometimes it won't. Tiny tweaks in the UCF file seem to have a large impact success or fail in the final result. (i.e. if I overconstrain a 100MHz clock to 9.9ns versus 10ns) Anyway, I'm curious about the solution you found for your system. You recommended running the BRAMDSOCMCLK input to the dsbram_if_cntlr at 1-4x the processor clock, right? Where in the data sheet for the controller does it say this is required? Maybe I've got an older version with EDK 7.1 because I can't find it. You're correct, though, that this clock signal is passed directly through the controller module and becomes the clock input to the BRAM (either BRAM_CLK_A or _B). As far as I can find, the whole point of setting the clock ratio in the C_DSCNTLVALUE parameter in the dscom module is to allow a *slower* BRAM clock than PowerPC clock, not a *faster* clock. On the VIIPro, you can go up to a ratio of 4:1. This is from the PowerPC block reference guide in the table that shows the ratio of CPMC405CLOCK : BRAMDSOCMCLK. I guess the problem with clocking the BRAM : PowerPC at a 1:1 ratio is that it's impossible for me to do. I run my PowerPC's at 300Mhz, and there's no way I can clock the rest of the controller logic and the 4 BRAMs at that speed. (The mapper tells me it's impossible even given perfect routing). I'm actually suprised you were able to route the BRAM successfully at 200MHz, as the best I can get is maybe 125 MHz given the rest of the contraints of the design. Good work! Thanks, Jeff > "Joseph" <joeylrios@gmail.com> wrote in message > news:1141335040.252179.271460@t39g2000cwt.googlegroups.com... >> Not sure if this is relevant to your problem anymore, but I found the >> problem with my design (briefly described above). There is only one >> signal that can be assigned in the dsbram_if_cntlr, that is >> BRAMDSOCMCLK. We were running our PPCs at 200MHz and our PLB bus at >> 100MHz using proc_clk_s and sys_clk_s, respectively. It was such a >> habit to assign all non-processor clks to sys_clk_s, that we did so for >> BRAMDSOCMCLK. After reading the data sheet for dsbram_if_cntlr, we >> found that the BRAMDSOCMCLK signal needed to be 1-4X the processor clk. >> The slow clock we gave to the BRAM caused our unpredictable behavior. >> If anything, I have learned to read those data sheets a little better. >> This may or may not be the same as your problem, Jeff, but thought I >> would follow up with the fix we came up with for our system. We are >> running a prodcuer/consumer type system as well and haven't had any >> problem with inconsistencies. The shared BRAM is a circular FIFO in >> our system. I could provide details on its operation if you still have >> trouble with your system. >> > >Article: 100124
My device is Spartan 3. The RAM blocks were used by one of the modules which beside RAM included some memory bank decoders. RAM blocks were instantiated by that module. I wanted to have bi-directional bus going from this module to another one. For now, I had to disable that and use separate busses as a quick fix, but I think in this situation bi-directional busses should be supported. What do you think? Note that the bus might not actually be visible from outside of fpga, so there are no ports involved. Alexey Lopich wrote: > On Tue, 28 Mar 2006 05:42:52 +0100, Isaac Bosompem <x86asm@gmail.com> > wrote: > > > I think it is doing this because you are not using it as an input. Also > > if you are working with FPGA's I think it would be a good idea to only > > use unidirectional ports in sub modules. While using bidirectional > > ports for top level devices (SDRAM, SRAM, Flash, etc.) > > > > -Isaac > > > > I think it depends on actual FPGA. On those ones that support 3-state > buffers in their > units (e.g. Virtex) it's fine, if you really need it of course. On the > other hand on something like > Spartan, where 3-states are not supported (except IOs), implementation of > 3states is based on logic chain > which is, probably, not the best way :) > > > -- > Alex
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