Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarApr2017

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search

Authors (J)

95486158j:
    6507: 97/05/30: Re: Cheap way to develop for FPGAs?
j:
    27511: 00/11/26: Fifo design problem
    27639: 00/11/30: Re: Orca 3t sram gsr question
    53490: 03/03/14: Re: RESET --- Synchronous Vs Asynchronous
J Adams:
    3916: 96/08/19: SAMS Needs Your Electronics URLs
J buytaert:
    90181: 05/10/06: ACTEL ProASIC plus mixed-voltage I/O macro's in Designer 6.2 ....?
    90190: 05/10/06: Re: ACTEL ProASIC plus mixed-voltage I/O macro's in Designer 6.2 ....?
J Kenens:
    40030: 02/02/25: Virtex-E,Spartan2 and cpld jtag chain problem
    40095: 02/02/27: Re: Virtex-E,Spartan2 and cpld jtag chain problem
J Klukan:
    10719: 98/06/12: Free Computer (Read--Easy, No money down)
J Mills:
    15923: 99/04/21: Asynchronous Logic in Altera 10K devices
j n:
    32203: 01/06/19: Re: Re: Flexlm license and windows 2000
J o h n _ E a t o n (at) hp . com (no spaces):
    80236: 05/03/02: Re: Need suggestion abt FFs without RST for pipelined datapath.
    99361: 06/03/23: Re: OpenSPARC released
    99375: 06/03/23: Re: OpenSPARC released
    99641: 06/03/27: Re: OpenSPARC released
    99811: 06/03/29: Re: OpenSPARC released
    99823: 06/03/29: Re: OpenSPARC released
    100096: 06/04/03: Re: OpenSPARC released
    105471: 06/07/24: Re: Hardware book like "Code Complete"?
J R:
    50464: 02/12/11: Urgent : Need help with VHDL modeling on Cypress's Warp 5.2
J Silverman:
    98926: 06/03/17: Support software for XC3042
    98958: 06/03/17: Re: Support software for XC3042
    98960: 06/03/17: Re: Support software for XC3042
    99042: 06/03/19: Re: Support software for XC3042
J Thomas:
    108084: 06/09/05: Re: Forth-CPU design
    108148: 06/09/06: Re: Forth-CPU design
    108161: 06/09/06: Re: Forth-CPU design
    108165: 06/09/06: Re: Forth-CPU design
j zhang:
    41559: 02/04/01: pricing and gate count info
J&P Lezcano:
    16195: 99/05/08: SE VENDE FINCA EN MADRID
J-Wing:
    59289: 03/08/13: Memory map in Altera NIOS
    59420: 03/08/18: determine clock cycles (wait states) in interface to user logic in NIOS.
    59435: 03/08/19: User logic to NIOS processor with bigger data width
    60198: 03/09/07: system simulation and verification methods (NIOS)
    60309: 03/09/10: simulating memory models in sopc builder
    63734: 03/12/02: increase NIOS processor clock speed on APEX20K200E device
    64366: 03/12/30: dynamic memory allocation NIOS
j.:
    150066: 10/12/09: Interfacing DS92LV1021 with FPGA serdes
    150079: 10/12/10: Re: Interfacing DS92LV1021 with FPGA serdes
J. A. Herrera Camacho:
    3782: 96/07/31: Multi-FPGA Partitioners?
J. Boss:
    22404: 00/05/08: Programming FPGA
    22460: 00/05/09: Re: Programming FPGA
    22617: 00/05/14: Bidirectional BUS!!!
J. Jansen:
    7657: 97/10/01: Re: vme vs compact pci
J. Khatib:
    8162: 97/11/22: FPAA Motorola's new tech.
    9185: 98/02/28: Dsp Fpga and vhdl project
    9521: 98/03/20: Dual port
    9577: 98/03/24: Best solution
    11201: 98/07/24: CPLD vs. FPGA
    12319: 98/10/08: FPGA core design
    14787: 99/02/17: Free circuit design
    15008: 99/03/03: Selt-Timed circuit
    15638: 99/04/05: Re: HELP NEEDED: FPGA and Neural Networks
    15738: 99/04/11: Re: Does any one want to talk about Dynamic Configuration?
    15772: 99/04/13: bitstream
    15788: 99/04/14: SUBSCRIBE
    16202: 99/05/10: Bitstream size
    16203: 99/05/10: Re: FPGA, PLD, EPLD, CPLD differences
    16338: 99/05/17: Dual Port mem
J. Mark Wolf:
    9057: 98/02/17: Trade device programmer for 8051 C compiler
    9087: 98/02/18: Will trade device programmer for 8051 C compiler
J. Mejia:
    7098: 97/07/31: Re: Quick prototyping? Best solution?
    7109: 97/08/01: Re: Where is Actel's www?
J. Michael Milner:
    53195: 03/03/05: Re: Issues in Outsourcing?
    65540: 04/02/01: Re: Differences between Xilinx ISE and Altera Quartus software
J. Reed Walker:
    36234: 01/11/02: JTAG problem
J. Scott Dickson:
    3618: 96/07/03: Re: FSM encoding in VHDL with MAX+plusII
    3671: 96/07/10: Re: FPGA capacity comparison
J. Scott Fuller:
    8222: 97/11/30: Re: what is metastability time of a flip_flop
j.bernspang:
    109739: 06/10/04: Re: logarithm look-up table
J.Curtis:
    47914: 02/10/07: String Matching Developments on FPGA's
<j.d.morrison@gmail.com>:
    123724: 07/09/03: Re: An FPGA startup is seeking testcase from potential customers
    123726: 07/09/03: Re: Die size, pitch size?
J.F. FOURCADIER:
    64477: 04/01/05: Altera CPLD - Illegal assignment-global clock
J.G.:
    52541: 03/02/12: FPGA for audio record and playback???
J.H.R. Schrader:
    28817: 01/01/25: Field Programmable Gate Array selection and task suitability
J.Ho:
    35196: 01/09/25: Virtex2 slice level instantiation in verilog question
    35207: 01/09/25: Re: Virtex2 slice level instantiation in verilog question
    40813: 02/03/15: [Virtex 2] DCM: "Factory_JF" option box in FPGA editor question
    41007: 02/03/19: Re: [Virtex 2] DCM: "Factory_JF" option box in FPGA editor question
    63860: 03/12/05: How to explicitly call out cell elements in Altera Stratix?
<j.kreyssig@fh-wolfenbuettel.de>:
    9792: 98/04/05: installation altera maxplus2 8.2
J.L. Mitchell:
    26099: 00/10/04: test
<j.m.granville@gmail.com>:
    153628: 12/04/06: Re: Digital Tachometer VHDL
    153746: 12/05/04: Re: FPGA and Package-on-Package
    153748: 12/05/05: Re: Smallest GPL UART
    153798: 12/05/23: Re: Smallest GPL UART
    153801: 12/05/23: Re: Logic Glitches in Spartan-3?
    153813: 12/05/24: Re: Logic Glitches in Spartan-3?
    153846: 12/06/04: Re: Questions about LCMXO2280-B-EVN and LCMXO2-1200ZE-B-EVN ev kits
    153906: 12/06/28: Re: Replacement for XC4005E
J.Mawer:
    4387: 96/10/23: Re: VHDL for Xilinx designs?
    5116: 97/01/24: Designing Xilinx with cadence
J.Niu:
    27261: 00/11/16: test
    27262: 00/11/16: Re: Basic question on PLD & FPGA
    27263: 00/11/16: can FPGA perform float point calculaton?
    27264: 00/11/16: Can FPGA perform float point calculation?
J.Oscar:
    59629: 03/08/25: Esquematic with XC2S100
J.P.Liao:
    15079: 99/03/05: Can multiple FPGA share same SPROM for configuration?
J.R.:
    19356: 99/12/15: Speed grade
    19528: 99/12/29: An online division unit with constant divisor
    19874: 00/01/15: EARN MONEY EASILY-READ THIS!!
    20562: 00/02/14: Is EDIF format adopted by all FPGA manufacturers???
    20732: 00/02/19: Re: BEHAVIOURAL VHDL
    20801: 00/02/23: Help!!!
    20811: 00/02/23: Re: Help!!!
    21517: 00/03/24: ERROR:NgdHelpers:312
    21802: 00/04/01: FPGA price vs Size
J.Ram:
    119473: 07/05/21: Timing not met but working on board
    119576: 07/05/22: Design running on board but timing are not met
    120662: 07/06/13: programming virtex2 FPGA
    120701: 07/06/13: Re: programming virtex2 FPGA
    136682: 08/11/30: simulation results is correct but synthesis result is not correct
    136701: 08/12/02: Re: simulation results is correct but synthesis result is not correct
    138093: 09/02/06: clock generation by divide and reset
J.Simmons:
    10683: 98/06/10: Re: XILINX Foundation - how to minimize project archive?
    10684: 98/06/10: Re: Atmel AT40K
    10685: 98/06/10: Re: Xilinx Foundation
J.W. Holloway:
    72807: 04/09/02: StateCad, IO vector question.
J.W. Krych:
    22711: 00/05/18: FPGA emultaion of a microprocessor
J.Walliker:
    1995: 95/09/29: Altera EPX880QC132-10 Availability?
    3083: 96/03/28: Re: Low-power FPGA or EPLD
    3329: 96/05/14: Re: Looking for free FPGA softw./Xilinx
J.Wild:
    124058: 07/09/11: application about hardeware attributes
    125091: 07/10/16: Re: application about hardeware attributes
j93005:
    103506: 06/06/05: How to use usb on Alter EPXA4??
J?rgen:
    66584: 04/02/23: Usage of Xilinx Library elements in ModelSim simulation
    66963: 04/03/02: Re: Usage of Xilinx Library elements in ModelSim simulation
    67648: 04/03/16: Modelsim & ISE Foundation: Hierarchical update
    69344: 04/05/07: Error while simulation with XILINX DCM
    69386: 04/05/10: Re: Error while simulation with XILINX DCM
    69389: 04/05/10: Re: Error while simulation with XILINX DCM
JA:
    12198: 98/10/04: Re: Which FPGA tool is better
    16786: 99/06/08: Re: Altera EPC1 PROM + Data IO ChipWriter
Jaakko Varteva:
    88606: 05/08/23: Re: Good SystemC tutorials or books?
Jaan Sirp:
    28233: 01/01/03: Re: FFs in IOBs in XC4000
    28258: 01/01/04: Re: Serial interface (urgent)
    28301: 01/01/05: Re: Spartan-II DLL Usage
    28359: 01/01/10: Re: grey code counters
    28389: 01/01/11: Re: grey code counters
    28390: 01/01/11: Re: grey code counters
    28744: 01/01/23: Re: VirtexII and high speed counter
    28967: 01/01/31: Re: XILINX FPGA programming through JTAG
    29149: 01/02/08: Re: JTAG debugging?
    29441: 01/02/21: Re: Infering DPRAM with both outputs
    29713: 01/03/06: Re: Suggestions for I/O card
    29717: 01/03/06: Re: Suggestions for I/O card
    29836: 01/03/13: Re: sample code for JTAG configuration of Virtex, Spartan II?
    29889: 01/03/15: Re: Low volume users (was: Re: VirtexE LVPECL I/O Ports? experience?)
    29890: 01/03/15: Re: Programming CPLD and FPGA on XESS board for Ethernet.
    31170: 01/05/14: Bug in Xilinx Hardware Debugger?
    31175: 01/05/14: Re: Bug in Xilinx Hardware Debugger?
    68209: 04/03/30: Virtex2 partial reconfiguration
    68216: 04/03/30: Re: maybe a stupid question
Jaap H. Mol:
    14185: 99/01/18: Re: Programmng ALTERA EPROMS
    18775: 99/11/14: Altera NOT-gate push back
    23963: 00/07/18: Re: Quartus
    25369: 00/09/08: IEEE 754 Floating point VHDL functions / MATH package
    38949: 02/01/28: QuartusII Timing Analysis
Jaap Mol:
    5740: 97/03/11: Re: ACTEL RAM BASED FPGAs
    6026: 97/04/06: Re: clock edge specification for Synopsys synthesis
    7321: 97/08/26: Re: MaxPlusII from Altera.
    52122: 03/02/01: Re: How to do on-the-fly reconfiguration of a Flex10ke using an EPC16?
    55822: 03/05/20: Ethernet MAC IP-core in Nios design
    56694: 03/06/11: Re: Virtex 2 evaluation board
    56695: 03/06/11: Re: about the uclinux in Altera Nios
    56698: 03/06/11: Re: Constant on Multiplier Synthesis problem with XST for VirteX 2/E
    56701: 03/06/11: Re: Which Init Technique for BlockRAMs and Modelsim?
    56726: 03/06/12: Re: Post P&R Verilog/VHDL netlist
Jabari Zakiya:
    66393: 04/02/18: Re: Dual-stack (Forth) processors
    66433: 04/02/19: Re: Dual-stack (Forth) processors
Jabberwork:
    18033: 99/09/24: Re: Modelsim,synplify,Leonardo,MAX+plus, you name it!!
Jac Athow:
    75823: 04/11/16: Extending chipscope capture memory by using external async SRAM
Jacek Mocki:
    68931: 04/04/22: Re: Document State Machines?
    68968: 04/04/23: transport applications
    69141: 04/04/28: Re: transport applications
    69142: 04/04/28: Re: transport applications
Jacek Wawrzaszek:
    70923: 04/07/01: Re: Compact FPGA Board?
    103634: 06/06/07: Re: API on Virtex 4 FPGA or the email of Delon Levi wanted
Jack:
    32774: 01/07/08: Offer: Extra Xilinx PCI development kit (HOT 2)
    35799: 01/10/18: Career advice in fpga/asic design
    47314: 02/09/23: Re: Altera Cyclone low-cost FPGA chips?
    47423: 02/09/25: Re: Altera Cyclone low-cost FPGA chips?
    49707: 02/11/19: how to use carry chain in Virtexe
    49761: 02/11/20: Re: how to use carry chain in Virtexe
    57340: 03/06/27: projects for beginners
    64701: 04/01/11: Altera NIOS cyclone edition development board problem
    64839: 04/01/14: Re: Altera NIOS cyclone edition development board problem
    67983: 04/03/23: study verilog or vhdl?
    69929: 04/05/25: VPR & Reconfigurable system ?
    75989: 04/11/21: Re: FPGA development board
    78653: 05/02/04: memory size of C code
    78704: 05/02/06: warning messages,NgdBuild:454,DesignRules:331
    78772: 05/02/07: Re: warning messages,NgdBuild:454,DesignRules:331
    78832: 05/02/08: BRAM utilization - how to calculate
    79308: 05/02/17: thread programming support in EDK?
    79375: 05/02/17: microblaze with opb, brams?
    79377: 05/02/17: Re: thread programming support in EDK?
    79455: 05/02/19: distributed shared memory in fpga?
    84772: 05/05/26: V2pro configuration problem - PROM SIZE
    87608: 05/07/26: how to measure number of cycles in ISE6.3
    91135: 05/10/30: array type implementable in ISE?
    132769: 08/06/06: Re: ANNOUNCE:-- TimingAnalyzer Free Version -- Draw timing diagrams
    144455: 09/12/08: FPGA kit
jack:
    28518: 01/01/16: help
    83807: 05/05/06: how can i join the comp.arch.fpga group
    83809: 05/05/06: how can i add my math library libm.a in my project
    150808: 11/02/14: Xilinx USB programming cable.
    150852: 11/02/16: Re: Xilinx USB programming cable.
Jack Crenshaw:
    31922: 01/06/08: Re: My80-- i8080A instruction compatible processor core
Jack D. Ma:
    22000: 00/04/11: Is there any DSP and FPGA based board suitable to motor drive control?
Jack Daly:
    102278: 06/05/13: Trouble understanding Synplicity timing report
    102281: 06/05/13: Re: Trouble understanding Synplicity timing report
Jack Falk:
    85858: 05/06/17: Atmel tools: any way to edit intra-cell connections in IDS/Figaro?
    87153: 05/07/18: chips with partial reconfig other than atmel & xilinx?
    87154: 05/07/18: "Tbufs don't exist"
Jack Greenbaum:
    504: 94/12/12: Re: L-Edit and Benchmarks
    1736: 95/08/21: Re: Design protection
    2299: 95/11/17: Re: [Q] FPGA Software for Linux
    2497: 95/12/18: Re: Floor Planning for Xilinx
    7709: 97/10/06: Re: FPGA multiprocessors
    16904: 99/06/16: Re: Evolutionary computation
Jack Huang:
    8015: 97/11/07: Where can I find documents talking about constraining FPGA?
Jack Klein:
    77186: 04/12/28: Re: Primers for Handel-C
    94194: 06/01/06: Re: Programming Xilinx PowerPC
    105834: 06/08/01: Re: Where are Huffman encoding applications?
    111124: 06/10/29: Re: Hardware mapping of algorithms
    132886: 08/06/09: Re: how to prevent timer code firmware running on Microblaze from being optimised
    139784: 09/04/13: Re: Find FPGA updates On Twitter
Jack Lai:
    8836: 98/01/30: Re: xilinx M1 protection
    9038: 98/02/16: Re: the problem about counter.
    9146: 98/02/24: Re: Correlation implementation...
    24379: 00/08/05: Abel from dataIO?
jack lalo:
    79488: 05/02/19: Help using the ML310 developement board
    79654: 05/02/22: Is there any compatibility difference between The parallel JTAG PC4 and JTAG III??
jack lee:
    114997: 07/01/29: virtex-II DCM phase shift problems
    120145: 07/06/01: How to guarantee the same relative placement and routing in ISE?
Jack Leong:
    149283: 10/10/13: Re: i don't have any idea to select write mode at ASMI_PARALLEL
    153481: 12/03/08: Re: CPU Design in Xilinx Spartan 3E
    153482: 12/03/08: Re: Error JTAG chain problem detected
    153483: 12/03/08: Re: configuring an Altera Cyclone 3
    153484: 12/03/08: Re: Using both Verilog and VHDL for Xilinx simulation
Jack Moderatz:
    67252: 04/03/09: bit stream file examples ?
    67316: 04/03/10: FPGA benchmark....and ..... some questions
Jack Mott:
    1241: 95/05/21: Re: affordable fpga design tools?
Jack Nimble:
    33549: 01/07/30: Help: Simple counter example in WebPack schamatic capture
    41706: 02/04/05: Help: Design a crystal oscillator in a Xilinx XCR3256XL
Jack Ogawa:
    766: 95/02/25: Re: Looking for Tech Info
    866: 95/03/16: Re: FPGA multi-chip modules ?
    3621: 96/07/04: RE: Sanity check for 100K gate DSP FPGA project
    3656: 96/07/09: RE: Sanity check for 100K gate DSP FPGA project
Jack Sandell:
    2361: 95/11/23: Re: Industry Trends
Jack Seredyniecki:
    59265: 03/08/13: Re: Can i trace client activity?
Jack Smith:
    57421: 03/06/30: advice
Jack Stone:
    58524: 03/07/25: Relative placement constraints in VHDL for Virtex multipliers
    59830: 03/08/28: Re: Moving Sum
    59935: 03/09/01: Re: Moving Sum
Jack Tai:
    34578: 01/08/29: Model sim vhdl simulation crash
    35845: 01/10/19: memory dump for Xilinx block ram
    37507: 01/12/12: Re: xilinx ise 4
Jack Zhu:
    76173: 04/11/27: Q:iMPACK:583 - '1' error
Jack Zkcmbcyk:
    108482: 06/09/11: Help for Altera Nios II Cyclone EP1C12 evaluation kit!
    108519: 06/09/12: Re: Help for Altera Nios II Cyclone EP1C12 evaluation kit!
    109112: 06/09/21: Verification errors using Xilinx Spartan 3E board
jack.gassett:
    140369: 09/05/11: Re: Getting started with FPGA
    140983: 09/06/01: Open Source FPGA circuit design.
    141001: 09/06/02: Re: Open Source FPGA circuit design.
    141520: 09/06/26: Using Xilinx tools with ft2232 based programming cable.
    144253: 09/11/23: Goal to make $30-40 Open Source Logic Analyzer with Spartan 3E.
jack.harvard@googlemail.com:
    128232: 08/01/18: Re: How is FIFO implemented in FPGA and ASIC?
    128238: 08/01/18: Re: How is FIFO implemented in FPGA and ASIC?
    128433: 08/01/25: Thoughts about memory controller problems
    129398: 08/02/22: Re: Interview questions
    129399: 08/02/22: Re: Interview questions
    133072: 08/06/17: Xilinx Spartan FPGA BlockRAM in Simulation
    133683: 08/07/09: Question: What are the tricks mentioned on Viterbi Decoder Wikipedia
    134817: 08/09/02: Inferring dual-port RAM in Spartan-3A Starter Kit FPGA?
    134818: 08/09/02: Re: why does inferred RAM cause synthesis times to explode?
    134820: 08/09/02: Re: Inferring dual-port RAM in Spartan-3A Starter Kit FPGA?
    134836: 08/09/03: Re: Inferring dual-port RAM in Spartan-3A Starter Kit FPGA?
    134841: 08/09/03: Re: Inferring dual-port RAM in Spartan-3A Starter Kit FPGA?
    135287: 08/09/24: decimal to ieee 754 single precision floating point
    135439: 08/10/02: floating point round off errors
    135451: 08/10/02: Re: floating point round off errors
    135475: 08/10/03: synopsys designware components on xilinx fpga
    139570: 09/04/03: Xilinx Spartan3A XC3S700A die area?
<jack.pett.son@gmail.com>:
    154334: 12/10/03: fft in fpga using polar form
    154348: 12/10/11: fixed point fft butterfly stage testing help
Jack// ani:
    75339: 04/11/02: FPGA/CPLD Basics
    75363: 04/11/03: Re: FPGA/CPLD Basics
    75386: 04/11/03: Re: FPGA/CPLD Basics
    75952: 04/11/20: FPGA development board
    75991: 04/11/22: Re: FPGA development board
    76031: 04/11/22: Re: FPGA development board
    76156: 04/11/26: Re: FPGA development board
JackBonn:
    149104: 10/10/01: Microblaze, Xilkernel, and g++
JackC:
    48239: 02/10/14: Power Cnsumption Benchmark
    62171: 03/10/21: Structure of the Embedded Multiplier?
Jacke:
    41030: 02/03/19: Fixed Point Library
    41190: 02/03/22: SystemC compiler
<jackhab@gmail.com>:
    104942: 06/07/10: PROM files: build .bin for daisy chain on the fly
    104960: 06/07/10: Re: PROM files: build .bin for daisy chain on the fly
    105275: 06/07/19: Virtex-4 PowerPC and Trace32 ICD - start up help wanted
Jackie Meyer:
    4210: 96/09/27: CFP: Design and Test
    4236: 96/10/03: CFP: Memory Technology Design and Testing
    4557: 96/11/13: CFP Memory Workshop
    4728: 96/12/06: Re: ASICs Vs. FPGA in Safety Critical Apps.
    4929: 97/01/01: CFP Memory Technology Workshop
    5000: 97/01/10: CFP Memory Technology Workshop
    5389: 97/02/12: CFP Design and Test special issue
    6038: 97/04/07: CFP: Design and Test, FPGA special issue
    6174: 97/04/22: Memory workshop, San Jose, August 11-12
    6181: 97/04/23: CFP Design and Test (FPGA issue)
    6400: 97/05/21: memory workshop ram/rom/pld/fpga
    6577: 97/06/03: Memory workshop, San Jose
    7074: 97/07/29: Memory workshop
    8965: 98/02/10: IEEE memory workshop
    9093: 98/02/19: [CFP] San Jose workshop on MEMORY
    10561: 98/05/29: ieee Memory workshop
    10664: 98/06/09: papers wanted on DRAM
    10983: 98/07/08: papers sought, DRAM
    11262: 98/07/31: register for IEEE memory workshop
    11482: 98/08/19: memory workshop starts Monday
jackm:
    157736: 15/02/25: Program Xilinx with Altera JTAG Programmer?
    157739: 15/02/25: Re: Program Xilinx with Altera JTAG Programmer?
    157751: 15/03/01: Re: Program Xilinx with Altera JTAG Programmer?
jacko:
    106532: 06/08/14: Re: Crystal input for FPGA
    106587: 06/08/15: Re: Maximum Current Draw of FPGA
    106588: 06/08/15: Re: Maximum Current Draw of FPGA
    106833: 06/08/20: Re: CPU design
    106839: 06/08/20: Re: CPU design
    106876: 06/08/21: Re: CPU design
    106880: 06/08/21: CPU design
    106881: 06/08/21: hex format 16 bit?
    106905: 06/08/22: Re: CPU design
    106935: 06/08/22: hex and AHDL?
    106936: 06/08/22: Re: Xilinx Virtual Platform
    107047: 06/08/23: Re: CPU design
    107134: 06/08/24: Re: JOP as SOPC component
    107176: 06/08/25: Re: Why No Process Shrink On Prior FPGA Devices ?
    107759: 06/08/31: Re: CPU design
    108003: 06/09/03: Re: Forth-CPU design
    108076: 06/09/04: Re: Forth-CPU design
    108080: 06/09/05: Re: Forth-CPU design
    108085: 06/09/05: Re: Forth-CPU design
    108087: 06/09/05: Re: Forth-CPU design
    108112: 06/09/05: LUT Blocks?
    108351: 06/09/08: Re: Why No Process Shrink On Prior FPGA Devices ?
    108360: 06/09/08: Re: ddr with multiple users
    109432: 06/09/26: Re: PUBLISHABLE PAPER RELATED TO FPGA!
    109439: 06/09/26: Re: PUBLISHABLE PAPER RELATED TO FPGA!
    109440: 06/09/26: Re: uBlaze prototype PCB UART issues
    109441: 06/09/26: BSD Indi FPGA processor seeks new webserver
    109444: 06/09/26: Re: PERISHABLE PAPER RELATED TO FPGA!
    109660: 06/10/02: Modules for IO on BSD indi processor ideas?
    109670: 06/10/02: Re: Modules for IO on BSD indi processor ideas?
    109681: 06/10/03: Re: Modules for IO on BSD indi processor ideas?
    109699: 06/10/03: Re: Modules for IO on BSD indi processor ideas?
    109792: 06/10/05: BSD indi processor IP compiles at 283 LEs
    109800: 06/10/05: Re: Just a matter of time
    109802: 06/10/05: Re: SMPTE310 interface
    109819: 06/10/05: Re: BSD indi processor IP compiles at 386 LEs (MAX II)
    109827: 06/10/05: Re: BSD indi processor IP compiles at ($13.30)
    109829: 06/10/05: Re: BSD indi processor IP compiles at ($13.30)
    109878: 06/10/06: Re: BSD indi processor IP compiles at ($13.30)
    109884: 06/10/06: Re: BSD indi processor IP compiles at 283 LEs
    109896: 06/10/07: Re: Just a matter of time
    109898: 06/10/07: Re: BSD indi processor IP compiles at 283 LEs
    109946: 06/10/08: Re: Antifuse, lower cost?
    110041: 06/10/09: Re: BSD indi processor IP compiles at ($13.30)
    110059: 06/10/10: Re: BSD indi CPLD processor IP 60MHz 12MIPS 330LEs
    110083: 06/10/10: Re: BSD indi CPLD processor IP 60MHz 12MIPS 330LEs
    110248: 06/10/12: Re: New Electronic Design Web site
    110297: 06/10/13: Re: New Electronic Design Web site
    110435: 06/10/15: echo $LM_LICENCE_FILE not working
    110443: 06/10/15: Re: echo $LM_LICENCE_FILE not working
    110478: 06/10/16: Re: echo $LM_LICENCE_FILE not working
    110592: 06/10/18: Re: BSD indi CPLD processor IP 60MHz 12MIPS 330LEs
    110622: 06/10/18: Re: Cheapest FPGA board to study VHDL on
    111259: 06/10/31: Re: Question about bandwidth of scope?
    112585: 06/11/25: Dev Kit Shipping Costs
    113833: 06/12/23: max II dev kit pin grid
    114297: 07/01/10: Santa Clara Connector and LVTTL etc
    114299: 07/01/10: altera MAX II dev kit LCD mountings??
    121685: 07/07/11: Re: Anyone really use those opensource CPUs (OR1K, Lattice Mico32, Leon)?
    134361: 08/08/07: Nibz processor @ 472 LEs (16 bit generic specified)
    134454: 08/08/11: Re: Altera question - MAX3000 vs MAX7000
    134494: 08/08/13: Re: Altera question - MAX3000 vs MAX7000
    136209: 08/11/05: nibz processor new version
    138799: 09/03/11: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
    140126: 09/04/29: Quartus Timing
    140667: 09/05/21: Nibz VHDL Processor (Version G-spot)
    140708: 09/05/22: Re: Nibz VHDL Processor (Version G-spot)
    140729: 09/05/22: 512*256 resolution on VGA (generic code available)
    140849: 09/05/27: Nibz (Version P)
    145765: 10/02/22: Re: Looking for Ultimate RISC/MISC that runs LINUX Website
    145934: 10/02/28: Re: Frustration with Vendors!
    145994: 10/03/02: Re: Tabula. (FPGA start up)
    146422: 10/03/17: Re: Awkward Arithmetic
    146423: 10/03/17: Re: Nested interrupts in Nios system and hung system
    146526: 10/03/22: Re: Awkward Arithmetic
    146807: 10/03/29: Re: Which is the most beautiful and memorable hardware structure in a
    147084: 10/04/13: Re: Nios Memory Protection Unit
    148370: 10/07/15: Re: 1-wire question
    151461: 11/04/11: Altera web 10.1sp1
    151515: 11/04/16: NibzX7 processor
    151524: 11/04/17: Re: NibzX7 processor
    151528: 11/04/17: Re: NibzX7 processor
    151548: 11/04/18: Re: NibzX7 processor
    151564: 11/04/19: Re: NibzX7 processor
    151568: 11/04/20: Re: NibzX7 processor
    151571: 11/04/20: Re: NibzX7 processor
    151574: 11/04/20: Re: NibzX7 processor
    151579: 11/04/21: Re: NibzX7 processor
Jacko:
    106408: 06/08/12: dynamic fpga via bytecode sequence?
    106409: 06/08/12: Re: Embedded clocks
    138781: 09/03/10: Re: Integer arithmetic in HDLs
    138804: 09/03/11: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
    138816: 09/03/11: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
    138817: 09/03/11: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
    138836: 09/03/12: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
    138837: 09/03/12: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
    138842: 09/03/12: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
    138847: 09/03/12: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
    138853: 09/03/12: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
    138874: 09/03/12: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
    138883: 09/03/13: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
    138884: 09/03/13: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
    138894: 09/03/13: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
    138912: 09/03/14: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
    138915: 09/03/14: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
    138925: 09/03/14: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
    138969: 09/03/17: Re: Zero operand CPUs
    138984: 09/03/17: Re: Zero operand CPUs
    138986: 09/03/17: Re: Zero operand CPUs
    139001: 09/03/18: Re: Zero operand CPUs
    139009: 09/03/18: Re: Zero operand CPUs
    139022: 09/03/18: Re: Zero operand CPUs
    139057: 09/03/19: Re: Zero operand CPUs
    139063: 09/03/19: Re: Zero operand CPUs
    139067: 09/03/19: Re: Zero operand CPUs
    139074: 09/03/19: Re: Zero operand CPUs
    139101: 09/03/20: Re: Zero operand CPUs
    139106: 09/03/20: Re: Re Zero operand CPUs
    139111: 09/03/20: Re: Re Zero operand CPUs
    139128: 09/03/21: Re: Re Zero operand CPUs
    139159: 09/03/22: Re: Re Zero operand CPUs
    139179: 09/03/22: Re: Re Zero operand CPUs
    139323: 09/03/26: Re: some nibz decoding ?
    140135: 09/04/29: Re: Quartus Timing
    140158: 09/04/30: Re: Quartus Timing
    140342: 09/05/09: Re: Dual Port RAM Inference
    140348: 09/05/10: Re: implementing arbitrary combinational functions using block rams
    140466: 09/05/14: Re: cheapest FPGA?
    140684: 09/05/21: Re: Nibz VHDL Processor (Version G-spot)
    140688: 09/05/21: Re: Nibz VHDL Processor (Version G-spot)
    140689: 09/05/21: Re: Nibz VHDL Processor (Version G-spot)
    140726: 09/05/22: Re: Nibz VHDL Processor (Version G-spot)
    140863: 09/05/27: Re: Nibz (Version P)
    140865: 09/05/27: Re: Nibz (Version P)
    140899: 09/05/28: Re: When is it to generate transparent latch or usual combinational
    141173: 09/06/10: Re: async. SRAM control signal generation
<Jackolantern25@gmail.com>:
    90301: 05/10/10: 16550 VHDL code
<jacks343@msn.com>:
    11668: 98/08/29: Here is my page of DIRTY PICTURES
Jackson Pang:
    71356: 04/07/15: Xilinx EDK PCI
    71362: 04/07/15: RE: Xilinx Virtex-II Configuration in Slave Serial
    71394: 04/07/16: Re: Xilinx EDK PCI
    71652: 04/07/26: Re: Xilinx EDK PCI
    71710: 04/07/28: Re: Xilinx EDK PCI
    71711: 04/07/28: Re: Xilinx EDK PCI
    71717: 04/07/28: Re: XUP Support
jacky:
    120261: 07/06/04: modelsim
    120292: 07/06/05: Re: modelsim
Jacky Renaux:
    36659: 01/11/14: Re: interleaver delay question
    40665: 02/03/12: Re: 32-taps FIR !
    40971: 02/03/19: Re: simple Free FPGA tool
    42467: 02/04/24: Re: INIT constrain
    42545: 02/04/26: Re: Changing ROM contents
    43566: 02/05/24: Re: FPGA and VHDL: question about RAM initialization
    43567: 02/05/24: Re: FPGA and VHDL: question about RAM initialization
    43800: 02/06/03: Re: Pipelining
    44422: 02/06/19: barrel shifter
    44465: 02/06/20: Re: barrel shifter
    48280: 02/10/15: Re: AHDL Command Reference?
    50823: 02/12/20: Re: 16-bit LFSR
    52601: 03/02/15: end-around-carry
    52810: 03/02/23: Re: end-around-carry
jacky Renaux:
    37338: 01/12/07: Re: xilinx ise 4.1i
    38107: 02/01/05: RNS
    65089: 04/01/20: Re: Which version of ISE Webpack has FPGA Editor on it?
Jaco Naude:
    121665: 07/07/11: Re: XilinxSystemGenerator and Simulink
    121684: 07/07/11: Re: MiG : Memory Interface (DDR SDRAM) as an ISE schematic symbol
    121686: 07/07/11: Re: MiG : Memory Interface (DDR SDRAM) as an ISE schematic symbol
    121727: 07/07/12: Re: MiG : Memory Interface (DDR SDRAM) as an ISE schematic symbol
    141057: 09/06/04: Xilinx FIR Compiler gives zero only output in hardware
    141093: 09/06/04: Re: How to generate clocks of higher frequency?
    141094: 09/06/04: Re: Xilinx FIR Compiler gives zero only output in hardware
    153477: 12/03/07: Virtex 6 System Monitor sensor readings in ChipScope gives weird values
    154179: 12/08/29: Cross-vendor firmware design management environment
jacob:
Jacob =?iso-8859-1?q?S=F8rensen?=:
    65518: 04/01/31: Altera DSP builder problem with delay and Integrator
    65627: 04/02/03: Re: Altera DSP builder problem with delay and Integrator
    65677: 04/02/04: Re: Altera DSP builder problem with delay and Integrator
Jacob Bower:
    76407: 04/12/01: EDIF -> Map & Place -> EDIF ?
    76418: 04/12/01: Re: EDIF -> Map & Place -> EDIF ?
    76437: 04/12/02: Re: EDIF -> Map & Place -> EDIF ?
    76455: 04/12/02: Re: EDIF -> Map & Place -> EDIF ?
    76456: 04/12/02: Re: EDIF -> Map & Place -> EDIF ?
    76469: 04/12/03: Re: EDIF -> Map & Place -> EDIF ?
    76482: 04/12/03: Re: EDIF -> Map & Place -> EDIF ?
    76583: 04/12/06: FPGA as host for a USB peripheral
    76613: 04/12/07: Re: FPGA as host for a USB peripheral
    78517: 05/02/02: Modifying a post PAR xilinx design
    78518: 05/02/02: Re: Modifying a post PAR xilinx design (solved)
Jacob Eluz:
    16095: 99/05/03: Virtex
Jacob Schaffner:
    129556: 08/02/27: Re: Xilinx's microblaze hangs when a timer interrupt occurs after a
Jacob Sparre Andersen:
    87417: 05/07/23: Re: Best Practices to Manage Complexity in Hardward/Software Design?
Jacob W Janovetz:
    6677: 97/06/12: Power consumption (Xilinx FPGA) questions
    6713: 97/06/18: Re: Help: Interfacing a Xilinx 4k to a microprocessor
    6766: 97/06/25: Re: FPGA prototype board
    7818: 97/10/18: Q: Clocking for address decode/chip select.
    7862: 97/10/24: Xilinx 4000 on an ISA bus...
    7992: 97/11/05: Re: Digital reverberator on FPGA
    8007: 97/11/06: Re: I'm interested in FPGAs. How do I start ?
    8082: 97/11/16: Re: I need Help
    8224: 97/12/01: Xilinx .bit file format.
    9186: 98/02/28: Re: Xilinx Info.
    9147: 98/02/25: Leonardo/VHDL and pullups in FPGAs.
    9187: 98/02/28: Re: The case for Linux and EDA
    9218: 98/03/03: Debugging question.
    9233: 98/03/03: Re: Debugging question.
    9306: 98/03/06: Leonardo/Xilinx BUFGLS question
    9307: 98/03/06: Re: Leonardo/Xilinx BUFGLS question
    9422: 98/03/12: Re: SOS!! Big Urgent Problem
    9498: 98/03/19: Re: Cypress ISR
    9764: 98/04/03: Xilinx routing optimization?
    9799: 98/04/06: Re: Xilinx routing optimization?
    9820: 98/04/07: Re: Xilinx routing optimization?
    9909: 98/04/13: Re: Xilinx routing optimization?
    9950: 98/04/16: Xilinx RPMs for DSP (16-tap 8-bit FIR)
    10100: 98/04/27: Re: FPGA pin assignment for I/O
    10200: 98/05/03: Re: Xilinx Foundation and Linux
    11289: 98/08/02: Re: how much ? prices of Xilinx chips
    11301: 98/08/03: Re: [****] VHDL Compile Error ( +, & Operator )
    13065: 98/11/14: Xilinx COREgen and Leonardo troubles...
    13107: 98/11/16: Re: Xilinx COREgen and Leonardo troubles...
    13276: 98/11/23: Xilinx XL vs XLA.
<jacob.bower@gmail.com>:
    87500: 05/07/25: Re: verilog to blif(lut)
    99191: 06/03/21: Ignoring hierachy while flagging false with with Xilinx flow.
    104486: 06/06/28: Synplify prepending Z's to top level signal names in Verilog
    104500: 06/06/28: Re: Synplify prepending Z's to top level signal names in Verilog
jacobo:
    69633: 04/05/16: Please, I need help with a mpeg layer 1 decoder in vhdl
    69644: 04/05/17: Re: Please, I need help with a mpeg layer 1 decoder in vhdl
jacobusn@xilinx.com:
    121808: 07/07/13: Re: MiG : Memory Interface (DDR SDRAM) as an ISE schematic symbol
    122237: 07/07/24: Re: DDR2 w/ MIG on Xilinx ML501 Board
    122607: 07/08/01: Re: Xilinx Webpack 9.2 and Windows 2000 Pro?
    122689: 07/08/03: Re: Spartan 3E starter kit DDR SDRAM
    122691: 07/08/03: Re: Spartan 3E starter kit DDR SDRAM
    122717: 07/08/04: Re: SDR SDRAM controller for Xilinx Spartan-3E
    122878: 07/08/09: Re: Xilinx Webpack 9.1: How do I export a netlist to another project?
    122977: 07/08/13: Re: Xilinx 13th August opportunity
    124300: 07/09/18: Re: Unexplained behavior with DDR2 controller on Xilinx V5
    124999: 07/10/15: Re: MIG for Linux?
    126595: 07/11/28: Re: DDR2 controler
Jacqueline Linich:
    29628: 01/03/02: San Francisco bay Hardware engineers
Jacques athow:
    55952: 03/05/24: Has anyone tried Internet Design Team.
    56304: 03/06/02: Re: HDLmaker update available
    58308: 03/07/19: XILINX frequency meter from XCELL design question.
    58329: 03/07/20: Re: XILINX frequency meter from XCELL design question.
    58694: 03/07/30: DDS question. How to generate a square from a sine wave?
    58711: 03/07/31: Re: DDS question. How to generate a square from a sine wave?
    59577: 03/08/22: Re: Question about slew rate for SpartanII using ISE5.1
    64059: 03/12/15: FLEX 10K50E, which software support it?
    65470: 04/01/29: One bit Virtex BRAM.
    65500: 04/01/30: Re: One bit Virtex BRAM.
    67151: 04/03/06: Can anyone advise me on how to reduce the compilation time for our design...
    67231: 04/03/08: Re: Can anyone advise me on how to reduce the compilation time for our design...
    67629: 04/03/15: PACE 6.2 pin assignment before design HOW TO??
    68767: 04/04/16: Huh, anybody wants to play some NES???
    68771: 04/04/17: Re: Huh, anybody wants to play some NES???
    68835: 04/04/19: Re: Huh, anybody wants to play some NES???
    68841: 04/04/20: Re: Huh, anybody wants to play some NES???
    72952: 04/09/08: Re: Need assistance with an FPGA based project.
    72974: 04/09/09: Re: Need assistance with an FPGA based project.
    74306: 04/10/07: Re: XILINX SHIPS ONE MILLION SPARTAN-3 FPGAS
Jacques GENIN:
    108384: 06/09/10: X4000 bad configuration
    108509: 06/09/12: Re: X4000 bad configuration
    108604: 06/09/13: Re: X4000 bad configuration
    108609: 06/09/14: Re: X4000 bad configuration
    109248: 06/09/22: Re: X4000 bad configuration
    109272: 06/09/22: Re: X4000 bad configuration
    109311: 06/09/23: Re: X4000 bad configuration
    109313: 06/09/23: Re: X4000 bad configuration
Jacques Pelletier:
    6153: 97/04/18: FLEX 8000 FPGA Configuration
Jacques-Olivier Haenni:
    7779: 97/10/14: AHDL to VHDL translation
<jacques77@gmail.com>:
    87404: 05/07/22: Transfert data to Memec Virtex II Pro Card from PC
Jaded:
    59750: 03/08/27: Help ! compxlib Error " mti_se not found" while Bulding XILINX libraries for ModelSim SE
<jadey@my-deja.com>:
    23829: 00/07/12: Re: FFT/IFFT for FPGA
jadwin79:
    142380: 09/08/07: Stale RTL schematic from VHDL in Xilinx ISE 11.1
Jae Cho:
    95: 94/08/13: translator needed
    4028: 96/09/04: speed up Xilinx P & R
    4879: 96/12/23: Integer divide IC
Jae-cheol Lee:
    30536: 01/04/13: Is there any free processor core for vertex series?
    30538: 01/04/13: Thank you very much.
    33392: 01/07/25: Q: dividing by 2 results in out-of-phase pulse sometimes
    36129: 01/10/31: what about FPGA with embedded processor?
Jae-Ho Shin:
    4720: 96/12/06: Or- gated clock solution?
    5309: 97/02/06: PMC alternative
    5310: 97/02/06: PMC alternative
Jaerder Sousa:
    142128: 09/07/26: How to start FPGA development
    142168: 09/07/28: Re: How to start FPGA development
    142247: 09/07/30: Re: Antti-Brain, should I keep going?
JaeYong Kim:
    21277: 00/03/15: Difference between FPGA, PLD, CPLD ?
jag9624:
    138777: 09/03/10: Finding aligned clock transitions with state machine
    138779: 09/03/10: Re: Finding aligned clock transitions with state machine
    138795: 09/03/11: Re: FPGA LVDS for AC-decoupled transmit over CAT-5 cable
    138796: 09/03/11: Re: Finding aligned clock transitions with state machine
    138810: 09/03/11: Re: Finding aligned clock transitions with state machine
jagadeesh:
    85624: 05/06/12: xilinx ml310 : to run applications on 2 nd ppc
    86587: 05/06/30: Re: ppc 405 in debug halt mode
    86816: 05/07/07: Re: ppc 405 in debug halt mode
Jagadeesh:
    86222: 05/06/23: Re: ppc 405 in debug halt mode
jaggu:
    86136: 05/06/22: ppc 405 in debug halt mode
    86415: 05/06/27: Re: ppc 405 in debug halt mode
Jaggu:
    82996: 05/04/21: xilinx ml310 + linux + System.map file problem
Jahagirdar Vijayvithal S:
    87300: 05/07/21: Re: Block Diagram Viewer / Hierarchy Parser for VHDL/Verilog?
Jahanzebanwer:
    149845: 10/11/28: EDIF netlist access in Xilinx ISE 8.1i
Jahid:
    134468: 08/08/12: Re: Block Rams
jai:
    12792: 98/10/29: 3.3V PCI without clamp diodes.
    13120: 98/11/16: newbie question about timing
Jai:
    110574: 06/10/18: how to implement integrator?
    110658: 06/10/19: Re: how to implement integrator?
jai kishan:
    11980: 98/09/22: 3.3V PCI to 5V local bus interface?
    12834: 98/10/31: Re: 3.3V PCI to 5V local bus interface?
jai.dhar@gmail.com:
    86608: 05/06/30: Re: Small FPGA
    86707: 05/07/04: Ethernet FPGA development board
    86771: 05/07/06: Re: Ethernet FPGA development board
    88794: 05/08/28: Bootloading with flash-config devices
    89177: 05/09/07: Re: Cyclone conf flash - 25p10 !
    89227: 05/09/08: Re: Cyclone conf flash - 25p10 !
    89248: 05/09/08: Re: Cyclone conf flash - 25p10 !
    89259: 05/09/09: Re: Cyclone conf flash - 25p10 !
    89271: 05/09/09: Re: Cyclone conf flash - 25p10 !
    89356: 05/09/13: Re: SDRAM quality
    89556: 05/09/19: FPGA's in bulk and pricing
    89567: 05/09/19: FPGA's in bulk and pricing
    89686: 05/09/22: Re: FPGA's in bulk and pricing
    89817: 05/09/27: Re: altera new bee
    90278: 05/10/07: New Ethernet Development board, open-source
    90479: 05/10/14: Re: How to Reduce Interconnects (VDD and VSS)
    90487: 05/10/14: Re: How to Reduce Interconnects (VDD and VSS)
    90531: 05/10/15: Re: How to Reduce Interconnects (VDD and VSS)
    90544: 05/10/16: Re: How to Reduce Interconnects (VDD and VSS)
    90547: 05/10/16: Re: How to Reduce Interconnects (VDD and VSS)
    90573: 05/10/17: Re: How to Reduce Interconnects (VDD and VSS)
    90974: 05/10/26: Re: ETHERNET MAC
    91735: 05/11/11: Re: How do i detect ethernet frames of layer 2 using ethereal?
    91736: 05/11/11: Re: SDRAM controller.
    100648: 06/04/14: Re: PCB Stack
    100667: 06/04/15: Re: PCB Stack
    106341: 06/08/11: Clock domain crossing (again)
    106411: 06/08/12: Re: Clock domain crossing (again)
    108996: 06/09/19: Re: E1 to ethernet conversion
    114603: 07/01/20: Re: Altera EP2S60 rebooting itself
    120633: 07/06/12: TDM stream multiplex/demultiplex
jaideep:
    34587: 01/08/29: XC2V3000-4BF957
    44113: 02/06/11: Digital FM demodulator in FPGA
    44119: 02/06/12: Digital FM demodulator in FPGA-continue
    44167: 02/06/12: Re: Digital FM demodulator in FPGA-continue
    45457: 02/07/23: Field Programmable SoC's
    59465: 03/08/19: random address
    60294: 03/09/09: Re: AWGN in VHDL
    60980: 03/09/25: Re: WARNING do not use your real email address in USENET postings! Swem/Gibe virus will spam you 1000x!
Jaime Andres Aranguren C.:
    148078: 10/06/19: Re: Anyone else need bigger parts in small (low pin count) packages
    148131: 10/06/22: Re: Xilinx BULLSHITIX-8, when?
    149325: 10/10/16: Re: FPGA or CPLD?
Jaime Andres Aranguren Cardona:
    33732: 01/08/02: 4 (8) bit Microporcessor Implementation
    33784: 01/08/04: FPGA - VHDL Design Tools (Was: 4 (8) bit Microporcessor Implementation)
    33790: 01/08/05: Which is the best Design Toolchain?
    33800: 01/08/05: Re: Which is the best Design Toolchain?
    33826: 01/08/06: Re: Which is the best Design Toolchain?
    36381: 01/11/07: "Illegal assignment" message, NEED HELP, PLEASE!!!
    36428: 01/11/08: Re: "Illegal assignment" message, NEED HELP, PLEASE!!!
    41328: 02/03/25: I2C Slave sampling edge
    48427: 02/10/17: Proveedor de Soluciones uC/FPGA/DSP - uC/FPGA/DSP Solutions Provider
    48457: 02/10/17: Re: Proveedor de Soluciones uC/FPGA/DSP - uC/FPGA/DSP Solutions Provider
    59352: 03/08/15: Re: FPGA/DSP Expert - business partner for innovative FFT
    72578: 04/08/25: Re: DSP/FPGA/video board?
    94053: 06/01/05: ModelSim vsim-3601 message
    94065: 06/01/05: Re: ModelSim vsim-3601 message
    94206: 06/01/07: Re: ISE 7.1 & ModelSim - Simulating Internal Signals
    94384: 06/01/11: Re: Downloading WebPack-8.1, server maxes out at 30 kB / second (= > 7 hours)?
    94385: 06/01/11: Re: Xilinx 7.1 ISE ModelSim input files
    127415: 07/12/21: PowerPC & Spartan-3E Embedded Processing Development Kit - SP3E1600E MicroBlaze Edition
    127417: 07/12/21: Re: PowerPC & Spartan-3E Embedded Processing Development Kit - SP3E1600E MicroBlaze Edition
    130945: 08/04/06: Re: Examples for Spartan3 StarterKit
    141593: 09/06/29: Re: usefulness of Virtex-II devices
    141594: 09/06/29: Re: Spartan3E or Cyclone III ?
Jaime Andrés Aranguren Cardona:
    20775: 00/02/21: Installing Xilinx Foundation on PC
    74660: 04/10/15: Re: Introducing MANIK - a 32 bit Soft-Core RISC Processor
    74806: 04/10/19: Re: Introducing MANIK - a 32 bit Soft-Core RISC Processor
    94264: 06/01/09: Downloading Nios II Eval from Altera website
    94766: 06/01/17: Re: xilinx free Sample Pack info now also on Xilinx own webpages
    112746: 06/11/28: Re: logic analyzer using FPGA
<jaime.aranguren@ieee.org>:
    28203: 00/12/29: Re: Verilog or VHDL
<jaimearanguren@my-deja.com>:
    28204: 00/12/29: MAX+Plus II Output. to HEX
"Jaimeet Aneja":
    29481: 01/02/23: Partial reconfig
    29561: 01/02/27: Partial Reconfig using JBits
    29562: 01/02/27: Re: Re: Partial reconfig
    29594: 01/02/28: Re: Re: Partial Reconfig using JBits
jaimico:
    142961: 09/09/10: Re: UART testbench debug
jaink:
    134037: 08/07/22: Re: XAUI v7.2 - timing issue - *channel bonding attributes*
jajo:
    109989: 06/10/09: Control of physical layer in a 802.11b
    110042: 06/10/09: Finite State Machine
    112236: 06/11/18: Input setup time & Output valid delay
    112241: 06/11/18: Static Timing Analysis vs Dinamic Timing Analysis
    112310: 06/11/20: Input setup time & Hold Input
    117560: 07/04/04: Conceptos about VCCINT,VCCAUX,etc
JAK:
    35265: 01/09/27: Xilinx Xactstep 5.1/6.1
Jakab Tanko:
    28295: 01/01/05: Re: Fixing pins on Spartan II
    28312: 01/01/05: Re: Fixing pins on Spartan II
    28914: 01/01/29: Xilinx NODELAY attribute question
    29163: 01/02/08: Re: Xilinx vs Altera
    29193: 01/02/09: Re: Xilinx vs Altera
    29275: 01/02/12: Re: Xilinx vs Altera
    29749: 01/03/07: Re: Is there any Virtex-II Evaluation Board?
    31030: 01/05/09: Re: Good VHDL/synthesis book
    66755: 04/02/26: Re: DCM Simulation Error
    67256: 04/03/09: Re: HOW to Increase jitter in ALTERA PLL ?
    67337: 04/03/10: Re: HOW to Increase jitter in ALTERA PLL ?
    67589: 04/03/15: Re: Which should I use, Floorplanner or PACE
    159096: 16/07/27: Altera Ethernet MAC without DMA
    159110: 16/07/31: Re: Altera Ethernet MAC without DMA
jakab tanko:
    17578: 99/08/11: Xilinx: Verilog only???
    20315: 00/02/04: Re: Conditional compilation in VHDL?
    36121: 01/10/30: Re: Autostart Problem SPROM->FPGA
    36419: 01/11/08: Xilinx dedicated IO pins
    36435: 01/11/08: Re: Xilinx dedicated IO pins
    37454: 01/12/11: DCM error
    37493: 01/12/12: Re: DCM error
    39563: 02/02/13: Re: Altera's new family Stratix
    41599: 02/04/03: Re: Configuring the Virtex II FPGA
    42482: 02/04/24: Re: SpartanII design considerations...
    43219: 02/05/16: Re: SPARTAN II - Master serial mode configuration problem
    44236: 02/06/14: Re: MAP problem with RLOC'ed macros
    44461: 02/06/20: Re: 12 years experience in Digital HW/ FPGA design, looking for job in the US
    44943: 02/07/07: Re: DC to DC converter at 1.5V
    45390: 02/07/22: Re: Xilinx (spartan 2) - SI even applies to the config pins
    45855: 02/08/07: Re: Xilinx hiring practises
    47059: 02/09/16: Re: Question about Virtex-II DCM's jitter
    47221: 02/09/20: Re: Apex unused pins voluntarily assigned by Quartus?
    47422: 02/09/25: Re: virtex II pro development board
    48268: 02/10/15: Virtex2 5V tolerant I/O ??
    51117: 03/01/02: Re: interface DRAM to FPGA
    51120: 03/01/02: Re: interface DRAM to FPGA
    51135: 03/01/03: Re: interface DRAM to FPGA
    52637: 03/02/17: Measuring die temperature
    52971: 03/02/27: Re: Unprogrammed XC9536XL is driving the databus high
    56393: 03/06/04: Re: FPGA's an Flash
    60496: 03/09/15: USB transceiver for FPGA
    60508: 03/09/15: Re: USB transceiver for FPGA
    60509: 03/09/15: Re: USB transceiver for FPGA
    60549: 03/09/16: Re: USB transceiver for FPGA
    61357: 03/10/02: Re: Good VHDL/Verilog editor?
    61418: 03/10/03: Interesting article about FPGAs
    62063: 03/10/17: ISE5.2 to ISE6.1
    62130: 03/10/20: Re: Altium DXP for designing Xilinx FPGA
    68719: 04/04/15: Re: what is a better approach to synthezise synchronous reset on FPGA?
    70947: 04/07/02: Re: DCM ISE6.2.3 sim problem
    71034: 04/07/06: Re: Place & route question in Xilinx...
<jakab.tanko@gmail.com>:
    82650: 05/04/15: DCI question
    82803: 05/04/18: Missing post
Jake:
    43353: 02/05/20: Upgrade to ISE4.1/4.2 ?
    80762: 05/03/11: re:Looking for low-cost protoboards.
    109933: 06/10/08: Re: free CAN field bus IP for EDK ?
    109959: 06/10/09: Re: free CAN field bus IP for EDK ?
Jake Janovetz:
    11991: 98/09/23: Re: How to reduce ringing/ground bounce from FPGA output pin?
    12077: 98/09/27: Re: Faster 32_bit integer multiplier required !!
    12147: 98/10/01: Synthesis: Exemplar or Synopsys
    12161: 98/10/01: Re: Synthesis: Exemplar or Synopsys
    12304: 98/10/08: Re: Synthesis: Exemplar or Synopsys
    15365: 99/03/20: Re: Bit Error Rate Test
    15943: 99/04/22: Re: Job Advert Netiquette?
    17317: 99/07/20: Re: Solaris vs. NT
    17367: 99/07/22: Re: Solaris vs. NT
    17368: 99/07/22: Re: Solaris vs. NT
    54412: 03/04/10: Xilinx IOB flip flop mapping
    54453: 03/04/10: Re: Xilinx IOB flip flop mapping
    54473: 03/04/11: Re: Xilinx IOB flip flop mapping
    55034: 03/04/24: Large adder placement / synthesis
    55070: 03/04/25: Re: Large adder placement / synthesis
    55345: 03/05/04: Re: PLL chips
    55610: 03/05/13: "Primitives" in XST?
    55620: 03/05/14: Re: "Primitives" in XST?
    55667: 03/05/15: Re: "Primitives" in XST?
    55832: 03/05/20: Re: a (PC) workstation for FPGA development
    55889: 03/05/22: Re: FPGA design: firmware or hardware?
    56240: 03/05/31: Re: FSM Coding Style
    56419: 03/06/04: Protel DXP or other schematic entry?
    56453: 03/06/05: Re: Galois Fields Applications
    56871: 03/06/17: Re: Simple FEC algorithm
    56892: 03/06/18: Re: Simple FEC algorithm
    59526: 03/08/20: Re: DCM vs state machine
    60526: 03/09/15: Xilinx ISE 6.1i
    60564: 03/09/16: Re: Xilinx ISE 6.1i
    60565: 03/09/16: Re: Xilinx ISE 6.1i
    60641: 03/09/18: Re: Using LUTs for array of coefficients
    60736: 03/09/20: Re: pipelined divider
    61015: 03/09/26: Re: WARNING do not use your real email address in USENET postings! Swem/Gibe virus will spam you 1000x!
    61050: 03/09/26: Re: Graphics rendering
    61058: 03/09/26: Re: FF with CE doesn't synthesize correctly by XST?
    61170: 03/09/29: Re: Counting ones
    61327: 03/10/01: Good VHDL/Verilog editor?
    61329: 03/10/01: Re: Parameterized Multiplier in Xilinx FPGA
    61330: 03/10/01: Re: Parameterized Multiplier in Xilinx FPGA
    61377: 03/10/02: Re: Good VHDL/Verilog editor?
    61442: 03/10/03: Re: Good VHDL/Verilog editor?
    61693: 03/10/08: Spartan 3 pinout typo?
    61854: 03/10/14: Re: Spartan 3 pinout typo?
    61973: 03/10/15: Re: To our future engineers, smart and otherwise...
    62029: 03/10/16: Re: Spartan-3 non-ES availability, and misleading pricing info
    62077: 03/10/17: Re: ISE5.2 to ISE6.1
    62114: 03/10/19: Re: CPU vs. FPGA vs. RAM
    62115: 03/10/19: Re: CPU vs. FPGA vs. RAM
    62167: 03/10/21: Re: Altium DXP for designing Xilinx FPGA
    62454: 03/10/29: Re: How to protect fpga based design against cloning?
    62856: 03/11/10: Re: ISE 5.2 to 6.1
    62877: 03/11/10: Re: Home grown CPU core legal?
    63224: 03/11/18: Re: Xilinx Design entry via Schematic Capture - What tool to use ?
    63759: 03/12/03: Command line in Windows?
    63801: 03/12/04: Re: Command line in Windows?
    63802: 03/12/04: Re: Command line in Windows?
    63803: 03/12/04: Re: Command line in Windows?
    65265: 04/01/22: Re: Spirit on Mars
    67058: 04/03/04: Re: Xilinx Spartan 3 configuration
    67080: 04/03/04: Re: Xilinx Spartan 3 configuration
    68108: 04/03/26: Generating Xilinx cores.
    69026: 04/04/25: Re: Looking for a USB-enabled flash-based microcontroller with CPLD/FPGA
    70498: 04/06/17: IOBs in NGC - problem with OBUFT
    70548: 04/06/20: Re: IOBs in NGC - problem with OBUFT
    70635: 04/06/22: Re: IOBs in NGC - problem with OBUFT
    72684: 04/08/28: Re: Counter counting on both clock edges.
    73309: 04/09/18: Reconfigure Spartan 3 without losing BRAM?
    73476: 04/09/22: Re: Virtex 4 integrated A/Ds? Yes it does.
    79542: 05/02/20: Re: why are PCI-based FPGA cards so expensive ?
    79913: 05/02/25: Re: Maximum Current utilized by Spartan-3
    79927: 05/02/25: Re: Maximum Current utilized by Spartan-3
    84703: 05/05/24: Re: Bresenham Algorithms
    84709: 05/05/24: Re: Bresenham Algorithms
    84765: 05/05/26: Re: State Machines.. and their efficiency.
    98586: 06/03/13: Why does Xilinx hate version control?
    98609: 06/03/13: Re: Why does Xilinx hate version control?
    98612: 06/03/13: Re: Soldering SMT/BGA
    98613: 06/03/13: Re: Soldering SMT/BGA
    98614: 06/03/13: Re: Soldering SMT/BGA
    98624: 06/03/13: Re: Why does Xilinx hate version control?
    98755: 06/03/16: Re: Why does Xilinx hate version control?
Jake Kelly:
    3136: 96/04/10: FREE Book: "Top Verilog Problems & How To Solve Them."
Jake7:
    140562: 09/05/17: Online tool that generates parallel CRC and Scrambler
    140905: 09/05/28: Re: Online tool that generates parallel CRC and Scrambler
    140906: 09/05/28: Re: Online tool that generates parallel CRC and Scrambler
Jakka Bhasker Reddy:
    45395: 02/07/22: Re: How could I generated an efficient 16*16 multiplier in Vertex-II?
Jakob:
    98983: 06/03/18: Spartan 3 Power Supply Design
    99006: 06/03/18: Re: Spartan 3 Power Supply Design
JAKOB NIKLASSON:
    24394: 00/08/06: Re: Circuit Drawing
Jaksa:
    111183: 06/10/30: FFT help
    111188: 06/10/30: Re: FFT help
    111234: 06/10/31: Re: FFT help
Jakub:
    69658: 04/05/17: Xilinx training
Jakub Dudek:
    65870: 04/02/09: Xilinx training
jalaram:
    108898: 06/09/18: xilinx fir ipcore
jaleco:
    10825: 98/06/24: How to Double Clk Freq in the FPGA design
    10827: 98/06/24: Re: How to Double Clk Freq in the FPGA design
Jalen.Ong@gmail.com:
    114453: 07/01/16: microcode in verilog?
    118056: 07/04/17: Interfacing FPGA with TTL
jam:
    28695: 01/01/21: Designing fractional counters?
Jamba:
    47412: 02/09/25: spartan II and PCI 5 volt
james:
    58051: 03/07/13: Re: Graduation Day: My first 4-layer PCB
    58054: 03/07/13: Re: Graduation Day: My first 4-layer PCB
    58082: 03/07/14: Re: Graduation Day: My first 4-layer PCB
    58084: 03/07/14: Re: Graduation Day: My first 4-layer PCB
    59560: 03/08/21: Re: Which software from Xilinx
    59562: 03/08/21: Re: 22V10, ABEL & Current Design Tools?
    60319: 03/09/10: Re: CMOS camera w/ USB2 -- crazy?
    60322: 03/09/10: Re: CMOS camera w/ USB2 -- crazy?
    60359: 03/09/11: Re: CMOS camera w/ USB2 -- crazy?
    60388: 03/09/12: Re: CMOS camera w/ USB2 -- crazy?
    77007: 04/12/20: Re: Digital clock synthesis
    80230: 05/03/02: Re: SoC positions in Bangalore
    80232: 05/03/02: Re: SoC positions in Bangalore
    88370: 05/08/16: Re: image sensor
    88552: 05/08/22: Re: how to reduce vga memory????????
    88594: 05/08/23: Re: how to reduce vga memory????????
    88784: 05/08/28: Re: TTL, CMOS and spartan
    98023: 06/03/03: Re: problem with ISE versions
    112074: 06/11/15: Re: Old Spartan-II, worth prototyping?
    133656: 08/07/08: How can I create a direct FSL connection?
    134972: 08/09/08: Re: Spartan 3E evaluation board manufacturers
    135006: 08/09/10: Re: Spartan 3E evaluation board manufacturers
    135009: 08/09/10: Re: Placing Verilog busses using Xilinx RPMs
    135010: 08/09/10: Re: What version of ISE is availabe for Virtex5?
    135011: 08/09/10: Re: Can Soft microprocessor replace DSP's
    135049: 08/09/12: Re: Placing Verilog busses using Xilinx RPMs
    135050: 08/09/12: Re: Spartan-II, config pins 5V tolerant? (slave serial)
    137422: 09/01/15: Webpack 10.1 on Windows XP
    137736: 09/01/28: Re: Problems when I download and install Xilinx ISE 10.1. Help please.
    137739: 09/01/28: Re: What software do you use for PCB with FPGA ?
    137749: 09/01/28: Re: What software do you use for PCB with FPGA ?
    137780: 09/01/29: Re: What software do you use for PCB with FPGA ?
    137933: 09/02/02: Re: Spartan-6
    138748: 09/03/07: Re: Character generator ROM and VGA controller for Spartan 3E
    139768: 09/04/13: Re: buy XSA-50
    140551: 09/05/16: Re: how i can use the external SRAM of FPGA
    141152: 09/06/09: Re: dsp with fpgas by Uwe Meyer-Baese
    141321: 09/06/17: Re: Do you know how aggressive the patent fighting between Xilinx and Altera is going?
    141585: 09/06/28: Re: usefulness of Virtex-II devices
    143616: 09/10/18: Re: Memory Interface Generator
    143617: 09/10/18: Re: Any interest in a group Xilinx FPGA board build/buy ??
    144031: 09/11/08: Re: OK Xilinx users, it's time I was let in on the joke...
    145218: 10/02/01: Re: How can I convert size requirements from Altera devices to Xilinx devices?
    145236: 10/02/02: Re: What MAXIM chip is used on Spartan 3E 1600E Microblaze Board for RS232 communication?
    145324: 10/02/05: Re: using an FPGA to emulate a vintage computer
    145418: 10/02/08: Re: using an FPGA to emulate a vintage computer
    145476: 10/02/11: Re: using an FPGA to emulate a vintage computer
    145478: 10/02/11: Re: using an FPGA to emulate a vintage computer
    145830: 10/02/25: Re: EDK spi ip core
    146368: 10/03/14: Re: Nu Horizons Spartan 3A DSP board
    146389: 10/03/15: Re: Nu Horizons Spartan 3A DSP board
    146448: 10/03/18: Re: Nu Horizons Spartan 3A DSP board
    146495: 10/03/20: Re: Xilinx only on Avnet now
    147156: 10/04/15: Re: Implementing bidirectional bus inside the FPGA
    147157: 10/04/15: Re: Implementing bidirectional bus inside the FPGA
    150463: 11/01/23: Re: Xilinx news
James:
    39298: 02/02/05: Programming Altera PGAs.
    39392: 02/02/08: Re: Programming Altera PGAs.
    52550: 03/02/13: Re: Generating EDIF from HandelC
    58275: 03/07/18: Block Ram Preloading Data
    58276: 03/07/18: Initialize Block RAM
    60241: 03/09/08: Programming Xilinx CPLD under linux
    63079: 03/11/13: Re: Code for accessing CF cards on Cyclone dev.board
    69963: 04/05/25: Re: www.opencores.org ???
    72199: 04/08/11: Re: Power Supply for Xilinx FPGA
    76451: 04/12/02: FPGA Floating Point core IPs
    78310: 05/01/29: Sensitive List Question
    78324: 05/01/29: Re: Sensitive List Question
    80866: 05/03/13: Newb: FSM in no valid state?
    80883: 05/03/13: Re: Newb: FSM in no valid state?
    80884: 05/03/13: Re: Newb: FSM in no valid state?
    114585: 07/01/19: Re: Beginner VHDL questions
    119352: 07/05/17: Unusual question about generic port use (optional ports??)
    142657: 09/08/24: Help with altera_attribute and AUTO_GLOBAL_CLOCK
    151419: 11/04/05: Help with SDC (specifically edge_shift)
    151425: 11/04/06: Re: Help with SDC (specifically edge_shift)
    152675: 11/09/26: Implementation Issue
    152679: 11/09/27: Re: Implementation Issue
James A:
    84456: 05/05/19: Newbie: Falling edge, what is the threshold? (Xilinx XC9572XL)
    84462: 05/05/19: Re: Newbie: Falling edge, what is the threshold? (Xilinx XC9572XL)
    84463: 05/05/19: Re: Newbie: Falling edge, what is the threshold? (Xilinx XC9572XL)
    84514: 05/05/20: Re: Newbie: Falling edge, what is the threshold? (Xilinx XC9572XL)
    84563: 05/05/21: Re: Newbie: Falling edge, what is the threshold? (Xilinx XC9572XL)
James Alston:
    70113: 04/06/03: Re: 5 V inputs to 3.3 V CPLD
James Baker:
    32923: 01/07/11: Erasing Altera EPC-1441?
James Ball:
    85843: 05/06/17: Re: NIOS2 exceptions...
James Beck:
    82494: 05/04/13: Re: Regarding driving of SCL and SDA pins of I2C
    82577: 05/04/14: Re: Regarding driving of SCL and SDA pins of I2C
James Birmingham:
    18303: 99/10/13: .cal .rbt file format
    18808: 99/11/17: viewing fpga config
James Bonanno:
    49009: 02/10/29: Re: power estimation XC2V2000 virtex-II FPGA
    49441: 02/11/12: Re: new to fpga, what language is better to start with
    50963: 02/12/23: Re: FPGA accelerated FPGA/ASIC tools
    50982: 02/12/24: Re: FPGA accelerated FPGA/ASIC tools
James Bond:
    91094: 05/10/29: xilinx design reuse netlist format
    91100: 05/10/29: Re: xilinx design reuse netlist format
James Brennan:
    30911: 01/05/03: FPGA based PCI cards
    31473: 01/05/27: JPEG cores
    33391: 01/07/25: A DIME module with simple RAM?
    33915: 01/08/09: Wildcard and Foundation tools
    33918: 01/08/09: Re: Wildcard and Foundation tools
    77013: 04/12/20: Modelsim Segmentation faults
    77020: 04/12/20: Re: Modelsim Segmentation faults
James Buchanan:
    27245: 00/11/16: Actel Compiler errors..... from Synplify?!
James C. LaLone:
    21614: 00/03/26: Re: Clock nets using non-dedicated resources
James C. Schwalbe:
    35710: 01/10/15: Re: Linux tools
    36600: 01/11/13: Re: Virtex 2 parts availability???
    36601: 01/11/13: Re: PLL in Altera's Apex20K
James Calivar:
    62632: 03/11/03: Re: Shannon Entropy for Black Holes
James Chang:
    60601: 03/09/17: FPGA congress on Asia
James Cleary:
    5416: 97/02/14: Re: Gate level Simulation with Mentors Quicksim from Galileo
James Cook:
    9910: 98/04/13: Altera MAX+Plus II for sale
    10075: 98/04/25: For sale: Altera MAX+Plus II
James Craig Ziegler:
    8726: 98/01/22: Re: hdl, schematic, simulation, graphical front ends: (was xilinx stock)
James Dickson:
    563: 95/01/05: Re: What's Up At ViewLogic?
    614: 95/01/19: Re: Multiple FPGAs
    711: 95/02/14: Re: Can I implement a digital PLL in an FPGA??
    1106: 95/04/29: Re: VMEbus interface using fpgas
James Doherty:
    12021: 98/09/24: Re: Which FPGA tool is better
    12234: 98/10/06: Re: Which FPGA tool is better
    12172: 98/10/02: Re: ISP Synario - need a help!
James Dow Allen:
    145354: 10/02/06: Re: using an FPGA to emulate a vintage computer
    145378: 10/02/07: Re: using an FPGA to emulate a vintage computer
James E. Stine:
    12132: 98/09/30: Re: Fastest Add
    12133: 98/09/30: Re: FIR Filter Design
    12139: 98/10/01: Re: Fastest Add
    12163: 98/10/01: Re: Fastest Add
    12363: 98/10/09: Re: Help Desperately Needed with Altera Microprocessor Design.
    12479: 98/10/13: Re: Digital Sine Generator
    12481: 98/10/13: Re: Digital Sine Generator
    12496: 98/10/13: Re: Digital Sine Generator
James E. Stine, Jr.:
    9913: 98/04/13: Synplicity
    9914: 98/04/13: Re: VHDL compiler differences ?
James Fakas:
    5023: 97/01/14: Great Xilinx FPGA Kits & prices
    5342: 97/02/08: Re: REPOST: New Web Site Dedicated to Programmable Logic
James Fitzsimons:
    55958: 03/05/25: Newbie CPLD question
    55969: 03/05/25: Re: Newbie CPLD question
    55971: 03/05/25: Re: Newbie CPLD question
    55998: 03/05/27: Re: Newbie CPLD question
    60244: 03/09/09: Re: Programming Xilinx CPLD under linux
    60252: 03/09/09: Re: Programming Xilinx CPLD under linux
James Flanagan:
    52759: 03/02/20: Cupl Simulation Question
    53629: 03/03/18: Low Power CPLD suggestion request...
James G:
    17372: 99/07/22: Low Cost latched I/O
James H. Grandt:
    1573: 95/07/19: FPGA Software...
James Hadley:
    325: 94/10/19: Analog FPGAs
James Harris:
    123711: 07/09/02: Beginning FPGA programming
    123712: 07/09/02: FPGA CPU
    123728: 07/09/03: Re: FPGA CPU
    123785: 07/09/04: Re: FPGA CPU
    123786: 07/09/04: Re: FPGA CPU
    123787: 07/09/04: Re: FPGA CPU
    123796: 07/09/04: Re: FPGA CPU
    124232: 07/09/15: Re: Beginner Advice (Languages, tools etc.)
    134642: 08/08/22: Re: Apple II on FPGA
    135409: 08/10/01: Re: $99 XMOS Dev kit
    135753: 08/10/14: Re: $99 XMOS Dev kit
    135776: 08/10/15: Re: $99 XMOS Dev kit
    135890: 08/10/20: Re: Looking for a FPGA board for starter
    136202: 08/11/05: Xmos now shipping sillicon
    136203: 08/11/05: Re: Xmos now shipping silicon
    136216: 08/11/06: Re: TCP/IP 3 way handshake
    139105: 09/03/20: Re: FPGA users, Please take a few seconds to report SPAM
    140714: 09/05/22: Re: SPAM?
    141681: 09/07/03: Re: TimingAnalyzer is now freeware
    142821: 09/09/02: Re: Choice of Language for FPGA programming
    145352: 10/02/06: Re: using an FPGA to emulate a vintage computer
    146885: 10/03/30: Re: Which is the most beautiful and memorable hardware structure in a
    149179: 10/10/06: Re: Starting a career with FPGAs
James Harry:
    87707: 05/07/29: Re: Soft IPs licensing -gpl
James Horn:
    8902: 98/02/06: Re: Power consumption
    9520: 98/03/20: Re: Ideas for an FPGA Project?
    21442: 00/03/22: Windowed Altera 1810s?
    22230: 00/05/02: Re: How to Prevent theft of FPGA design
    29789: 01/03/09: Springboard design contest
    31850: 01/06/06: Re: one state machine
    31857: 01/06/06: Re: one state machine
    31934: 01/06/08: Re: Flash programming via FPGA's JTAG ????
    37306: 01/12/06: Re: where is designed FPGA for APPLE....?
    39996: 02/02/23: Re: Coolrunner and ISP
    40212: 02/03/01: Re: Altera Excalibur
    40584: 02/03/11: Re: Sandwich board at ESC
    41079: 02/03/20: Re: FPGA or Micro-controller in Lowpower designs?
    41241: 02/03/22: Re: A poor man's boundary scan test tool
    41318: 02/03/25: Re: Can't detect Altera MAX7000s using JTAG
    42631: 02/04/29: Re: ABEL for the Altera MAX 7000
    43820: 02/06/03: Re: divide by 5
    45659: 02/07/30: Re: Impedance Measureing
    46910: 02/09/11: Re: FPGA comes with a DAC?
    57203: 03/06/25: GAL16V8 reverse compilation
    57211: 03/06/25: Re: GAL16V8 reverse compilation
    58802: 03/08/01: Re: Size does matter
    89032: 05/09/03: Re: Digilent's JTAG-USB cable with chipscope
    89033: 05/09/03: Re: Platform Cable USB
James Jackson:
    15900: 99/04/20: PIN/PAD files to Schematic Symbols
James Kellar:
    12297: 98/10/08: Re: Help Desperately Needed with Altera Microprocessor Design.
    14586: 99/02/05: Re: can I trust Altera Simulator?
James Kennedy:
    23358: 00/06/23: What tools do people use for Xilinx FPGAs?
    22977: 00/06/07: VHDL code works in foundation 1.5, dosen't work in 2.1?
    44322: 02/06/18: Re: Internal oscillator in CPLD?
    94123: 06/01/06: Re: Beginner help with VHDL, Xilinx 9536XL, and ISE7.1
    96331: 06/02/02: Re: Spartan3 pullups
James Kim:
    9978: 98/04/20: Xilinx FPGAs: Usable Pins on XS Boards (Help)
James L Horn:
    7543: 97/09/20: Re: Altera FPGA - asynch serial
James LaLone:
    9745: 98/04/02: Re: Synthesizable 8B/10B Encoder/Decoder wanted
    9776: 98/04/04: Re: Smoking Crater in a Xilinx 3k FPGA
    13125: 98/11/17: Synthesizeablel fifo
    13187: 98/11/19: Re: Synthesizeablel fifo
James Lawrence:
    29560: 01/02/27: Computer Guide
James Lee:
    10998: 98/07/09: Re: question on combinational logic synthesis for FPGA
    34348: 01/08/22: Re: Principles of Verifiable RTL Design (2nd ed)
James Lewis:
    40936: 02/03/18: Xilinx makesrc problem/questions
    41100: 02/03/20: Xilinx Spartan XL VHDL????
James Ma:
    96822: 06/02/11: Using Ethernet to control/initialize FPGA
    103649: 06/06/07: Easily add 4 Gb/s Ethernet link to FPGA systems for control & data transfer
James Meyer:
    14036: 99/01/08: Re: Glitchless Logic, hazards, and Metastability - Was Re: 22V10 Metastability - help please
James Morrison:
    66180: 04/02/13: Re: Sensible starter FPGA board
    68574: 04/04/08: Re: Can I use the Done signal in FPGA to reset my design
    68902: 04/04/21: Re: FPGA within demonstration
    68932: 04/04/22: Re: cpld in plcc84 package
    69411: 04/05/10: Re: Monolithic state machine or structured state machine?
    77899: 05/01/19: Re: LVDS through connectors
    77914: 05/01/20: Re: LVDS through connectors
    77985: 05/01/21: Re: Configuring FPGA using PROM/uP
    80910: 05/03/14: Re: XCF01's in the UK
    81287: 05/03/21: Re: TPS75003 for FPGAs
    85814: 05/06/16: BGA Rework/Prototype Placement Anyone?
    85841: 05/06/16: Xilinx Spartan 3 DCI Power Consumption
    86152: 05/06/22: Re: disappointed with Altera this time
    86249: 05/06/23: Re: iMPACT downloading error
    86258: 05/06/23: Re: Issues with Xilinx xapp635: Interface for TigerSharc Link Ports.
    86610: 05/06/30: Re: Coverting .mcs file to .bit file
    88551: 05/08/22: Generic Memory-Mapped VHDL Module
    97316: 06/02/20: Re: Is FPGA code called firmware?
    104816: 06/07/06: Can a BUFGMUX drive a global clock in the Spartan-3?
James Peters:
    124466: 07/09/23: Any advice on Steve Kilts' "Advanced FPGA Design: Architecture, Implementation,
James Robinson:
    143200: 09/09/25: Super Small MIPS-compatible Altera-Based Soft Processor and compiler
    143212: 09/09/25: Re: Super Small MIPS-compatible Altera-Based Soft Processor and
    143254: 09/09/28: Re: Super Small MIPS-compatible Altera-Based Soft Processor and
James S.:
    25852: 00/09/22: Need Help: Xilinx FastCLK (XC4000XLA)
    26388: 00/10/13: clk'event
    26881: 00/11/02: OT: Xilinx T-Shirt
James Salisbury:
    145758: 10/02/22: Re: FPGA platform??
    146665: 10/03/25: Re: EMC discussion
    147197: 10/04/17: Re: Which 32 bit cores support full Linux?
James Srinivasan:
    38642: 02/01/20: Re: Nios development kit
    38643: 02/01/20: Altera Nios v2
    38647: 02/01/20: Re: Altera Nios v2
    38772: 02/01/24: Re: Altera Nios v2
    39952: 02/02/22: Re: Pin assignments in QUARTUS
    39961: 02/02/22: Re: Pin assignments in QUARTUS
    42172: 02/04/17: Re: Problems with Nios 2.0
    42442: 02/04/24: Re: Reasonably Priced Development Software ??
    42444: 02/04/24: Re: Reasonably Priced Development Software ??
    53660: 03/03/19: Re: Quartus2 : assigning I/O pins
    53685: 03/03/20: Re: Quartus2 : assigning I/O pins
    53759: 03/03/21: Re: Using FPGAs as coprocessors in a PC
James Stine:
    9569: 98/03/24: Re: New radix-4 CORDIC for computing sine and cosine
    12151: 98/10/01: Re: Fastest Add
    12152: 98/10/01: Re: FIR Filter Design
James T. White:
    22665: 00/05/16: Re: PC104+ FPGA Board
    96542: 06/02/06: Re: Protected power calculation spread sheets
    114013: 07/01/02: Re: Surface mount ic's
James Thiele:
    4815: 96/12/17: Re: ASICs Vs. FPGA in Safety Critical Apps.
James Thurley:
    41301: 02/03/25: Can't detect Altera MAX7000s using JTAG
    41343: 02/03/26: Re: Can't detect Altera MAX7000s using JTAG
James Tucker:
    106767: 06/08/18: Re: Open-source JTAG software?
James W. Swonger:
    4972: 97/01/07: Re: ASICs Vs. FPGA in Safety Critical Apps.
    6269: 97/05/07: Re: Advantages/disadvantages between CMOS/BiCMOS
James Wallis:
    29462: 01/02/22: PCI : Not booting on ASUS
    29706: 01/03/05: Re: PCI : Not booting on ASUS
James Wang:
    32801: 01/07/09: Spartan-II implementation woes
    48671: 02/10/22: Altera FPGA and EPLD Download ByteBlaster
    48904: 02/10/26: Re: Altera FPGA and EPLD Download ByteBlaster
    48906: 02/10/26: Altera ByteBlaster
    48922: 02/10/26: Announce: FPGA Demo Board
    68528: 04/04/07: Altera ByteBlasterMV Download Cable
    71064: 04/07/07: Minford Altera FPGA CPLD Byteblaster Downloader
    72315: 04/08/14: Minford MF160 FPGA and CPLD Downloader -- Replace for Altera ByteBlaster II
    72643: 04/08/27: Replace for Altera ByteBlaster II -- Minford MF160 FPGA and CPLD Downloader
James West:
    4864: 96/12/20: Re: I2C Bus Interface in FPGAs
    5098: 97/01/23: Re: Altera support better than Xilinx
    5841: 97/03/20: Re: Sole source
James Williams:
    60831: 03/09/23: IEEE 1284 Core for Xilinx
    60833: 03/09/23: New to VHDL for Xilinx
    60842: 03/09/23: Re: New to VHDL for Xilinx
    60849: 03/09/23: Re: New to VHDL for Xilinx
    60892: 03/09/24: Re: IEEE 1284 Core for Xilinx
    60945: 03/09/25: Re: IEEE 1284 Core for Xilinx | Reading Japanese FPGA pages
    60948: 03/09/25: Re: IEEE 1284 Core for Xilinx | Reading Japanese FPGA pages
    61005: 03/09/26: Re: IEEE 1284 Core for Xilinx | Reading Japanese FPGA pages
    61213: 03/09/30: Re: Is Xilinx Webpack 6.1 help crippled?...
    61216: 03/09/30: Re: Is Xilinx Webpack 6.1 help crippled?...
    61232: 03/09/30: Implementing multiple registers with one single input output bus and address select in VHDL.
James Wolffe:
    17559: 99/08/10: Re: Emulating a transputer on FPGA
James Wong:
    47179: 02/09/19: designing DDR I/O in CPLD
James Wu:
    114535: 07/01/18: Beginner VHDL questions
James Yeh:
    17448: 99/07/28: Re: Xilinx Virtex Block Select RAM, is is reg or flow thru output
    17936: 99/09/17: Question about Alliance 2.1i
    18242: 99/10/08: Re: Capacity metrics for Virtex
    18546: 99/10/29: StateCAD versus Viewdraw
    18549: 99/10/30: Re: StateCAD versus Viewdraw
    19478: 99/12/23: viewlogic problem
    19484: 99/12/24: Re: viewlogic problem
James Young:
    23112: 00/06/14: Question: Xilinx FPGA PROGRAM pin
James Zaiter:
    43409: 02/05/21: i need help getting started with fpgas
<james.e.steward@gmail.com>:
    135580: 08/10/08: ChipScope on Ubuntu 7.10 - blank screen
<james.knoll@gmail.com>:
    92064: 05/11/21: JTAG read from xc18v04
<james.lbs@gmail.com>:
    123864: 07/09/06: FATAL ERROR ISE9.1i
    124169: 07/09/13: Xilinx System Generator Error!
<james.r.lamb@comcast.net>:
    90759: 05/10/20: C source for Spartan-3 with microblaze soft core for RS-232 comm
james.rowland1:
    29062: 01/02/04: initialise state machine on Altera
    30535: 01/04/13: Re: RC4/ARC4 on an FPGA.
James07:
    158072: 15/07/30: Picking the best synthesis result before implementation
<james7uw@yahoo.ca>:
    103959: 06/06/15: Xilinx MicroBlaze and Multimedia Demo. board: Debugging: 8.1.03i EDK - Unable to sync with stub on board
    103961: 06/06/15: Re: Xilinx MicroBlaze and Multimedia Demo. board: Debugging: 8.1.03i EDK - Unable to sync with stub on board
    108372: 06/09/09: Xilinx ISE ver 8.2.02i is optimizing away and removing "redundant" logic - help!
    108376: 06/09/09: Re: Xilinx ISE ver 8.2.02i is optimizing away and removing "redundant" logic - help!
    108401: 06/09/10: Re: Xilinx ISE ver 8.2.02i is optimizing away and removing "redundant" logic - help!
    108456: 06/09/11: Re: Xilinx ISE ver 8.2.02i is optimizing away and removing "redundant" logic - help!
    108478: 06/09/11: Re: Xilinx ISE ver 8.2.02i is optimizing away and removing "redundant" logic - help!
    108516: 06/09/12: Re: Xilinx ISE ver 8.2.02i is optimizing away and removing "redundant" logic - help!
    108552: 06/09/12: Re: Xilinx ISE ver 8.2.02i is optimizing away and removing "redundant" logic - help!
    108553: 06/09/12: Re: Xilinx ISE ver 8.2.02i is optimizing away and removing "redundant" logic - help!
    108642: 06/09/14: Re: Xilinx ISE ver 8.2.02i is optimizing away and removing "redundant" logic - help!
    109339: 06/09/24: Now on 8.2.03i Re: Xilinx ISE ver 8.2.02i is optimizing away and removing "redundant" logic - help!
    109343: 06/09/24: Re: Now on 8.2.03i Re: Xilinx ISE ver 8.2.02i is optimizing away and removing "redundant" logic - help!
    109367: 06/09/25: Does anyone know what "SE" and "PE" stand for in ModelSim?
    109382: 06/09/25: Re: Does anyone know what "SE" and "PE" stand for in ModelSim?
    109388: 06/09/25: Re: Now on 8.2.03i Re: Xilinx ISE ver 8.2.02i is optimizing away and removing "redundant" logic - help!
    109389: 06/09/25: Re: Now on 8.2.03i Re: Xilinx ISE ver 8.2.02i is optimizing away and removing "redundant" logic - help!
    109390: 06/09/25: Re: Now on 8.2.03i Re: Xilinx ISE ver 8.2.02i is optimizing away and removing "redundant" logic - help!
    109393: 06/09/25: Re: Now on 8.2.03i Re: Xilinx ISE ver 8.2.02i is optimizing away and removing "redundant" logic - help!
    109420: 06/09/26: Re: Does anyone know what "SE" and "PE" stand for in ModelSim?
    109443: 06/09/26: Re: Now on 8.2.03i Re: Xilinx ISE ver 8.2.02i is optimizing away and removing "redundant" logic - help!
    109564: 06/09/28: Re: Now on 8.2.03i Re: Xilinx ISE ver 8.2.02i is optimizing away and removing "redundant" logic - help!
    109565: 06/09/29: ModelSim path problem as fed by Xilinx ISE ver 8.2.03i
    109596: 06/09/29: Re: ModelSim path problem as fed by Xilinx ISE ver 8.2.03i
    109597: 06/09/29: Re: ModelSim path problem as fed by Xilinx ISE ver 8.2.03i
James823:
    154283: 12/09/23: Getting in to the industry
    154510: 12/11/22: Set-up and hold times and metastability
    154517: 12/11/22: Re: Set-up and hold times and metastability
    154519: 12/11/22: Re: Set-up and hold times and metastability
    154531: 12/11/23: Re: Set-up and hold times and metastability
<jamesantone@if.rmci.net>:
    12865: 98/11/02: Altera bitstream file format
    12925: 98/11/04: Re: Altera bitstream file format
jamesp:
    92875: 05/12/08: What graphical entry/documentation tools?
<jamesxy@hotmail.com>:
<jamicrotech@gmail.com>:
    131001: 08/04/08: OBUF gate delay
Jamie:
    55103: 03/04/26: Re: ISE 5.2i evaluation and problem with Windows ME
    99999: 06/03/31: Re: Concatenate String in Verilog?
jamie:
    72883: 04/09/07: Re: VHDL code for 16-32 bit counter for quadrature encoder signals
    72927: 04/09/08: Re: VHDL code for 16-32 bit counter for quadrature encoder signals
Jamie Honan:
    20238: 00/02/02: Foundation 1.5 VHDL compiler command line
Jamie Lokier:
    10902: 98/06/29: Re: Xilinx file compression
    11169: 98/07/22: Re: Too much advertising in this news group?
    11269: 98/07/31: Re: Schematic Symbol Generation
    11270: 98/07/31: Re: TRISTATE in FPGA
    11271: 98/07/31: Altera tools on Linux
    11277: 98/08/01: Re: Altera tools on Linux
    11558: 98/08/24: Re: Altera FLEX10K ClockLock/ClockBoost ?
    11559: 98/08/24: Re: Data I/O Chiplab and NT
    11955: 98/09/21: Re: ASIC -> FPGA async issues
    12511: 98/10/14: Re: Altera MAXPLUS2 V9 slow.
    12512: 98/10/14: Re: 100 MHz FPGA
    12948: 98/11/06: Re: FPGA on ASIC (Was: Re: New free FPGA CPU)
    12866: 98/11/03: Re: Altera bitstream file format
    13150: 98/11/17: Re: Synthesizeablel fifo
    13223: 98/11/20: Re: Synthesizeablel fifo
    13260: 98/11/22: Re: Synthesizeablel fifo
    13983: 99/01/06: Re: 22V10 Metastability - my 2c
    14020: 99/01/07: Re: Glitchless Logic, hazards, and Metastability - Was Re: 22V10 Metastability - help please
    14148: 99/01/15: Re: AHDL VS. VHDL
    14149: 99/01/15: The development of a free FPGA synthesis tool
    14175: 99/01/17: Re: The development of a free FPGA synthesis tool
    14211: 99/01/20: Re: The development of a free FPGA synthesis tool
    14332: 99/01/26: C to Hardware translators [was: The development of a free FPGA synthesis tool]
    14333: 99/01/26: Re: small correction
    14425: 99/01/29: Re: The development of a free FPGA synthesis tool
    14427: 99/01/29: Re: C to Hardware translators [was: The development of a free FPGA synthesis tool]
    14428: 99/01/29: Re: C to Hardware translators [was: The development of a free FPGA synthesis tool]
    14460: 99/01/30: Re: C to Hardware translators [was: The development of a free FPGA synthesis tool]
    14463: 99/01/30: Re: C to Hardware translators [was: The development of a free FPGA synthesis tool]
    14501: 99/02/02: Re: C to Hardware translators [was: The development of a free FPGA synthesis tool]
    14839: 99/02/19: Re: P&R times for Altera10K200E and Virtex
    14860: 99/02/20: Re: P&R times for Altera10K200E and Virtex
    15792: 99/04/14: Re: bitstream
    15802: 99/04/15: Re: bitstream
    15803: 99/04/15: Re: Problems with high pin count FPGA systems
    15931: 99/04/22: Re: Asynchronous Logic in Altera 10K devices
    16387: 99/05/19: Re: flex10k 1 gate change
    16589: 99/05/29: Re: Xilinx M1.5 Crash
    17078: 99/06/29: Re: Read/Writes to memories/register files for PIC core
    17094: 99/06/30: Re: Read/Writes to memories/register files for PIC core
    17349: 99/07/22: Re: Solaris vs. NT
    18813: 99/11/17: Re: implementing TCP/IP on PLD
    18852: 99/11/19: Re: implementing TCP/IP on PLD
    18858: 99/11/19: Re: implementing TCP/IP on PLD
    19443: 99/12/22: Re: Speed grade
    20840: 00/02/23: Re: Looking for a small, fast CPU core for FPGA
    20899: 00/02/25: Re: Looking for a small, fast CPU core for FPGA
    23350: 00/06/23: Re: Error: Clock skew plus hold time of destination register exceeds register-to-register delay
    25814: 00/09/21: Re: Ethernet MII + bit ordering
    26036: 00/10/01: Re: Altera FPGA experts needed
    26037: 00/10/01: Re: multi-input adders in virtex ?
    26140: 00/10/05: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
    26172: 00/10/06: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
    26260: 00/10/10: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
    26261: 00/10/10: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
    26262: 00/10/10: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
    26263: 00/10/10: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
    26265: 00/10/10: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
    26266: 00/10/10: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
    26267: 00/10/10: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
    26268: 00/10/10: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
    26276: 00/10/10: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
    26285: 00/10/10: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
    26303: 00/10/11: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
    26309: 00/10/11: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
    26341: 00/10/12: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
    26342: 00/10/12: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
    26349: 00/10/12: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
    26379: 00/10/13: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
    26383: 00/10/13: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
    26916: 00/11/03: Re: Alliance under Linux?
    27215: 00/11/15: Re: jobs for FPGA designer (remote)
    27379: 00/11/20: Re: In the news
    27830: 00/12/11: Re: jtag for fpga
    27996: 00/12/19: Re: dual port ram for altera
    28435: 01/01/12: Re: Alliance for Linux
    28521: 01/01/16: Re: Alliance for Linux
    28522: 01/01/16: Re: revision control tools ??
    28523: 01/01/16: Re: http://www.datasheetlocator.com/nl
    28960: 01/01/31: Re: Advice on FPGA board.
    29304: 01/02/13: Re: Handel-C language.
    29321: 01/02/14: Re: Handel-C language.
    29541: 01/02/26: Re: cpul vs vhdl
    30477: 01/04/10: Re: Handel-C
    30478: 01/04/10: Re: free software
    30977: 01/05/07: Re: Shannon Capacity
jamie morken:
    13285: 98/11/24: Foundation 1.4 error message
    13330: 98/11/26: parallel cable III -> Spartan
    13707: 98/12/18: Re: MP3 and FPGA's
    14707: 99/02/12: Re: reconfiguring Logiblox ROM's
    14708: 99/02/12: XC6200 series
    14812: 99/02/18: four signals into array?
    14847: 99/02/19: Re: four signals into array?
    14848: 99/02/19: variable assignment in process or outside of process
Jamie Morken:
    15333: 99/03/19: Xilinx Vhdl "'event" synthesis problem
    15351: 99/03/19: Re: Xilinx Vhdl "'event" synthesis problem
    15389: 99/03/21: HDL-307 error
    15430: 99/03/23: Re: HDL-307 error
    15431: 99/03/23: big/little endian mishap
    15522: 99/03/29: virtex partial reconfiguration
    47682: 02/10/02: Re: Implementing Delta-Sigma ADC and DAC in Spartan IIE
    47725: 02/10/02: Re: Implementing Delta-Sigma ADC and DAC in Spartan IIE
    48394: 02/10/17: multiple clocks
    48468: 02/10/18: using the JTAG port for debugging
    48672: 02/10/22: clock divider
    48687: 02/10/22: Re: clock divider
    50264: 02/12/06: Clocking in a Spartan IIE
    50268: 02/12/07: Re: Clocking in a Spartan IIE
    50289: 02/12/07: Re: Clocking in a Spartan IIE
    50311: 02/12/08: Using DLL's
    50312: 02/12/08: Re: Clocking in a Spartan IIE
    50361: 02/12/09: Re: Clocking in a Spartan IIE
    56781: 03/06/15: xilinx webpack programming
    56783: 03/06/16: Re: xilinx webpack programming
    56834: 03/06/17: Re: xilinx webpack programming
    134405: 08/08/09: altera cyclone3 484BGA package
    134417: 08/08/09: altera cyclone3 vertical migration
    134499: 08/08/14: Re: altera cyclone3 484BGA package
    134587: 08/08/20: Re: altera cyclone3 vertical migration
    134651: 08/08/24: Re: altera cyclone3 vertical migration
    136282: 08/11/09: FIR filter in Quartus
    137034: 08/12/19: PLL and clock in altera cyclone 2 fpga
    137050: 08/12/21: filtering decimation of a signal
Jamie Neilson:
    23562: 00/06/30: Re: Canadian University
Jamie Sanderson:
    14531: 99/02/03: Re: VHDL clocked one-shot Implementation Problem
    14833: 99/02/19: Re: multiple clock domain problem
    14924: 99/02/25: Re: Where do I connect my reset pins to?
    15775: 99/04/13: Re: Placement constraints on LOGIBLOX instances
    16237: 99/05/11: Re: Synchronizer design?
    16265: 99/05/12: Re: Synchronizer design?
    16562: 99/05/28: Re: High speed with VHDL
    16779: 99/06/08: Re: LINE DELAYS USING RAMS
    17211: 99/07/09: Re: how to choose only a set of pins
    18097: 99/09/29: Re: Need help programming Spartan FPGA with Atmel serial EEPROM
    18880: 99/11/19: Virtex: Getting flip-flops into the pads
    18936: 99/11/22: Re: Virtex: Getting flip-flops into the pads
    19156: 99/12/02: Re: Connection of light diode and FPGA
    19157: 99/12/02: Re: Tristate bidirectional pads with Xilinx
    19178: 99/12/03: Help with ROM in Xilinx Virtex
    19182: 99/12/03: Solution: ROM in Xilinx Virtex
    19211: 99/12/06: Re: Help with ROM in Xilinx Virtex
    19248: 99/12/08: Re: Is there two-read one-write asynchronous SRAM in FPGA?
    21537: 00/03/24: Altering Xilinx FPGA version/ID after PAR
    21663: 00/03/28: Re: Altering Xilinx FPGA version/ID after PAR
    22200: 00/05/01: Re: Initial DFF value for Virtex in VHDL
    25248: 00/09/01: Re: More than 4 clocks in virtex
    25252: 00/09/01: Virtex-E DLL Question
    25794: 00/09/20: Re: VHDL to SCHEMATIC
    26835: 00/10/31: Re: Alliance under Linux?
    27104: 00/11/10: Virtex 32x1 RAM - Prevent usage
    27727: 00/12/05: Route/Logic delay ratio
    27913: 00/12/14: Re: VHDL technique for synchronizer ?
    27914: 00/12/14: Re: Is it necessary to synchronize the reset signal in an FPGA ?
    27915: 00/12/14: Re: Verilog or VHDL
    27977: 00/12/18: Re: Verilog or VHDL
    28414: 01/01/11: CRC - from long division to XOR, how?
    28436: 01/01/12: Re: CRC - from long division to XOR, how?
    28501: 01/01/15: Re: CRC - from long division to XOR, how?
    28624: 01/01/18: Re: CRC - from long division to XOR, how?
    28626: 01/01/18: Re: revision control tools ??
    28645: 01/01/19: Re: revision control tools ??
    28789: 01/01/24: Re: Encryption is supported in new Virtex II but.....
    28863: 01/01/26: RAM reset question - Xilinx Virtex
    29211: 01/02/09: Re: Need help using bitgen
    29212: 01/02/09: Re: Low skew lines in Virtex-E
    29326: 01/02/14: Re: Duplicate definitions for timing specs (xilinx fnd)
    30258: 01/03/29: Re: PCI-X core
    30507: 01/04/11: Re: Changing Xilinx ROM contents without recompiling
    32027: 01/06/11: Xilinx PCI core location constraints
    32125: 01/06/14: Re: Xilinx PCI core location constraints
    32645: 01/07/04: Re: Is the Grass Greener for an Engineer in the USA?
    32653: 01/07/04: Re: Is the Grass Greener for an Engineer in the USA?
    32704: 01/07/05: Re: How to estimate the number of CLBs ?
    32971: 01/07/13: Re: Xilinx BRAM failures
    33227: 01/07/19: Re: 30 m cable reception with APEX LVDS I/O ?????
    33325: 01/07/23: Re: Synchronous output enable not supported?
    34146: 01/08/15: Internal clock skew when using DLL
    34153: 01/08/15: Re: Internal clock skew when using DLL
    34154: 01/08/15: Re: Internal clock skew when using DLL
    34207: 01/08/16: Re: Internal clock skew when using DLL
    34249: 01/08/17: Re: Internal clock skew when using DLL
    34261: 01/08/17: Re: Internal clock skew when using DLL
    35115: 01/09/21: Xilinx PCI bridge reference design
    35237: 01/09/26: Re: Logical constraints of LUT
    35238: 01/09/26: Re: Virtex 2 : using IOB registers
    36026: 01/10/26: Re: future Xilinx products wish list ...
    69707: 04/05/18: Re: Drive strength on I/O pads
<jamiehl@gmail.com>:
    99241: 06/03/21: need help with vhdl code in custom IP
Jamil:
    50893: 02/12/22: Compiling Altera LPM on leonardo
    51001: 02/12/25: Free Opne hardware designs and tools on CDROMs
Jamil Hayder:
    158511: 15/12/09: Error in converting code to VHDL
Jamil Khaib:
    17646: 99/08/18: Re: fpga board : make it or buy it?
    17993: 99/09/21: Free Hardware "CPLD board"
    18259: 99/10/11: GNU License for Hardware
    18356: 99/10/18: free Online ASIC course
    19492: 99/12/26: FIFO design
    19520: 99/12/29: USB2 core call for Volunteers
    19521: 99/12/29: OpenIPCore call for examples
    19522: 99/12/29: sim error & webfitter
    19547: 99/12/30: Re: USB2 core call for Volunteers
    19727: 00/01/10: PCI/USB project started
    19745: 00/01/11: HW resources increased
    19787: 00/01/12: Re: PCI/USB project started
    19819: 00/01/13: call for comments
    19904: 00/01/17: Design flow needed
    19906: 00/01/17: Re: Partly reprogrammable FPGAs
    19920: 00/01/18: Cores interfaces
    20010: 00/01/23: Re: WebFitter???
    20216: 00/02/01: part time
    20268: 00/02/03: please help me
Jamil Khatib:
    14168: 99/01/16: Run-Time-Reconfigurable logic
    15512: 99/03/29: FIFO design
    15579: 99/04/01: Re: IP cores and software industry
    15713: 99/04/09: Re: Reconfigurable Computing
    15715: 99/04/09: Re: Does any one want to talk about Dynamic Configuration?
    15716: 99/04/09: Re: FIFO
    15964: 99/04/23: JBITs
    16600: 99/05/29: Modelsim, VHDL & mem core
    17230: 99/07/12: Memory cores
    17235: 99/07/13: OpenIP Call for contribution
    20519: 00/02/13: FPGA verification
    20535: 00/02/14: LUT & VHDL
    20915: 00/02/27: clocked or not clocked?
    21632: 00/03/27: Stimulus generator
    21738: 00/03/30: Memory cores
    21824: 00/04/02: Re: RISC/CISC Processor with Reconfigurable Logic
    21900: 00/04/06: Power up set
    21963: 00/04/10: Distributed Arithmetic
    21989: 00/04/11: LUT
    21991: 00/04/11: LUT
    21988: 00/04/11: LUT
    21990: 00/04/11: LUT
    22023: 00/04/13: Parallel to serial
    22070: 00/04/18: Re: synchronous FIFO
    22125: 00/04/26: Foundation 2.1i
    22127: 00/04/26: Re: Any good third-party place and route tools?
    22215: 00/05/02: random integer
    22293: 00/05/04: Vital glitch
    22500: 00/05/10: Re: Hardware TCP/IP stack?
    22963: 00/06/06: Re: DCT and FPGA !!!!
    22964: 00/06/06: Free tools "OpenTech cdrom"
    23051: 00/06/11: Virtex questions
    23129: 00/06/15: Re: FIFO design
    23269: 00/06/20: Re: FIFO design
    23452: 00/06/26: Canadian University
    23933: 00/07/16: Re: FPGA Intro
    24078: 00/07/26: Arithmetic Operators
    24084: 00/07/26: Variable shifting
    24235: 00/07/31: Re: Variable shifting
    24272: 00/08/02: FPGA selection
    24299: 00/08/03: Re: FPGA selection
    31322: 01/05/18: CDROMs with Free tools and designs
    31449: 01/05/24: Vhdl coding style for fpga
    31470: 01/05/26: Internal tri states
    31625: 01/05/31: Help in FIFO design
    31734: 01/06/05: FPU IEEE-754 calculation
    137250: 09/01/05: OpenTech Package
<jamil.khatib@googlemail.com>:
    103711: 06/06/09: The 3rd International Electronics Design Contest for Students
<jamil.khatib@pmail.net>:
    24870: 00/08/21: Re: fifo;s
    24873: 00/08/21: OpenTech cdrom new release
    24874: 00/08/21: OpenTech cdrom new release
    25265: 00/09/03: Win a free OpenTech cdrom
<jamilkhatib75@yahoo.com>:
    89166: 05/09/07: OpenTech open source designs and tools
<jamilkhatib@my-deja.com>:
    24384: 00/08/06: Re: FPGA selection
Jamin:
    69295: 04/05/05: Re: JTAG, Master Serial Mode
jammurao:
    136198: 08/11/05: Usage of Rocket IO GTP for 32 bit interface
jams:
    115818: 07/02/21: up down lfsr
jan:
    46516: 02/09/02: synthesizing hard coded numbers
    154165: 12/08/24: Re: How do you do an incdir in Vivado
Jan:
    60455: 03/09/13: DDC design
    61456: 03/10/04: Re: Graphics rendering revisited
    135782: 08/10/16: Simulation
    135788: 08/10/16: Distributed Dual-Port RAM
    135789: 08/10/16: Re: Distributed Dual-Port RAM
    135810: 08/10/16: Re: Distributed Dual-Port RAM
    135830: 08/10/17: Re: Simulation
    135849: 08/10/17: Port mapping (combining components)
    135852: 08/10/17: Re: Port mapping (combining components)
    135871: 08/10/19: Field update
    136358: 08/11/12: Using the FF @ Port pin
    136363: 08/11/13: Re: Using the FF @ Port pin
    136902: 08/12/11: Re: How to insert ChipScope
    136977: 08/12/16: Microblaze without external ram
    137091: 08/12/22: Adding userports to a custom peripheral in XPS
    137105: 08/12/23: Re: Adding userports to a custom peripheral in XPS
    137278: 09/01/07: Re: Which revision control do fpga designers use (2009)
    138026: 09/02/04: Choosing RAM for microblaze and connecting it.
Jan Bernauer:
    78113: 05/01/25: Re: trouble setting up ISE 6.3i in linux
    86002: 05/06/20: Re: Microblaze address space and variables
Jan Bruns:
    74511: 04/10/13: HDL-Models of CLB/Slice
    74530: 04/10/13: Re: HDL-Models of CLB/Slice
    74690: 04/10/16: Re: SPARTANI II - PCI target logic - what code generates burst read ?
    74792: 04/10/19: alternatives to xst-map
    74801: 04/10/19: Re: alternatives to xst-map
    74826: 04/10/20: Re: alternatives to xst-map
    79765: 05/02/24: routing delays (Xilinx)
    79770: 05/02/24: Re: How to synthesize the xilinx ip core?
    79906: 05/02/25: Re: routing delays (Xilinx)
    81358: 05/03/22: VREF for SSTL out only / PCB
    81379: 05/03/22: Re: VREF for SSTL out only / PCB
    81851: 05/04/02: Re: [info] Sine generation
    81885: 05/04/04: Re: how to use both FFs in a CLB's slice using LOC or RLOC
    82029: 05/04/06: CPLD: collapse
    82032: 05/04/06: Re: collapse
    82096: 05/04/06: Re: collapse
    82103: 05/04/07: Re: CPLD: collapse
    136399: 08/11/14: purpose of MULTAND
    136409: 08/11/14: Re: purpose of MULTAND
    136491: 08/11/19: Spartan3 SRL16 + SliceFF, LUT stability
    136492: 08/11/19: Re: Linux on Microblaze
    136497: 08/11/19: Re: Spartan3 SRL16 + SliceFF, LUT stability
    136503: 08/11/19: Re: Spartan3 SRL16 + SliceFF, LUT stability
    136508: 08/11/19: Re: Spartan3 SRL16 + SliceFF, LUT stability
    136511: 08/11/19: Re: Spartan3 SRL16 + SliceFF, LUT stability
    136515: 08/11/19: Re: Spartan3 SRL16 + SliceFF, LUT stability
    136517: 08/11/19: Re: Spartan3 SRL16 + SliceFF, LUT stability
    136524: 08/11/20: Re: Spartan3 SRL16 + SliceFF, LUT stability
    136526: 08/11/20: Re: Spartan3 SRL16 + SliceFF, LUT stability
    136530: 08/11/20: Re: Spartan3 SRL16 + SliceFF, LUT stability
    136568: 08/11/22: Re: Small adders in XST?
    136570: 08/11/22: Re: Small adders in XST?
    136586: 08/11/24: Re: Small adders in XST?
    136621: 08/11/26: Re: added jitter on FPGAs
    136945: 08/12/15: Re: JTAG / IMPACT / VIRTEX
    137317: 09/01/08: Re: New to FPGA's, please help
    137441: 09/01/16: Re: Death of the RLOC?
    137444: 09/01/16: Re: Death of the RLOC?
    137461: 09/01/18: Re: Using memory blocks generated by CoreGen
    137499: 09/01/21: config prob with spartan3
    137507: 09/01/21: Re: config prob with spartan3
    137553: 09/01/22: Re: config prob with spartan3
    137661: 09/01/27: Spartan3: 3.3V IOB on 2.5V config lines
    137662: 09/01/27: Re: Spartan3: 3.3V IOB on 2.5V config lines
    137678: 09/01/27: Re: Spartan3: 3.3V IOB on 2.5V config lines
    137697: 09/01/28: Re: XST Makes Odd Choice
    137713: 09/01/28: Re: XST Makes Odd Choice
    137753: 09/01/29: Re: XST Makes Odd Choice
    137774: 09/01/29: Re: XST Makes Odd Choice
    137855: 09/02/01: Re: Heavily pipelined design
    137948: 09/02/03: Re: fpga reset
    137959: 09/02/03: Re: Why the second flip-flop in Virtex-6?
    137979: 09/02/03: Re: Why the second flip-flop in Virtex-6?
    137996: 09/02/03: Re: Why the second flip-flop in Virtex-6?
    138000: 09/02/04: Re: Why the second flip-flop in Virtex-6?
    153383: 12/02/14: LUT6 FPGAs and Carry Logic
    153384: 12/02/15: Re: Life after XDL
    153396: 12/02/15: Re: LUT6 FPGAs and Carry Logic
    153400: 12/02/16: Re: LUT6 FPGAs and Carry Logic
    153404: 12/02/17: Re: LUT6 FPGAs and Carry Logic
    153406: 12/02/17: Re: LUT6 FPGAs and Carry Logic
    153408: 12/02/17: Re: LUT6 FPGAs and Carry Logic
    157154: 14/10/18: Re: Fast and slow clocks
Jan Buytaert:
    59333: 03/08/15: jamplayer on WinXP ?
Jan C. =?iso-8859-1?Q?Vorbr=FCggen?=:
    46703: 02/09/06: Re: Hardware Code Morphing?
jan coombs:
    19304: 99/12/11: Re: Is there two-read one-write asynchronous SRAM in FPGA?
Jan Coombs:
    11788: 98/09/09: Re: 22V10 programming
    12848: 98/11/02: Re: Q: 3.3 V regulators suitable for XILINX - ?
    13950: 99/01/05: Re: Bit-Serial Multiplier
    36281: 01/11/05: Re: JTAG problem
    91122: 05/10/30: Re: Anyone remember the really early Xilinx FPGAs?
    96045: 06/01/28: Re: So Xilinx, is XDL and related libraries an available open source
    96649: 06/02/08: Re: Microblaze using SPI flash as instruction memory
    145108: 10/01/28: Re: Achronix FPGA
    148100: 10/06/21: Re: Programming the Actel Smartfusion Eval Kit in Linux
    148124: 10/06/22: Re: Programming the Actel Smartfusion Eval Kit in Linux
    148923: 10/09/10: Re: Want to get into FPGA
    151570: 11/04/20: Re: NibzX7 processor
    151584: 11/04/22: Re: NibzX7 processor
    151826: 11/05/21: Re: J1 forth processor in FPGA - possibility of interactive work?
    153113: 11/12/05: Re: Is it possible to save the FPGA state periodically?
    153721: 12/04/30: Re: Smallest GPL UART
    157792: 15/03/28: Re: Intel in Talks to buy Altera
    157952: 15/05/20: Re: AHDL VS. VHDL
    158049: 15/07/28: Re: Finally! A Completely Open Complete FPGA Toolchain
    158050: 15/07/28: Re: Finally! A Completely Open Complete FPGA Toolchain
    158052: 15/07/29: Re: Finally! A Completely Open Complete FPGA Toolchain
    158101: 15/08/07: Re: Is it possible to have a parameterized verilog module name in
    158177: 15/09/10: Re: Why is this group so quiet?
    159199: 16/09/01: Re: PALCE22v10 / GAL22v10 programming algorithms needed
    159296: 16/09/26: Re: learning verilog
    159310: 16/10/02: Re: learning verilog (or VHDL (or even MyHDL))
    159312: 16/10/02: Re: PALCE22v10 / GAL22v10 programming algorithms ... Found?
    159534: 16/12/03: Libre tools, was Re: Phrasing!
    159899: 17/04/24: Re: glitching AND gate
Jan De Ceuster:
    52244: 03/02/05: Re: Clock Enables
    52625: 03/02/17: Re: SoC pheripheral Design Resouraces
    52726: 03/02/20: Re: SoC pheripheral Design
    62162: 03/10/21: Re: Running Quartus II on ReadHat Linux 9.0
    62163: 03/10/21: Re: Running Quartus II on ReadHat Linux 9.0
    62201: 03/10/22: Re: Running Quartus II on ReadHat Linux 9.0
    62744: 03/11/06: Re: Creating a vector out of other vectors
    72363: 04/08/17: Re: Spooling from FPGA to the PC
    76561: 04/12/06: Re: quartus and pll
    76808: 04/12/13: altera DDR core simulation with NCSim
    76812: 04/12/13: Re: altera DDR core simulation with NCSim
    76814: 04/12/13: Re: UART receiver
    76815: 04/12/13: Re: UART receiver
    76839: 04/12/14: Re: altera DDR core simulation with NCSim
    76876: 04/12/15: Re: Cyclone device misteriously overheats
Jan Decaluwe:
    1813: 95/09/06: Re: Altera's Max+Plus2 vhdl output, bad!
    1875: 95/09/13: Re: REPOST: Design Contest Write-up ( was "Jury Verdict + Test Benches" )
    1895: 95/09/16: Re: REPOST: Design Contest Write-up ( was "Jury Verdict + Test Benches" )
    1894: 95/09/16: Re: REPOST: Design Contest Write-up ( was "Jury Verdict + Test Benches" )
    1897: 95/09/18: Re: REPOST: Design Contest Write-up ( was "Jury Verdict + Test Benches" )
    1898: 95/09/18: Re: REPOST: Design Contest Write-up ( was "Jury Verdict + Test Benches" )
    1981: 95/09/28: Re: REPOST: Design Contest Write-up ( was "Jury Verdict + Test Benches" )
    1980: 95/09/27: Re: REPOST: Design Contest Write-up ( was "Jury Verdict + Test Benches" )
    2060: 95/10/08: Re: REPOST: Design Contest Write-up ( was "Jury Verdict + Test Benches" )
    2102: 95/10/14: Re: REPOST: Design Contest Write-up ( was "Jury Verdict + Test Benches" )
    2103: 95/10/15: Re: REPOST: Design Contest Write-up ( was "Jury Verdict + Test Benches" )
    2586: 96/01/07: Re: Career value: VHDL or Verilog?
    10077: 98/04/26: Re: Make a delay in Xilinx FPGAs (Help)?
    23701: 00/07/05: Re: VHDL code for LFSR
    92926: 05/12/09: Re: ISE = Intelligent Synthesis Expectable :-)
    93038: 05/12/12: Re: ISE = Intelligent Synthesis Expectable :-)
    93462: 05/12/22: Re: More beginner's verilog questions
    93592: 05/12/25: Re: More beginner's verilog questions
    93972: 06/01/04: [ANNOUNCE] MyHDL 0.5 released
    94079: 06/01/05: Re: [ANNOUNCE] MyHDL 0.5 released
    94452: 06/01/11: Re: [ANNOUNCE] MyHDL 0.5 released
    99336: 06/03/23: Xilinx ISE tutorial revisited using MyHDL
    99337: 06/03/23: Xilinx ISE tutorial revisited using MyHDL
    99505: 06/03/25: Re: OpenSPARC released
    99731: 06/03/28: Re: OpenSPARC released
    99778: 06/03/29: Re: OpenSPARC released
    99783: 06/03/29: Re: OpenSPARC released
    101647: 06/05/04: Cordic-based Sine Computer in MyHDL
    101721: 06/05/05: Re: Cordic-based Sine Computer in MyHDL
    111042: 06/10/27: FPGA-based music synthesizer (with MyHDL)
    118880: 07/05/05: Re: Atom HDL
    118885: 07/05/05: Re: Atom HDL
    126234: 07/11/17: Re: VHDL language is out of date! Why? I will explain.
    126263: 07/11/18: Re: VHDL language is out of date! Why? I will explain.
    126496: 07/11/25: Re: VHDL language is out of date! Why? I will explain.
    126508: 07/11/26: Re: VHDL language is out of date! Why? I will explain.
    126587: 07/11/28: Re: VHDL language is out of date! Why? I will explain.
    127232: 07/12/14: Re: VHDL language is out of date! Why? I will explain.
    127233: 07/12/15: Re: VHDL language is out of date! Why? I will explain.
    137057: 08/12/21: Why MyHDL?
    137067: 08/12/21: Re: Why MyHDL?
    137079: 08/12/22: Re: Why MyHDL?
    137127: 08/12/24: Re: which HLL for HPC applications implementation?
    137340: 09/01/09: [ANNOUNCE] MyHDL 0.6 released
    138780: 09/03/10: Integer arithmetic in HDLs
    140655: 09/05/21: Re: Sigasi Public Beta: future of VHDL design
    140830: 09/05/27: Re: Online tool that generates parallel CRC and Scrambler
    140859: 09/05/27: Re: Online tool that generates parallel CRC and Scrambler
    141957: 09/07/19: Re: Do you prefer paper or plastic... er, I mean paper or e-books?
    142862: 09/09/04: Re: Choice of Language for FPGA programming
    144041: 09/11/09: Re: free software/open source projects and FPGA?
    144076: 09/11/10: [Announce] Jan on HDL Design
    144092: 09/11/11: Re: Jan on HDL Design
    145550: 10/02/14: Re: VHDL vs Verilog
    147036: 10/04/10: Re: I'd rather switch than fight!
    147037: 10/04/10: Re: I'd rather switch than fight!
    147047: 10/04/12: Re: I'd rather switch than fight!
    147125: 10/04/14: Re: I'd rather switch than fight!
    147151: 10/04/15: Re: I'd rather switch than fight!
    147188: 10/04/17: Re: I'd rather switch than fight!
    147230: 10/04/19: Re: I'd rather switch than fight!
    147249: 10/04/20: Re: I'd rather switch than fight!
    147261: 10/04/21: Re: I'd rather switch than fight!
    147295: 10/04/22: Re: I'd rather switch than fight!
    147305: 10/04/22: Re: I'd rather switch than fight!
    147307: 10/04/22: Re: I'd rather switch than fight!
    147318: 10/04/22: Re: I'd rather switch than fight!
    147342: 10/04/23: Re: I'd rather switch than fight!
    147362: 10/04/23: Re: I'd rather switch than fight!
    147395: 10/04/26: Re: I'd rather switch than fight!
    149883: 10/11/30: Re: Brain Cramps...
    149903: 10/12/01: Re: Brain Cramps...
    149929: 10/12/02: Re: Brain Cramps...
    150096: 10/12/13: Re: Brain Cramps...
    150108: 10/12/14: Re: Brain Cramps...
    150169: 10/12/24: [ANNOUNCE] MyHDL 0.7
    150212: 11/01/01: Re: I Give Up!
    150388: 11/01/15: Re: Verilog Book for VHDL Users
    150389: 11/01/15: Re: Verilog Book for VHDL Users
    152501: 11/08/29: A free lunch
    152514: 11/08/30: Re: A free lunch
    152515: 11/08/30: Re: A free lunch
    153836: 12/06/01: Re: PRNG
    153946: 12/07/02: Re: The definition of comnatorial prcess?
    153948: 12/07/02: Re: The definition of comnatorial prcess?
    153958: 12/07/03: Re: The definition of comnatorial prcess?
    154535: 12/11/25: VHDL expert puzzle
    154541: 12/11/25: Re: VHDL expert puzzle
    154547: 12/11/26: Re: VHDL expert puzzle
    154553: 12/11/27: Re: VHDL expert puzzle
    154555: 12/11/27: Re: VHDL expert puzzle
    154557: 12/11/28: Re: VHDL expert puzzle
    154563: 12/11/28: Re: VHDL expert puzzle
    154575: 12/11/29: Re: VHDL expert puzzle
    154580: 12/11/29: Re: VHDL expert puzzle
    154591: 12/11/30: Re: VHDL expert puzzle
    154592: 12/11/30: Re: VHDL expert puzzle
    154593: 12/11/30: Re: VHDL expert puzzle
    154597: 12/11/30: Re: VHDL expert puzzle
Jan Gray:
    501: 94/12/11: homebuilt processors using FPGAs (long)
    888: 95/03/22: Re: FPGA accelerated engines for volume rendering
    1973: 95/09/27: Re: FPGA for a 20k gates micro-controller
    2114: 95/10/17: "XACT 5.1 is incompatible with everything!!!!!!!!" -- a mild exaggeration, plus some Win95 hints
    2136: 95/10/19: Re: "XACT 5.1 is incompatible with everything!!!!!!!!" -- a mild exaggeration, plus some Win95 hints
    2203: 95/11/01: Re: small superscalar design ?
    2204: 95/11/01: Re: small superscalar design ?
    2392: 95/11/28: XBLOX vs. "CNets", lfsr dividers, etc.
    2707: 96/01/26: Re: HowTo access a SRAM with a XC4000
    2799: 96/02/09: Re: FPGA density
    2800: 96/02/09: Re: Performance Benchmarks: Emulating FPGAs Using General Purpose Processors
    2801: 96/02/09: Repost: Performance Benchmarks: Emulating FPGAs Using General Purpose Processors
    2849: 96/02/16: Re: New Reconfigurable Computing Threads. -- Java machines
    3180: 96/04/19: On FPGAs as PC coprocessors
    3263: 96/05/06: On FPGAs as PC coprocessors [rererepost]
    3350: 96/05/17: considering a new XC4010E/XC4013E proto board with RAM
    4397: 96/10/24: Re: Has anyone ever used a C -> Xilinx netlister?
    5071: 97/01/20: Re: advice request: CPUs vs. FPGAs again
    5080: 97/01/21: Re: FPGA with SRAM
    5688: 97/03/07: Re: Xilinx 4002 RAM Question
    6309: 97/05/14: Re: Cheap way to develop for FPGAs?
    6441: 97/05/24: Xilinx future features?
    6561: 97/06/03: Re: What is M1?
    6562: 97/06/03: Re: New Reconfigurable Computing newsgroup?
    7673: 97/10/02: FPGA multiprocessors
    7716: 97/10/07: Re: FPGA multiprocessors => vs. uniprocessors
    7717: 97/10/07: Re: FPGA multiprocessors
    7718: 97/10/07: Re: FPGA multiprocessors
    7723: 97/10/07: Re: FPGA multiprocessors => vs. uniprocessors
    7771: 97/10/14: Re: FPGA based CPU ideas, and novel extensions => distributed RAM and Altera CPUs
    9550: 98/03/22: Re: Dual port, new Altera FLEX 10KE EABs
    9573: 98/03/24: Re: Dual port, new Altera FLEX 10KE EABs
    9999: 98/04/21: Re: Could you help me save CLB's?
    10449: 98/05/19: Re: Minimal ALU instruction set.
    10506: 98/05/25: Re: [++] Fast Life code (Was:Re: FPGA-based CPUs (was Re: Minimal ALU instruction set))
    11083: 98/07/17: Re: Floorplanning Intro?
    11106: 98/07/19: Re: Too much advertising in this news group?
    11458: 98/08/16: RAMBUS for FPGAs -- was Re: Why is Intel *really* pushing rambus into desktop PCs ?
    11748: 98/09/06: Re: Altera 10K20 Register File Implementation??
    11814: 98/09/10: Re: Xilinx Spartan vs. 4K series
    11975: 98/09/22: Re: Efficient max-function architecture?
    11987: 98/09/22: Re: Efficient max-function architecture? -- "parallel bitwise max"
    12119: 98/09/30: Re: Efficient max-function architecture? -- "parallel bitwise max"
    12123: 98/09/30: Re: Efficient max-function architecture? -- "parallel bitwise max"
    12218: 98/10/05: Re: info requested for design course
    12374: 98/10/10: Re: Help Desperately Needed with Altera Microprocessor Design.
    12782: 98/10/29: Re: Q: Configure FPGA from an ISA bus?
    13327: 98/11/25: Re: Combining busses Xilinx
    13332: 98/11/25: Re: Xilinx 5.2/6 tools v M1.5 tools for an XC4013E part.....
    14755: 99/02/15: FPGA array computers
    15149: 99/03/09: Re: micro computer using Xilinx
    15729: 99/04/10: Re: FPGA vs CPLD? Any Experts out there?
    15741: 99/04/11: Re: FPGA vs CPLD? Any Experts out there?
    15763: 99/04/12: Re: FPGA vs CPLD? Any Experts out there?
    15768: 99/04/12: Re: FPGA vs CPLD? Any Experts out there?
    15880: 99/04/18: Re: Forth Processor
    16322: 99/05/15: Re: How synthesize tools concern with size of the design?
    16440: 99/05/21: The Economist article: "Hardware goes soft"
    16952: 99/06/18: Re: Read/Writes to memories/register files for PIC core
    16964: 99/06/21: Re: Read/Writes to memories/register files for PIC core
    16982: 99/06/22: Re: Question: Does FPGA Express 3.2 support RPMs?
    16983: 99/06/22: Xilinx "Virtex Configuration Architecture Advanced Users' Guide" appears
    17148: 99/07/03: Re: Floating point on fpga, and serial FP adders
    17185: 99/07/07: Alto in an FPGA (was CPU's directly executing HLL's)
    17406: 99/07/25: Re: Microcomputer buses for use inside FPGA/ASIC devices?
    17407: 99/07/25: Re: Microcomputer buses for use inside FPGA/ASIC devices?
    17424: 99/07/27: Re: Microcomputer buses for use inside FPGA/ASIC devices?
    17558: 99/08/10: Re: Emulating a transputer on FPGA
    17852: 99/09/14: Re: Relative Location attribute
    18442: 99/10/24: Re: xilinx foundation: bit_gen warning becasue of pullUps
    19246: 99/12/08: Re: Is there two-read one-write asynchronous SRAM in FPGA?
    19483: 99/12/24: regular expression matching and parsing in FPGAs (was chess...)
    19839: 00/01/14: Re: fastest 32 bit RISC
    19850: 00/01/14: Re: fastest 32 bit RISC
    21357: 00/03/20: "Building a RISC System in an FPGA" magazine series, and XSOC/xr16 RISC SoC
    21750: 00/03/30: Re: VGA interface and VHDL
    22040: 00/04/14: XSOC news: articles, Verilog, talk
    22800: 00/05/25: Re: 8087 in FPGA?
    23638: 00/07/04: on arbitrary m-cycle n-bit lfsrs
    23654: 00/07/04: Altera and Xilinx processor core announcements
    23684: 00/07/05: Re: on arbitrary m-cycle n-bit lfsrs
    23830: 00/07/12: C++/Java generators vs. synthesizers
    23851: 00/07/12: Re: C++/Java generators vs. synthesizers
    23867: 00/07/13: Re: C++/Java generators vs. synthesizers
    24383: 00/08/06: help -- of RAMs, FFs, latches, inverted clocks, and other curiosities
    24665: 00/08/16: Re: what does 0.35 micron mean
    24813: 00/08/19: Re: Xilinx Student Edition Floorplanning
    24882: 00/08/21: Re: Arg! 8051 - 6502 and friends
    24883: 00/08/21: hard FPGA CPU cores do not moot soft cores
    25065: 00/08/25: Re: help -- of RAMs, FFs, latches, inverted clocks, and other curiosities
    25077: 00/08/25: Re: help -- of RAMs, FFs, latches, inverted clocks, and other curiosities
    25086: 00/08/25: Re: help -- of RAMs, FFs, latches, inverted clocks, and other curiosities
    25107: 00/08/26: Re: help -- of RAMs, FFs, latches, inverted clocks, and other curiosities
    25386: 00/09/09: Re: How many 4005s (4010s) does it take to make a general purpose CPU?
    25388: 00/09/09: Re: How many 4005s (4010s) does it take to make a general purpose CPU?
    25879: 00/09/24: Re: Xilinx Student Edition 2.1i with "Digital Design:Principles and Practices"
    26057: 00/10/02: "Xilinx Adds FPGA Support to Free Web Design Tools"
    26064: 00/10/02: Re: multi-input adders in virtex ?
    26084: 00/10/03: Re: JVM processor
    26085: 00/10/03: Re: JVM processor
    26113: 00/10/04: Re: JVM processor
    26116: 00/10/04: Re: JVM processor
    26243: 00/10/09: Re: 68000 vhdl model
    26405: 00/10/15: 35 CLB 8-bit MCU
    26556: 00/10/20: Re: How safe is the algorithm implemented with FPGA?
    26996: 00/11/07: Re: ISO C -> VHDL translator, prefer open source
    27064: 00/11/09: FPSLIC
    27140: 00/11/12: Virtex circuit tricks -- add/mux in one LUT per bit
    27167: 00/11/13: Re: XC4000 maps better than Spartan2
    27212: 00/11/15: Re: Job posting info
    27258: 00/11/16: 8-way MIMD multiprocessor in an XCV50E
    27269: 00/11/16: Re: can FPGA perform float point calculaton?
    27389: 00/11/20: Re: 8-way MIMD multiprocessor in an XCV50E
    27613: 00/11/30: Re: Reverse-engineering FPGA's
    28285: 01/01/05: Re: Nondeterministic FSMs in hardware?
    28324: 01/01/06: Re: Update on nondeterministic FSMs in hardware
    28441: 01/01/12: Re: Stereo vision on Virtex
    28677: 01/01/20: Re: Synplicity newsgroup?
    28752: 01/01/23: Re: Designing fractional counters?
    28874: 01/01/26: XtremeDSP seminar comments -- Virtex-II 4xPowerPC chip multiprocessor!
    28882: 01/01/27: Re: RAM reset question - Xilinx Virtex
    28883: 01/01/27: Re: RAM reset question - Xilinx Virtex
    28966: 01/01/31: Re: Xilinx fast carry counter question
    29060: 01/02/04: Re: FPGA Conferences
    29103: 01/02/06: Re: switching Matrix, FPGA or CPLD? - smatrix.JPG (0/1)
    29174: 01/02/08: on making it too convenient to download PDFs
    29259: 01/02/11: Re: OT: IEEE & Floating point
    29266: 01/02/11: Re: Wired-or on Virtex FPGAs
    29268: 01/02/12: Re: New DES/AES (RIJNDAEL) Cores
    29564: 01/02/27: Re: Xilinx tools: RLOC hierarchy with HDL design?
    29580: 01/02/27: Re: Xilinx tools: RLOC hierarchy with HDL design?
    29943: 01/03/19: Re: TBUFs in Virtex and later chips, going out of fashion, what instead
    30027: 01/03/20: Re: TBUFs in Virtex and later chips, going out of fashion, what instead
    30068: 01/03/22: Re: reduced precision floating point
    30279: 01/03/30: Re: VIRTEX BLOCK RAM
    30460: 01/04/09: MicroBlaze
    30463: 01/04/09: Re: MicroBlaze
    30537: 01/04/12: Re: Is there any free processor core for vertex series?
    30763: 01/04/27: Re: Setting Pins High
    32599: 01/07/02: Re: xr16vx: a GPL 16-bit xr16 microcontroller in JHDL
    33752: 01/08/03: Re: 4 (8) bit Microporcessor Implementation
    33882: 01/08/07: Re: Spartan II and asynchronous memory interface
    34021: 01/08/11: Re: Reconfigurable Computational Accelerator
    35444: 01/10/04: Re: Barrel Shifter
    35677: 01/10/12: Re: High level synthesis will never work well :)
    35748: 01/10/16: Re: System Gates
    35856: 01/10/20: Re: I search a free 8086 core...
    36894: 01/11/23: Re: how to imply tristate buffer in APEX20K
    37028: 01/11/28: Re: SpartanIIE
    37428: 01/12/10: Re: where is designed FPGA for apple II computer...?
    38396: 02/01/13: Re: Homebrew computers using FPGA?
    38763: 02/01/24: Re: www.fpga.org
    38984: 02/01/29: Re: tri-state vs. Mux
    40106: 02/02/27: RAM32X1S, Virtex-II, 4.1i PAR travails
    40346: 02/03/05: Xilinx announces Virtex-II Pro is shipping
    40831: 02/03/16: Re: Difference between Virtex-II(E) und Virtex-E
    40833: 02/03/16: Re: Difference between Virtex-II(E) und Virtex-E, correction
    40902: 02/03/17: Re: Difference between Virtex-II(E) und Virtex-E
    41308: 02/03/25: Re: question on LFSR
    41322: 02/03/25: Re: question on LFSR
    41541: 02/04/01: Re: Laying out the design
    41568: 02/04/02: Re: powerpc in virtex2pro
    41631: 02/04/03: Re: powerpc in virtex2pro
    41764: 02/04/07: Re: powerpc in virtex2pro
    42552: 02/04/26: Re: Newbie Advice Please
    42599: 02/04/28: Re: Xilinx Easypath- Selling parts with known defects
    42831: 02/05/03: Re: Xilinx 2GB limit... something has to be done
    42847: 02/05/04: Re: Xilinx 2GB limit... something has to be done
    43503: 02/05/22: Re: fpga cpu
    46020: 02/08/14: Re: transputers
    46029: 02/08/14: Re: Xilinx tools: which one? Esp. schematic
    46092: 02/08/17: Re: Xilinx tools: which one? Esp. schematic
    46484: 02/08/31: Virtex/E/2/2P area efficient addmux, reiterating PAR timing modeler enhancement request
    46508: 02/09/01: Re: Virtex/E/2/2P area efficient addmux, reiterating PAR timing modeler enhancement request
    46518: 02/09/02: Verilog 2001 < VHDL
    46581: 02/09/03: MAP problem: Trivial RPM fails
    46582: 02/09/03: Warning: Xilinx 4.2i + Windows 2000 SP3 => blue screen of death
    46583: 02/09/03: Re: Warning: Xilinx 4.2i + Windows 2000 SP3 => blue screen of death
    46592: 02/09/03: Re: Warning: Xilinx 4.2i + Windows 2000 SP3 => blue screen of death
    46605: 02/09/04: Re: Any resource about MCU and DSP
    46837: 02/09/09: Re: minimalist FPGA system
    46941: 02/09/12: Re: Virtex/E/2/2P area efficient addmux, reiterating PAR timing modeler enhancement request
    47260: 02/09/21: Re: RPM zippering redux
    47316: 02/09/23: Re: Altera Cyclone low-cost FPGA chips?
    47396: 02/09/24: RPM_GRID (was MAP problem: Trivial RPM fails)
    47540: 02/09/27: Why no ROC for Xilinx Verilog sim and synthesis?
    47555: 02/09/28: Re: Why no ROC for Xilinx Verilog sim and synthesis?
    47560: 02/09/28: Re: Why no ROC for Xilinx Verilog sim and synthesis?
    47709: 02/10/02: Re: Help for Altera's FPGAs' pinout
    47763: 02/10/03: Re: TCP/IP in FPGA
    47764: 02/10/03: Re: TCP/IP in FPGA
    47818: 02/10/04: Re: TCP/IP in FPGA
    47819: 02/10/04: Re: TCP/IP in FPGA
    47820: 02/10/04: Re: TCP/IP in FPGA
    47827: 02/10/04: Re: TCP/IP in FPGA
    48388: 02/10/16: Re: Xilinx microblaze vs. picoblaze
    48398: 02/10/16: Re: Xilinx microblaze vs. picoblaze
    48513: 02/10/18: Re: Xilinx microblaze vs. picoblaze
    48515: 02/10/18: Re: Floorplanner RPM. How to use it?
    48522: 02/10/18: Re: Floorplanner RPM. How to use it?
    48610: 02/10/21: Re: Newbie Questions - Jan Gray XSOC
    48736: 02/10/23: Re: More Newbie Questions - What teaching resources
    48891: 02/10/25: Re: Xilinx microblaze vs. picoblaze
    49162: 02/11/03: Re: 16-bit FGPA CPU core (commercial)
    49163: 02/11/03: Re: 16-bit FGPA CPU core (commercial)
    49164: 02/11/03: Re: 16-bit FGPA CPU core (commercial)
    49276: 02/11/07: Project Navigator Console thumb behavior (was Re: Xilinx, where is DesignManager in ISE 5.1 ?)
    49333: 02/11/09: Re: Xilinx LUT-based FPGAs
    49354: 02/11/10: Re: LU-decomposition
    49420: 02/11/11: Re: LU-decomposition
    49463: 02/11/12: Re: LU-decomposition
    49465: 02/11/12: Re: HDL vs RTL
    50009: 02/11/28: Xilinx XC2S400E and XC2S600E
    50378: 02/12/09: Re: Tiny Forth Processors
    51561: 03/01/16: Re: 200K gates FPGA for GPU
    52979: 03/02/27: Re: picoChip - DSP as fast as an FPGA - is this for real
    53752: 03/03/21: Re: Using FPGAs as coprocessors in a PC
    54152: 03/04/03: Re: Internal net names on ISE Foundation
    54156: 03/04/03: Re: Internal net names on ISE Foundation
    55746: 03/05/18: Re: smallest embedded cpu....and the most pain?
    57650: 03/07/03: Re: Parallel processing
    61256: 03/10/01: Re: FPGA implementation of a lexer and parser - feasible?
    61368: 03/10/02: Re: Graphics rendering -- use a BRAM line buffer
    69851: 04/05/22: Re: Never right, always room for improvement
    70131: 04/06/04: Re: tri-state in altera and xilinx
    70132: 04/06/04: Re: tri-state in altera and xilinx
    70138: 04/06/04: Re: tri-state in altera and xilinx
    70191: 04/06/08: V4 teaser
    70192: 04/06/08: Re: V4 teaser, correction
    72513: 04/08/22: Re: XST synthesis
    73040: 04/09/11: Re: Need some help with some technical claims...
    74069: 04/10/03: Re: spartan-3 sram
    74376: 04/10/09: Re: add/sub 2:1 mux and ena in a single LE (Cyclone)
    75641: 04/11/11: Re: Internal architecture of lut
    76297: 04/11/30: Re: lowest-cost FPGA
    76560: 04/12/06: Re: internal tristates and busses
    77637: 05/01/13: Re: (d)ram interface
    78033: 05/01/23: Re: Master's Project
    78749: 05/02/07: Re: WARNING:Xst:382 - Why so many?
    81003: 05/03/16: Re: Register file with LUTs in a SPARTAN3
    81363: 05/03/22: Re: PowerPC soft-core?
    81375: 05/03/22: Re: PowerPC soft-core?
    81403: 05/03/23: Re: PowerPC soft-core?
    81426: 05/03/23: Re: PowerPC soft-core?
    81453: 05/03/24: Re: PowerPC soft-core?
    84822: 05/05/28: Re: Control asynchronous SRAM like synchronous SRAM
    117216: 07/03/27: Re: RISC implementation questions
    117219: 07/03/27: Re: RISC implementation questions
    117668: 07/04/06: Re: Transition from ASIC to FPGA
    117689: 07/04/07: Re: Transition from ASIC to FPGA
Jan Guffens:
    22667: 00/05/17: Re: c -> FPGA netlist compiler
    27001: 00/11/07: Re: ISO C -> VHDL translator, prefer open source
Jan Hansen:
    104886: 06/07/08: Re: Can I use all 18bits of a BlockRAM?
    104887: 06/07/08: Re: Fastest platform to run ISE?
    104904: 06/07/09: SP305- PROM configuration
    105022: 06/07/12: Re: Programming the Spartan-3E Starter Kit using Linux?
    105049: 06/07/12: Re: Development Boards -Your chance to suggest features
    105441: 06/07/23: Re: How to print a state flow graph for a state machine using Xilinx ISE or ModelSim
Jan Humme:
    5456: 97/02/17: Xilinx or Altera?
    5463: 97/02/18: Re: Xilinx or Altera?
    5464: 97/02/18: Re: Xilinx or Altera?
    5481: 97/02/19: Re: Xilinx or Altera?
Jan Kindt:
    28942: 01/01/30: Re: C2VHDL
    29030: 01/02/02: Re: Xilinx question
    30444: 01/04/08: Re: Spartan II Configuration
    30480: 01/04/10: Re: VHDL falling edge in Xilinx Foundation...
    59916: 03/09/01: BlockRam @ 333MHz
    60250: 03/09/09: Re: VGA display
Jan Krakora:
    120590: 07/06/11: Re: Problems to simulate (behavioural) in XPS
Jan Kubuschok:
    2266: 95/11/15: Xilinx XACT Windows Version
Jan Lellmann:
    22855: 00/05/27: Buying FPGAs in Germany
Jan Losansky:
    67796: 04/03/19: Spartan-3 DSL-KIT
    69250: 04/05/03: XILINX System Generator "fatal error"
    69274: 04/05/04: Re: XILINX System Generator "fatal error"
    83229: 05/04/26: Memec JTAG cable IJC-3
Jan Lucas:
    152366: 11/08/12: Re: Help needed to emulate a microcontroller.
Jan Maris:
    2504: 95/12/20: Altera related Qs.
Jan Martin:
    33478: 01/07/27: Re: 3.3i service pack 8
    33567: 01/07/30: Re: 3.3i service pack 8
    40651: 02/03/12: Re: Mystery two wire interface, or am I being dense?
Jan Martin Wagenaar:
    12749: 98/10/27: Re: DynaText **!?!?
    12750: 98/10/27: Re: DynaText **!?!?
Jan Mikkelsen:
    5373: 97/02/11: Re: DES Challenge
    20953: 00/02/29: Re: Extremely fault tolerant strategies
Jan Muska:
    6605: 97/06/05: NEED YOUR HELP - IN RETURN COULD WIN FREE ANTI-VIRUS SOFTWARE
Jan Panteltje:
    23163: 00/06/16: Re: Designing a narrowband bandpass filter to pass a tone (analog domain)
    53943: 03/03/28: Question about case statement in XilinX webpack
    53982: 03/03/29: More xilinx webpack verilog questions: always @(clock) legal?
    53986: 03/03/30: Re: More xilinx webpack verilog questions: always @(clock) legal?
    53987: 03/03/30: Re: More xilinx webpack verilog questions: always @(clock) legal?
    53988: 03/03/30: Re: Question about case statement in XilinX webpack
    55235: 03/05/01: Some general questions about WebPack and debugging and logic in FPGA and layout in the chip and...
    55275: 03/05/02: I want a 800 k gates FPGA in 40 pin DIL
    55294: 03/05/02: Re: I want a 800 k gates FPGA in 40 pin DIL
    55317: 03/05/03: Re: I want a 800 k gates FPGA in 40 pin DIL
    55318: 03/05/03: Re: I want a 800 k gates FPGA in 40 pin DIL
    55319: 03/05/03: Re: I want a 800 k gates FPGA in 40 pin DIL
    55519: 03/05/11: Re: I want a 800 k gates FPGA in 40 pin DIL
    55520: 03/05/11: Confused about timing report in clock doubler in XST
    55549: 03/05/12: OK I am pissed off with Xilinx webpack.
    55596: 03/05/13: Re: OK I am pissed off with Xilinx webpack.
    55646: 03/05/14: Re: OK I am pissed off with Xilinx webpack.
    55718: 03/05/16: Re: OK I am pissed off with Xilinx webpack.
    55829: 03/05/20: Re: OK I am pissed off with Xilinx webpack.
    55894: 03/05/22: Re: Xilinx : Tools
    57962: 03/07/10: Re: Fpga design with multiple audio rate (44, 48khz ...)
    59656: 03/08/25: Re: Interfacing to pc parallel port?
    59758: 03/08/27: Re: Free FPGA samples anywhere?
    60078: 03/09/04: Re: Input comparator
    60285: 03/09/09: Re: Impact error
    60335: 03/09/10: Re: Crystal Input to FPGA
    60512: 03/09/15: Re: fpga +cpu + wireless
    60553: 03/09/16: Re: Digilent board
    60574: 03/09/16: Re: fpga +cpu + wireless
    60879: 03/09/24: WARNING do not use your real email address in USENET postings! Swem/Gibe virus will spam you 1000x!
    61087: 03/09/27: Re: WARNING do not use your real email address in USENET postings! Swem/Gibe virus will spam you 1000x!
    61166: 03/09/29: Re: WARNING do not use your real email address in USENET postings!
    61307: 03/10/01: Re: Frustrations with Marketing
    61308: 03/10/01: Re: USB Core (Japanese Version)
    62996: 03/11/12: Trying to digitize video with CTT differential input, but webpack wont't cooperate...:-)
    63012: 03/11/12: Trying to digitize video with CTT differential input, but webpack wont't cooperate...:-)
    63062: 03/11/13: Re: Trying to digitize video with CTT differential input, but webpack wont't cooperate...:-)
    63064: 03/11/13: Re: Frequency Doubler - VHDL/Verilog
    63110: 03/11/15: Do I need to connect all Vref in a bank together?
    63119: 03/11/15: More basic questions about Spartan 2 IOB
    63130: 03/11/15: Re: More basic questions about Spartan 2 IOB
    63183: 03/11/17: Re: Do I need to connect all Vref in a bank together?
    63238: 03/11/18: Re: Do I need to connect all Vref in a bank together?
    63239: 03/11/18: Re: Do I need to connect all Vref in a bank together?
    63246: 03/11/18: Re: Do I need to connect all Vref in a bank together?
    63252: 03/11/18: Re: Do I need to connect all Vref in a bank together?
    63393: 03/11/20: Re: 400 Mb/s ADC
    63685: 03/11/29: Re: Digilent Inc.
    63716: 03/12/01: Re: about digilent board
    64035: 03/12/12: Question about filters and verilog etc..
    64043: 03/12/13: Re: Question about filters and verilog etc..
    64052: 03/12/14: Re: advantages of ethernet MAC ip core
    64251: 03/12/22: A simple horizontal frequency doubler PLL for TV line doubler.
    65296: 04/01/23: Re: Spirit on Mars
    65400: 04/01/27: Re: Image sensor?
    65840: 04/02/07: Re: Pricing, 101
    65903: 04/02/09: Re: Pricing, 101
    66774: 04/02/26: Re: SmartMedia writer (implments using VHDL)....
    66866: 04/02/28: Re: SmartMedia writer (implments using VHDL)....
    67694: 04/03/17: Re: FPGA protyping board (Avnet or others)
    68140: 04/03/27: Re: study verilog or vhdl?
    68218: 04/03/30: Re: Is there any Sync separator IP(Intellectual property) exists?
    68225: 04/03/30: Re: Is there any Sync separator IP(Intellectual property) exists?
    68230: 04/03/30: Re: Is there any Sync separator IP(Intellectual property) exists?
    68232: 04/03/30: Re: study verilog or vhdl?
    69419: 04/05/10: Re: SAA7111 YUV
    70016: 04/05/27: Re: Good Devlopement Board for learning
    70359: 04/06/14: 90nm Xilinx FPGA?
    70460: 04/06/17: Re: Xilinx ParallelCable IV vs. Linux
    70463: 04/06/17: Re: Xilinx ParallelCable IV vs. Linux
    70473: 04/06/17: Re: Xilinx ParallelCable IV vs. Linux
    70619: 04/06/22: Re: JTAG - XC2S200E-PQ208
    81022: 05/03/16: Re: Cheap 100mbit/s ethernet MAC/PHY daughterboard ?
    83443: 05/04/29: Re: Patent issues in implementing embedded fpgas
    84279: 05/05/16: Re: FPGA design under Mac OS X ?
    85794: 05/06/16: Re: Idea exploration - Image stabilization by means of software.
    86295: 05/06/24: Re: Xilinx webshop
    87486: 05/07/25: Re: Best Practices to Manage Complexity in Hardward/Software Design?
    88906: 05/08/31: Re: LCD Interface
    90643: 05/10/18: Re: Data2Mem usage - help required
    90846: 05/10/22: Re: .dat to .bit
    90888: 05/10/24: Re: a few questions
    90944: 05/10/25: Re: a few questions
    90978: 05/10/26: Re: 7.1i on Linux installation saga
    91259: 05/11/02: Re: FPGA C Compiler on sourceforge.net (TMCC derivative)
    91383: 05/11/04: Re: icarus verilog
    91394: 05/11/04: Re: icarus verilog
    91480: 05/11/07: Re: icarus verilog
    91482: 05/11/07: Re: Verilog Editor.
    91525: 05/11/08: Re: Verilog Editor.
    91661: 05/11/10: Re: open-sourced FPGA (vhdl, verilog, C variants) design libraries,
    92048: 05/11/21: Re: Sounds or other means to indicate end of compilation in Xilinx ISE
    92869: 05/12/08: Re: FPGA development board with digital image camera
    93075: 05/12/13: Re: mixed signal flash FPGAs launched!
    93076: 05/12/13: Re: mixed signal flash FPGAs launched!
    93278: 05/12/18: Re: Altera based Video development board
    93768: 05/12/30: Re: Power Optimization: can the routing and placement really save power?
    93892: 06/01/03: Re: CPU86 (Intel 8086) VHDL now available (thanks to HT-LAB !)
    93999: 06/01/04: Re: CPU86 (Intel 8086) VHDL now available (thanks to HT-LAB !)
    94365: 06/01/10: Downloading WebPack-8.1, server maxes out at 30 kB / second (= > 7 hours)?
    94375: 06/01/10: Re: Downloading WebPack-8.1, server maxes out at 30 kB / second (= > 7 hours)?
    94539: 06/01/13: Re: FPGA Journal Article
    94676: 06/01/16: Re: Don't even get me started on lead,
    95002: 06/01/20: Re: Xilinx padding LC numbers, how do you feel about it?
    95190: 06/01/21: Re: Irrelevant, stupid, racist, and worse.
    95201: 06/01/21: Re: FPGA-Programmable power supply
    95669: 06/01/25: Re: encryption
    95687: 06/01/25: Re: encryption
    95830: 06/01/26: Re: open source fpga programmer programs
    96105: 06/01/30: Re: Xilinx Legal
    96141: 06/01/30: Re: Xilinx Legal
    96972: 06/02/14: Re: digital logic library by 74xxxx part number?
    97236: 06/02/19: Re: help with VGA timings
    97317: 06/02/20: Re: help with VGA timings
    97498: 06/02/23: Re: Input stage for VHF frequency counter in an FPGA?
    97599: 06/02/24: Re: Combinatorial Division?
    97693: 06/02/26: Re: fpga to 5v ttl logic
    97763: 06/02/27: Re: Combinatorial Division?
    97788: 06/02/27: Re: Combinatorial Division?
    97789: 06/02/27: Re: Combinatorial Division?
    97790: 06/02/27: Re: Combinatorial Division?
    97853: 06/02/28: Re: FPGA communication, I2C and DAC
    98526: 06/03/12: Have webpack-81i running on grml Linux, rewrote ppcableIII jtag driver for Digilent to use direct io.
    98585: 06/03/13: Re: Have webpack-81i running on grml Linux, rewrote ppcableIII jtag driver for Digilent to use direct io.
    98659: 06/03/14: Re: fpga to 5v ttl logic
    98854: 06/03/17: Re: Where are FPGA heading?
    99126: 06/03/20: Re: ignore thread
    99147: 06/03/20: Re: FPGA FIR advice
    99148: 06/03/20: Re: Xilinx programming cable; Linux notebook w/o parallel port; Am I doomed?
    99499: 06/03/25: I am a bit stuck with error INTERNAL_ERROR:Xst:cmain.c:3068:1.158.10.1
    99543: 06/03/26: Re: XST takes unusually long
    99601: 06/03/27: Re: Altera web site inaccessible
    99629: 06/03/27: Re: Altera web site inaccessible
    99694: 06/03/28: Re: Altera web site inaccessible
    99737: 06/03/28: Re: Altera web site inaccessible
    100285: 06/04/06: Re: Xilinx Schematic Entry
    100380: 06/04/07: Re: Accessing compact flash?????????
    100656: 06/04/14: Re: Counting bits
    100669: 06/04/15: Re: Counting bits
    100699: 06/04/16: Re: Where is the xilinx online store gone?
    100731: 06/04/17: Re: Which is the best way to measure low frequencies?
    101301: 06/04/28: DRC has announced its newest FPGA that drops into AMD's Socket 940
    101444: 06/05/01: Re: FPGA Single LED Demos: FPGA board for a good ideas/suggestions
    101893: 06/05/08: Re: Can an FPGA be operated reliably in a car wheel?
    101929: 06/05/08: Re: Can an FPGA be operated reliably in a car wheel?
    102096: 06/05/10: Re: Quartus II 6.0 available
    102232: 06/05/12: Re: JTAG tutorial
    102564: 06/05/17: Re: disappointing 550Mhz performance of V5 DSP slices
    102582: 06/05/17: Re: disappointing 550Mhz performance of V5 DSP slices
    102587: 06/05/17: Re: disappointing 550Mhz performance of V5 DSP slices
    102590: 06/05/17: Re: disappointing 550Mhz performance of V5 DSP slices
    103062: 06/05/25: Re: ISE sends sensitive information to Xilinx site!
    103063: 06/05/25: Re: ISE sends sensitive information to Xilinx site!
    103068: 06/05/25: Re: ISE sends sensitive information to Xilinx site!
    103072: 06/05/25: Re: ISE sends sensitive information to Xilinx site!
    103094: 06/05/25: Re: ISE sends sensitive information to Xilinx site!
    103149: 06/05/26: Re: ISE sends sensitive information to Xilinx site!
    103244: 06/05/29: Re: ISE sends sensitive information to Xilinx site!
    103541: 06/06/05: Re: Webpack larger than CDs
    104842: 06/07/07: Re: Chaos in FF metastability
    104967: 06/07/11: Re: High-speed DAC/ADC with FPGA
    104971: 06/07/11: Re: High-speed DAC/ADC with FPGA
    105088: 06/07/13: Re: Programming the Spartan-3E Starter Kit using Linux?
    105167: 06/07/16: Re: An idea for a product (FPGA/ASIC based)
    105524: 06/07/25: Re: 2Khz clock signal from 50Hz main frequency with ADPLL
    105531: 06/07/25: Re: 2Khz clock signal from 50Hz main frequency with ADPLL
    105753: 06/07/31: Re: Low Cost FPGA Charge Pump Power supply
    107191: 06/08/25: Re: high level languages for synthesis
    107233: 06/08/25: Re: high level languages for synthesis
    107256: 06/08/25: Re: high level languages for synthesis
    107331: 06/08/26: Re: high level languages for synthesis
    107486: 06/08/29: Re: high level languages for synthesis
    107729: 06/08/31: Re: Open-source CableServer for Impact (no more need for Jungo driver on Linux)
    107734: 06/08/31: Re: Open-source CableServer for Impact (no more need for Jungo driver on Linux)
    108367: 06/09/09: simplyrisc-s1 free core
    108699: 06/09/15: Re: Linear Interploation Algorithms
    110596: 06/10/18: Re: FIR filter fpga help
    110611: 06/10/18: Re: FIR filter fpga help
    112435: 06/11/22: Re: CORDIC FM Demodulation
    112440: 06/11/22: Re: CORDIC FM Demodulation
    112445: 06/11/22: Re: CORDIC FM Demodulation
    112446: 06/11/22: Re: CORDIC FM Demodulation
    112693: 06/11/27: Re: CORDIC FM Demodulation
    114721: 07/01/23: Re: Surface mount ic's
    114783: 07/01/24: Re: Surface mount ic's
    114930: 07/01/26: Webpack-9.1 working on debian / grml
    115018: 07/01/29: Re: Installing Webpack 9.1 on "low-memory" machine (SUSE-10.2)
    115019: 07/01/29: Re: Installing Webpack 9.1 on "low-memory" machine (SUSE-10.2)
    115401: 07/02/09: Re: ISE 9.1 Installation crash SuSE 10.2
    117184: 07/03/26: Re: Where is Open Source for FPGA development?
    117518: 07/04/03: Re: Help with a face recognition system
    117536: 07/04/03: Re: Help with a face recognition system
    117575: 07/04/04: Re: Help with a face recognition system
    118252: 07/04/20: Re: Free Hardware
    118257: 07/04/20: Re: Free Hardware
    118754: 07/05/03: Re: Video scaler for Spartan 3E?
    120958: 07/06/21: Re: Can anyone identify the manufacturer of this Chip ?
    120961: 07/06/21: Re: Can anyone identify the manufacturer of this Chip ?
    120971: 07/06/21: Re: Can anyone identify the manufacturer of this Chip ?
    120972: 07/06/21: Re: Can anyone identify the manufacturer of this Chip ?
    120980: 07/06/21: Re: Can anyone identify the manufacturer of this Chip ?
    120986: 07/06/21: Re: Can anyone identify the manufacturer of this Chip ?
    121739: 07/07/12: Re: Anyone really use those opensource CPUs (OR1K, Lattice Mico32,
    121753: 07/07/12: Re: Anyone really use those opensource CPUs (OR1K, Lattice Mico32,
    139427: 09/03/29: Re: added jitter on FPGAs
    142964: 09/09/10: An email from Altera
    154980: 13/03/14: The Raspberry Pi JTAG programmer
    156075: 13/11/22: Re: microZed adventures
    156088: 13/11/22: Re: microZed adventures
    156206: 14/01/17: Re: my first microZed board
    156213: 14/01/17: Re: my first microZed board
    156221: 14/01/18: Re: my first microZed board
    156497: 14/04/11: Re: on-chip bypass caps
    157982: 15/06/10: Re: PCIe card with FPGA and DAC
Jan Pech:
    33148: 01/07/18: Re: Spartan2XC2S30 vs ACEXEP1K30
    34403: 01/08/23: Re: DRAM burst mode
    34426: 01/08/24: Spartan-II & clock
    34431: 01/08/24: Re: Spartan-II & clock
    34508: 01/08/28: Re: Spartan-II & clock
    34519: 01/08/28: Re: Orcad Symbol
    34886: 01/09/13: Block RAM initialization
    34910: 01/09/13: Re: Block RAM initialization
    35771: 01/10/17: Re: Recommended Newsgroup
    35814: 01/10/18: Re: Firewire chipset
    35910: 01/10/23: New Spartan-II Evaluation Board
    38470: 02/01/15: Re: RS232 on Atmel ATSTK40 board
    39283: 02/02/05: Re: FPGA vs GAL : Lattice
    39929: 02/02/22: Re: Linux tools
    47647: 02/10/01: iMPACT in WebPACK 5.1
    48176: 02/10/12: Re: where can I find the FAQs for this news group???
    48182: 02/10/13: Re: where can I find the FAQs for this news group???
    48927: 02/10/27: Re: A PCI Data Aqcuisition Card Design
    48937: 02/10/27: Re: A PCI Data Aqcuisition Card Design
    49208: 02/11/05: WebPACK 5.1 SP2
    49217: 02/11/05: Re: WebPACK 5.1 SP2
    49248: 02/11/06: Re: webpack 5.1 under w2k
    49713: 02/11/19: Re: Free FPGA Development Board
    51881: 03/01/24: Re: Problems with "impact.exe" from ISE webpack 5.1
    53069: 03/03/03: Re: FPGA demo board schematic
    85040: 05/06/03: ISE under Linux: 32 vs 64 bits
    120174: 07/06/02: Re: Xilinx OPB External Memory Controller
    120199: 07/06/03: Re: Xilinx OPB External Memory Controller
    126065: 07/11/14: Re: Synthesis-place&route performance test.
    126067: 07/11/14: Re: VCD Files Viewer?
    126082: 07/11/14: USR_ACCESS_VIRTEX4 usage
    126184: 07/11/16: Re: USR_ACCESS_VIRTEX4 usage
    126383: 07/11/20: FPGA Editor (9.2.03i) under Linux x86_64
    126888: 07/12/05: Re: can't install Centos 5.1 x86_64 and Xilinx ISE 9.2 evaluation
    128558: 08/01/30: EPC in Xilinx EDK 9.2
    129207: 08/02/18: Re: Ballpark PLB frequency
    129284: 08/02/20: Re: scanf problem in EDk 9.1i (Microbaze)
    137984: 09/02/03: Re: Why the second flip-flop in Virtex-6?
    138724: 09/03/06: Re: make ise take ngc as source
    140243: 09/05/05: Re: Setting top level VHDL generics in XST
    141019: 09/06/02: Re: Xilinx GbE performance
    141022: 09/06/02: Re: Xilinx GbE performance
    141023: 09/06/02: Re: Xilinx GbE performance
    141895: 09/07/15: FPGA editor in Fedora 11 x86_64
    141958: 09/07/20: Re: FPGA editor in Fedora 11 x86_64
    141967: 09/07/20: Re: FPGA editor in Fedora 11 x86_64
    144061: 09/11/09: Re: Microblaze performance in V6
    144102: 09/11/11: Re: How to interface sgmii core to copper media ?
    145583: 10/02/15: Re: Can the Altera USB cable attach to a KVM XP VM?
    145584: 10/02/15: Re: Can the Altera USB cable attach to a KVM XP VM?
    145598: 10/02/15: Re: Can the Altera USB cable attach to a KVM XP VM?
    146970: 10/04/06: Re: Extract single bit from std_logic_vector ...
    147746: 10/05/21: Re: Xilinx FIFO cannot be written
    150546: 11/01/26: Re: strange problem with RTL
    152570: 11/09/15: Re: Can't get the Xilinx cable drivers installed on SL6.1 (RHEL
    153226: 12/01/12: Re: Can't get the Xilinx cable drivers installed on SL6.1 (RHEL
    154907: 13/02/12: Re: Vivado - Pack I/O Registers?
    154914: 13/02/13: Re: Vivado - Pack I/O Registers?
Jan Stumps:
    21150: 00/03/08: Q: Hitachi FPGA HD61J215P: Searching Infos!!!
Jan Tjernberg:
    32611: 01/07/02: Re: Is the Grass Greener for an Engineer in the USA?
    92773: 05/12/06: Re: XUP PLATFORM USB CHIPSCOPE COMPATIBILITY PROBLEMS
Jan Van Belle:
    46332: 02/08/26: Starting with VHDL
Jan Vermaete:
    16722: 99/06/04: Xilinx symbols, Viewlogic
    16758: 99/06/07: Re: Xilinx symbols, Viewlogic
    17201: 99/07/08: IEEE1394 core
    24712: 00/08/17: Re: how to use script file in the Design Manager
    28488: 01/01/15: Re: revision control tools ??
Jan Vorbrueggen:
    4824: 96/12/18: Re: ASICs Vs. FPGA in Safety Critical Apps.
    5061: 97/01/18: Re: ASICs Vs. FPGA in Safety Critical Apps.
    5195: 97/01/30: Re: ASICs Vs. FPGA in Safety Critical Apps.
    5264: 97/02/03: Re: ASICs Vs. FPGA in Safety Critical Apps.
    17574: 99/08/11: Re: Emulating a transputer on FPGA
    28352: 01/01/09: Re: Nondeterministic FSMs in hardware?
Jan Zegers:
    9267: 98/03/05: Re: Questions about creating personal package
    9394: 98/03/09: Re: Whats wrong with this method
    11822: 98/09/11: Re: 16 bit CRC
Jan Ziak:
    43215: 02/05/16: What properties has FPGA?
    43244: 02/05/17: Re: What properties has FPGA?
    43461: 02/05/21: Re: What properties has FPGA?
    43482: 02/05/22: Re: What properties has FPGA?
Jan-Hinnerk Reichert:
    46526: 02/09/02: Re: Hardware Code Morphing?
jan.kindt:
    125241: 07/10/18: Re: VHDL trivia?
<jan_mothers@hotmail.com>:
Janaka:
    123847: 07/09/05: Re: high bandwitch ethernet communication
<janbeck@gmail.com>:
    76982: 04/12/17: Re: about digilent board
    89653: 05/09/21: data logging via JTAG?
    89654: 05/09/21: Re: JTAG USB Circuit
    118495: 07/04/27: Is there a reset signal available in verilog in Xilinx FPGAs?
    122294: 07/07/25: Virtex-5 and powerpc
<jancooo@gmail.com>:
    157881: 15/05/08: Re: synthesis tool for systemc
jandc:
    67792: 04/03/19: Re: Why It Is not Recommended to Infer latches in VLSI Design...
    67985: 04/03/24: Re: study verilog or vhdl?
    79863: 05/02/25: Re: Synthesis question
    80638: 05/03/09: Re: RS232 VHDL-core
    81478: 05/03/24: Re: DDR SDRAM interface working with AMBA-AHB
Jane:
    31854: 01/06/06: Re: FPGA / starterkit / VHDL
    77388: 05/01/05: VCCO on bank 0
Jane Milton:
    49031: 02/10/30: Handel-C Coding for the Motorola 68HC11 chip
Janes:
    83956: 05/05/10: Re: Clock delay vs. clock skew
Janet Ellsworth:
    3757: 96/07/25: Question about books for FPGA
Janet Rivers:
Janet Tite:
    349: 94/10/26: NIM: FPD '95 - Call for Papers
Janick Bergeron:
    6315: 97/05/14: Re: VHDL or Verilog?
janigav:
    141276: 09/06/15: Ethernet y MicroBlaze with Spartan 3e starter kit
Jann:
    22769: 00/05/23: FPGA implementation of LCD controller
    22786: 00/05/24: Re: FPGA implementation of LCD controller
Janos Ero:
    21886: 00/04/05: Re: Memory cores
    21895: 00/04/06: Re: Memory cores
Janos Szamosfalvi:
    3982: 96/08/28: RAM inside FLEX 10k
    4124: 96/09/13: Re: How to Begin with FPGA design?
    4203: 96/09/25: Re: Q: PLD vs. FPGA
    4788: 96/12/15: Re: Fpga, Epld, cpld....
Jansyn:
    77462: 05/01/07: Showing schematic changes
    84644: 05/05/23: Re: VHDL vs. Schematic Capture
janusson:
    74855: 04/10/20: Re: How To Provide External Input & Output To Startix 1S40..?
Janusz Raniszewski:
    31884: 01/06/07: Re: FPGA & uC8031
    43447: 02/05/21: Re: fpga cpu
    43821: 02/06/04: Re: NIOS GNUPro tool chain + SDK for Linux
    43989: 02/06/08: Re: fpga cpu
    44924: 02/07/06: Re: Triscend: SDK CD-ROM : where ?
    46488: 02/09/01: Re: Thermoelectric Controller by FPGAs
    47622: 02/10/01: Re: TCP/IP in FPGA
    47875: 02/10/06: Re: Implementing Delta-Sigma ADC and DAC in Spartan IIE
JanW:
    142306: 09/08/03: ucf and clock pin placement on Spartan 3E?
    142311: 09/08/03: Re: ucf and clock pin placement on Spartan 3E?
jara:
    127716: 08/01/06: Re: How to connect a LED with a clock?
Jared:
    57886: 03/07/08: Leonardo changes name of lpm megafunction
Jared Bytheway:
    275: 94/10/11: Xilinx configuration
Jared Casper:
    145946: 10/03/01: Re: Spice simulation of IBIS details - model examples
Jared Church:
    21300: 00/03/16: Re: Difference between FPGA, PLD, CPLD ?
    21375: 00/03/21: Re: Clock disabling
    21453: 00/03/23: Re: Clock disabling
Jared L. Colflesh:
    1839: 95/09/08: looking for a book
<jared.pierce@gmail.com>:
    132477: 08/05/28: HDL - simulation vs synthesis
    132496: 08/05/28: Re: HDL - simulation vs synthesis
Jarek:
    40268: 02/03/04: Atmel back annotation problems
    64281: 03/12/24: VHDL-Xilinx-Simulation (signal not connected to port) ?
    80891: 05/03/14: Re: Trying to find some Actel A54SX16P FPGAs to purchase
Jarek Lis:
    1545: 95/07/12: Intel FLEXLogic
    1816: 95/09/06: Lattice ispLSI problem
Jarek Patrzalek:
    16641: 99/06/01: Fixed delay in FSM
Jarek Pawelczyk:
    77251: 05/01/01: Live Design Ev. Kit with Altera Cyclone
    77536: 05/01/10: Re: Configuration devices
Jarek Rozanski:
    121566: 07/07/08: LiveDesign, Altium [opinion]
    121605: 07/07/09: Re: LiveDesign, Altium [opinion]
    121964: 07/07/16: Re: Revisit: Altera vs Xilinx (NIOS II vs Microblaze)
    124658: 07/09/29: Re: Own soft-processor
    124744: 07/10/02: Re: Basic VHDL Development kit
    124808: 07/10/04: Re: How to do one hot state machine in verilog for Xilinx V5 using XST
JaReZ:
    119306: 07/05/16: Cyclone II can't enter configuration mode with EPCS1 active serial.
    119307: 07/05/16: Cyclone II can't enter in configuration mode with EPCS1.
Jari:
    64538: 04/01/06: Generate the first interrupt for MB XMK
    64593: 04/01/08: Re: Generate the first interrupt for MB XMK
JarJarJP12:
    92426: 05/11/29: Successful use of MGT on Virtex 4
    92505: 05/11/30: Re: Successful use of MGT on Virtex 4
    92506: 05/11/30: Re: Successful use of MGT on Virtex 4
    92565: 05/12/01: Re: Successful use of MGT on Virtex 4
Jarmo:
    47410: 02/09/25: PCB Design for Altera FPGA
    47813: 02/10/04: Re: PCB Design for Altera FPGA
    52130: 03/02/02: How to program Altera EPC1213
Jarod2046@gmail.com:
    121463: 07/07/04: Power PC Reference Design timing failed
Jaromir Kolouch:
    64677: 04/01/11: PCB for FG456: layers
<jaroslav.sykora@gmail.com>:
    126982: 07/12/07: Re: SDRAM and S3E - is the example broken?
Jaroslaw Cichorski Jr.:
    8021: 97/11/08: Fitter for PALASM without bug where to download ?
    13004: 98/11/10: Problem with the ABEL to Macro convertion in XILINX FB1.3
    13032: 98/11/12: Re: Problem with the ABEL to Macro convertion in XILINX FB1.3
Jaroslaw Guzinski:
    62161: 03/10/21: Altera programming problem
    62204: 03/10/22: Re: Altera programming problem
    62285: 03/10/24: Re: Altera programming problem
Jaroslaw Kaczynski:
    14778: 99/02/16: Re: Xilinx Foundation Base = Useless?
    16907: 99/06/16: Re: Recursive Structures under Aldec AVHDL3.3
Jaroslaw Kubica:
    21437: 00/03/22: Re: How to implement STARTBUF / GSR with SpartanXL and VHDL on FNDTN
    21572: 00/03/25: Re: Clock on non-dedicate pin
    21633: 00/03/27: Re: Clock on non-dedicate pin
    21660: 00/03/28: Re: Clock on non-dedicate pin
Jaroslaw Pawelczyk:
    94744: 06/01/17: Unassigned pins
    94748: 06/01/17: Re: Unassigned pins
Jarrod Wood:
    104990: 06/07/11: Xilinx Virtex-4 APU Controller Questions
Jas:
    36773: 01/11/20: AHDL to VHDL
    37245: 01/12/05: Altera to Actel conversion
jas:
    35022: 01/09/18: Xilinx FPGA development boards
    35057: 01/09/19: Xilinx equivalent gate count value in the *.mrp report
    35509: 01/10/08: FPGA reset
    44886: 02/07/04: glitches in back annotation
    148048: 10/06/16: Re: How to detect a sync and start of a frame in an optimal way
    149268: 10/10/12: Regarding Synchronization of multiple control signals
jasen:
    108324: 06/09/08: Re: Please help me with (insert task here)
    108383: 06/09/10: Re: Performance Appraisals
    118655: 07/05/01: Re: debounce state diagram FSM
    118686: 07/05/02: Re: debounce state diagram FSM
    118687: 07/05/02: Re: debounce state diagram FSM
Jasen Betts:
    121949: 07/07/16: Re: ESR Meter - design contest
    157972: 15/06/09: Re: PCIe card with FPGA and DAC
    159387: 16/10/21: Re: Microsoft's FPGA Translates Wikipedia in less than a Tenth of a
JASH:
    89970: 05/09/30: Re: I am planning to purchase a Virtex-4 Eval board.
    89971: 05/09/30: Re: Prevue - FPGA Dev Board Sale
    91574: 05/11/08: Re: BRAMs readback
    91576: 05/11/08: Re: old xilinx components
    91794: 05/11/13: Re: FPGA KIT recommendation
Jasim Khan:
    156149: 13/12/19: PPC 405 communication with custom IP ml403
    156151: 13/12/19: Re: ppc405 communication with custom ip ml403
    156615: 14/05/13: virtex4 software reset problem.
<jasimpson@gmail.com>:
    109257: 06/09/22: Altera configuring/programming for FLEX10KE with EPC2 - sof or pof?
jasmile:
    147742: 10/05/21: speed grade and temperature grade aren't marked??
Jasmine Hau:
    64903: 04/01/15: Can nios_gnupro support file system?
    64969: 04/01/16: Re: Can nios_gnupro support file system?
    65651: 04/02/04: Altera Nios UART communication
    71631: 04/07/25: Gate Count vs Logic Element (LE)
    71692: 04/07/27: Re: nios-run: waiting for target.......?
    71815: 04/07/31: Re: FPGA prototype board with ethernet interfaces
    71816: 04/07/31: LE and EAB on FPGA board
    79238: 05/02/15: How to use file input output function?
jason:
    48765: 02/10/23: Re: How full is too full?
Jason:
    33870: 01/08/07: Reconfigurable Computational Accelerator
    34140: 01/08/15: FPGA for Reconfigurable Computing
    34259: 01/08/17: Re: FPGA for Reconfigurable Computing
    37298: 01/12/06: XC6200
    65350: 04/01/25: Re: Spirit on Mars
    65391: 04/01/27: Re: Spirit on Mars, upsets on Earth -- does your vendor know? How?
    68863: 04/04/20: the No. of gates of Xilinx FPGA
    68866: 04/04/20: calculate the number of logic gate in FPGA
    80126: 05/03/01: MGT RXLOSSOFSYNC problem
    114399: 07/01/14: SDK 8.2 error 127
    117284: 07/03/27: longest webcase record
    148417: 10/07/21: Re: Announcing AjarDSP - an open source VLIW DSP
    152263: 11/07/29: Re: Bitstream compression
Jason A. Daughenbaugh:
    27908: 00/12/14: Re: Verilog or VHDL
Jason Agron:
    110831: 06/10/24: Re: Survey on Quartus SOPC/Nios-II
    120731: 07/06/15: Re: Build error for multiprocessor sytem.
    126577: 07/11/27: Re: 33+ Regs in PLB IPIF
    136971: 08/12/16: Re: Problem with infering BRAM in XST
    142656: 09/08/24: Re: Multiple Interrupt handling in XPS 8.2i
Jason Berringer:
    36778: 01/11/19: ISA interface
    36939: 01/11/26: Which vendor to choose
    37362: 01/12/08: ISA syncronization?
    37395: 01/12/09: Re: ISA syncronization?
    37587: 01/12/16: SPI interface in VHDL
    38045: 02/01/02: A Fast counter in VHDL?
    38067: 02/01/03: Re: A Fast counter in VHDL?
    38132: 02/01/06: Re: A Fast counter in VHDL?
    45706: 02/08/01: Division
    45964: 02/08/12: Re: Division
    51163: 03/01/04: conversions and some assistance please
    51285: 03/01/09: Re: conversions and some assistance please
    56825: 03/06/16: An All Digital Phase Lock Loop
    56866: 03/06/17: Re: An All Digital Phase Lock Loop
    57701: 03/07/03: constraints, etc
    58097: 03/07/14: Re: An All Digital Phase Lock Loop
    58639: 03/07/29: Re: binary to BCD assistance
    58745: 03/07/31: Re: binary to BCD assistance
    59195: 03/08/11: Webpack sees 2 clocks when there is only one
    59233: 03/08/12: Re: Webpack sees 2 clocks when there is only one
    62905: 03/11/10: Layout examples
    69380: 04/05/09: Re: VHDL Beginner: Reset a counter (instead of "000000000....000000") - better way ?
    70154: 04/06/05: Quick question
    70197: 04/06/08: Re: Quick question
    70237: 04/06/09: Re: Quick question
    71928: 04/08/03: Re: FPGA and RS422
    75064: 04/10/25: Re: Async reset
    75065: 04/10/25: Bus interfaces & FSMs
    74881: 04/10/20: Async reset
    75666: 04/11/11: asynchronous bus transfers
    75728: 04/11/13: Re: asynchronous bus transfers
    75729: 04/11/13: Re: asynchronous bus transfers
    75730: 04/11/13: Re: asynchronous bus transfers
    76147: 04/11/25: Re: Programming flash connected to CPLD via JTAG
    76530: 04/12/05: internal tristates and busses
    76592: 04/12/06: Re: internal tristates and busses
    77524: 05/01/09: constraints
    82172: 05/04/07: FPGA Layout question
    82206: 05/04/08: Re: FPGA Layout question
    82226: 05/04/08: Re: FPGA Layout question
    82371: 05/04/11: Re: FPGA Layout question
    82734: 05/04/17: Re: FPGA/Embedded courses online or near Toronto
    82755: 05/04/17: Re: FPGA/Embedded courses online or near Toronto
    85833: 05/06/16: Re: BGA Rework/Prototype Placement Anyone?
Jason Caulkins:
    11457: 98/08/16: SCSI core
    12580: 98/10/17: Re: PCI target code
Jason Chan:
    14907: 99/02/24: Batch compliation using Altera maxplus2?
Jason Cong:
    2353: 95/11/22: FPGA'96 Advance Program
Jason Crawford:
    3847: 96/08/08: Extended libraries for OrCAD/Xilinx schematic entry
    4150: 96/09/18: OrCAD schematic based multiplier for XC4000 series
    45384: 02/07/22: Clock-gating in Virtex-E parts
    47117: 02/09/18: linear-log converter required
    65696: 04/02/05: PS/2 Keyboard opencore (keyboard side) available ???
Jason Daughenbaugh:
    27522: 00/11/27: Re: Fifo design problem
    28020: 00/12/19: Re: 3V -> 5V clock signal level conversion
    29136: 01/02/07: Re: 8B/10B Encoding
    31923: 01/06/08: Re: Force tristate enable register into IOB
    32068: 01/06/12: Video Compression on an FPGA
    32844: 01/07/10: XC17S00XL vs XC17S00A
    35517: 01/10/09: Re: FPGA reset
    40933: 02/03/18: Re: Difference between Virtex-II(E) und Virtex-E
    41299: 02/03/25: Re: Missing Timing by 30,000 ns
    47326: 02/09/23: Re: Fast serial interconnect bus using spartan-II
    58126: 03/07/15: Re: programming a PLD/CPLD with a PIC?
    60716: 03/09/19: LVDS in Xilinx (Spartan-3)
Jason Flood:
    1840: 95/09/08: Re: Jury Verdict + Test Benches
Jason Gomez:
    1533: 95/07/10: FPGA modules compatible with 6u VME ???
    1511: 95/07/05: FPGA modules compatible with 6u VME
    1510: 95/07/05: FPGA modules compatible with 6u VME
Jason Hannula:
    50495: 02/12/11: Any experience with Altera Apex PCI Development Kit?
Jason Hou:
    1467: 95/06/26: Re: InOut Port in the Synopsys FPGA Compiler
Jason Hsu:
    133588: 08/07/04: HELP! How do I install Xilinx ISE WebPack?
    134478: 08/08/12: Using a Spartan 3 FPGA kit with a USB/DB9
    134481: 08/08/12: Re: Using a Spartan 3 FPGA kit with a USB/DB9
Jason Hu:
    89800: 05/09/26: How to run ngcbuild in windows xp environment?
    89803: 05/09/26: Re: How to run ngcbuild in windows xp environment?
    89805: 05/09/26: Re: question about creating RPM
Jason Lade:
    53335: 03/03/11: Interested in FPGA programming using systemc
Jason Langkamer-Smith:
    37519: 01/12/13: FPGA introduction
Jason LaPenta:
    39883: 02/02/21: Problems : INOUT not allowed, alternatives
Jason Lawley:
    31896: 01/06/07: Re: Xilinx RapidIO?
Jason Lewis:
    81273: 05/03/20: TPS75003 for FPGAs
jason lim:
    32164: 01/06/17: How to connect mp3 player with a hard disk
Jason Lohn:
    13538: 98/12/08: CFP: The First NASA/DOD Workshop on Evolvable Hardware
    14697: 99/02/11: 2nd CFP: THE FIRST NASA/DoD WORKSHOP ON EVOLVABLE HARDWARE
    14923: 99/02/25: EH'99 deadline extended to March 10
    16769: 99/06/07: Call for Participation: The First NASA/DoD Workshop on Evolvable
    19919: 00/01/18: CFP: The Second NASA/DoD Workshop on Evolvable Hardware
    21106: 00/03/07: REMINDER: CFP: The Second NASA/DoD Workshop on Evolvable Hardware
Jason Luska:
    151092: 11/03/05: IP Core Delivery Format Info
    151112: 11/03/08: Re: IP Core Delivery Format Info
Jason Moore:
    40770: 02/03/14: Re: Proto boards for labs
    41921: 02/04/10: Re: ChipScope ILA, cable requirements
Jason Morgan:
Jason Nunn:
    10405: 98/05/16: Re: Design/document/reference of motion encoder interface wanted
Jason Ozolins:
    87376: 05/07/22: Re: (x86 linux) SSE2 usage by simulation applications?
    88715: 05/08/26: Re: Library of eBooks on FPGA's and other programming stuff
Jason Pattison:
    14107: 99/01/14: Programmng ALTERA EPROMS
    15403: 99/03/23: Re: FLEX 10K question
    15659: 99/04/07: Re: newbie: FPGA suggestion
    16916: 99/06/17: Re: Altera EPC1 replacement?
Jason Phillips:
    46406: 02/08/28: Re: V2 Pipelined Embedded Mulitplier PAR issues
Jason Rosinski:
    93395: 05/12/21: Re: More beginner's verilog questions
    93418: 05/12/21: Re: More beginner's verilog questions
Jason Sewall:
    54545: 03/04/13: Re: Hardware acceleration for raytracing purposes
Jason Stratos Papadopoulos:
    33417: 01/07/26: prospects for tiny FPGA supercomputer?
    33455: 01/07/26: Re: prospects for tiny FPGA supercomputer?
    34028: 01/08/12: Re: prospects for tiny FPGA supercomputer?
Jason Sze:
    8775: 98/01/26: For sales - Electroinic components
Jason T. Wright:
    4263: 96/10/07: Re: FPGA for Reed-Solomon Codec
    4339: 96/10/17: Re: xc4000 and 2 clocks
    4547: 96/11/12: Re: UART FOR FPGAS
    4718: 96/12/05: Re: Memory Requirements
    4841: 96/12/19: Re: Cascaded serial PROMS
    5301: 97/02/05: Embedded SRAM in FPGAs
    5303: 97/02/05: Re: Duplicate PLD?
    5322: 97/02/06: Re: Xilinx Xact Step Software
    6054: 97/04/08: Re: Chip Temperature (was:Re: Sole source)
    6281: 97/05/08: Re: Xilinx .UCF file examples
    7453: 97/09/11: Re: Cheap (sub $10) hardwired FPGA? Which manufacturers?
    7780: 97/10/14: Re: How fast can fully pipelined XC4000 logic go?
    7782: 97/10/14: Re: Synopsys, XACT, XC4000: CLB estimates
    8037: 97/11/10: Re: FPGA basics please ?
    8184: 97/11/25: Re: AT17C256 problems
    8091: 97/11/17: Re: Xilinx Logiblox in Synopsys
    16496: 99/05/25: Re: Synthesis problem
    16498: 99/05/25: Re: Synthesis problem
    17909: 99/09/16: Re: xilinx v2.1i
    18796: 99/11/16: Re: FPGA Expess vs. Synplify vs. Leonardo Spectrum
    18824: 99/11/18: Re: FPGA to ASIC conversion
    18994: 99/11/23: Re: VHDL vs. schematic entry
    20491: 00/02/11: Re: xilinx
    21552: 00/03/24: Re: FPGA openness
    21553: 00/03/24: Re: FPGA openness
    23496: 00/06/27: Re: FPGA and ASIC
    23497: 00/06/27: Re: inferring global buffers in Leonardo?
    23685: 00/07/05: Re: Serial Number embedded in PROM.
    23686: 00/07/05: Re: 2.1i better than 1.5?
    23875: 00/07/13: Re: hold time errors in FPGA's ?
    25229: 00/08/31: Re: Latches
    25230: 00/08/31: Re: Synopsys Synthesis
    32092: 01/06/13: Re: who needs clk180
    32618: 01/07/02: Re: Modelsim waveform
    32797: 01/07/09: Re: Need some help using Synplify ... and also considering Xilinx
    36190: 01/11/01: Synplicity, Xilinx, & unwanted BUFGs
    37461: 01/12/11: Re: What do you like/dislike about place and route tools?
    37462: 01/12/11: Re: XNF file gets corrupted
    41383: 02/03/26: Re: Too many clocks
    42933: 02/05/07: Re: Timing Scores
    55190: 03/04/30: Re: Two RAMs in one slice
    55346: 03/05/05: Re: Two RAMs in one slice
Jason Tang:
    84271: 05/05/16: Re: Xilinx tools from the commandline
    84272: 05/05/16: Re: Impact Kernel 2.6
    84321: 05/05/17: Re: Xilinx "Free ISE WebPACK 7.1i" under Fedora core 3 ?
Jason Tayles:
    4567: 96/11/15: Job Post 2 Hardware Engineers Needed VHDL, FPGA $80
    4711: 96/12/05: US LA *Job Post* Vhdl, FPGA, Mentor Engineer Needed to $75/hr
Jason Thibodeau:
    145890: 10/02/26: Place and Route
    145908: 10/02/27: Re: Place and Route
    146015: 10/03/03: Re: Laptop for FPGA design?
    146051: 10/03/04: Looking for a USB JTAG cable
    146054: 10/03/04: Re: Place and Route
    146553: 10/03/22: Re: Why hardware designers should switch to Eclipse
    146559: 10/03/22: Standard cell library help
    146588: 10/03/23: Re: Standard cell library help
    146599: 10/03/23: Re: Standard cell library help
    146602: 10/03/23: Re: Standard cell library help
    146606: 10/03/23: Re: Standard cell library help
    146612: 10/03/23: Re: Standard cell library help
    146616: 10/03/23: Implementation of IWLS benchmark- Manual place and route
    146625: 10/03/24: Re: Implementation of IWLS benchmark- Manual place and route
    146639: 10/03/24: Ring Oscillator -> counter differences
    146654: 10/03/25: Re: Ring Oscillator -> counter differences
    146667: 10/03/25: XST optimization
    146712: 10/03/26: Re: XST optimization
    146713: 10/03/26: Re: Ring Oscillator -> counter differences
    146769: 10/03/28: Re: XST optimization
    146785: 10/03/28: Re: XST optimization
    146811: 10/03/29: Re: XST optimization
    146814: 10/03/29: Re: XST optimization
    146819: 10/03/29: Re: XST optimization
    146826: 10/03/29: Re: XST optimization
    146852: 10/03/30: Re: XST optimization
    147608: 10/05/06: Re: FPGA Compilation Time Windows vs Linux
    148614: 10/08/06: Re: Vendor Tool Stability
Jason Wang:
    535: 94/12/27: Re: fpga-compiler (synopsys)
    606: 95/01/18: Re: ACTEL and EXEMPLAR
Jason White:
    45340: 02/07/19: fpga or cpld?
Jason Whitwam:
    121564: 07/07/08: Question on Virtex2p DCMs usability
    121572: 07/07/08: Re: Question on Virtex2p DCMs usability
    121573: 07/07/08: Re: Question on Virtex2p DCMs usability
Jason Wu:
    82325: 05/04/11: XMD only operating in compatibility mode under Suse9.2 pro
    83857: 05/05/08: Parallel Cable IV operating in "Compatibility Mode" under linux kernel 2.6.x
    84584: 05/05/21: Re: How to download uClinux on Virtex4 Board.
    88899: 05/08/30: Re: Virtex4 : Downloading error
Jason Zheng:
    71146: 04/07/09: Re: Icarus Verilog for Windows
    80051: 05/02/28: Re: FPGA tool benchmarks on Linux systems
    80106: 05/03/01: Re: FPGA tool benchmarks on Linux systems
    80113: 05/03/01: Re: FPGA tool benchmarks on Linux systems
    80250: 05/03/02: timing diagram tool linux
    80521: 05/03/07: Re: state encoding in FSM for simple cases ?
    80523: 05/03/07: Re: state encoding in FSM for simple cases ?
    80526: 05/03/07: Re: state encoding in FSM for simple cases ?
    80530: 05/03/07: Re: state encoding in FSM for simple cases ?
    80531: 05/03/07: Re: state encoding in FSM for simple cases ?
    80577: 05/03/08: Re: state encoding in FSM for simple cases ?
    80679: 05/03/09: Re: Xilinx vs Altera high-end solutions
    80721: 05/03/10: Re: Xilinx vs Altera high-end solutions
    80723: 05/03/10: Re: Xilinx vs Altera high-end solutions
    80739: 05/03/10: Re: Xilinx vs Altera high-end solutions
    80810: 05/03/11: Re: Xilinx vs Altera high-end solutions
    81926: 05/04/04: Re: Stupid question
    82911: 05/04/19: actel blockram the easy way?
    83256: 05/04/26: Re: PCI plug n play and Graphics card implementation
    83312: 05/04/27: x on ml300?
    83324: 05/04/27: Re: x on ml300?
    86871: 05/07/07: Re: Verilog exponential operator issues in simulation (ISE 7.1 SP3
    93247: 05/12/16: Re: Inverter Chain Synthesis Problem
    96351: 06/02/02: Re: How will synthesizers handle these statements?
    99368: 06/03/23: Re: OpenSPARC released
    99746: 06/03/28: Re: OpenSPARC released
    99801: 06/03/29: Re: OpenSPARC released
    131582: 08/04/25: Re: Breaking News ... Accellera Verification Working Group Forming
    133174: 08/06/19: Re: which commercial HDL-Simulator for FPGA?
    133215: 08/06/20: Re: which commercial HDL-Simulator for FPGA?
    138410: 09/02/20: Re: GTKWave 3.2.0 for Windows is available
    142184: 09/07/28: Re: iCore7 vs Core2 simulation & FPGA tool performance?
    142583: 09/08/18: Re: GTKWave 3.2.2 for Windows is available
    144081: 09/11/10: Re: Jan on HDL Design
    146864: 10/03/30: Re: Which is the most beautiful and memorable hardware structure in
Jason Zimmernann:
    41961: 02/04/11: PCI Bridge Question
    41999: 02/04/12: Re: PCI Bridge Question
    42000: 02/04/12: Re: Difference between the Virtex and the Virtex II
<jason.hy.wu@gmail.com>:
    135523: 08/10/06: Re: Reading files from CF (microblaze 7 and plb)
    138318: 09/02/15: Re: ERROR:NgdBuild:604
jason.stubbs:
    82525: 05/04/13: Re: Xilinx VIIPro power supplies
    82574: 05/04/14: Re: Xilinx VIIPro power supplies
    82575: 05/04/14: Connecting Virtex2pro to Virtex4 via RocketIO MGT's
    82587: 05/04/14: Re: Connecting Virtex2pro to Virtex4 via RocketIO MGT's
    82598: 05/04/14: Re: Connecting Virtex2pro to Virtex4 via RocketIO MGT's
    83081: 05/04/22: Virtex 4 Power consumption
    83156: 05/04/25: Re: Virtex 4 Power consumption
    83184: 05/04/25: Re: Virtex 4 Power consumption
    83695: 05/05/05: System Ace: How many FPGA's in the JTAG chain before require buffers?
    84340: 05/05/17: Virtex 4 MGTVREF pin reference circuit
<jason.stubbs@gmail.com>:
    82508: 05/04/13: Re: Xilinx VIIPro power supplies
<jason_hatley@my-deja.com>:
    24680: 00/08/16: ASIC folks of all stripes needed in Spokane
    24681: 00/08/16: Re: ASIC ---- send resumes to
jasonal:
    102340: 06/05/15: uClinux on MicroBlaze: Can't ping now
<jasonf>:
    2608: 96/01/10: Re: Emulation for a wireless chip
    2634: 96/01/16: Re: Emulation for a wireless chip
    2718: 96/01/29: Re: Emulation for a wireless chip
<jasonkailuu@gmail.com>:
    155864: 13/10/06: VTR 7.0 Release Announcement
jasonL:
    115686: 07/02/16: Does Xilinx XST synthesize combinational divider?
    120406: 07/06/06: What should be taken care of when two FPGA broad connected together?
    120423: 07/06/06: Re: What should be taken care of when two FPGA broad connected together?
    128629: 08/01/31: Why use small resistor for Vcco voltage regulator
    128664: 08/02/02: Re: Why use small resistor for Vcco voltage regulator
    129297: 08/02/20: From ASIC RTL to FPGA, what are the things I should take care of?
    129410: 08/02/22: Re: From ASIC RTL to FPGA, what are the things I should take care of?
Jasper Hendriks:
    23903: 00/07/14: Need help with Maxplus and large bus multiplexer
    24582: 00/08/14: clock skew problem please help!!
    24706: 00/08/17: Re: clock skew problem please help!!
<jasuris@gmail.com>:
    123329: 07/08/23: ROUTING=CLOSED in Xilinx 9.1 PR tools
    123356: 07/08/24: Re: ROUTING=CLOSED in Xilinx 9.1 PR tools
Jatan C. Shah:
    1776: 95/08/30: Neede verilog model for xc4000 clb and xc4000 iob..
Jatan Shah:
    869: 95/03/17: Synopsys XACT Interface...
    910: 95/03/28: Memory in xc4000 using synopsys...
    969: 95/04/05: Xilinx simulation models for synopsys..
    1179: 95/05/11: Simulation of Xilinc components on VSS..
    1235: 95/05/19: Multi-chip partitioning for XC4k devices
Jatin Bhateja:
    128107: 08/01/15: Question on FPGA
<javaguy11111@gmail.com>:
    99648: 06/03/27: Re: OpenSPARC released
    99674: 06/03/27: Re: OpenSPARC released
    120053: 07/05/31: Can't get AREA_GROUP to work
    120060: 07/05/31: Re: Can't get AREA_GROUP to work
    120073: 07/05/31: Can't get AREA_GROUP to work
    120148: 07/06/01: Modular Design Example
    120154: 07/06/01: Re: Modular Design Example
    120223: 07/06/03: TBUF and modular design flow on spartan
    120250: 07/06/04: Re: TBUF and modular design flow on spartan
    120276: 07/06/04: Re: TBUF and modular design flow on spartan
<javaguy11111@yahoo.com>:
    76060: 04/11/23: Re: Low cost million gate Spartan 3 board?
Javi:
    105544: 06/07/25: Clock signal remains HIGH forever in Spartan-3 Starter Kit from Digilent
    105548: 06/07/25: Re: Clock signal remains HIGH forever in Spartan-3 Starter Kit from Digilent
Javi Diaz:
    36707: 01/11/16: Spartan2 - 5 V tolerance question
javid:
    43919: 02/06/06: Xilinx ise software?
    50392: 02/12/10: Xilinx ISE 5.1 Wait for statement unsupported??
    50430: 02/12/10: Re: Xilinx ISE 5.1 Wait for statement unsupported??
    50465: 02/12/11: Re: Xilinx ISE 5.1 Wait for statement unsupported??
    58071: 03/07/14: programming a PLD/CPLD with a PIC?
    58103: 03/07/14: Re: programming a PLD/CPLD with a PIC?
    58115: 03/07/15: Re: programming a PLD/CPLD with a PIC?
    58158: 03/07/15: Re: programming a PLD/CPLD with a PIC?
    60882: 03/09/24: Portable computer for FPGA/CPLD tools
    69293: 04/05/05: Max7000s: how to use the enable of the dffe flip-flop?
    69318: 04/05/06: Re: Max7000s: how to use the enable of the dffe flip-flop?
    69796: 04/05/20: Timing Questions?
    70714: 04/06/24: synchronizer and Reset question?
    73640: 04/09/27: MAX7000s GCLRn Pin input current?
    76214: 04/11/29: internal logic signal to global routing resource in QII?
<javidiaz@my-deja.com>:
    20956: 00/03/01: AMS board simple questions
    20979: 00/03/02: AMS board design advice asked
    28894: 01/01/28: Standard Deviation Moving Window
Javier =?iso-8859-1?Q?Fern=E1ndez?=:
    49919: 02/11/25: Help: Virtex-II Pro eval.brd for System Generator
    51156: 03/01/04: Re: Running 2 inter related programs on the FPGA
Javier =?iso-8859-1?Q?Fern=E1ndez?= Baldomero:
    45129: 02/07/13: Re: FPGA CPU?
    61224: 03/09/30: ISE WebPack 6.1 Impact problem
    61262: 03/10/01: Re: ISE WebPack 6.1 Impact problem
    61647: 03/10/08: Re: ISE WebPack 6.1 Impact problem
Javier Castillo:
    72681: 04/08/28: Re: SOC and ASIC ?
    72920: 04/09/08: Re: why systemc?
    72962: 04/09/09: Re: why systemc?
    73091: 04/09/14: Re: Newbie question systemc
    73103: 04/09/14: Re: why systemc?
    76806: 04/12/13: Re: Inferring dual port RAMs with different bus widths.
    76807: 04/12/13: Re: UART receiver
    77029: 04/12/20: New release of SystemC to Verilog translator
    80004: 05/02/28: SystemC to Verilog Translator v0.4
    80013: 05/02/28: Re: synthesis tool for systemc
    85893: 05/06/17: Xilinx FFT
    88058: 05/08/08: Hiding data inside a FPGA
    88128: 05/08/10: Re: Hiding data inside a FPGA
    88223: 05/08/12: Re: Delays in verilog
    88356: 05/08/16: Re: Modular design flow
    88408: 05/08/17: Re: FPGA-Based system design project
    88852: 05/08/30: Re: openrisc, jp1 jtag debug utility
    88901: 05/08/31: Re: openrisc, jp1 jtag debug utility
    90318: 05/10/10: systemc to verilog translator v0.5
    90424: 05/10/12: RAMB16 primitive write/read collision differences betweem virtex2 and virtex4
    90437: 05/10/13: Re: RAMB16 primitive write/read collision differences betweem virtex2 and virtex4
    90438: 05/10/13: Re: RAMB16 primitive write/read collision differences betweem virtex2 and virtex4
    90456: 05/10/13: Re: RAMB16 primitive write/read collision differences betweem virtex2 and virtex4
    90755: 05/10/20: Re: RAMB16 primitive write/read collision differences betweem virtex2 and virtex4
    90861: 05/10/24: Re: RS232 Uart for Virtex-II Pro
    92238: 05/11/24: Re: Access to long lines in Virtex-II
    92917: 05/12/09: Re: partial reconfig of Virtex-4 : iMPACT warning makes the chip pause
    92923: 05/12/09: Re: partial reconfig of Virtex-4 : iMPACT warning makes the chip pause
    92937: 05/12/09: Re: partial reconfig of Virtex-4 : iMPACT warning makes the chip pause
    93052: 05/12/13: Re: who can help me? i want to know the bitsream format of Virtex-II
    93289: 05/12/19: Re: Inverter Chain Synthesis Problem
    95658: 06/01/25: Re: Xilinx Partial Reconfiguration add-on module
    96979: 06/02/14: Re: dynamic partial reconfiguration of Xilinx Virtex-4 FPGAs
    97026: 06/02/15: Re: dynamic partial reconfiguration of Xilinx Virtex-4 FPGAs
    97608: 06/02/24: Re: OpenRisc 1200 on Spartan 3 - problems with stability and enabling cache
    101209: 06/04/27: Re: OpenRisc 1200 on a XUP
Javier Garcia:
    48602: 02/10/21: Buy Small quantities
    48670: 02/10/22: Buy fpga
Javier Lopez:
    93871: 06/01/02: Re: Actel Fusion
Javier Moran Carrera:
    239: 94/09/30: Area of a FPGA tile.
    494: 94/12/07: Any benchmark for FCMs?.
Javier Paricio Rodríguez:
    10792: 98/06/19: HELP. Anybody knows Orcad Express (VHDL)?
Javier SERRANO:
    27589: 00/11/29: Re: PLL vs DLL
    27972: 00/12/18: Help with encoder/decoder
Javier Serrano:
    47053: 02/09/16: Question about Virtex-II DCM's jitter
    47058: 02/09/16: Re: Question about Virtex-II DCM's jitter
    47065: 02/09/16: Re: Question about Virtex-II DCM's jitter
    47090: 02/09/17: Re: Question about Virtex-II DCM's jitter
<javier@world>:
    2485: 95/12/15: WAnted: correlator!!!!!
    2484: 95/12/15: WAnted: correlator!!!!!
jawahar ali:
    30807: 01/04/30: FPGA-CPLD
Jawahar Ali:
    31281: 01/05/16: PowerPC
Jawbreaker:
    111058: 06/10/27: Re: FPGA-based music synthesizer (with MyHDL)
<jaxato@gmail.com>:
    79525: 05/02/20: difficult to build counter, some help please : (
    79536: 05/02/20: Re: difficult to build counter, some help please : (
    80022: 05/02/28: Re: difficult to build counter, some help please : (
    80029: 05/02/28: Re: difficult to build counter, some help please : (
    80218: 05/03/02: Re: Signal Integrity, ground bounce, crosstalk, SSOs, BGA pin-outs, parasitic inductance...
    80229: 05/03/02: Re: Signal Integrity, ground bounce, crosstalk, SSOs, BGA pin-outs, parasitic inductance...
    80300: 05/03/03: How to readback a BRAM
    80408: 05/03/04: Re: How to readback a BRAM
    83860: 05/05/08: Re: Which chip should I use?
    92111: 05/11/22: Re: Sounds or other means to indicate end of compilation in Xilinx ISE
    92763: 05/12/06: XUP PLATFORM USB CHIPSCOPE COMPATIBILITY PROBLEMS
    92769: 05/12/06: Re: XUP PLATFORM USB CHIPSCOPE COMPATIBILITY PROBLEMS
    92772: 05/12/06: Re: XUP PLATFORM USB CHIPSCOPE COMPATIBILITY PROBLEMS
    92778: 05/12/06: Re: xilinx research labs
    93006: 05/12/11: Hello PPl, is there a way of locking a design (NGC) to a particular FPGA board?
    93047: 05/12/12: Re: Hello PPl, is there a way of locking a design (NGC) to a particular FPGA board?
    93147: 05/12/14: Re: Hello PPl, is there a way of locking a design (NGC) to a particular FPGA board?
    93190: 05/12/15: Re: Hello PPl, is there a way of locking a design (NGC) to a particular FPGA board?
    93259: 05/12/16: Re: Avnet hav2 s3e starter kit?
    96612: 06/02/07: Spartan3 Live Insertion with XC9572XL chip
    100072: 06/04/02: Re: KEEP_HIERARCHY
    100676: 06/04/15: Where is the xilinx online store gone?
    100685: 06/04/15: Re: Where is the xilinx online store gone?
    100696: 06/04/16: Re: Petition about the xilinx online store ?
    100707: 06/04/16: Re: Petition about the xilinx online store ?
    101283: 06/04/28: What would be the tariff classification of an FPGA development board?
    101358: 06/04/29: Re: What would be the tariff classification of an FPGA development board?
    101364: 06/04/29: Re: What would be the tariff classification of an FPGA development board?
    103110: 06/05/25: DSP48E, What are the internal implementations used?
    103115: 06/05/25: Re: DSP48E, What are the internal implementations used?
    103122: 06/05/25: Re: DSP48E, What are the internal implementations used?
    103704: 06/06/08: Re: stable, tested 6502 core
    107469: 06/08/28: Re: What is the truth about the Virtex5 ?
    138774: 09/03/09: Re: Image loading into FPGA - from computer
<jaxatwork1@gmail.com>:
    95367: 06/01/22: Re: Reading user data from PROM
<jaxatwork@gmail.com>:
    84490: 05/05/19: Re: Spartan 3 CPI
jay:
    133398: 08/06/26: NVRAM design in CPLD
    133405: 08/06/27: Re: NVRAM design in CPLD
    143440: 09/10/11: ncelab: *W,SDFINF warning when back annotating SDF
    143484: 09/10/12: How to get clocks from DCM that the duty cycle is not 1:1
    143511: 09/10/13: Re: How to get clocks from DCM that the duty cycle is not 1:1
    143514: 09/10/14: Re: How to get clocks from DCM that the duty cycle is not 1:1
    143535: 09/10/15: Re: How to get clocks from DCM that the duty cycle is not 1:1
    143559: 09/10/16: Re: How to get clocks from DCM that the duty cycle is not 1:1
    144140: 09/11/13: An incomplete Mux and Latch?
    144145: 09/11/13: Re: An incomplete Mux and Latch?
    144146: 09/11/13: Re: An incomplete Mux and Latch?
    151103: 11/03/06: Re: IP Core Delivery Format Info
    151106: 11/03/07: Re: IP Core Delivery Format Info
    151109: 11/03/07: Re: IP Core Delivery Format Info
    151327: 11/03/23: Re: pcb&bitstream
Jay:
    33657: 01/08/01: Re: What way for Xilinx to ASIC migration ?
    33658: 01/08/01: Re: Altera MPLD
    33772: 01/08/03: Re: UART problems
    34011: 01/08/10: Re: Question on use of FPGA in a special Data Aquisition system
    36508: 01/11/09: Re: speed of HW JPEG implementations
    36874: 01/11/22: Re: too large a 32 entry 3 read 2 write register file
    36875: 01/11/22: Re: slew rate of virtex output buffers figures
    36876: 01/11/22: Re: Fast Fourier Transformation - camera data
    36877: 01/11/22: Re: How can I solve the "clock" warning of synplify.
    38278: 02/01/10: Re: FPGA and CCD : any experience?
    38279: 02/01/10: Re: Interpreting Xilinx Timing Analyser report files
    38280: 02/01/10: Re: multiply (*) 11000000000
    38291: 02/01/10: Re: ASIC faster than VirtexII FPGA?
    38292: 02/01/10: Re: How do I use Altera's PLL megafunction to multiply some frequency ?
    38294: 02/01/10: Re: The speedest FPGA
    38295: 02/01/10: Re: ROM die area question
    38495: 02/01/15: Re: FPGA and CCD : any experience?
    38496: 02/01/15: Re: Altera Compiling Error..WHY?????
    38498: 02/01/15: Re: remainder
    38499: 02/01/15: Re: SYN_HIER attribute in synplify v7.0
    38500: 02/01/15: Re: variable declare
    38523: 02/01/16: Re: Synthesis in FPGA Express
    38734: 02/01/23: Re: Q: can ROM content affect logic syn result
    38740: 02/01/23: Re: APEX-II vs VIRTEX-II
    38742: 02/01/23: Re: Simple shift register not working
    38743: 02/01/23: Re: Xilinx Timing report question
    39232: 02/02/04: Re: RAM question
    39234: 02/02/04: Re: FPGA or Micro-controller in Lowpower designs?
    39236: 02/02/04: Re: LARGE ultra low power FPGA/CPLD recommendation
    39237: 02/02/04: Re: Dual ported RAM in SpartanII, output = ?????
    39238: 02/02/04: Re: Pin assignment on ACEX1K
    39239: 02/02/04: Re: Flex10KA vs MAX7000S
    39299: 02/02/05: Re: Virtex-II and SDRAM Controller at 133MHz
    39327: 02/02/06: Re: Making Altera development quicker
    39331: 02/02/06: Re: random
    39338: 02/02/06: Re: Making Altera development quicker
    39339: 02/02/06: Re: designing a protocol analyzer for proprietary serial bus
    39340: 02/02/06: Re: the cause of the simulation/synthesis mismatch
    39374: 02/02/07: Re: Which PC for ALTERA development tools ?
    39375: 02/02/07: Re: BRAM, clka too short setup time
    39377: 02/02/07: Re: Virtex2-3000 (XC2V3000) engineering samples and chipscope
    39426: 02/02/08: Re: Help on bus interface needed.
    39427: 02/02/08: Re: the cause of the simulation/synthesis mismatch
    39428: 02/02/08: Re: Multiple clock domein synchronization.
    39486: 02/02/11: Re: Help on bus interface needed.
    39520: 02/02/12: Re: Making Altera development quicker
    39521: 02/02/12: Re: Help on bus interface needed.
    39542: 02/02/12: Re: Help on bus interface needed.
    39573: 02/02/13: Re: Help on bus interface needed.
    39589: 02/02/13: Re: Is Leonardo spectrum OEM version for Altera limited?
    39774: 02/02/19: Re: Virtex-E BRAM timing
    39775: 02/02/19: Re: Maximum # of logic level
    39776: 02/02/19: Re: Edge selection with RAM
    39777: 02/02/19: Re: Multipliers in Altera FPGAs
    39778: 02/02/19: Re: FPGA: JTAG CABLE
    39792: 02/02/19: Re: Faster designs
    39794: 02/02/19: Re: Coolrunner and ISP
    39795: 02/02/19: Re: Xilinx IP Core multiplier performance
    39798: 02/02/19: Re: Clocking issues w/ CoolRunner & Webpack
    39829: 02/02/20: Re: Counter does not fit CPLD?
    39830: 02/02/20: Re: gate array
    39875: 02/02/21: Re: Need largest CPLD devices?
    39976: 02/02/22: Re: CPLD PROJECT
    40049: 02/02/25: Re: Comparison between two FPGAs- what is decisive factor?
    40050: 02/02/25: Re: Beginner Altera Questions
    40074: 02/02/26: Re: Beginner Altera Questions
    40075: 02/02/26: Re: Quartus (finding node)
    40108: 02/02/27: Re: Beginner Altera Questions
    40120: 02/02/27: Re: SDRAM+FPGA
    40146: 02/02/28: Synopsys Design Compiler
    40209: 02/03/01: Re: Synopsys Design Compiler
    40289: 02/03/04: Re: share two months salary with you if you have job information
    40290: 02/03/04: Re: What FPGA to use?
    40327: 02/03/05: Re: digital video PLL
    40329: 02/03/05: Re: share two months salary with you if you have job information
    40333: 02/03/05: Re: exceeding 2GB limits in xilinx
    40344: 02/03/05: Re: FPGA problems
    40469: 02/03/07: Re: Using a battery instead of Config device
    40470: 02/03/07: Re: Fast transmission
    40471: 02/03/07: Re: Virtex-II : Temperature Sensing Diodes
    40472: 02/03/07: Re: V-II DCM options
    40484: 02/03/07: Re: Clamping Diode in the I/O !!!
    40523: 02/03/08: Re: exceeding 2GB limits in xilinx
    40531: 02/03/08: Re: Sandwich board at ESC
    40612: 02/03/11: Re: Newbie choosing a language - Verilog, VHDL, or ABEL
    40613: 02/03/11: Re: Synopsys Design Compiler
    40623: 02/03/11: Re: high active and low active reset signal mixed in a design
    40624: 02/03/11: Re: floating pins
    40668: 02/03/12: Re: nOOb: wants to start using an fpga
    40669: 02/03/12: Re: floating pins
    40753: 02/03/14: Re: Synthesis tools comparison?
    40754: 02/03/14: Re: Difference between Virtex-II(E) und Virtex-E
    40797: 02/03/15: Re: where to start with constraining..
    40947: 02/03/18: Re: How to deal with a high fan-out net in FPGA.
    41000: 02/03/19: Re: High speed clock routing
    41020: 02/03/19: Re: 1,5V power supply?
    41021: 02/03/19: Re: Xilinx : Altera pin compatibility
    41023: 02/03/19: Re: state machine coding style
    41098: 02/03/20: Re: how to deal with signal pass through two clock domain
    41102: 02/03/20: Re: Possibility of RTL and Gate-level simulation dont match?
    41103: 02/03/20: Re: Fixed Point Library
    41584: 02/04/02: Re: pricing and gate count info
    41620: 02/04/03: Re: ByteblasterMV EPM7064S voltage problem
    41621: 02/04/03: Re: ACEX maximal clock...
    41622: 02/04/03: Re: Pullup of Spartan-2
    41672: 02/04/04: Re: ACEX maximal clock...
    41724: 02/04/05: Re: Help: Design a crystal oscillator in a Xilinx XCR3256XL
    41726: 02/04/05: Re: How to force Foundation to NOT use an ILB flop?
    41748: 02/04/06: Re: Distributed ram
    41749: 02/04/06: Re: How to probe internal signals from Xilinx netlist?
    41751: 02/04/06: Re: strange RAM timing problem (VirtexE)
    42229: 02/04/18: Re: 1000 I/O Pins -- What is cheapest FPGA?
    42236: 02/04/18: Re: fpga limitation
    42239: 02/04/18: Re: FPGA Timing Problem
    42245: 02/04/18: Re: prototyping an ASIC
    42252: 02/04/18: Re: GND Outputs being optimized out using FPGA Express 3.6.1 in ISE4.2.01
    42292: 02/04/19: Xilinx Easypath- Selling parts with known defects
    42295: 02/04/19: Re: fpga limitation
    42307: 02/04/19: Re: ModelSim closes for unknown reason
    42352: 02/04/21: Re: Xilinx Easypath- Selling parts with known defects
    42403: 02/04/22: Re: Xilinx Easypath- Selling parts with known defects
    42417: 02/04/23: Re: Maximum Usage in a Virtex FPGA
    42473: 02/04/24: Re: Using PAL/GAL/FPGA to replace CPU's (correct news group?)
    42474: 02/04/24: Re: Xilinx Easypath- Selling parts with known defects
    42503: 02/04/25: Re: Input Frequence
    42510: 02/04/25: Re: configuration mystery
    42743: 02/05/01: Vertex 2 IOB- unwanted flops inside
    42793: 02/05/02: Re: Vertex 2 IOB- unwanted flops inside
    42830: 02/05/03: Xilinx 2GB limit... something has to be done
    43152: 02/05/14: Re: Driving high speed external devices from an FPGA
    43153: 02/05/14: Re: Bus arbiter with low latency
    43225: 02/05/16: Re: 50 mA sink
    43602: 02/05/26: Re: Xilinx chip scope: Comments
    43603: 02/05/26: Re: P&R times
    43713: 02/05/30: Re: about Configure FLEX10K10 with 89c51
    43771: 02/06/01: Re: CMOS camera
    43809: 02/06/03: Re: Looking for FPGA board with USB interface
    43810: 02/06/03: Re: Pipelining
    43812: 02/06/03: Re: Clock double trigger problem
    43901: 02/06/05: Re: synthesis issue
    43902: 02/06/05: Re: Do I have metastability issues?
    43904: 02/06/05: Re: chipscope
    43934: 02/06/06: Re: xc3042
    43937: 02/06/06: Re: How to add delay in fpga(spartan)?
    44077: 02/06/11: Re: where did my MHz go!
    44080: 02/06/11: Re: OFFSET constraint for internal clock
    44102: 02/06/11: Re: burning a design
    44103: 02/06/11: Re: Busses & permutations
    44137: 02/06/12: Re: where did my MHz go!
    44141: 02/06/12: Re: virtual ground in Xilinx XC9572 CPLD?
    44195: 02/06/13: Re: clock gating by any other name...
    44196: 02/06/13: Re: constrains for external memory
    44201: 02/06/13: Re: fpga and ultra highspeed counters
    44479: 02/06/20: Re: 12 years experience in Digital HW/ FPGA design, looking for job in the US
    44480: 02/06/20: Re: fpga and ultra highspeed counters
    44519: 02/06/21: Re: Logic Minimization in Max+Plus II compiler
    44534: 02/06/22: Re: Bad Virtex2 devices - any similar experiences
    44625: 02/06/24: Re: skew control between different signals ?
    44626: 02/06/24: Re: Will this clock divider be good on hardware?
    44659: 02/06/25: Re: too hot fpga device
    44687: 02/06/26: Re: fast adders using HDL in Xilinx fpga
    44725: 02/06/27: Re: VIRTEX II DCM Question
    44757: 02/06/29: Re: VIRTEX II DCM Question
    44759: 02/06/29: Re: Altera equivalent for GAL 16V8
    44760: 02/06/29: Re: Programming a Xilinx CPDL with a Microcontroller
    44761: 02/06/29: Re: clock skew in quartus, not in maxplus
    44849: 02/07/02: Re: VHDL Compliation Problem in Synario
    44850: 02/07/02: Re: Converting to Altera Quartus
    45180: 02/07/14: Re: Sensitivity list (VHDL) & FPGA pin assignment
    45181: 02/07/14: Re: 6 parallel inputs to Mux? How?
    45219: 02/07/16: Re: I want to buy 4 Xilinx FPGA
    45251: 02/07/17: Re: problem porting sync write, async read RAM to Xilinx...
    45252: 02/07/17: Re: Security features
    45255: 02/07/17: Re: Xilinx (spartan 2) - SI even applies to the config pins
    45257: 02/07/17: Re: dsp v fpga
    45403: 02/07/22: Re: How could I generated an efficient 16*16 multiplier in Vertex-II?
    45405: 02/07/22: Re: Verilog newbie question
    45690: 02/08/01: Re: Who can compare the synthesis tools for me ?
    45875: 02/08/08: ... milk for free, Opencores?
    45876: 02/08/08: Re: Asynchronous signals recommendations?
    45877: 02/08/08: Re: Xilinx TIG
    45880: 02/08/08: Re: Xilinx hiring practises
    45937: 02/08/11: Re: ASIC conversion
    47294: 02/09/22: Re: Can a fpga replace external inverters in a crystal osc ?
    47427: 02/09/25: Re: PCB Design for Altera FPGA
    47428: 02/09/25: Re: Altera Cyclone low-cost FPGA chips?
    47474: 02/09/26: Re: Dual Port RAM
    47583: 02/09/29: Re: Chipscope cores
    47834: 02/10/04: Re: system item in synplify report
    47919: 02/10/07: Re: .13 micron - what does it indicate
    48106: 02/10/10: Re: Gate array & standard cell based design.
    48107: 02/10/10: Re: extreme cell usage minimization req.
    48155: 02/10/11: Re: How to keep components from being optimized out of VHDL
    48156: 02/10/11: Re: Sync Reset without clocks
    48464: 02/10/17: Re: Quartus design question
    48585: 02/10/21: Re: Transferring Design from XILINX --> ALTERA
    48626: 02/10/21: Re: Buy Small quantities
    48688: 02/10/22: Re: low power embedded FPGA
    48743: 02/10/23: Re: Serial PROM Configuration
    48746: 02/10/23: Re: Altera FPGA and EPLD Download ByteBlaster
    48751: 02/10/23: Re: clock divider
    48884: 02/10/25: Re: DLL and PLL in Xilinx and Altera
    48885: 02/10/25: Re: Who has some Lecture materialson I2C Bus?
    48886: 02/10/25: Re: GlobalReset hogging routing resources
    48936: 02/10/27: Re: #1's in verilog
    49044: 02/10/30: Re: Can we retaining EAB Data using BACK UP power SUPPLY for Vccint
    49045: 02/10/30: Re: GlobalReset hogging routing resources
    49078: 02/10/31: Re: How important is simulation?
    49145: 02/11/01: Re: How important is simulation?
    49146: 02/11/01: Re: FPGA convert to ASIC
    49177: 02/11/04: Re: Incremental design question
    49181: 02/11/04: Re: Excessive heating on Xilinx XC9500XL
    49336: 02/11/09: Re: LUT Consumption in Virtex-2
    49363: 02/11/10: Re: VersaRing
    49367: 02/11/10: Re: Unexplained signal interaction
    49368: 02/11/10: Re: Quicklogic PAsic problem
    49370: 02/11/11: Re: FPGA convert to ASIC
    49480: 02/11/12: Re: Registering inputs or outputs of modules
    49481: 02/11/12: Re: How to disable IOB register packing?
    49519: 02/11/13: Re: creating a fabric in an FPGA
    49821: 02/11/21: Re: clock enable timing analysis
    49822: 02/11/21: Re: Virtex timing problem
    49823: 02/11/21: Re: XCS-05-3PC84 and XCS10-3PC84 Question
    49824: 02/11/21: Re: programmable oscillator for Virtex-E (XCV2000E)
    49830: 02/11/21: Re: exp^x in virtex 2
    49902: 02/11/24: Re: What's the matter with "clock skew and data delay"?
    49917: 02/11/25: Re: What's the matter with "clock skew and data delay"?
    50015: 02/11/28: question about PCB traces for FPGA board... ?
    50017: 02/11/28: Re: Custom FPGA synthesis
    50121: 02/12/02: Re: string to int conversion
    50191: 02/12/04: Re: ISA bus VGA
    50192: 02/12/04: Re: Full-Page in SDRAM
    50193: 02/12/04: Re: Clock fan-out and other issues
    50255: 02/12/06: Re: Full-Page in SDRAM
    50256: 02/12/06: Re: meaning of system gates vs. logic gates?
    50449: 02/12/10: Re: question about fft vs. cross corelation in fpga
    50570: 02/12/12: Re: Two clocks for the same module
    50571: 02/12/12: Re: Distributed RAM in cyclone
    50604: 02/12/13: Re: Hold violation in synthesis but not fitting
    50605: 02/12/13: Re: Two clocks for the same module
    50606: 02/12/13: Re: Distributed RAM in cyclone
    50607: 02/12/13: Re: AN: FPGA-based Personal Logic Analyzer, 500MHz, $166
    50609: 02/12/13: Re: Can I use bus keeper like this?
    50697: 02/12/17: Re: Is it true that if you have a clock routed to non-clock resources then you are not allowed to use the clock nets?
    50698: 02/12/17: Re: Xilinx FPGA PAR warning
    50710: 02/12/17: Re: Video timing generator on a Flex 20K / Acex 1K.
    50903: 02/12/22: Re: I didn't understand altera's max+plus2 software to setting up.
    50904: 02/12/22: Re: FPGA Supercomputing opportunity
    51126: 03/01/02: Re: BP programmer questions, prices, alternatives
    52339: 03/02/06: Re: Clock Enables
    52390: 03/02/07: Re: Clock Enables
    56118: 03/05/29: Re: Multiply 19.44MHz with Virtex-II DCM
    56197: 03/05/30: Is something wrong with ISE5.1 simulation library
    56441: 03/06/05: ASIC prototype software
    57062: 03/06/23: Re: What's the difference between ASIC and FPGA?
    57064: 03/06/23: Virtex-II's IO Level?
    57229: 03/06/26: Everything need a reset?
    57616: 03/07/03: post-PAR simulation model
    57697: 03/07/04: Re: post-PAR simulation model
    57698: 03/07/04: Re: Everything need a reset?
    57776: 03/07/06: Re: DCM usage question
    58061: 03/07/13: Re: Graduation Day: My first 4-layer PCB
    58098: 03/07/15: Re: problems on using CLKDLL in Xilinx ISE
    58107: 03/07/15: Re: An All Digital Phase Lock Loop
    58219: 03/07/17: Re: An All Digital Phase Lock Loop
    58292: 03/07/19: Phase / frequency detector types
    58558: 03/07/26: Simple circuit / good design?
    58660: 03/07/30: PLL / DPLL phase question
    58792: 03/08/01: Re: PLL / DPLL phase question
    58853: 03/08/02: Re: PLL / DPLL phase question
    58883: 03/08/04: Gates Counting?
    58887: 03/08/04: Re: Gates Counting?
    58952: 03/08/05: Conflict found between ActiveHDL6.1 and ModelSim SE
    58999: 03/08/06: Re: Conflict found between ActiveHDL6.1 and ModelSim SE
    59044: 03/08/07: Re: Gates Counting?
    59076: 03/08/07: Re: Size does matter
    59285: 03/08/14: Anyone familiar with ispXPLD?
    59422: 03/08/19: Re: Anyone familiar with ispXPLD?
    59431: 03/08/19: Re: Anyone familiar with ispXPLD?
    59491: 03/08/20: Re: performance tweaking FPGA designs
    59697: 03/08/26: Multi-clock / clocking counter
    59722: 03/08/27: Asynchronous clock switching circuits vs. BUFGMUX
    59763: 03/08/27: Re: Multi-clock / clocking counter
    59861: 03/08/30: Re: DCM divide/phase problem
    59862: 03/08/30: Re: Selecting between two clock signals
    59982: 03/09/03: OT: Block diagramming tools?
    60065: 03/09/04: Flex6K configuration PROM
    60099: 03/09/05: Re: Flex6K configuration PROM
    60100: 03/09/05: Re: Flex6K configuration PROM
    60103: 03/09/05: Re: Flex6K configuration PROM
    60225: 03/09/08: Re: Flex6K configuration PROM
    62154: 03/10/21: Re: please help, modelsim does not simulate
    62397: 03/10/29: Re: BoardScope
    62400: 03/10/29: Re: Virtex-II DCM frequency synthesizer
    63145: 03/11/17: Vertex-II configuration in slave SelectMap mode
    63150: 03/11/17: ISE5.2 on solaris, can't use promgen
    63201: 03/11/18: Re: ISE5.2 on solaris, can't use promgen
    63202: 03/11/18: Re: Xilinx Design entry via Schematic Capture - What tool to use ?
    63413: 03/11/21: Re: Does anyone know anything about DC-FPGA?
    63588: 03/11/26: Input pins without Vcco supply-- Virtex-II
    63637: 03/11/27: Re: Input pins without Vcco supply-- Virtex-II
    64575: 04/01/08: Re: iMPACT error : Done did not go high.
    64576: 04/01/08: Re: DPRAM using the CoreGenerator, VHDL-example
    64749: 04/01/13: Re: using signal as clk source
    66104: 04/02/12: Re: Programmable clock, FPGA PLLs, and Actel PLL Core
    69037: 04/04/26: Re: PLL and DLL
    112527: 06/11/23: Are FPGAs available with ADCs onchip ?
    120908: 07/06/20: How to use UART on Spartan 3E Starter Kit
    120911: 07/06/20: Re: How to use UART on Spartan 3E Starter Kit
    133697: 08/07/10: Re: Altera FPGA and data from matlab workspace.
    148843: 10/09/02: Re: Xilinx Series 7 device availability
    150551: 11/01/26: Interfacing with a 5v micro controller
    150559: 11/01/26: Re: Interfacing with a 5v micro controller
    150573: 11/01/26: Re: Interfacing with a 5v micro controller
    150593: 11/01/27: Re: Interfacing with a 5v micro controller
    150600: 11/01/27: Re: Interfacing with a 5v micro controller
    150613: 11/01/28: Re: How to place some delay blocks adjacent to each other after Xilinx ISE P&R tool?
    150847: 11/02/16: Re: Xilinx USB programming cable.
Jay Berg:
    37582: 01/12/16: Certicom challenge and FPGA based modular math
    37591: 01/12/16: Re: Certicom challenge and FPGA based modular math
    37593: 01/12/16: Re: Certicom challenge and FPGA based modular math
    37594: 01/12/16: Re: Certicom challenge and FPGA based modular math
    37609: 01/12/17: Re: Certicom challenge and FPGA based modular math
    37611: 01/12/17: Re: Certicom challenge and FPGA based modular math
    37613: 01/12/17: Re: Certicom challenge and FPGA based modular math
    37644: 01/12/18: Re: Certicom challenge and FPGA based modular math
Jay Darmon:
    9182: 98/02/28: The case for Linux and EDA
    9360: 98/03/07: Re: The case for Linux and EDA (Vox Populi?)
Jay Francis:
    2356: 95/11/22: Re: Device Programmer Selection
    2371: 95/11/24: Re: (no subject)
    2372: 95/11/24: Re: (no subject)
Jay K:
    141338: 09/06/18: Spartan 3A vs 3E SSO guidelines
Jay Lessert:
    2396: 95/11/28: Re: Lattice GAL16VP8 -is it real ?
    8334: 97/12/09: Re: what is metastability time of a flip_flop
    8337: 97/12/09: Re: what is metastability time of a flip_flop
    17297: 99/07/19: Re: License sharing for synopsys/cadence/modeltech
    17316: 99/07/20: Re: License sharing for synopsys/cadence/modeltech
jay mitchell:
    38336: 02/01/11: Re: asic vs. fpga
Jay Southard:
    1124: 95/05/02: Re: Viewlogic VHDL for Xilinx
jay.diem:
    151208: 11/03/15: HiTech Global Virtex5 PCIe Board
jaya:
    133653: 08/07/08: How do I send data and receive data from the FPGA and simulink/matlab
    134084: 08/07/24: Using signal tap analysis with multiple clock domains in Simulink
    134783: 08/08/29: Serial port issues with Matlab
Jaya Rajesh:
    17123: 99/07/01: Re: ALTERA GDF to VHDL QUESTION
    17138: 99/07/02: Re: ALTERA GDF to VHDL QUESTION
Jaya_Kanajan:
    9957: 98/04/17: state machine
<jayadeep90kodali@gmail.com>:
    157050: 14/09/16: Comparision of Advantages/Disadvantges of Verilog or VHDL in Hardware verification
Jayant Nagda:
    15637: 99/04/05: Re: Application Consulting Engineer (ACE)
jayantbala:
    140425: 09/05/13: connecting FPGA with PC using ethernet MAC layer only
    140455: 09/05/14: Re: connecting FPGA with PC using ethernet MAC layer only
    140458: 09/05/14: EDK Enviorment setting problem
    141201: 09/06/11: XILINX WEB SERVER DEMO
Jayaram_Bhasker:
    1150: 95/05/05: Call for Papers: Fall95 VIUF
<jayblue_16@yahoo.com>:
    130596: 08/03/27: Re: problem simulating in modelsim - swiftpli_mti.dll
<jayloveben@hotmail.com>:
    152823: 11/10/26: newable need help
<jaymode@gmail.com>:
    128395: 08/01/24: EDK 9.2i install issues in Linux
    128448: 08/01/26: Re: EDK 9.2i install issues in Linux
<jaypt123@my-deja.com>:
    27113: 00/11/11: Webpack 3.2WP3.x from Xilinx is useless
jaypt@hotmail.com:
    70970: 04/07/03: A simple VHDL question
    71586: 04/07/22: How to program a spartan-3
<jazimme2@yahoo.com>:
    85721: 05/06/14: Re: Help with USB cable, Xilinx XUP board, Linux FC3 and EDK
    85749: 05/06/15: Re: Help with USB cable, Xilinx XUP board, Linux FC3 and EDK
jazzy_21:
    149844: 10/11/28: MicroBlaze Simulation Question
JB:
    41648: 02/04/04: Monostable multivibrator
    150260: 11/01/07: Detecting cold reset on flash FPGA
    150264: 11/01/07: Re: Detecting cold reset on flash FPGA
    150273: 11/01/07: Re: Detecting cold reset on flash FPGA
    151992: 11/06/20: Sporadic simulation result with modelsim
    151994: 11/06/20: Re: Sporadic simulation result with modelsim
    152012: 11/06/21: Re: Sporadic simulation result with modelsim
    152013: 11/06/21: Re: Sporadic simulation result with modelsim
    152017: 11/06/22: Re: Sporadic simulation result with modelsim
    152035: 11/06/23: Re: Sporadic simulation result with modelsim
jb:
    44816: 02/07/02: Re: How can I preserve FFs in LeonardoSpectrum?
    60466: 03/09/14: logic from jed file
    60470: 03/09/14: Re: logic from jed file
    147921: 10/06/02: Re: How good are Actel tools
<jb@capsec.org>:
    127675: 08/01/05: Re: DDR SDRAM demo for Spartan-3E starter kit?
    127695: 08/01/05: Re: DDR SDRAM demo for Spartan-3E starter kit?
    127713: 08/01/06: Re: DDR SDRAM demo for Spartan-3E starter kit?
    127786: 08/01/08: Re: DDR SDRAM demo for Spartan-3E starter kit?
    130343: 08/03/20: Re: ISE 10.0 finally with multi-threading and SV support ?
<jb@nospam.com>:
    53845: 03/03/25: Re: Permanent Local Damage to FPGA
<jball99653@aol.com>:
    20610: 00/02/16: Re: clock
jbj:
    145310: 10/02/05: ISPLever, devlist command
jbnote:
    110058: 06/10/10: Virtex-4 configuration details
    110281: 06/10/13: Xilinx documentation typos
    110583: 06/10/18: from LUT contents to boolean equation
    110588: 06/10/18: Re: from LUT contents to boolean equation
    110777: 06/10/22: Virtex4 debug bitstream generation problem
    111034: 06/10/27: Re: Xilinx documentation typos
    111421: 06/11/02: Re: Dual-port BlockRAM "write first" puzzler...
    112179: 06/11/17: Re: memory init in Altera bitfiles, (like data2mem) is it possible?
    112239: 06/11/18: Re: memory init in Altera bitfiles, (like data2mem) is it possible?
    112276: 06/11/19: Re: memory init in Altera bitfiles, (like data2mem) is it possible?
    112280: 06/11/19: Re: memory init in Altera bitfiles, (like data2mem) is it possible?
    112283: 06/11/19: Re: memory init in Altera bitfiles, (like data2mem) is it possible?
    113631: 06/12/18: Re: incremental compiles in quartus
    114648: 07/01/22: Re: "Divide" a video line in two stripe
    114650: 07/01/22: Re: "Divide" a video line in two stripe
    114652: 07/01/22: Re: "Divide" a video line in two stripe
    114746: 07/01/23: Re: FPGA damage from bad bitstream
    114748: 07/01/23: Re: Xilinx ISE 8.2
    114773: 07/01/24: Re: "Divide" a video line in two stripe
    114775: 07/01/24: Re: FPGA damage from bad bitstream
    114861: 07/01/25: Re: video buffering scheme, nonsequential access (no spatial locality)
    115235: 07/02/04: Re: Xilinx Interconnects/Routing
    115240: 07/02/04: Re: Xilinx Interconnects/Routing
    116673: 07/03/15: Re: .bit file to VHDL/verilog source code
    116691: 07/03/15: Re: .bit file to VHDL/verilog source code
    117949: 07/04/13: Re: Where is Open Source for FPGA development?
    117954: 07/04/14: Re: Where is Open Source for FPGA development?
<jbnote@gmail.com>:
    105594: 06/07/26: Re: Calculate CRC in Virtex-Spartan II bitstream
    105808: 06/08/01: Re: Quick way to change Xilinx BRAM init values
    105819: 06/08/01: Re: Quick way to change Xilinx BRAM init values
    106426: 06/08/13: Re: virtex II inner organisation
<jboothbee@gmail.com>:
    97057: 06/02/15: Re: digital logic library by 74xxxx part number?
jbs80922:
    77205: 04/12/29: Rocket I/O Fail modes/problems help
jc:
    1446: 95/06/23: Job Opportunities in UK: ATM (RBB) VHDL/C++ ASIC/FPGA
    10697: 98/06/11: Re: Are you looking for a good VHDL/Verilog Editor?
    64509: 04/01/06: Xilinx Virtex II Output Register
    142432: 09/08/11: DDR2 Controllers: Bursting to Odd Addresses
    142435: 09/08/11: Re: DDR2 Controllers: Bursting to Odd Addresses
    145113: 10/01/28: Re: Please help, Xilinx FIFO problem!
    145116: 10/01/28: Re: Please help, Xilinx FIFO problem!
    145699: 10/02/19: Re: Unpredictable design
    145774: 10/02/23: Re: System design in FPGA
    149158: 10/10/05: Re: FPGA design not working!
    149579: 10/11/08: Re: Statemachine debugging with Chipscope
    149586: 10/11/08: Re: Statemachine debugging with Chipscope
    149593: 10/11/09: Re: Statemachine debugging with Chipscope
    149611: 10/11/11: Re: Statemachine debugging with Chipscope
    149627: 10/11/12: Re: Statemachine debugging with Chipscope
    149634: 10/11/12: Re: Statemachine debugging with Chipscope
    149635: 10/11/12: Re: Statemachine debugging with Chipscope
    149706: 10/11/19: Re: What is the meaning of 'combinatorial path crossing multiple units'?
    149759: 10/11/23: Re: Synthesis/place and route with Solid-State Drives
    149787: 10/11/24: Re: Synthesis/place and route with Solid-State Drives
    149818: 10/11/25: Re: Synthesis/place and route with Solid-State Drives
    149837: 10/11/26: Re: Multiple clock domains
    149850: 10/11/28: Re: Synthesis/place and route with Solid-State Drives
    149949: 10/12/03: Re: FSM single process...BIG question
    149972: 10/12/04: Re: FSM single process...BIG question
    150192: 10/12/30: Re: Error in Clock Divider!
    150245: 11/01/05: Re: Transfer data from one clock domain to another clock created by
    151489: 11/04/13: Re: Source of Dynamic Power Consumption in FPGAs
    151641: 11/04/29: Re: same RTL on two same boards giving different behaviour
    151770: 11/05/16: Re: Random behavior of xilinx simple dual port block ram
    151848: 11/05/24: Re: comparator fast implementation
    151938: 11/06/10: Re: multiplication in indexation
    151999: 11/06/21: Re: Sporadic simulation result with modelsim
    152028: 11/06/23: Re: Sporadic simulation result with modelsim
    152034: 11/06/23: Re: Sporadic simulation result with modelsim
    152185: 11/07/17: Re: RTL timing issue
jcain:
    10908: 98/06/29: Sr. Hardware Engineer?
jcalder:
    7609: 97/09/26: USB Legacy Implementation
jcarr@linuxmachines.com:
    89193: 05/09/07: Re: Spartan-3E Starter Kit availability slips to December
jcding:
    38719: 02/01/23: Analog input into Altera FLEX10K using ADC. Can anyone help??
    38757: 02/01/24: Re: Analog input into Altera FLEX10K using ADC. Can anyone help??
    38789: 02/01/25: Re: Analog input into Altera FLEX10K using ADC. Can anyone help??
<jcpsoft@my-deja.com>:
    16744: 99/06/06: Digital Filter Design Software
<jcr_alr@xplornet.com>:
    122650: 07/08/02: DOSFS for EDK
    127217: 07/12/14: Re: FPGA Board design basics
    127263: 07/12/16: Re: Spartan-3E starter kit, what's "J8" 6-pin for?
    127555: 08/01/02: Re: Where are the LCD or OLED bitmapped displays?
    128763: 08/02/05: Problems with GDB in EDK 9.2
    128832: 08/02/07: Re: Problems with GDB in EDK 9.2
<jcurren@my-deja.com>:
    19411: 99/12/20: Re: hobbyist friendly pld?
<jcvilleneuve@hotmail.com>:
    11571: 98/08/25: PROM alternative
jd:
    116838: 07/03/19: a project work
JD Newcomb:
    115408: 07/02/09: Applications under MontaVista Linux on ML310
    115419: 07/02/09: Re: Interrupts and PPC/opb_intc
    121551: 07/07/08: XPS 8.2 "UPDATE Tcl procedures"?
    121606: 07/07/09: Re: Build error for multiprocessor sytem.
    121618: 07/07/10: Re: XPS 8.2 "UPDATE Tcl procedures"?
    122327: 07/07/25: EDK Microblaze project without OPB?
    123180: 07/08/18: Re: EDK 9.1.02i warnings flood
    127740: 08/01/06: MicroBlaze floating point precision issues
    127744: 08/01/06: Re: MicroBlaze floating point precision issues
    127759: 08/01/07: Re: MicroBlaze floating point precision issues
JD_Design:
    83527: 05/05/02: Xilinx V4 Power Calculations
    83587: 05/05/03: Re: Xilinx V4 Power Calculations
    83590: 05/05/03: Re: Xilinx V4 Power Calculations
    83602: 05/05/03: Re: Xilinx V4 Power Calculations
    83637: 05/05/04: Re: Xilinx V4 Power Calculations
    83694: 05/05/05: Re: Xilinx V4 Power Calculations
    83710: 05/05/05: Re: Xilinx V4 Power Calculations
    87228: 05/07/19: Virtex-4 hot-swappable?
    87859: 05/08/02: Re: Virtex-4 hot-swappable?
    88108: 05/08/09: Re: Virtex-4 hot-swappable?
<jdaughenb@my-deja.com>:
    29003: 01/02/01: Re: More then 4 Clocks
<jdehaven@my-dejanews.com>:
    12995: 98/11/10: Re: Why doesn't Xilinx's simulator work?
    13215: 98/11/20: Re: Serial EPROMs
jdhduighejhvkxjcn:
    28180: 00/12/24: Re: driving color VGA from FPGA ??
jdiaz_pr:
    32743: 01/07/06: Floating Point SQRT
    32927: 01/07/11: FPGA-based board vs bigger FPGA
    33713: 01/08/02: Simple Division by Shift/Add (2nd try)
    34918: 01/09/13: Foundation 3.1i REINSTALLATION
    34919: 01/09/13: Looking for knowledge on CORDIC, division, correlators, TSBs, sorting, and path-delay handling
Jdon:
    91616: 05/11/09: Rocket IO reset problem
    99253: 06/03/21: need help on asynchronous buffer
    99256: 06/03/21: Re: need help on asynchronous buffer
    99257: 06/03/21: Re: need help on asynchronous buffer
JDS:
    53236: 03/03/07: Multipliers Architectures use on FPGA COREGEN
    53276: 03/03/09: Minimum Real-state K-multiplier/divider
    53464: 03/03/13: Path delay and timer question
    53518: 03/03/14: Re: Path delay and timer question
    55461: 03/05/08: Missing App Notes
<jdy0803@hotmail.com>:
    78299: 05/01/28: How do I get the contents in FPGA
    78413: 05/01/31: FPGA configration Data/Firmware
Jean Lachance:
    4674: 96/11/28: Re: How to utilize XC4000e IOB FFs in Synopsys?
JEAN NICOLLE:
    23938: 00/07/17: better than a long explanation, the LFSR testbench
Jean Nicolle:
    27574: 00/11/29: Re: Fifo design problem
    27748: 00/12/06: Re: ALTERA MAX PLUS LPM FIFOs
    56122: 03/05/29: fpga4un
    56532: 03/06/08: tiny FPGA board
    56651: 03/06/10: Re: Learning FPGAs
    56780: 03/06/15: fpgas are fun
    56930: 03/06/19: Re: Altera FPGA
    57057: 03/06/22: fpga4fun
    57089: 03/06/23: Re: fpga4fun
    57179: 03/06/25: Re: fpga4fun
    57447: 03/06/30: pong game
    57775: 03/07/07: control R/C servos with FPGAs
    57810: 03/07/07: Re: Altera licenses
    59138: 03/08/09: Re: I am new and I want to help
    59402: 03/08/18: Re: serial communication between pc and altera fpga
    59692: 03/08/26: How to listen to music through an FPGA pin?
    59895: 03/08/31: Re: How to listen to music through an FPGA pin?
    59903: 03/09/01: Re: Xilinx bit files
    60106: 03/09/05: Sending and receiving Ethernet traffic
    60130: 03/09/05: Re: Sending and receiving Ethernet traffic
    60239: 03/09/09: Re: Sending and receiving Ethernet traffic
    60291: 03/09/10: Re: VGA display
    62574: 03/11/02: Re: Minimalist RS232 on Cyclone
    63146: 03/11/17: Re: getting started in FPGA
    63483: 03/11/22: Re: Affordable Development Board
    63640: 03/11/27: Re: Slightly unmatched UART frequencies
    63988: 03/12/11: Re: Soldering of FPGAs
    64046: 03/12/13: Re: advantages of ethernet MAC ip core
    64050: 03/12/14: Re: advantages of ethernet MAC ip core
    64435: 04/01/04: Re: rs-232 trouble
    64560: 04/01/07: Tutorials for ISE and Quartus
    64564: 04/01/07: Re: Tutorials for ISE and Quartus
    64757: 04/01/13: Send Ethernet traffic from an FPGA
    64775: 04/01/13: Re: Send Ethernet traffic from an FPGA
    64811: 04/01/14: Re: Send Ethernet traffic from an FPGA
    64998: 04/01/18: Re: Send Ethernet traffic from an FPGA
    64999: 04/01/18: Re: Send Ethernet traffic from an FPGA
    65001: 04/01/18: Re: fpga4fun
    65023: 04/01/19: Re: Send Ethernet traffic from an FPGA
    65085: 04/01/20: Re: Send Ethernet traffic from an FPGA
    65298: 04/01/23: Re: Send Ethernet traffic from an FPGA
    65461: 04/01/29: Re: FPGA basics
    65464: 04/01/30: Re: Where to get FPGA devices for testing?
    65497: 04/01/31: Re: Where to get FPGA devices for testing?
    65498: 04/01/31: Re: Where to get FPGA devices for testing?
    65534: 04/02/01: Differences between Xilinx ISE and Altera Quartus software
    65541: 04/02/01: Re: Differences between Xilinx ISE and Altera Quartus software
    65543: 04/02/01: Re: Differences between Xilinx ISE and Altera Quartus software
    65544: 04/02/01: Re: Clocking an FPGA??
    65547: 04/02/02: Re: Differences between Xilinx ISE and Altera Quartus software
    65583: 04/02/03: Re: Differences between Xilinx ISE and Altera Quartus software
    65584: 04/02/03: Re: Differences between Xilinx ISE and Altera Quartus software
    65805: 04/02/06: Re: Differences between Xilinx ISE and Altera Quartus software
    65845: 04/02/08: Re: Differences between Xilinx ISE and Altera Quartus software
    65846: 04/02/08: Re: Differences between Xilinx ISE and Altera Quartus software
    66149: 04/02/13: Re: Programmable clock, FPGA PLLs, and Actel PLL Core
    66199: 04/02/14: Re: Programmable clock, FPGA PLLs, and Actel PLL Core
    67773: 04/03/19: Re: PCI Development Board
    68016: 04/03/24: Re: cheapest & best FPGA???
    68510: 04/04/07: Re: Cyclone and ByteBlasterMV?
    70042: 04/05/28: Re: How to generate a 320x200 VGA signal?
    70060: 04/06/01: Re: solderless breadboard + fpga + smt-adaptable socket?
    80368: 05/03/04: Re: Newby Getting started with FPGA
    83104: 05/04/23: is the 8051 architecture public domain?
    102220: 06/05/12: JTAG tutorial
    102260: 06/05/12: Re: JTAG tutorial
    102261: 06/05/12: Re: JTAG tutorial
    112613: 06/11/26: vccaux and vccint
    112624: 06/11/27: Re: vccaux and vccint
    113259: 06/12/09: Re: FPGA+Ethernet
    116251: 07/03/05: Multiple devices within one ISE project
Jean Paul Heron -COD-RW:
    4013: 96/09/03: Xact 6000
Jean Williams:
    32250: 01/06/21: Help with VHDL
Jean-Baptiste:
    148470: 10/07/26: Performing incremental code coverage with modelsim
jean-baptiste:
    98669: 06/03/14: Re: slice macro replace the bus macro in the virtex-4 how to do that?????
Jean-Baptiste Monnard:
    35024: 01/09/18: Re: Altera Quartus II: Ouput skew ;-(
    35174: 01/09/25: Re: How to fix the hold time violation (clock skew>data skew) in QuartusII
    39949: 02/02/22: Re: Pin assignments in QUARTUS
<jean-baptiste.nouvel@jdsu.com>:
    104856: 06/07/07: PCI IOs, tiofoi, source sampling bypass
    104862: 06/07/07: Re: PCI IOs, tiofoi, source sampling bypass
    104972: 06/07/11: Re: PCI IOs, tiofoi, source sampling bypass
    104973: 06/07/11: Re: PCI IOs, tiofoi, source sampling bypass
    104982: 06/07/11: Re: High-speed DAC/ADC with FPGA
    104984: 06/07/11: Re: High-speed DAC/ADC with FPGA
    116549: 07/03/12: /* synopsys enum state_code */ on XST???
    116550: 07/03/12: Heatsink on FPGA?
    116622: 07/03/14: Re: Heatsink on FPGA?
    116623: 07/03/14: Re: Heatsink on FPGA?
    116749: 07/03/16: Re: Xilinx FPGA, OFFSET OUT AFTER
Jean-francois Hasson:
    17977: 99/09/20: Maxplus+II and constraints on a MAX9000 chip
jean-francois hasson:
    25088: 00/08/25: PCI macros
    26374: 00/10/13: 5V compatible Virtex
    28899: 01/01/28: Actel's FPGA : A54SX32A
    29005: 01/02/01: A54SX type FPGA from ACTEL questions
    39988: 02/02/23: Question about multiple Virtex DLLs locking management after configuration
    59097: 03/08/08: Clocking in a virtex 2 without using the clock trees : questions
    59186: 03/08/11: Re: Clocking in a virtex 2 without using the clock trees : questions
    59277: 03/08/13: Skew on a clock tree on a virtex II : what is the good figure ?
    59296: 03/08/14: Re: Skew on a clock tree on a virtex II : what is the good figure ?
    59927: 03/09/01: DDR capabilities of a Virtex II device
    60136: 03/09/05: Automatic signal fanout management in an FPGA (Xilinx type in this case)
    62470: 03/10/30: CLKFX problem with a Virtex II
    63883: 03/12/07: Skew between the output of a DCM ?
    63976: 03/12/10: Re: Skew between the output of a DCM ?
    64942: 04/01/16: Impact of voltage variations on timings for an FPGA
    69186: 04/04/29: package choice, temperature and obsolesence issues with a xilinx fpga
    72331: 04/08/15: SSO and other banks behavior of Xilinx FPGAs
    72534: 04/08/23: SSO and decoupling relationship
    72548: 04/08/24: Maximum allowable ground bounce for xilinx fpgas
    80313: 05/03/03: Jitter calculation for RocketIO reference clock
    82711: 05/04/16: rocketio decoupling
    108297: 06/09/07: Altera CPLD 7128S heating up
    109092: 06/09/20: Use of XMD in EDK7.1i
    109114: 06/09/21: Profiling issue with EDK 7.1
    139832: 09/04/15: Synchronous clocking between Cyclone III and SDRAM
Jean-Francois Richard:
    16270: 99/05/13: floating points to fixed points on a FPGA
    16271: 99/05/13: Reference on word lenght quantization
Jean-Jacques Bordes:
    62228: 03/10/22: Re: mp3 project
Jean-Louis VERN:
    9695: 98/03/31: Re: New radix-4 CORDIC for computing sine and cosine
Jean-Luc:
    58659: 03/07/30: apex20ke library and simulation
    58702: 03/07/31: Re: apex20ke library and simulation
Jean-Luc Cooke:
    47601: 02/09/30: Diving in for the first time
    47602: 02/09/30: correction
Jean-Luc danger:
    17693: 99/08/24: APEX20K boards
Jean-Luc Nagel:
    22647: 00/05/16: PC104+ FPGA Board
    22666: 00/05/17: Re: PC104+ FPGA Board
    22695: 00/05/18: Re: PC104+ FPGA Board
jean-marc:
    20483: 00/02/11: Processing a sdf file
Jean-Marc Bourguet:
    28294: 01/01/05: Re: Nondeterministic FSMs in hardware?
Jean-Marc Lienher:
    152935: 11/11/02: Re: draw lines, circles, squares on FPGA by mouse and display on
Jean-marc Lienher:
    159566: 16/12/31: Re: Slightly OT: Digital watch circuits
Jean-Marc REMONDEAU:
    8703: 98/01/21: Re: complex number challenge
Jean-Marie Bussat:
    24480: 00/08/10: Viewlogic to Orcad conversion
    27033: 00/11/08: Re: Anything wrong with Xilinx website?
    30220: 01/03/28: VHDL question
    30228: 01/03/28: Re: VHDL question
    30254: 01/03/29: Re: VHDL question
    30280: 01/03/30: Re: HAL-15
    30578: 01/04/17: Re: Getting license for Modelsim in Xilinx webpack?
    32096: 01/06/13: Re: High Speed Sampling Oscilloscope in an FPGA
Jean-Michel GUEUGNOT:
    29025: 01/02/02: Re: FPGA board with lots of SRAM?
Jean-Michel Vuillamy:
    3879: 96/08/14: Xilinx Product Strategy
    4418: 96/10/25: Re: Synplicity vs. FPGA Express
    6854: 97/07/02: Re: Verilog Simulation and Synthesis for FPGA Devices
    144830: 10/01/07: Re: PMC or XMC based on Altera parts (preferably Stratix)
Jean-Paul GOGLIO:
    20294: 00/02/04: Re: Spartan 2 & Foundation
    20295: 00/02/04: Re: Spartan 2 & Foundation
    20296: 00/02/04: Re: Spartan 2 & Foundation
    20374: 00/02/08: Timing constraint on a DLL output
    20375: 00/02/08: Re: Timing constraint on a DLL output
    20376: 00/02/08: Re: Timing constraint on a DLL output
    20378: 00/02/08: Re: Timing constraint on a DLL output
    20607: 00/02/16: Re: Simulating Virtex
    21855: 00/04/04: Re: JTAG programming
    21896: 00/04/06: Re: JTAG programming
    21903: 00/04/06: Re: JTAG programming
    21930: 00/04/07: Re: multiprocessor support of IC design tools
    21936: 00/04/07: Re: multiprocessor support of IC design tools
    21959: 00/04/10: Re: multiprocessor support of IC design tools
    21987: 00/04/11: Virtex E Pads Output Impedance
    26872: 00/11/02: Bits swapping with XC18V02
    27491: 00/11/24: Re: How to reduce the Tco
    27500: 00/11/24: Re: How to reduce the Tco
Jean-Paul Ricaud:
    8084: 97/11/17: What is the difference between CPLD and FPGA ?
Jean-Paul Smeets:
    2427: 95/12/04: Xilinx vs Altera with Verilog/VHDL
    4088: 96/09/09: Xilinx ViewLogic package and simulating VHDL
    4089: 96/09/09: Re: ViewSynthesis and Xilinx
    24294: 00/08/03: Re: Desperatly needing a SpartanII
    25597: 00/09/15: Xilinx PCI interface: buy the LogiCORE or do it yourself?
    29138: 01/02/07: Re: Switching matrix, FPGA or CPLD? - smatrix.JPG (0/1)
    29291: 01/02/13: QuickLogic PCI arbiter in QAN24 completely wrong
    29419: 01/02/20: Re: Altera process change....
    31581: 01/05/31: Barrel shifter in Xilinx Virtex-E
Jean-Pierre Gehrig:
    31246: 01/05/16: XilinxCoreLib with Renoir
Jean-Réginald Louis:
    21242: 00/03/13: DSP with FPGA
    21247: 00/03/13: Re: DSP with FPGA
Jean-sébastien LEROY:
    128936: 08/02/11: RC340E board to sell
    128984: 08/02/12: XiRisc softcore processor
    129027: 08/02/13: Re: XiRisc softcore processor
    129330: 08/02/21: Re: XiRisc softcore processor
    129331: 08/02/21: Re: Which Linux Distro to use for Xilinx tools
    129620: 08/02/29: DSP Ip Core
Jeanan Del:
    33266: 01/07/20: Re: SystemC
    41356: 02/03/26: Handel-C useless.. Move to SystemC
    41598: 02/04/02: Re: Handel-C vs SystemC
<jeanfrancois62@gmail.com>:
    139840: 09/04/15: Re: Synchronous clocking between Cyclone III and SDRAM
<jeanpaul@stack.urc.tue.nl>:
    1306: 95/05/30: Re: affordable fpga design tools?
Jecel:
    77953: 05/01/20: Re: Copying/Reverse Engineering PAL
    78090: 05/01/24: Re: Copying/Reverse Engineering PAL
    78107: 05/01/24: Re: Copying/Reverse Engineering PAL
    78263: 05/01/27: Re: Copying/Reverse Engineering PAL
    80529: 05/03/07: Re: Asynchronous processor !?!
    82730: 05/04/16: Re: Xilinx tools on Linux
    90054: 05/10/03: Re: Xilinx dev board with high quality video?
    90110: 05/10/04: Re: Xilinx dev board with high quality video?
    90112: 05/10/04: Re: Xilinx dev board with high quality video?
    91440: 05/11/06: Re: Why Spartan-3e is the best
    91538: 05/11/08: Re: Why Spartan-3e is the best
    104032: 06/06/16: Re: High speed differential to single ended
    107944: 06/09/02: Re: Forth-CPU design
    108000: 06/09/03: Re: Forth-CPU design
    108068: 06/09/04: Re: Forth-CPU design
    108122: 06/09/05: Re: Forth-CPU design
    108822: 06/09/17: Re: old computer architecture book
    111762: 06/11/09: Re: How to send data/program to the memory of a Spartan 3 starter kit board
    111831: 06/11/10: Re: JOP @ Spartan3 Starter Kit - Compile error (missing components)
    111832: 06/11/10: Re: JOP @ Spartan3 Starter Kit - Compile error (missing components)
    115162: 07/02/01: Webpack 9.1 problems with Impact on parallel cable
    115168: 07/02/01: Re: Webpack 9.1 problems with Impact on parallel cable
    124644: 07/09/28: Re: FPGA NTSC signal with 2 resistors and PWM
    124677: 07/09/29: Re: FPGA NTSC signal with 2 resistors and PWM
    124716: 07/10/01: Re: FPGA NTSC signal with 2 resistors and PWM
    124722: 07/10/01: Re: FPGA NTSC signal with 2 resistors and PWM
    124772: 07/10/03: Re: FPGA NTSC signal with 2 resistors and PWM
    125514: 07/10/26: Re: FPGA vs ASIC
    126852: 07/12/04: Re: Researching Reconfigurable Computing
    127764: 08/01/07: Re: Processor in CPLD
    128404: 08/01/24: Re: EDK 9.2i install issues in Linux
    130184: 08/03/17: Re: Designing CPU
    130206: 08/03/17: Re: Designing CPU
    130299: 08/03/19: Re: A Challenge for serialized processor design and implementation
    130345: 08/03/20: Re: A Challenge for serialized processor design and implementation
    132125: 08/05/14: Re: xsa-50 issues
    137059: 08/12/21: Re: Bit width in CPU cores
    138659: 09/03/03: Re: Lattice announces ECP3
    138702: 09/03/05: Re: Lattice announces ECP3
    139071: 09/03/19: Re: Documenting a simple CPU
    139326: 09/03/26: Re: Dynamic reconfiguration in Spartan 3
    140633: 09/05/20: Re: Open source processors
    140690: 09/05/21: Re: Open source processors
    145366: 10/02/06: Re: using an FPGA to emulate a vintage computer
    145401: 10/02/08: Re: using an FPGA to emulate a vintage computer
    145402: 10/02/08: Re: using an FPGA to emulate a vintage computer
    151563: 11/04/19: Re: NibzX7 processor
    152487: 11/08/28: Re: Very cheap Spartan3 board that can be configured by simple USB
    154804: 13/01/13: Re: Chisel as alternative HDL
    154811: 13/01/14: Re: Chisel as alternative HDL
    154824: 13/01/15: Re: Chisel as alternative HDL
    156141: 13/12/09: Re: Implementing multiple interrupts
    156946: 14/08/01: Re: Professional VHDL Examples?
    158900: 16/05/16: Re: FPGA boards in egypt
    159018: 16/06/13: Re: J1 forth processor in FPGA - possibility of interactive work?
    159020: 16/06/14: Re: J1 forth processor in FPGA - possibility of interactive work?
    159022: 16/06/15: Re: J1 forth processor in FPGA - possibility of interactive work?
    159024: 16/06/16: Re: J1 forth processor in FPGA - possibility of interactive work?
    159030: 16/06/17: Re: J1 forth processor in FPGA - possibility of interactive work?
    159034: 16/06/18: Re: J1 forth processor in FPGA - possibility of interactive work?
    159083: 16/07/27: Re: Mod-24: The State of High-Level Synthesis in 2016
    159753: 17/02/24: Re: designing a fpga
jedes:
    58279: 03/07/18: Multi device Altera configuration problem
    58293: 03/07/19: Multi device ALTERA chain configuration problem!
JeDi:
    132718: 08/06/05: HDL tricks for better timing closure in FPGAs
    132787: 08/06/06: Re: HDL tricks for better timing closure in FPGAs
jedi:
    80844: 05/03/12: Re: Free Stencil For SMD Soldering
    88513: 05/08/21: Altera mysupport
Jedi:
    77840: 05/01/18: cyclone jtag
    77875: 05/01/19: Re: video decoder for altera dev. board
    77876: 05/01/19: epcs prices
    78119: 05/01/25: Re: epcs prices
    78252: 05/01/27: Re: =?ISO-8859-1?Q?ProASIC=A7_Released?=
    78253: 05/01/27: EPCS binary files...
    78258: 05/01/27: Re: EPCS binary files...
    78287: 05/01/28: Re: =?ISO-8859-1?Q?ProASIC=A7_Released?=
    78294: 05/01/28: Is Atmel producing Altera EPCS memories???
    78309: 05/01/28: Altera Quartus 4.2 Service Pack 1 fails to install
    78320: 05/01/29: Re: Altera Quartus 4.2 Service Pack 1 fails to install
    78322: 05/01/29: Altera subscriptions deleted?
    78326: 05/01/29: Re: Is Atmel producing Altera EPCS memories???
    78334: 05/01/29: Re: Altera Quartus 4.2 Service Pack 1 fails to install
    78347: 05/01/30: Re: Is Atmel producing Altera EPCS memories???
    78380: 05/01/31: Re: Is Atmel producing Altera EPCS memories???
    78381: 05/01/31: Lattice LFEC20
    78452: 05/02/01: Re: Input logic level on Spartan 3?
    78466: 05/02/01: Re: Altera Quartus 4.2 Service Pack 1 fails to install
    78486: 05/02/01: Synplicity and Mentor denying evaluation licenses
    78552: 05/02/03: Re: Is Atmel producing Altera EPCS memories???
    78583: 05/02/03: Re: Is Atmel producing Altera EPCS memories???
    78623: 05/02/04: NIOS2 toolchain rebuild...
    78680: 05/02/05: Altera's NIOS2 examples...
    78739: 05/02/07: Re: Cyclone configuration device
    78753: 05/02/07: Re: Cyclone configuration device
    78843: 05/02/08: quartus "make clean" ?
    78885: 05/02/09: Re: Cyclone configuration device
    79029: 05/02/11: Why are the NIOS toolchain sources removed from Altera's ftp?
    79427: 05/02/18: Altera support getting worse and worse......
    79430: 05/02/18: nios2 flash programmer
    79452: 05/02/19: Re: Graphic LCD
    79583: 05/02/21: Re: NIOS2 toolchain rebuild...
    80301: 05/03/03: Re: Lattice lowcost flash FPGAs announced
    80518: 05/03/07: NIOS2 1.1 toolchain sources...
    80846: 05/03/12: Re: Free Stencil For SMD Soldering
    81425: 05/03/23: Re: Xilinx ISE 7.1 - Can this get any worse?
    81965: 05/04/05: Quartus 5
    84723: 05/05/25: Lattice ROM file tool....
    84756: 05/05/26: ARC A4
    84865: 05/05/31: Re: Nios II - Booting software from Flash
    84889: 05/05/31: Altera NIOS2 50.0 SOPC periphals broken???
    84892: 05/05/31: Re: Altera NIOS2 50.0 SOPC periphals broken???
    84982: 05/06/02: Altera's fast NIOS update service (o;
    85078: 05/06/03: Re: Altera's fast NIOS update service (o;
    85106: 05/06/04: Re: ispLSI1016
    85214: 05/06/06: Re: Altera NIOS2 50.0 SOPC periphals broken???
    85263: 05/06/07: nios32 -> nios2 assembly porting?
    85290: 05/06/07: Re: Sch & Layout Free Program
    85418: 05/06/09: Lattice LFEC20 DDR SDRAM connection
    85698: 05/06/14: Re: Altera's fast NIOS update service (o;
    85764: 05/06/15: NIOS2 exceptions...
    85971: 05/06/19: Lattice LFEC
    85988: 05/06/19: use lattice and actel synplify together...
    86013: 05/06/20: Re: Lattice LFEC
    86017: 05/06/20: Re: Lattice LFEC
    86023: 05/06/20: Re: Design tools comparison between Xilinx, Altera and Lattice for
    86029: 05/06/20: Re: Lattice LFEC
    86065: 05/06/21: JTAG port access in Cyclone
    86085: 05/06/21: Re: JTAG port access in Cyclone
    86086: 05/06/21: Re: dru files for eagle ?
    86116: 05/06/22: Re: JTAG port access in Cyclone
    86117: 05/06/22: Re: JTAG port access in Cyclone
    86124: 05/06/22: Re: JTAG port access in Cyclone
    86125: 05/06/22: Re: JTAG port access in Cyclone
    86169: 05/06/22: Re: JTAG port access in Cyclone
    86242: 05/06/23: NIOS2 subscription online?
    86243: 05/06/23: nios2 gnu sources broken for amd64 linux
    86256: 05/06/23: Re: nios2 gnu sources broken for amd64 linux
    86267: 05/06/23: Re: Good FPGA introduction book ?
    86300: 05/06/24: Re: Good FPGA introduction book ?
    86351: 05/06/26: good bye nios (o;
    86357: 05/06/26: Re: good bye nios (o;
    86372: 05/06/27: Re: good bye nios (o;
    86374: 05/06/27: Re: good bye nios (o;
    86375: 05/06/27: Re: good bye nios (o;
    86450: 05/06/28: Re: good bye nios (o;
    86493: 05/06/29: xp3/xp6 in ispLever
    86540: 05/06/29: Cyclone online store
    86571: 05/06/30: init ProASIC3 Ram from spi
    86626: 05/07/01: Re: init ProASIC3 Ram from spi
    86692: 05/07/04: nios2 toolchain sources...
    86714: 05/07/05: Re: nios2 toolchain sources...
    86720: 05/07/05: Re: nios2 toolchain sources...
    86729: 05/07/05: Re: nios2 toolchain sources...
    86972: 05/07/11: Re: Bazix introduce FPGA based One Chip computer system
    87022: 05/07/13: NIOS2 toolchain sources...
    87028: 05/07/13: Re: NIOS2 toolchain sources...
    87418: 05/07/23: Update contacts at Altera
    87489: 05/07/25: Re: Update contacts at Altera
    87592: 05/07/26: Re: Update contacts at Altera
<Jedi>:
    117696: 07/04/07: ispLever FTP Download
    117736: 07/04/09: ByteBlaster Parallel Driver for Linux > 2.6.13
    117854: 07/04/11: ispLever 6.1 complains about missing libc.so.6 on Gentoo 2006.1
    117857: 07/04/12: Re: ispLever 6.1 complains about missing libc.so.6 on Gentoo 2006.1
Jee:
    45693: 02/08/01: Xilinx ISE 4.2: UCF file name
    50739: 02/12/18: What's the easy way to port an ISE project
Jee Chi:
    44194: 02/06/13: what's difference between .edf and .edn
<Jee@hotmail.com>:
    49503: 02/11/13: how to name the IOBUF attribute in UCF
Jef Patat:
    81390: 05/03/22: clock division using DCM, how?
Jeff:
    8782: 98/01/26: Re: Radhard FPGA Vendors?
    8892: 98/02/05: Re: Can XACT6 run in a NT4 DOS box?
    9014: 98/02/13: Fun with Orcad Express and M1!
    9214: 98/03/02: Re: ORCAD front End Tools
    9283: 98/03/05: Re: ++ TMS320C6x DSP info website ++
    11317: 98/08/04: Re: how much ? prices of Xilinx chips
    30719: 01/04/25: What is wrong with Xilinx Foundation Simulator?
    30734: 01/04/26: Bidirection port simulation
    30743: 01/04/26: Bidirection Macro
    42825: 02/05/03: Hard macro with Xilinx
    42886: 02/05/06: Re: Hard macro with Xilinx
    43545: 02/05/23: Xilinx proprietary format?
    49246: 02/11/06: Re: Hard macro
    49261: 02/11/06: Question about algorithm implementing in FPGA
    49277: 02/11/07: Re: Question about algorithm implementing in FPGA
    50566: 02/12/12: Want to buy an board with Xilinx FPGA Virtex II
    50637: 02/12/15: Could you explain compact PCI, PCI and PCI bridge to me?
    50908: 02/12/22: Where can I download ISE 4.x?
    50913: 02/12/22: Re: Where can I download ISE 4.x?
    51000: 02/12/25: Question from newbie of WebPACK
    51106: 03/01/01: Question about HDL bencher (Xilinx) from newbie?
    51181: 03/01/05: Re: Question about HDL bencher (Xilinx) from newbie?
    51483: 03/01/14: How to run XST from command line?
    52216: 03/02/04: Re: Xilinx's XDL
    57968: 03/07/10: Questions about the figure in algorithm implimenting in hardware
    64508: 04/01/06: Questions about guard bits in CORDIC algorithm
    64529: 04/01/06: Re: Questions about guard bits in CORDIC algorithm
    64572: 04/01/07: Re: Questions about guard bits in CORDIC algorithm
    65352: 04/01/25: How to do with guard bits practically?
    65355: 04/01/26: Re: How to do with guard bits practically?
    65369: 04/01/26: Re: How to do with guard bits practically?
    66477: 04/02/20: altera, xilinx susceptible to power transients?
    95724: 06/01/25: Re: Spartan-3 Starter Board
    95729: 06/01/25: Re: Spartan-3 Starter Board
jeff:
    41881: 02/04/09: Need help with Insight Spartan II demo board and the counter demo.
    41925: 02/04/10: Re: Need help with Insight Spartan II demo board and the counter demo.
    41927: 02/04/10: Re: Need help with Insight Spartan II demo board and the counter demo.
    42259: 02/04/18: Update -- Need help with Insight Spartan II demo board and the counter demo.
    42262: 02/04/18: Re: Update -- Need help with Insight Spartan II demo board and the counter demo.
    42437: 02/04/23: Re: Reasonably Priced Development Software ??
Jeff and Bev Neil:
    29089: 01/02/06: .ucf commands
    34290: 01/08/18: Re: [Spartan-II] JTAG configuration problem ...
Jeff Berryhill:
    8444: 97/12/15: Re: bus design in Altera 10K, how to increase speed -- Check out Xilinx
    8456: 97/12/16: Re: bus design in Altera 10K, how to increase speed -- Check out Xilinx
    8469: 97/12/18: Re: bus design in Altera 10K, how to increase speed -- Check out Xilinx
    11589: 98/08/25: Re: PROM alternative
Jeff Brandenburg:
    434: 94/11/16: Re: Sources for FGPA's and "exotic" PLDs?
Jeff Brower:
    98935: 06/03/17: Re: Urgent Help Needed!!!!!
    99015: 06/03/18: Re: Urgent Help Needed!!!!!
    99701: 06/03/28: combinatorial always blocks + for-loops in XST
    99705: 06/03/28: Re: combinatorial always blocks + for-loops in XST
    99711: 06/03/28: Re: combinatorial always blocks + for-loops in XST
    99720: 06/03/28: Re: deglitching a clock
    99722: 06/03/28: Re: combinatorial always blocks + for-loops in XST
    99741: 06/03/28: Re: combinatorial always blocks + for-loops in XST
    99910: 06/03/30: no output from BUFGMUX
    99911: 06/03/30: Re: Xilinx Schematic Entry
    99925: 06/03/30: Re: Xilinx Schematic Entry
    100243: 06/04/05: initializing arrays with Verilog and XST
    100260: 06/04/05: Re: initializing arrays with Verilog and XST
    100263: 06/04/05: Re: Xilinx Schematic Entry
    100271: 06/04/05: Re: initializing arrays with Verilog and XST
    100508: 06/04/10: Configuration Rate with multiple .bit files
    100512: 06/04/10: Re: Configuration Rate with multiple .bit files
    100524: 06/04/10: Re: Configuration Rate with multiple .bit files
    100705: 06/04/16: XST not inferring distributed RAM
    100728: 06/04/17: Re: XST not inferring distributed RAM
    100760: 06/04/17: Re: Spartan 3 chips in power up
    100761: 06/04/17: Re: Spartan 3 chips in power up
    100767: 06/04/17: comparison with integer
    100794: 06/04/18: Re: Spartan 3 chips in power up
    100806: 06/04/18: Re: comparison with integer
    100855: 06/04/19: XST issues with loop code
    100904: 06/04/20: Re: Spartan 3 chips in power up
    100966: 06/04/21: XST pre-defined macros
    101234: 06/04/27: Re: Xilinx PCI 64/32 bits IP
    101240: 06/04/27: Re: Xilinx: Prohibit propagation of timing constraint through a mux
    101241: 06/04/27: initializing array of registers in XST
    101312: 06/04/28: Re: initializing array of registers in XST
    101315: 06/04/28: Re: initializing array of registers in XST
    101416: 06/04/30: Re: Pull up resistors on Spartan 3 mode pins
    101461: 06/05/01: Re: ISE 8.1 Comment Bug, Very hideous
    101517: 06/05/02: Re: Chaining multiple Xilinx "Six Easy Pieces" Clock Doubler
    101519: 06/05/02: Re: ISE 8.1 Comment Bug, Very hideous
    101623: 06/05/03: Re: ports of multidimentional arrays in verilog.
    101624: 06/05/03: Re: ISE8.1 inout, tristate Problem?Please help!
    101626: 06/05/03: Re: How to open an ISE 8.1 project in ISE 7.1?
    102004: 06/05/09: Re: Xilinx 3s8000?
    102015: 06/05/09: Re: Xilinx 3s8000?
    102213: 06/05/11: Re: Xilinx 3s8000?
    102214: 06/05/11: Re: Xilinx 3s8000?
    102483: 06/05/16: Re: getting good deals on small qty?
    102783: 06/05/20: initial block processing in XST 8.1
    102843: 06/05/22: Re: initial block processing in XST 8.1
    103163: 06/05/26: initial block processing in XST 8.1, part 2
    135916: 08/10/21: Spartan 3 IO banking rules problem in ISE
    135948: 08/10/23: Re: Spartan 3 IO banking rules problem in ISE
    135952: 08/10/23: Re: Spartan 3 IO banking rules problem in ISE
Jeff Buckles:
    6303: 97/05/12: Re: Desperate college students need help!!!
Jeff Carter:
    24418: 00/08/07: FPGA
    24523: 00/08/11: fpga
Jeff Christenson:
    16035: 99/04/29: Re: flex10k 1 gate change
Jeff Collins:
    542: 94/12/28: Dual Xilinx 4000->3000 question
    705: 95/02/13: Can I implement a digital PLL in an FPGA??
    754: 95/02/23: Re: Can I implement a digital PLL in an FPGA??
Jeff Cummings:
    173: 94/09/09: Re: Help, Please (Urgent)
Jeff Cunningham:
    260: 94/10/06: Re: AT&T ORCA FPGA
    1341: 95/06/02: Re: Latch up in Xilinx 3000 Series FPGA's. Part smokes &
    1292: 95/05/29: Re: Any company for conversion FPGA to ASIC?
    1668: 95/08/13: Re: Xilinx PROMs
    2777: 96/02/06: Re: Xilinx FPGA's with Mentor Tools?
    3869: 96/08/12: Re: ASIC simulations in multiple FPGAs
    30900: 01/05/02: Re: Need info : Training on ASIC/FPGA
    31304: 01/05/17: Can anyone comment on the difference between modelsim PE and XE
    31306: 01/05/17: Re: help for BGA ?
    31420: 01/05/22: Aldec, Synplify (was: free simulator)
    35418: 01/10/03: Re: What's a process?
    35575: 01/10/10: Re: Synplicity/Leonardo License Agreement Information
    36074: 01/10/27: Re: Firewire chipset
    37524: 01/12/13: referencing Spartan2 DLL to 24.576 Mhz?
    42434: 02/04/23: Re: Reasonably Priced Development Software ??
    45274: 02/07/17: Re: Simulating Xilinx Block RAM with ModelSim
    45276: 02/07/17: Re: Commercial FPGA Architectures
    45545: 02/07/25: Re: Xilinx ISE 4.2i Is A Step Backwards! Beware!!!
    45783: 02/08/05: Re: modelsim XE starter
    46264: 02/08/23: Re: How to include Xilinx library for both ModelSim and Synplify?
    48918: 02/10/26: Re: A PCI Data Aqcuisition Card Design
    50202: 02/12/04: Re: clock difference between DLL input and output?
    51841: 03/01/23: Re: VHDL or Verilog?
    52401: 03/02/07: Re: USB2 or firewire or 100Mb ethernet link to FPGA design
    52913: 03/02/25: Re: Licencing for downloadable FPGA tools
    52914: 03/02/25: Re: VHDL & FPGA Design tools
    53376: 03/03/12: Re: comp.arch.fpga : VCC shorted to GND within FPGA???
    58833: 03/08/02: Re: Multi Cycle path and False paths
    61903: 03/10/15: Re: Universities that focus on IC design
    62309: 03/10/26: Re: Are clock and divided clock synchronous?
    62399: 03/10/29: Re: Are clock and divided clock synchronous?
    62705: 03/11/05: Re: I/O on current FPGAs - deserialise first ??
    62732: 03/11/06: Re: I/O on current FPGAs - deserialise first ??
    62842: 03/11/10: Re: FPGAs and DRAM bandwidth
    64567: 04/01/07: Re: Synthesis in VHDL vs. Verilog
    67159: 04/03/07: Re: Release asynchrounous resets synchronously
    68992: 04/04/23: Re: What is MPGA?
    69439: 04/05/11: Re: One issue about free hardware
    69674: 04/05/18: Re: Instantiating subblock signals with VHDL
    69675: 04/05/18: Re: std_logic_vector vs unsigned
    70127: 04/06/03: Re: tri-state in altera
    71933: 04/08/04: Re: Choosing FPGAs: Xilinx vs Altera vs Actel vs Lattice
    74998: 04/10/23: Re: Altera Cubic Cyclonium
    76433: 04/12/02: Does Easypath make sense for a XC2S15 @ 20K units?
    76744: 04/12/10: Re: Getting Started With Simple Sound Synthesis
    76746: 04/12/10: Re: Open source FPGA EDA Tools
    76946: 04/12/16: Re: algorithm: square operation
    77313: 05/01/04: Re: Skew between signals
    77392: 05/01/06: Re: Utilisation of Xilinx FPGAs
    77393: 05/01/06: Re: Synchronous Interface to XScale CPU
    77819: 05/01/18: Re: FPGA Board with RF Front end
    78180: 05/01/26: Re: 60Hz clock on XC9572
    82449: 05/04/13: Re: General question about soft CPUs
    82674: 05/04/16: Re: Soft CPU vs Hard CPU's
    82998: 05/04/21: Is Cyclone-2 EP2C5 or EP2C8 available? If not, when?
    83830: 05/05/07: Re: Using capacitor to slow the rise time.
    83850: 05/05/08: Re: Using capacitor to slow the rise time.
    85021: 05/06/03: Re: Basics FPGA
    85395: 05/06/09: Re: FPGA I/O pin current sink
    85397: 05/06/09: Re: FPGA/CPLD trend
    85934: 05/06/18: Re: AbusivepPricing information in marketing publications
    86097: 05/06/22: Re: FPGAs: Where will they go?
    88719: 05/08/26: Re: Xilinx place and route cost table
    88777: 05/08/28: Re: mails from Aman Mediratta
    89104: 05/09/05: Re: Reading internal signals through a testbench.
    90392: 05/10/11: Re: LUT 4:1 VS FF
    92851: 05/12/07: Re: Virtex 4 not meeting timing constraints
    92913: 05/12/09: Re: some new PCIe products
    92950: 05/12/09: Re: Post PAR Simulation and Actual FPGA results differ
    95364: 06/01/22: Re: Xilinx padding LC numbers, how do you feel about it?
    96938: 06/02/13: Re: SCHEMATICS ... Is anybody as frustrated as I am with the software?
    97019: 06/02/14: Re: digital logic library by 74xxxx part number?
    97633: 06/02/24: Re: Combinatorial Division?
    98309: 06/03/08: Re: for all those who believe in ASICs....
    100342: 06/04/06: Re: Streamlining FIRs in System Generator
    106119: 06/08/07: Re: WHAT SITUATION I NEED A BUFFER
    106537: 06/08/14: chipscope_opb_iba woes in XPS EDK
    106590: 06/08/15: Re: chipscope_opb_iba woes in XPS EDK
    106953: 06/08/22: Re: ISE 8.2i and EDK 8.1i
    108619: 06/09/13: Re: Prefered ieee libraries?
    110349: 06/10/14: Re: Xilinx documentation typos
    110877: 06/10/25: XPS crashes while performing clock DRCs when I have DCR components
    111284: 06/10/31: Re: SPDIF receiver
    111308: 06/11/01: Re: SPDIF receiver
    111970: 06/11/13: Re: Why 64-bit PLB?
    114019: 07/01/02: Re: Xilinx: Connecting an on-chip memory-like component to Microblaze
    114021: 07/01/02: Re: PPC PLB <=> FPGA fabric
    114190: 07/01/06: Does Modelsim XE support coreconnect BFM simulation?
    114333: 07/01/11: Re: Does Modelsim XE support coreconnect BFM simulation?
    114519: 07/01/18: Re: running applications from external memory
    115963: 07/02/26: Re: Interfacing to 10Gig ethernet with Xilinx FPGAs
    115995: 07/02/27: Re: How can we know how many BRAM are used?
    116594: 07/03/13: using system ACE for generic app data storage - file system intelligence
    117029: 07/03/22: Re: Why is Xilinx's WebPACK so inferior?
    118050: 07/04/16: Re: PLB Master
    118051: 07/04/16: Re: FPGA High speed Transceivers for source synchronus bus application
    118100: 07/04/17: Re: PLB Master
    118559: 07/04/30: Re: DS18B20 connection on FPGA?
    118599: 07/04/30: Re: Please help me fast !!!!!
    119016: 07/05/09: Re: lwIP RAW mode support for V4 temac
    120007: 07/05/30: Re: Building Gradually Expertise on VHDL/Verilog Design
    120175: 07/06/02: Re: Xilinx Seminars in Wiesbaden, Berlin, Hannover
    120733: 07/06/15: booting a large V4 PPC program with a minimum of on chip bram
    120734: 07/06/15: How to make a small (<4Kbyte) program for V4 PPC
    120741: 07/06/15: Re: How to make a small (<4Kbyte) program for V4 PPC
    120743: 07/06/15: Re: booting a large V4 PPC program with a minimum of on chip bram
    120768: 07/06/15: Re: How to make a small (<4Kbyte) program for V4 PPC
    120771: 07/06/15: Re: booting a large V4 PPC program with a minimum of on chip bram
    120774: 07/06/15: Re: booting a large V4 PPC program with a minimum of on chip bram
    120813: 07/06/18: Re: booting a large V4 PPC program with a minimum of on chip bram
    121014: 07/06/21: is Ultracontroller-2 supposed to work under XPS/ISE 9.1?
    121323: 07/07/02: Re: Multiplier in Xilinx
    121869: 07/07/13: Re: ASM within C code in a PPC405 of VIRTEX II Pro
    121981: 07/07/16: Re: 1ms delay in V5 FPGA
    121990: 07/07/17: chipscope PLB IBA - how to get meaningful labels on signals?
    122007: 07/07/17: Re: chipscope PLB IBA - how to get meaningful labels on signals?
    122664: 07/08/02: V4 DSOCM always reads back zeroes
    122731: 07/08/05: Re: V4 DSOCM always reads back zeroes
    122761: 07/08/06: Re: bidirectional pin
    123418: 07/08/27: Re: bidirectional pin help
    123517: 07/08/29: Re: Problems with PLB_DDR2 core and soft reset
    124123: 07/09/12: Re: Address sensitive process, Xilinx virtex2pro
    124228: 07/09/14: Re: Beginner Advice (Languages, tools etc.)
    124240: 07/09/16: Re: Beginner Advice (Languages, tools etc.)
    124241: 07/09/16: Re: Beginner Advice (Languages, tools etc.)
    124360: 07/09/19: Re: Guess: what is the largest number of state machines in a current
    124362: 07/09/19: Re: Guess: what is the largest number of state machines in a current
    124402: 07/09/20: Re: DMA scatter gather with PLB bus?
    124601: 07/09/27: Re: Xilinx upgrade
    124602: 07/09/27: Re: Never buy Altera!!!!
    124809: 07/10/05: Re: How to do one hot state machine in verilog for Xilinx V5 using
    125008: 07/10/15: Re: FPGA quiz: what can be wrong
    125025: 07/10/15: Re: FPGA quiz: what can be wrong
    125140: 07/10/16: Re: FPGA quiz: what can be wrong
    125920: 07/11/08: Re: Microblaze PLB vs. OPB busses
    126334: 07/11/19: Re: Microblaze books
    126357: 07/11/20: Re: problem with adding custom logic to an IP core (xilinx edk)
    128081: 08/01/14: DCR_INTC usage in EDK - where is SR18804?
    128140: 08/01/16: Re: Basic FPGA question about Reset
    128685: 08/02/03: Re: Bitstream verification through readback
    128804: 08/02/06: Re: function/process to generate sine and cosine wave
    129176: 08/02/17: Re: Ballpark PLB frequency
    129201: 08/02/18: Re: Ballpark PLB frequency
    129267: 08/02/19: Re: Ballpark PLB frequency
    129290: 08/02/20: Re: Ballpark PLB frequency
    129554: 08/02/27: Why must a V4 be configured within 10 minutes of power up?
    129591: 08/02/28: Re: Making changes to custom IP in EDK
    129663: 08/03/02: Re: Software for FPGA-based PC scope
    129676: 08/03/03: Re: Software for FPGA-based PC scope
    129949: 08/03/11: Re: Could I develop a new gui using java based on the script language
    130756: 08/03/31: Re: Xilinx and Modelsim?
    130845: 08/04/03: Re: coregenerator bram in synplify pro error
    131287: 08/04/17: Re: Survey: FPGA PCB layout
    131673: 08/04/28: understanding xilinx silicon revisions (does ES come before CES4,
    131676: 08/04/29: Re: Debounce in Verilog?
    131780: 08/05/01: Re: Functional Simulation of Virtex-4 Block Memory
    131783: 08/05/01: Re: Functional Simulation of Virtex-4 Block Memory
    132051: 08/05/12: has anyone made PLB_DDR work with 1Gb DRAM chips?
    132256: 08/05/19: Re: 2-bit Pseudo Random Number Generator
    132260: 08/05/19: Re: bizarre state machine behavior
    132295: 08/05/20: Re: 2-bit Pseudo Random Number Generator
    132296: 08/05/20: Re: bizarre state machine behavior
    132651: 08/06/04: Re: Xilinx vs Altera
    133138: 08/06/18: Re: =?windows-1252?Q?NVIDIA=92s_Tesla_T10P_Blurs_Some_?=
    133140: 08/06/19: Re: Fixed point number hardware implementation
    133314: 08/06/24: Re: Migrating to 9.2i from 8.2i
    133507: 08/07/02: Re: How do I program an fpga once it has been designed and layout
    133763: 08/07/14: Re: Mismatch simulation & post sythese results
    134374: 08/08/07: Re: Downsizing Verilog synthesization.
    135037: 08/09/11: Re: Spartan-II, config pins 5V tolerant? (slave serial)
    136116: 08/11/02: Re: PLBv4.6 with more than 16 slaves
    136228: 08/11/07: Re: Tilera multicore replaces FPGA?
    136230: 08/11/07: Re: Setting FSM encoding in VHDL or in UCF for Xilinx
    136435: 08/11/16: Re: MAC PHY Configuration
    137032: 08/12/19: Re: FPGA partial/catastrophic failure mode question
    137033: 08/12/19: Re: Custom IP Core DMA (Xilinx Virtex II Pro)
    137176: 08/12/30: Re: FPGA > ASIC
    138526: 09/02/25: Re: Converting state machine encoding to std_logic_vector
    138941: 09/03/15: Re: Getting started with FPGA
    140103: 09/04/28: Re: a basics question: using input pins, pullup, short to ground
    140351: 09/05/10: Re: implementing arbitrary combinational functions using block rams
    146367: 10/03/14: Re: Tier Logic introduces the world's first 3D FPGA
    146942: 10/04/03: Re: Free VHDL or Verilog Simulator
    148603: 10/08/05: Re: Logic implementation probelm
    148604: 10/08/05: Re: Xilinx EasyPath Pricing
    149021: 10/09/21: Re: Xilinx XST and a State Machine - A Mystery
    149629: 10/11/12: Re: Statemachine debugging with Chipscope
Jeff Fox:
    66295: 04/02/16: Re: Dual-stack (Forth) processors
    66316: 04/02/17: Re: Dual-stack (Forth) processors
    66410: 04/02/18: Re: Dual-stack (Forth) processors
    66442: 04/02/19: Re: Dual-stack (Forth) processors
    66543: 04/02/21: Re: Dual-stack (Forth) processors
    138977: 09/03/17: Re: Zero operand CPUs
    139010: 09/03/18: Re: Bullshit! - Re: Zero operand CPUs
    139037: 09/03/18: Re: Bullshit! - Re: Zero operand CPUs
    139038: 09/03/18: Re: Bullshit! - Re: Zero operand CPUs
Jeff Graham:
    10412: 98/05/17: XC5200s and Foundation 1.4
    12392: 98/10/10: Re: Xilinx F1.5/FPGA Express wackiness
    23536: 00/06/29: Re: Xilinx XC5200 implementation with F2.1i
Jeff Hunsinger:
    2022: 95/10/03: Re: cheap (free) fpga design software (VHDL
    2533: 95/12/28: Re: [q][Reverse Engineering Protection]
    3479: 96/06/06: Re: FPGA Companies
    3796: 96/08/02: Xilinx/FPGA Timing Problems
    3807: 96/08/05: Re: Xilinx/FPGA Timing Problems
    3828: 96/08/07: Re: Xilinx/FPGA Timing Problems
    3895: 96/08/15: Re: Xilinx XC3090 intermittent place/route prob
    3967: 96/08/26: Re: CHEAP XILINX FPGA ROUTING SOFTWARE ?
    14748: 99/02/14: Xilinx Foundation Base = Useless?
    14783: 99/02/16: Re: Xilinx Foundation Base = Useless?
    14964: 99/02/27: Re: Foundation V1.5 Crash
    15289: 99/03/17: Xilinx Spartan configuration troubles
    15301: 99/03/17: Re: Xilinx Spartan configuration troubles
Jeff Hunsinger/RZXZ30/:
    5405: 97/02/13: Re: Anyone for Linux ?
Jeff Hutchings:
    258: 94/10/05: Motorola MPA (FPGA's)
    311: 94/10/18: Re: FPGA RISC Processor
Jeff Iverson:
    12531: 98/10/15: Re: books
    14980: 99/03/01: Re: newbie questions
    16042: 99/04/29: Re: Reconfigurable Computing
    17933: 99/09/17: Re: simple VHDL?
Jeff Johnson:
    108715: 06/09/15: upgrading firmware on stratix 2 without NIOS IDE
    108741: 06/09/15: Re: upgrading firmware on stratix 2 without NIOS IDE
    108970: 06/09/19: Re: upgrading firmware on stratix 2 without NIOS IDE
Jeff Kiser:
    16994: 99/06/22: Re: Altera/Synplicity TIMESTAMP?
Jeff koehler x221:
    999: 95/04/11: Re: Xilinx simulation models for synopsys..
Jeff Lucas:
    117: 94/08/17: Sizeable symbols using Actel/Concept?
Jeff Millar:
    4911: 96/12/29: Re: ASICs Vs. FPGA in Safety Critical Apps.
    7031: 97/07/25: Re: How do FPGAs outperform DSP at FFT?
    8142: 97/11/20: Re: what is metastability time of a flip_flop
Jeff Mock:
    42059: 02/04/14: Re: virtex2 bufgce or not bufgce
    42260: 02/04/18: Re: Understanding clock routing (or not)
    42803: 02/05/02: Re: Duplicating IOB FFs Without I/O Pads Being Inserted in XST
    43231: 02/05/16: Spartan2 on a Compact Flash card
    43380: 02/05/20: Re: How to generate fractional-N clock ?
    43694: 02/05/29: Re: place and route simulation time
    44513: 02/06/21: Re: 12 years experience in Digital HW/ FPGA design, looking for job in the US
    44723: 02/06/27: Re: VIRTEX II DCM Question
    44749: 02/06/28: Re: VIRTEX II DCM Question
    45013: 02/07/09: Re: how to keep info. in RAM during reconfiguration?
    45046: 02/07/10: Re: how to keep info. in RAM during reconfiguration?
    45051: 02/07/10: Re: How to locate the combinational loop in RTL source
jeff murphy:
    87039: 05/07/13: ise 7.1 Input clk is never used.
    87079: 05/07/14: Re: ise 7.1 Input clk is never used.
    87116: 05/07/15: Re: Linux Fedora and Xilinx ISE
    88841: 05/08/29: openrisc, jp1 jtag debug utility
    88893: 05/08/30: Re: openrisc, jp1 jtag debug utility
    89159: 05/09/06: Re: openrisc, jp1 jtag debug utility
Jeff Peterson:
    63291: 03/11/19: 400 Mb/s ADC
    63324: 03/11/19: Re: 400 Mb/s ADC
    63341: 03/11/19: Re: 400 Mb/s ADC
    63342: 03/11/19: Re: 400 Mb/s ADC
    63410: 03/11/20: Re: 400 Mb/s ADC
    63411: 03/11/20: Re: 400 Mb/s ADC
Jeff Piper:
    22112: 00/04/25: ****Easy Money****
Jeff Reeve:
    23742: 00/07/06: 56 independent PN streams
    45449: 02/07/24: 32-bit PCI Target core
Jeff Sampson:
    3453: 96/06/01: Re: PldShell -> Max+Plus2 conversion
    9430: 98/03/13: Strange Xilinx question?
    9441: 98/03/14: Re: Strange Xilinx question?
    9445: 98/03/14: Re: Strange Xilinx question?
    9446: 98/03/14: Re: Strange Xilinx question?
    59284: 03/08/13: Old Xilinx FPGAs
    59319: 03/08/14: Re: Old Xilinx FPGAs
    59323: 03/08/14: Re: Old Xilinx FPGAs
    59357: 03/08/15: Re: Old Xilinx FPGAs
    59457: 03/08/19: Re: Parallel interface to an FPGA
    59464: 03/08/19: Xilinx FPGA pin locking/assignment
    59495: 03/08/20: Re: Xilinx FPGA pin locking/assignment
    59528: 03/08/20: Re: Xilinx FPGA pin locking/assignment
    59529: 03/08/21: Re: Xilinx FPGA pin locking/assignment
Jeff Sasmor:
    8942: 98/02/08: Re: Free FPGA tools???
Jeff Seeger:
    8688: 98/01/20: Re: bypass for 68 pin PLCC
Jeff Seltzer:
    59809: 03/08/28: Re: Datasheet for National PAL20L10
    98493: 06/03/10: Re: Troubles when upgrading Embedded Virtex-4Fx PowerPc
Jeff Shafer:
    96371: 06/02/02: Sharing BRAM between Xilinx PowerPC's (on data-OCM ports)
    96396: 06/02/03: Re: Sharing BRAM between Xilinx PowerPC's (on data-OCM ports)
    96455: 06/02/03: Re: Sharing BRAM between Xilinx PowerPC's (on data-OCM ports)
    98032: 06/03/03: Re: Sharing BRAM between Xilinx PowerPC's (on data-OCM ports)
    99837: 06/03/29: Re: EDK/Xilinx : Insertion of ECC capability into BRAM controller
    100123: 06/04/04: Re: Sharing BRAM between Xilinx PowerPC's (on data-OCM ports)
    100180: 06/04/04: Re: Sharing BRAM between Xilinx PowerPC's (on data-OCM ports)
    115220: 07/02/03: Re: data OCM BRAM Issues
Jeff Simmons:
    10333: 98/05/12: Re: PALCE22v10 / GAL22v10 programming algorithms needed
Jeff Smith:
    19257: 99/12/09: Lattice ispLSI Security
Jeff Stout:
    9339: 98/03/06: Re: Version Control for schematics?
    13806: 98/12/28: Re: 22V10 Metastability - help please
    24604: 00/08/14: Re: Non-disclosures in job interviews
    24636: 00/08/15: Re: Non-disclosures in job interviews
    39262: 02/02/05: I want pla2tdf.exe
    40549: 02/03/09: Re: Xilinx Download Cable Connectors
Jeff Streznetcky:
    14811: 99/02/18: Re: Digital PLL
    17463: 99/07/29: Xilinx timing constraints question
    17776: 99/09/02: Re: Virtex dev boards
    17777: 99/09/02: Re: Virtex dev boards
    17778: 99/09/02: Re: Virtex dev boards
    17813: 99/09/07: xilinx placer score?
Jeff Tong:
    26352: 00/10/12: PCB board simulation - Need basic help!
Jeff Tucker:
    10607: 98/06/05: Re: Example of 8051 codes to configure Xilinx fpga
Jeff Vallier:
    13124: 98/11/16: Re: Low Cost FPGA Development Tools
    13126: 98/11/16: Re: Board for FPGA ?
    13562: 98/12/09: Re: The best PLD?
Jeff Wallace:
    42232: 02/04/18: XCV812E-6BG560C - Virtex - E !!!!!!!!!
    42828: 02/05/03: Re: Availability of XC2S150E-6FG456I
    42829: 02/05/03: CAN EVERYONE PLEASE READ THIS!! - FEEDBACK APPRECIATED!!
Jeff Weintraub:
    51272: 03/01/09: Re: Different Versions of Coregen
Jeff Wetch:
    1603: 95/07/25: Actel Place and Route response
    1604: 95/07/25: Actel Place and Route response
    3236: 96/04/30: Re: S-modules and C-modules of Actel's FPGA
    3878: 96/08/14: Re: ACTEL Security Fuse
    8385: 97/12/11: Re: Z80 in FPGA: clockspeed?
    47931: 02/10/07: Re: xilinx contact with regard to qpro
Jeff Wilkinson:
    2538: 95/12/29: Programmable Interconnect ICs
    2539: 95/12/29: Programmable Interconnect ICs - Repost
Jeff Wills:
    85: 94/08/11: Re: Would you like a free C to netlist compiler?
<jeff.johnson.au@gmail.com>:
    122995: 07/08/13: Using Virtex-II Pro MGT with external CDR
jeff_n_moz:
    68109: 04/03/26: counter design
<jeffbush001@gmail.com>:
    157712: 15/02/11: Open Source GPGPU core
    157715: 15/02/13: Re: Open Source GPGPU core
    157719: 15/02/13: Re: Open Source GPGPU core
    157721: 15/02/15: Re: Open Source GPGPU core
jeffcannon:
    93149: 05/12/14: Custom data rates with Virtex 2 Pro-X MGTs
    94172: 06/01/06: Re: Chipscope Pro
<jeffery_dong@hotmail.com>:
    130668: 08/03/29: Re: TCL testcase in Modelsim.
jeffg:
    136988: 08/12/17: Re: Microblaze without external ram
<jeffjcannon@gmail.com>:
    130525: 08/03/26: Re: Serial Transmission w/o 8B/10B encoding
    135089: 08/09/15: Re: Moving to Altera from Xilinx
    136469: 08/11/18: Re: Why memory for this Nios II is still not enough
JeffM:
    87934: 05/08/03: Re: System Engineering in the R/D World
    110233: 06/10/12: SPAM -- FPGA image processing camera
    110244: 06/10/12: Re: SPAM -- FPGA image processing camera
<jeffnewcomb@nci-usa.com>:
    104487: 06/06/28: Virtex5 Availability
    104502: 06/06/28: Re: Virtex5 Availability
    106755: 06/08/18: Problem Instantiating a DSP48E or RAMB36 for a Virtex5 in ISE 8.2 SP2
    106760: 06/08/18: Re: Problem Instantiating a DSP48E or RAMB36 for a Virtex5 in ISE 8.2 SP2
    106771: 06/08/18: Re: Problem Instantiating a DSP48E or RAMB36 for a Virtex5 in ISE 8.2 SP2
    106776: 06/08/18: Re: Problem Instantiating a DSP48E or RAMB36 for a Virtex5 in ISE 8.2 SP2
    107299: 06/08/26: What is the truth about the Virtex5 ?
    107340: 06/08/26: Re: What is the truth about the Virtex5 ?
    107345: 06/08/26: Re: What is the truth about the Virtex5 ?
    107494: 06/08/29: Re: What is the truth about the Virtex5 ?
Jeffrey Arnold:
    2936: 96/03/03: Re: Comp.Arch.FPGA
    3242: 96/05/02: Re: On FPGAs as PC coprocessors
    4609: 96/11/20: CFP: FCCM'97 IEEE Symp on Custom Computing Machines
    49948: 02/11/26: FCCM'03 Call for Papers
    64469: 04/01/05: FCCM'04 Reminder -- submission deadline Jan 19
Jeffrey Bain:
    2235: 95/11/07: Needed: Protozone Adapter
Jeffrey C. Marden:
    3514: 96/06/12: Re: FPGA Companies
    4495: 96/11/06: Actel Designer and Win NT 4.0
    7116: 97/08/01: Re: Download FLEX10K over the LPT port
Jeffrey David Cohen:
    259: 94/10/05: CLI
Jeffrey Ebert:
    3339: 96/05/15: Re: Looking for free FPGA softw./Xilinx
Jeffrey Graham:
    35107: 01/09/21: comparison of performance and advantages for fpga's versus
jeffrey j cook:
    19318: 99/12/13: VirtexE availability?
    19344: 99/12/15: Re: VirtexE availability?
    21621: 00/03/27: Virtex DLL Spread-spectrum clock sensitivity
    25271: 00/09/04: FS: Xilinx XCV200-5PQ240, IDT 71V3558S/133PF
Jeffrey L. Hutchings:
    1418: 95/06/20: Re: Low cost ISA board
    1597: 95/07/25: Re: Lattice isp programming adapters
    2574: 96/01/04: Re: What does VHDL stand for?
    5586: 97/02/26: Re: Customizing Viewdraw in Workview Office 7.3 ... Is it possible?
Jeffrey L. Jensen:
    16728: 99/06/04: Re: The Chickenshit War in Kosovo!
Jeffrey L. Madden:
    14086: 99/01/12: Problems with processes
Jeffrey LIU:
    12444: 98/10/13: Re: PCI target code
Jeffrey M. Arnold:
    62: 94/08/07: Charter (was Re: This (new) froup)
    80: 94/08/11: Re: Wanted: Literature on Reconfigurable Systems..
    205: 94/09/21: Mail reflector
    206: 94/09/21: C.A.F. WWW page (aperiodic reminder)
    254: 94/10/03: WWW server
    297: 94/10/14: FCCM'95 Call for Papers
    422: 94/11/14: C.A.F. WWW page (aperiodic reminder)
    421: 94/11/14: C.A.F. WWW page (aperiodic reminder)
    508: 94/12/13: FCCM'95 final Call for Papers
    538: 94/12/27: 6 th IEEE International Workshop Rapid Systems Prototyping
    696: 95/02/09: FCCM'95 Registration and Call for Participation
    792: 95/03/02: FPL'95: Final Call for Papers
    793: 95/03/03: C.A.F. WWW page (aperiodic reminder)
    852: 95/03/13: FCCM'95 Program
    893: 95/03/22: FCCM'95 Registration and Hotel
    931: 95/03/30: Re: FAQ/getting started/cheap?
    1014: 95/04/13: FCCM'95 Program
    1121: 95/05/02: Re: Web/FTP site for FPGA based research
    1288: 95/05/28: Re: Altera Contacts ...
    1521: 95/07/06: anonymous postings
    1866: 95/09/12: Archive reminder
    2023: 95/10/03: Call For Papers: FCCM'96
    2202: 95/10/31: Re: AMCC pci kit- problems
    2241: 95/11/08: FPL'96 Call for Papers
    2778: 96/02/06: FCCM'96 Registration
    3018: 96/03/14: FCCM'96 Preliminary Program
    3019: 96/03/14: FCCM'96 Registration
    4421: 96/10/27: CFP: FCCM'97 Int'l Symp on Custom Computing Machines, 16-18 April Napa, CA
    5675: 97/03/05: FCCM'97 Registration and Hotel Information
    5822: 97/03/18: FCCM'97 Preliminary Program
    5976: 97/04/01: FCCM'97 Preliminary Program
    6053: 97/04/08: Re: Reconfig computing and multimedia?
    6085: 97/04/10: Re: comp.arch.fpga archiv dead?
    6166: 97/04/21: FCCM'97 Photo album
    6184: 97/04/23: Re: Reconfigurable Computing
    6646: 97/06/09: Re: readback on xc40xx ?
    8031: 97/11/09: FCCM'98 Call For Papers
    8362: 97/12/10: Reminder: FCCM98 Call For Papers
    9455: 98/03/14: FCCM'98 Preliminary Program
    12645: 98/10/21: FCCM'99 Call for Papers
Jeffrey R. White:
    7028: 97/07/24: real-life Aptix experiences
Jeffrey S. Dutky:
    10377: 98/05/15: Re: Minimal ALU instruction set.
    19808: 00/01/12: Re: HW resources increased
    19840: 00/01/14: Re: HW resources increased
Jeffrey Smith:
    81864: 05/04/02: USB blaster
Jeffrey Turner:
    52255: 03/02/05: Re: clock ditribution tree
Jeffrey Vallier:
    31931: 01/06/08: Re: safe state machine design problem
    31933: 01/06/08: Re: Download problems
    32028: 01/06/11: Re: Xilinx webpack annoyances (long and whiny)
    32042: 01/06/11: Re: Doing Ethernet in a Virtex ?
    32091: 01/06/13: Re: Fifo Clock in SpartanII
    32429: 01/06/26: Re: Xilinx Spartan - Power Rail Related Timing Problem
    33052: 01/07/16: Re: Fixing routing in a Virtex FPGA
Jeffrey Yuan:
    2619: 96/01/11: Lattice isp Starter Kit and 3 ispLSI1016-80LJ Devices For Sale
jeffrey.johnson:
    137516: 09/01/21: Re: rank beginner here, need to know where to start to get RS232 comm's working, and ...
<jeffrey.thia@gmail.com>:
    159315: 16/10/03: Re: ANN: Amontec JTAGkey programs XC4VLX25 at 2.8s
<jeffreyzuelch@my-deja.com>:
    20627: 00/02/16: Re: 100% slice utilization in Virtex FPGA
    20628: 00/02/16: Re: 100% slice utilization in Virtex FPGA
    20629: 00/02/16: Re: 100% slice utilization in Virtex FPGA
jeffsen:
    77943: 05/01/20: How does a SDRAM controller work?
Jeffsen:
    74949: 04/10/22: Re: Partial reconfiguration of Xilinx
    74950: 04/10/22: CoreConnect Bus : How to speed up the PLB
    75770: 04/11/14: DMA for PPC in Virtex-II Pro/EDK6.2
    77965: 05/01/21: Re: Virtex-II bus macro doubt
    79014: 05/02/11: Re: C program to big for microblaze?
Jeffsen (dot):
    78956: 05/02/10: GEMAC and MGT on ML300
    78957: 05/02/10: Re: GEMAC and MGT on ML300
jeffsen (toberemoved):
    84569: 05/05/21: Re: For accessing my SDRAM,what should i do?
jega:
    122546: 07/07/31: Clarifications Regarding FlexRay Stand Alone Cotroller Interfacing With PIC Microcontroller
<jelle@bang.zap>:
    14743: 99/02/14: Re: Xilinx de-compiler
<jelloaman@gmail.com>:
    159822: 17/03/24: Re: Master Xilinx FPGA like Jtag bridge.
    159823: 17/03/24: Re: Master Xilinx FPGA like Jtag bridge.
Jelly:
    65669: 04/02/04: Reconfiguring at runtime internally?
Jen:
    34581: 01/08/29: Virtex II sizing rule of thumb
    34735: 01/09/05: Re: Virtex II sizing rule of thumb
    58011: 03/07/11: Re: Leonardo changes name of lpm megafunction
Jeniffer:
    52968: 03/02/27: Newbie Qn: Power connections with virtex FPGAs
    53112: 03/03/04: Implementation of latch in FPGA
    53289: 03/03/10: Static Tming Analysis
    53622: 03/03/18: Conversion of Xilinx bit file
Jenn Lee:
    72182: 04/08/10: Example of network router and # of LUTs utilized - Searching for 3rd party compilation of "typical" specs
Jennifer Hou:
    9873: 98/04/10: IEEE RTSS 98 -- Submission Deadline May 1
    9898: 98/04/11: IEEE RTSS 98 -- Submission Deadline May 1
Jennifer Jenkins:
    28340: 01/01/08: Re: WebPack-ISE .ucf problem?
    30156: 01/03/26: Re: Simplified ISP of XCR3256XL from BIF file fails
    32919: 01/07/11: Re: WebPACK problem
    33336: 01/07/23: Re: free VHDL and/or Verilog tools?
    33597: 01/07/31: Re: i2c master
    54351: 03/04/08: Re: Dead cpld?
    54574: 03/04/14: Re: request for simple UART
Jennifer Walton:
    31382: 01/05/21: Hardware Engineer-RTOS,PLD,VXworks,fibre channel
jenny howard:
    10894: 98/06/29: need help!
Jenny Pencis:
    2916: 96/02/28: Zycad GF100K FPGA's
Jens:
    87208: 05/07/19: ISE7.1 Map:Portability/export/Port_Main.h:127:1.22.234.1
jens:
    106691: 06/08/17: Re: FFT on an FPGA
    109806: 06/10/05: Re: An implementation of a clean reset signal
    109864: 06/10/06: Re: An implementation of a clean reset signal
    118587: 07/04/30: Re: debounce state diagram FSM
    128399: 08/01/24: Re: Random Number Generation in VHDL
    131129: 08/04/11: Re: case statements- verilog to vhdl
Jens Baumann:
    80206: 05/03/02: spartan3 development board in Europe?
    80227: 05/03/02: Re: spartan3 development board in Europe?
    80343: 05/03/04: Re: spartan3 development board in Europe?
    80622: 05/03/09: Re: spartan3 development board in Europe?
    81141: 05/03/18: Re: Spartan 3 to tempsensor interface
    82331: 05/04/11: free HDL ebook?
    89346: 05/09/13: Re: FFT implementation in Xilinx's Spartan 3
Jens Clausen:
    7608: 97/09/26: AMD TAXI
Jens Frauenschlaeger:
    37236: 01/12/04: JTAG readback format
    40065: 02/02/26: readback by JTAG
    41711: 02/04/05: Parallel cable IV schematic available???
    42755: 02/05/02: Re: JTAG programmer (ick!)
    42757: 02/05/02: Re: Xilinx Download Cable III
    49849: 02/11/22: Re: Look up tables
Jens Ginzel:
    6747: 97/06/23: looking for FPGA to access VMEBus
Jens Hagemeyer:
    109713: 06/10/04: Re: Virtex-II Pro Platform FPGA : Assembling the modules
    109730: 06/10/04: Re: Virtex-II Pro Platform FPGA : Assembling the modules
    109751: 06/10/05: Re: Virtex-II Pro Platform FPGA : Assembling the modules
    109790: 06/10/05: Re: Virtex-II Pro Platform FPGA : Assembling the modules
    109841: 06/10/06: Re: Virtex-II Pro Platform FPGA : Assembling the modules
    109885: 06/10/06: Re: Virtex-II Pro Platform FPGA : Assembling the modules
    110353: 06/10/14: Re: Virtex-II Pro Platform FPGA : Assembling the modules
    110383: 06/10/14: Re: Virtex-II Pro Platform FPGA : Assembling the modules
    130847: 08/04/03: Re: Beginner's silly question about ICAP
    133334: 08/06/25: Re: 1D or 2D Placement for dynamically partially reconfigurable
    136004: 08/10/27: vMAGIC 0.1.1 (alpha) released
Jens Hildebrandt:
    21699: 00/03/29: LUT components in Synopsys/Xilinx design flow
    21785: 00/03/31: Re: 82C54
    22060: 00/04/17: PULL-UPs on Xilinx-FPGA pads
    22072: 00/04/18: Re: PULL-UPs on Xilinx-FPGA pads
    22083: 00/04/20: Re: PULL-UPs on Xilinx-FPGA pads
    22668: 00/05/17: Re: SMT 7 segment display ??
    23643: 00/07/04: Re: Altera Ships Largest PLD
    23754: 00/07/07: Re: Clock Buffer
    23799: 00/07/10: Re: Clock Buffer
    25069: 00/08/25: "generate" and instance name indexes in Synopsys
    32019: 01/06/11: Re: Flash programming via FPGA's JTAG ????
    35933: 01/10/24: Re: Bidirectional port is converted to input during synthesis
    39079: 02/01/31: Re: Java or bytecode processors??
    42364: 02/04/22: Re: Xilinx Easypath- Selling parts with known defects
    42647: 02/04/30: Re: SpartanII ISA interface, IDE and ISA contention??
    45210: 02/07/16: Re: I want to buy 4 Xilinx FPGA
    52739: 03/02/20: Re: XCV800 Configuration PROM
    53121: 03/03/04: Re: Implementation of latch in FPGA
    53429: 03/03/13: Re: [Xilinx] Looking for Parallel Cable III ...
    53877: 03/03/26: Re: How to avoid this Latch
    54961: 03/04/23: Re: request for simple UART
    61697: 03/10/09: Re: beginner - exisit some free schematics programmer for fpga ?
    70382: 04/06/15: Re: Several Problems with Spartan2 Configuration
Jens Huettemann:
    53421: 03/03/13: Re: RESET --- Synchronous Vs Asynchronous
Jens Konig:
    26109: 00/10/04: Re: Whoa, Noise on a digital output pin?, and Minor rant on XC9500 S/W, was Re: Simon,Floating Inputs
Jens Lauer:
    18986: 99/11/23: Hyperstones RiscDSP Eva Kit seems buggy
Jens Mander:
    54325: 03/04/08: Educational FPGA board requirements
    54333: 03/04/08: Re: Power Supply for Spartan II FPGA
    54334: 03/04/08: Re: Constraints for high speed I/O signals.
    85484: 05/06/10: fast universal compression scheme and its implementation in VHDL
    88803: 05/08/29: fast universal compression scheme and its implementation in VHDL
Jens Niemann:
    39526: 02/02/12: Newbie SpartanII Block Ram question
    39557: 02/02/13: Re: Newbie SpartanII Block Ram question
    39659: 02/02/15: Newbie question Synchronous RAM
    47947: 02/10/08: Booting a FPGA via USB
    48018: 02/10/09: Re: Booting a FPGA via USB
    49511: 02/11/14: Programming a Spartan2 via JTAG
    51927: 03/01/26: Prob. with data-input of SDRAM-Controller
Jens Nowack:
    55135: 03/04/28: LVDS I/O with Altera Cyclone
    55159: 03/04/29: Re: LVDS I/O with Altera Cyclone
    55161: 03/04/29: clock i/o`s Altera Cyclone
    55537: 03/05/12: Register in FPGA
    55838: 03/05/21: Re: Register in FPGA
    56070: 03/05/28: Simulation in Altera Quartus II
    56479: 03/06/06: Quartus II time delay
Jens Petersen:
    156727: 14/06/08: Re: 22V10 programmer
Jens Popp:
    23737: 00/07/06: Xilinx Design Flow
    23764: 00/07/07: FPGA Express/Foundation Error 470
    23801: 00/07/10: Xilinx XC4000E / Renoir
    23922: 00/07/15: Renoir/Update Symbol from HDL
    28780: 01/01/24: Hardware Debugger crashes with Xchecker Cable
Jens Weigle:
    4488: 96/11/05: UART FOR FPGAS
Jens-Christian Lache:
    34944: 01/09/14: using BlockRAM
    34969: 01/09/17: Re: using BlockRAM
    34972: 01/09/17: Re: how to simulate virtex components?
    34978: 01/09/17: Re: how to simulate virtex components?
    35021: 01/09/18: Re: using BlockRAM
    35066: 01/09/20: Re: Timing constraints...
    35071: 01/09/20: Re: Timing constraints...
    35217: 01/09/26: Re: Virtex 2 : using IOB registers
    35218: 01/09/26: how to dublicate logic?
    35230: 01/09/26: Re: how to dublicate logic?
    35254: 01/09/27: Re: how to dublicate logic?
    35304: 01/09/28: Re: how to dublicate logic?
    35314: 01/09/28: Re: how to dublicate logic?
    35945: 01/10/24: Re: how to dublicate logic?
    36332: 01/11/06: placement for if (vhdl)
    36360: 01/11/07: Re: placement for if (vhdl)
    36429: 01/11/08: Re: Xilinx dedicated IO pins
Jens-Peter Kaps:
    8083: 97/11/16: Xilinx Logiblox in Synopsys
    9033: 98/02/16: Xilinx Simulation in Synopsys
<jens_strauss@my-deja.com>:
    19961: 00/01/20: Correlator with VHDL
jenze:
    97784: 06/02/27: Re: A dev board supporting partial/dynamic reconf.
    100048: 06/04/02: Re: Xilinx SelectMAP problem
    100073: 06/04/03: Re: Xilinx SelectMAP problem
    101722: 06/05/05: Re: Xilinx SelectMAP Question
    101970: 06/05/08: Re: Installing BFM toolkit
    102185: 06/05/11: Re: Installing BFM toolkit
Jeong-Gun Lee:
    68069: 04/03/26: Finding Triscend A7 Examples
Jep:
    101808: 06/05/07: flashing a led
    101834: 06/05/07: Re: flashing a led
Jer-Sheng Chen:
    13112: 98/11/16: Re: Looking for a good documentation on FPGA
Jered:
    91478: 05/11/07: ML402 DDR SDRAM
Jeremie:
    72341: 04/08/16: Re: Xilinx 804 Aurora vhdl Design patch
    120865: 07/06/19: Rocketio connection Virtex2pro-Virtex4
Jeremie Veyret:
    72294: 04/08/13: Xilinx 804 Aurora vhdl Design patch
Jeremie WEBER:
    47402: 02/09/25: Re: FPGA fail when Electrostatic discharge Occurs
    47404: 02/09/25: Re: FPGA fail when Electrostatic discharge Occurs
Jeremy:
    66605: 04/02/23: How to configure FPGA manually ?
    66693: 04/02/25: Example using a custom OPB slave core with and interrupt
    95167: 06/01/20: Virtual Pin in Xilinx ISE
    95559: 06/01/23: Re: Virtual Pin in Xilinx ISE
    121137: 07/06/26: Xilinx ISE 9.1 - Version Control - VSS
jeremy:
    39553: 02/02/13: CLKDLL doesn't work without BUFG ?
Jeremy Bennett:
    136634: 08/11/27: Re: opencores can core
    137077: 08/12/22: Re: Bit width in CPU cores
    137146: 08/12/28: Re: which HLL for HPC applications implementation?
    138877: 09/03/13: Re: What happens at opencores.org?
    139469: 09/03/31: Re: SiliconBlue on Wikipedia
Jeremy Cooke:
    27017: 00/11/07: Re: FPGA DESIGNER LONG ISLAND
    27018: 00/11/07: Architecture/environment suggestions
    27078: 00/11/09: Re: Microprocessor Verilog/VHDL Models
Jeremy D. Grotte:
    42452: 02/04/24: Using PAL/GAL/FPGA to replace CPU's (correct news group?)
    42488: 02/04/25: Re: Using PAL/GAL/FPGA to replace CPU's (correct news group?)
    42534: 02/04/26: Re: Using PAL/GAL/FPGA to replace CPU's (correct news group?)
Jeremy Harris:
    122736: 07/08/05: Re: bare bone PCI cards with FPGAs
Jeremy Price:
    106139: 06/08/08: Networking : Multicast Performance
    106509: 06/08/14: Error building mpmc2
Jeremy Ralph:
    101783: 06/05/06: FPGA-based hardware accelerator for PC
    101790: 06/05/06: Re: FPGA-based hardware accelerator for PC
    101792: 06/05/06: Re: FPGA-based hardware accelerator for PC
    101917: 06/05/08: Re: FPGA-based hardware accelerator for PC
    102110: 06/05/10: Re: FPGA-based hardware accelerator for PC
    103137: 06/05/25: Re: FPGA-based hardware accelerator for PC
    103994: 06/06/16: Re: ARM cores in FPGA ?
Jeremy Sonander:
    2559: 96/01/02: Re: VHDL Editor for Windows PC, Suggestions?
    3759: 96/07/26: Re: ATT serial EEPROMs
Jeremy Stringer:
    77764: 05/01/17: Re: Problems in timing simulations
    77952: 05/01/21: Re: X-checker Pod : Problem w/ X-checker and Win2000
    78529: 05/02/03: Spartan-3 Static Timing Analysis with Voltage/Temperature Pro-rating
    79538: 05/02/21: Re: why are PCI-based FPGA cards so expensive ?
    79604: 05/02/22: Jitter and Static Timing Analysis
    79607: 05/02/22: Re: Shift register example?
    79612: 05/02/22: Re: Jitter and Static Timing Analysis
    79841: 05/02/25: Re: publishing IP
    79983: 05/02/28: Re: Looking for some rules of thumb - migrating a discrete 74HCxxx
    80027: 05/03/01: Re: publishing IP
    80107: 05/03/02: Re: Problem with LXT970A
    80517: 05/03/08: Re: Looking for some rules of thumb - migrating a discrete 74HCxxx
    81040: 05/03/17: Re: Help with ram controller on Xilinx Spartan IIE
    81041: 05/03/17: Re: spartan3E price
    81042: 05/03/17: Re: SR latches in Xilinx devices?
    81051: 05/03/17: Re: Creating own RPMs using Xilinx ISE
    81274: 05/03/21: Re: Is the Xilinx EDK free?
    81407: 05/03/23: Re: Difference between simulation types
    81683: 05/03/30: Re: Difference between simulation types
    82038: 05/04/06: Re: Protection measurements
    82105: 05/04/07: Re: Open PowerPC Core?
    82366: 05/04/12: Re: process trouble, error: multi source
    83114: 05/04/24: Re: CAM for FPGA ...
    83338: 05/04/28: DCM Cycle-to-Cycle Jitter
    83392: 05/04/29: Re: DCM Cycle-to-Cycle Jitter
    83671: 05/05/05: Re: Newbie VHDL/FPGA question
    83677: 05/05/05: Re: Timing and synthesis problem+xilinx
    83993: 05/05/11: Re: Using capacitor to slow the rise time.
    84054: 05/05/12: Re: Using capacitor to slow the rise time.
    84363: 05/05/18: Re: Registers replication on Xilinx IOBs
    84506: 05/05/20: Jobs going in New Zealand
    84639: 05/05/24: Re: Jobs going in New Zealand
    84850: 05/05/31: Re: Jobs going in New Zealand
    84914: 05/06/01: Re: Xilinx Answer Record 21127
    85396: 05/06/09: Re: Why do VHDL gate level models simulate slower than verilog
    85475: 05/06/10: Re: floorplanning
    85629: 05/06/13: Re: FPGA or SSE2 ?
    85679: 05/06/14: Re: FPGA or SSE2 ?
    85731: 05/06/15: Re: Somewhat OT - falling behind the times ...
    85779: 05/06/16: Re: convert vhdl to edif
    85837: 05/06/17: Re: Idea exploration 1.1 - Inertia based angular sensor.
    85995: 05/06/20: Re: comp.arch.fpga.<mfr>
    85996: 05/06/20: ISE 7.1 Service Pack 2 - Ready yet?
    86033: 05/06/21: Re: ISE 7.1 Service Pack 2 - Ready yet?
    86616: 05/07/01: Re: ip core supply
    86622: 05/07/01: Re: Avnet V2P development kit woes
    86623: 05/07/01: Re: V4 and DDR2 666
    87093: 05/07/15: Re: Reading a PS/2 mouse
    87187: 05/07/19: Re: Reading a PS/2 mouse
    87712: 05/07/29: 2-bit RAM16X In a V2PRo
    87985: 05/08/05: Re: System Engineering in the R/D World
    88198: 05/08/12: Re: fpga- DDR or DDR2
    88334: 05/08/16: Re: Creating EDIF from VHDL
    88709: 05/08/26: Re: Kingston module structure
    90208: 05/10/07: Re: FSM with High load on clock signal
    90212: 05/10/07: Re: Xilinx IMPACT Problem... detects 101 unknown devices
    90465: 05/10/14: Re: How to Reduce Interconnects (VDD and VSS)
    90612: 05/10/18: Re: FPGA timming
    91222: 05/11/02: Re: can ethereal detect an ethernet packet for which crc is wrong
    91225: 05/11/02: Re: newbie question
    91348: 05/11/04: Re: FPGA C Compiler on sourceforge.net (TMCC derivative)
    91429: 05/11/07: Re: FPGA C Compiler on sourceforge.net (TMCC derivative)
    91486: 05/11/08: Re: clock timing
    91603: 05/11/10: Re: What are important factors when selecting Intellectual Property?
    91626: 05/11/10: Re: Bus for Spartan3
    91824: 05/11/15: Re: i2c slave does not acknowlege
    93104: 05/12/14: SGMII Interface
    93148: 05/12/15: Re: SGMII Interface
    93430: 05/12/22: Re: Is there anyboay work on the subject with the embeded system
    93490: 05/12/23: Re: Place and Route Algorithms: where's the fat?
    94495: 06/01/13: Re: How to create a delay BUF?
    94519: 06/01/13: Re: How to create a delay BUF?
    94649: 06/01/16: Re: Don't even get me started on lead,
    97385: 06/02/22: Re: FPGA - software or hardware -2-
    97803: 06/02/28: Re: VHDL to create LUT based delay
    98745: 06/03/16: Re: Soldering SMT/BGA
    98808: 06/03/17: Re: Debugging ideas.
    98826: 06/03/17: Re: Urgent Help Needed!!!!!
    99233: 06/03/22: Re: Virtex-4 RocketIO and G.709 OTU-2
    99650: 06/03/28: Re: OpenSPARC released
    100171: 06/04/05: Source-synchronous IO constraints in Synplify
    100456: 06/04/10: Re: FPGA FAQ and the spam problem
    109121: 06/09/21: Re: VHDL oddity
    112016: 06/11/15: Re: Influence of temperature and manufacturing to propagation delay
Jeremy Webb:
    61726: 03/10/09: Re: Digesting runs of ones or zeros "well"
    61755: 03/10/09: Re: Digesting runs of ones or zeros "well"
    73028: 04/09/10: Re: Simulation probs with Altera LPM_FIFO+
    73030: 04/09/10: Re: Simulation probs with Altera LPM_FIFO+
    74766: 04/10/18: Re: Modelsim simulation problem
Jeremy Whatley:
    37297: 01/12/06: Xilinx CPLD pin mapping with Foundation F3.1i
    44980: 02/07/08: ISE 4.2i : Clock Buffer Disable
    52855: 03/02/24: Delay element in Virtex2
    59306: 03/08/14: Virtex II Output Impedance
Jeremy Wood:
    92171: 05/11/23: Design Implementation in Xilinx XST
    92183: 05/11/23: Re: Design Implementation in Xilinx XST
    106448: 06/08/13: Xilinx Webpack inferring BRAMS, RedHat version
<jeremy.webb@ieee.org>:
    76559: 04/12/06: Re: JTAG recognise xcv50e instead of xc2s50e
    79101: 05/02/14: Re: Using the 7 segment displays on Xilinx Spartan 3 kit
    79130: 05/02/14: Re: Using the 7 segment displays on Xilinx Spartan 3 kit
jeremywwebb@gmail.com:
    137095: 08/12/22: Re: Adding userports to a custom peripheral in XPS
Jerker Hammarberg (DST):
    63757: 03/12/03: Spartan IIE daisy chain problems
    71075: 04/07/07: FSM in illegal state
    71081: 04/07/07: Re: FSM in illegal state
    71082: 04/07/07: Re: FSM in illegal state
    71090: 04/07/07: Re: FSM in illegal state
    71094: 04/07/07: Re: FSM in illegal state
    71098: 04/07/08: Re: FSM in illegal state
    71108: 04/07/08: Re: FSM in illegal state
    71121: 04/07/08: Re: FSM in illegal state
    71123: 04/07/08: Re: FSM in illegal state
    71125: 04/07/08: Re: FSM in illegal state
    71126: 04/07/08: Re: FSM in illegal state
    71269: 04/07/13: Re: FSM in illegal state (conclusion)
    72350: 04/08/16: Usercode in bit/mcs file
    72355: 04/08/16: Re: How to ? 2.1i to ISE6.2 SCHEMATIC converter!!
    72369: 04/08/17: Re: Usercode in bit/mcs file
Jeroen:
    6285: 97/05/08: Neede: Resellers for Adv. Comp. Products.(only serious replies).
    62920: 03/11/11: Code for accessing CF cards on Cyclone dev.board
    65088: 04/01/20: Re: Help on qu@rtus memory initialization file
    66171: 04/02/13: makefile to generate memory contents in Altera SOPC Builder
    69544: 04/05/13: EPCS4 Configuration+firmware, Quartus problem
    69545: 04/05/13: Re: Anyone who has worked with Altera Cyclone???
    69739: 04/05/19: Re: Nios II Going Live...
    69741: 04/05/19: Re: Inversion of signals on synthesis
    69932: 04/05/25: Re: HOWTO calculate the binary size of a .hexout/.flash/.germs file
    69933: 04/05/25: Re: USB HUB?
    70727: 04/06/25: Re: Why does Quartus take 4 hours for a pin I/O change?
    71234: 04/07/12: Re: Programable Logic & Video stuff
    72306: 04/08/14: Re: NIOS II - Instantiating array on SDRAM
    73039: 04/09/11: Re: Need some help with some technical claims...
    73300: 04/09/18: Re: Problem with I/O state while power on
    73434: 04/09/21: Re: From whence the MAC on an Altera NIOS devel kit board?
    73459: 04/09/22: Re: edge reset
    73535: 04/09/23: Re: using both edges of clocks in a design - effects on synthesis
    73960: 04/10/01: Re: Removing set/reset logic for shift register (HDL ADVISOR )
    73240: 04/09/16: Re: Twister + Lancelot
    76129: 04/11/25: Re: MIL-Qualified RTOS for uBlaze or NiosII
    76731: 04/12/10: Re: Getting Started With Simple Sound Synthesis
    76743: 04/12/10: Re: Getting Started With Simple Sound Synthesis
    76827: 04/12/13: Re: Cyclone device misteriously overheats
    76829: 04/12/14: Re: Cyclone device misteriously overheats
    76843: 04/12/14: Re: Cyclone device misteriously overheats
    76865: 04/12/15: Re: Cyclone device misteriously overheats
    76957: 04/12/17: Re: JTAG vs. Passive Serial Config speed
    77155: 04/12/26: Re: PS: Synchronous design and power consumption
    77548: 05/01/10: Re: Configuration devices
    78277: 05/01/28: Re: EPCS binary files...
Jeroen Belleman:
    148191: 10/06/25: Re: fooling the compiler
    149628: 10/11/12: Re: cool BGA pattern
Jeroen Fokker:
    11412: 98/08/11: Re: Combinatoric Divide-by-3 Algorithm
Jeroen Tenbult:
    106924: 06/08/22: Re: ISE 8.1: Process "Map" failed
Jeroen Van den Keybus:
    38805: 02/01/25: Pin assignment on ACEX1K
    38978: 02/01/29: Re: Pin assignment on ACEX1K
<jeroen.claes@gemidis.be>:
    127783: 08/01/08: Bad micro blaze behaviour during power off
    127837: 08/01/09: Re: Bad micro blaze behaviour during power off
    127864: 08/01/09: Re: Bad micro blaze behaviour during power off
Jerome:
    70563: 04/06/21: Re: VDHL implementation of RAM with serial input and parallel outpout ? thx
    74526: 04/10/13: Re: simprim errors
    88387: 05/08/17: Re: image sensor
    91095: 05/10/29: Re: xilinx design reuse netlist format
    93221: 05/12/16: Re: FPGA-pci communication
    93266: 05/12/17: Re: FPGA-pci communication
    94436: 06/01/11: Re: Samples
    94462: 06/01/12: Re: Samples
    94895: 06/01/19: Re: clock generation with DOPPLER shift
    96583: 06/02/07: cheap USB analyzer based on FPGA
    96639: 06/02/08: Re: cheap USB analyzer based on FPGA
    96733: 06/02/09: Re: cheap USB analyzer based on FPGA
    96840: 06/02/11: Re: cheap USB analyzer based on FPGA
    96944: 06/02/14: Re: cheap USB analyzer based on FPGA
    96947: 06/02/14: Re: cheap USB analyzer based on FPGA
    98534: 06/03/12: Re: LEON processor core
    98541: 06/03/12: Re: LEON processor core
    101075: 06/04/25: Virtex 2 Config Times
    103722: 06/06/09: PCI Express - Root Complex ?
    114074: 07/01/04: Re: DC timing violation, what to do first?
    114230: 07/01/08: Re: Use Multi-cycle Path or Pipeline?
jerome:
    67639: 04/03/16: FPGA protyping board (Avnet or others)
    67674: 04/03/17: Re: FPGA protyping board (Avnet or others)
    75181: 04/10/28: information about Nuhorizon Spartan-3 Development Board ?
Jerre:
    34968: 01/09/17: xilinx prom readback with jtag
    35960: 01/10/25: How to make an implementable big counter?
    43497: 02/05/22: stability/timing problem on reset
    43879: 02/06/05: Resetting problem on my Xi 4000 due to very slow reset
    44060: 02/06/11: How to implement synchronous reset on an FPGA
    44335: 02/06/18: How to deal with a slowly rising reset signal?
jerry:
    48606: 02/10/21: Re: Buy Small quantities
Jerry:
    27901: 00/12/14: Spartan configuration : Why Done returns to Low?
    27902: 00/12/14: Re: Spartan configuration : Why Done returns to Low?
    27923: 00/12/14: Re: Spartan configuration : Why Done returns to Low?
    27971: 00/12/18: Re: Spartan configuration : Why Done returns to Low?
    33454: 01/07/26: Re: Scope of libraries in leonardo spectrum
    33849: 01/08/06: Re: Which is the best Design Toolchain?
    36619: 01/11/13: Re: Incrementing counter from state-machine
    45647: 02/07/30: VirtexE : OrCAD capture part symbol
    49445: 02/11/12: Re: HDL vs RTL
    49542: 02/11/14: Re: why systemc?
    49756: 02/11/20: Convert AHDL design to schematics(RTL)
    51673: 03/01/18: Multi Project DIE
    51745: 03/01/20: Re: Multi Project DIE
    52285: 03/02/05: Redhat versions
    52953: 03/02/26: linux vs windows
    52998: 03/02/27: Re: linux vs windows
    53157: 03/03/04: Re: Issues in Outsourcing?
    53571: 03/03/16: Re: FPGA dev boards
    54002: 03/03/30: Re: $4000 FPGAs
    54039: 03/03/31: What would it take?
    54046: 03/03/31: Re: What would it take?
    54072: 03/04/01: Re: What would it take?
    55953: 03/05/24: Re: FPGA Board
    55954: 03/05/24: Re: FPGA Board
    56928: 03/06/18: Re: FPGA to Custom ASIC ??
    57347: 03/06/27: Re: ASIC divider in FPGA?
    57830: 03/07/07: eCOS port for NIOS
    58965: 03/08/05: Re: Patent granted for "system on a chip" framework?
    60176: 03/09/06: Stratix pricing
    60967: 03/09/25: NIOS and OCI
    61092: 03/09/27: Re: NIOS and OCI
    61180: 03/09/29: Re: NIOS and OCI
    61252: 03/09/30: Re: Frustrations with Marketing
    61399: 03/10/02: Re: Quartus II tutorial vs the real world
    62244: 03/10/22: Re: The Luddite Needs Reference Books...
    62642: 03/11/03: Re: Altera "my support" :-(
    63131: 03/11/15: standalone IMPACT
    64399: 04/01/01: Re: SOS : 4-bit binary divider circuit PLEASE!!!!!!!
    64441: 04/01/04: Re: is this a good idea
    70268: 04/06/10: Re: SOPC BUILDER - SOFTWARE GENERATION
    71560: 04/07/21: Altera Cyclone Web presentation
    72144: 04/08/09: Re: Now I am really confused!
    72145: 04/08/09: Altera winner?
    72186: 04/08/10: Re: Altera winner?
    72279: 04/08/12: Re: Altera winner?
    72473: 04/08/19: NIOS II Sim
    72500: 04/08/20: Re: NIOS II Sim
    72901: 04/09/07: Altera DDR SDRAM & external DSP
    72904: 04/09/07: Re: I NEED HELP / MENTOR
    73372: 04/09/20: Re: Virtex 4 integrated A/Ds? Yes it does.
    76745: 04/12/09: XPS errors
    76833: 04/12/13: ISE/XPS ERRORS
    82543: 05/04/13: Altera DSP dev board stratix II
    82614: 05/04/14: Re: Altera DSP dev board stratix II
    88614: 05/08/23: 802.11 IP
    88615: 05/08/23: Re: Verilog examples???
    90553: 05/10/16: LSI RAPIDCHIP
    90689: 05/10/18: Re: LSI RapidChip
    90690: 05/10/18: Re: LSI RAPIDCHIP
    97863: 06/02/28: DDR2 FPGA PWB SIMULATION
    104184: 06/06/20: Re: altera cyclone memory example
Jerry Avins:
    9188: 98/02/28: Re: Dsp Fpga and vhdl project
    10761: 98/06/16: Re: Do You need any components
    12002: 98/09/23: Re: easier testing for PCI cards??
    20148: 00/01/28: Re: ADC to DSP... FIFO?
    20415: 00/02/09: Re: ADC to DSP... FIFO?
    20772: 00/02/21: Re: Distributed Arithmetic De-mystified
    20812: 00/02/23: Re: Bit Serial Arithmetic De-mystified
    20813: 00/02/23: Re: Bit Serial Arithmetic De-mystified
    20826: 00/02/23: Re: Bit Serial Arithmetic De-mystified
    20835: 00/02/23: Re: Bit Serial Arithmetic De-mystified
    20837: 00/02/23: Re: Bit Serial Arithmetic De-mystified
    20870: 00/02/24: Re: Bit Serial Arithmetic De-mystified
    22393: 00/05/08: Re: ANNOUNCE: Embedded Systems Glossary and Bibliography
    22405: 00/05/08: Re: ANNOUNCE: Embedded Systems Glossary and Bibliography
    22421: 00/05/08: Re: ANNOUNCE: Embedded Systems Glossary and Bibliography
    22458: 00/05/09: Re:OT ANNOUNCE: Embedded Systems Glossary and Bibliography
    22555: 00/05/11: Re: OT ANNOUNCE: Embedded Systems Glossary and Bibliography
    22594: 00/05/12: Re: OT ANNOUNCE: Embedded Systems Glossary and Bibliography
    25134: 00/08/27: Re: Non-disclosures in job interviews, Round Two
    25141: 00/08/27: Re: Non-disclosures in job interviews, Round Two
    27019: 00/11/07: Re: ANNOUNCE: New article about Network Processors
    30015: 01/03/20: Re: TOA measurement
    30044: 01/03/21: Re: TOA measurement
    30074: 01/03/22: Re: TOA measurement
    38347: 02/01/11: Re: speech recognition - active noise cancellation
    38367: 02/01/12: Re: speech recognition - active noise cancellation
    39189: 02/02/03: Re: solutions manuals, and no they are not for school
    39285: 02/02/05: Re: solutions manuals, and no they are not for school
    39380: 02/02/07: Re: solutions manuals, and no they are not for school
    39417: 02/02/08: Re: solutions manuals, and no they are not for school
    39437: 02/02/09: Re: solutions manuals, and no they are not for school
    43281: 02/05/17: Re: SDRAM pricing
    45438: 02/07/23: Re: xilinx v ti
    48446: 02/10/17: Re: Proveedor de Soluciones uC/FPGA/DSP - uC/FPGA/DSP Solutions Provider
    56049: 03/05/27: Re: JTAG madness
    56051: 03/05/27: Re: JTAG madness
    56082: 03/05/28: Re: JTAG madness
    56086: 03/05/28: Re: JTAG madness
    56114: 03/05/28: Re: JTAG madness
    58366: 03/07/21: Re: Phase / frequency detector types
    62551: 03/10/31: OT Shannon Entropy for Black Holes
    62635: 03/11/03: Re: Shannon Entropy for Black Holes
    62790: 03/11/07: Re: Shannon Entropy for Black Holes
    65900: 04/02/09: Re: iteration Vs LUT table entry vs accuracy in Cordic
    65949: 04/02/10: Re: iteration Vs LUT table entry vs accuracy in Cordic
    66437: 04/02/19: Re: Dual-stack (Forth) processors
    66438: 04/02/19: Re: Dual-stack (Forth) processors
    66444: 04/02/19: Re: Dual-stack (Forth) processors
    66452: 04/02/19: Re: Dual-stack (Forth) processors
    66455: 04/02/19: Re: Dual-stack (Forth) processors
    66459: 04/02/19: Re: Dual-stack (Forth) processors
    66461: 04/02/19: Re: Dual-stack (Forth) processors
    67972: 04/03/23: Re: Bus width between registers in IIR
    68024: 04/03/24: Re: Bus width between registers in IIR
    68822: 04/04/19: Re: Image-reject IF downmixing
    83074: 05/04/22: Re: What is the cause of a "can not see clock" problem in logic analyser?
    83075: 05/04/22: Re: What is the cause of a "can not see clock" problem in logic analyser?
    86365: 05/06/26: Re: Idea exploration 1.1 - Inertia based angular sensor.
    87356: 05/07/22: Re: Best Practices to Manage Complexity in Hardward/Software Design?
    87395: 05/07/22: Re: Best Practices to Manage Complexity in Hardward/Software Design?
    87410: 05/07/22: Re: Best Practices to Manage Complexity in Hardward/Software Design?
    87427: 05/07/23: Re: Best Practices to Manage Complexity in Hardward/Software Design?
    87429: 05/07/23: Re: Best Practices to Manage Complexity in Hardward/Software Design?
    87448: 05/07/24: Re: Best Practices to Manage Complexity in Hardward/Software Design?
    87449: 05/07/24: Re: Best Practices to Manage Complexity in Hardward/Software Design?
    87450: 05/07/24: Re: Best Practices to Manage Complexity in Hardward/Software Design?
    87454: 05/07/24: Re: Best Practices to Manage Complexity in Hardward/Software Design?
    87455: 05/07/24: Re: Best Practices to Manage Complexity in Hardward/Software Design?
    87460: 05/07/24: Re: Best Practices to Manage Complexity in Hardward/Software Design?
    87461: 05/07/24: Re: Best Practices to Manage Complexity in Hardward/Software Design?
    87473: 05/07/24: Re: Best Practices to Manage Complexity in Hardward/Software Design?
    87474: 05/07/24: Re: Best Practices to Manage Complexity in Hardward/Software Design?
    87475: 05/07/24: Re: Best Practices to Manage Complexity in Hardward/Software Design?
    87499: 05/07/25: Re: Best Practices to Manage Complexity in Hardward/Software Design?
    87503: 05/07/25: Re: Best Practices to Manage Complexity in Hardward/Software Design?
    87548: 05/07/25: Re: Best Practices to Manage Complexity in Hardward/Software Design?
    87563: 05/07/26: Re: Best Practices to Manage Complexity in Hardward/Software Design?
    87564: 05/07/26: Re: Best Practices to Manage Complexity in Hardward/Software Design?
    87758: 05/07/31: Re: Best Practices to Manage Complexity in Hardward/Software Design?
    87787: 05/08/01: Re: Best Practices to Manage Complexity in Hardward/Software Design?
    88030: 05/08/06: Re: System Engineering in the R/D World
    88034: 05/08/07: Re: System Engineering in the R/D World
    88040: 05/08/07: Re: System Engineering in the R/D World
    88049: 05/08/07: Re: Good intro books on OFDM?
    92353: 05/11/28: Re: AD9218, what will the negative values be in binary mode?
    92375: 05/11/28: Re: Why does two channels of ADC give different outputs?
    92400: 05/11/29: Re: Why does two channels of ADC give different outputs?
    92588: 05/12/01: Re: Quick question, how do I supply +-5V?
    92590: 05/12/01: Re: Quick question, how do I supply +-5V?
    92626: 05/12/02: Re: Quick question, how do I supply +-5V?
    92630: 05/12/02: Re: Quick question, how do I supply +-5V?
    92646: 05/12/02: Re: Quick question, how do I supply +-5V?
    92735: 05/12/05: Re: Quick question, how do I supply +-5V?
    93080: 05/12/13: Re: How can I surpress noise in an ADC board?
    95333: 06/01/22: Re: How in Design Compiler disable writing out "Assign" statement
    102725: 06/05/19: Re: Output gain adjuster of digital filters
    102741: 06/05/19: Re: Output gain adjuster of digital filters
    107731: 06/08/31: Re: Performance Appraisals
    107749: 06/08/31: Re: Performance Appraisals
    107891: 06/09/01: Re: Performance Appraisals
    107898: 06/09/01: Re: Performance Appraisals
    107933: 06/09/02: Re: Performance Appraisals
    108138: 06/09/05: Re: Forth-CPU design
    108315: 06/09/07: Re: Performance Appraisals
    108436: 06/09/11: Re: Performance Appraisals
    109245: 06/09/22: Re: Dell Laptop for Embedded Work
    109319: 06/09/23: Re: IBM Thinkpads, used
    113427: 06/12/13: Re: IQ multiplier
    113504: 06/12/14: Re: IQ multiplier
    113527: 06/12/15: Re: IQ multiplier
    116797: 07/03/18: Re: how to transform Arun's LDPC code to max-product (Min-sum)?
    132796: 08/06/06: Re: ANNOUNCE:-- TimingAnalyzer Free Version -- Draw timing diagrams
    133933: 08/07/19: Re: ANNOUNCE: TimingAnalyzer version beta 0.87
    133937: 08/07/20: Re: ANNOUNCE: TimingAnalyzer version beta 0.87
    133958: 08/07/20: Re: ANNOUNCE: TimingAnalyzer version beta 0.87
    133960: 08/07/20: Re: ANNOUNCE: TimingAnalyzer version beta 0.87
    133961: 08/07/20: Re: ANNOUNCE: TimingAnalyzer version beta 0.87
    133970: 08/07/20: Re: ANNOUNCE: TimingAnalyzer version beta 0.87
    133971: 08/07/20: Re: ANNOUNCE: TimingAnalyzer version beta 0.87
    141502: 09/06/25: Re: 720 Mhz IF Processing
    141756: 09/07/06: Re: How to interpret polyphase coefficients generated in MATLAB
    141758: 09/07/06: Re: How to interpret polyphase coefficients generated in MATLAB
Jerry Coffin:
    93481: 05/12/22: Re: real-time compression algorithms on fpga
    93488: 05/12/22: Re: real-time compression algorithms on fpga
    93491: 05/12/22: Re: real-time compression algorithms on fpga
    93525: 05/12/23: Re: real-time compression algorithms on fpga
    95624: 06/01/24: Re: Xilinx padding LC numbers, how do you really feel about it?
    95871: 06/01/26: Re: open source fpga programmer programs
    95897: 06/01/26: Re: open source fpga programmer programs
    96028: 06/01/28: Re: open source fpga programmer programs
    96221: 06/01/31: Re: Impact 8.1 problems=> uClinux rules on MicroBlaze !!!
    96367: 06/02/02: Re: Die Area
    96859: 06/02/11: Re: which one among the available FPGAs is best for a fresher?
    97254: 06/02/19: Re: FPGA - software or hardware?
    97709: 06/02/26: Re: VGA specification
    97733: 06/02/26: Re: VGA specification
    97794: 06/02/27: Re: ironic Xcell journal 1Q2006 cover art, S3E Starter Kit
    97795: 06/02/27: Re: ironic Xcell journal 1Q2006 cover art, S3E Starter Kit
    97838: 06/02/28: Re: ironic Xcell journal 1Q2006 cover art, S3E Starter Kit
    97858: 06/02/28: Re: ironic Xcell journal 1Q2006 cover art, S3E Starter Kit
    98005: 06/03/02: Re: FPGA - software or hardware -2-
    98008: 06/03/02: Re: FPGA - software or hardware -2-
    98159: 06/03/06: Re: Which CPU and Screen Rez for ISE 6.3i ?
    98344: 06/03/08: Re: for all those who believe in ASICs....
    98407: 06/03/09: Re: delay in altera cyclone about led
    101910: 06/05/08: Re: PCI Express and DMA
    101960: 06/05/08: Re: Xilinx 3s8000?
    116444: 07/03/08: Re: Introducing picosecond delay between two output signals
Jerry D. Harthcock:
    46543: 02/09/02: Re: Actel Proto Boards
    46545: 02/09/02: Re: MicroBlaze processor core
    46567: 02/09/03: Re: Actel Proto Boards
    46616: 02/09/04: Re: Any resource about MCU and DSP
    46620: 02/09/04: Re: Actel Proto Boards
    46687: 02/09/05: Re: Actel Libero
    46748: 02/09/06: Re: Actel Proto Boards
    46794: 02/09/09: Re: minimalist FPGA system
    48881: 02/10/25: Re: Please recommend a FPGA chip!
    63002: 03/11/12: Re: Home grown CPU core legal?
jerry english:
    11966: 98/09/21: Re: Verilog newsgroup
    12986: 98/11/09: Re: FPGA on ASIC (Was: Re: New free FPGA CPU)
    12952: 98/11/06: FPGA HDL tool benchmarks
    13403: 98/12/01: HELP, Tool selection
    13696: 98/12/18: GSR
    13703: 98/12/18: Re: GSR
    14287: 99/01/23: Re: small correction
    14507: 99/02/02: Re: Espresso logic tool
    14686: 99/02/11: Re: Current of I/O driver
    15005: 99/03/02: Re: Fast-turn ASIC vendors
    15470: 99/03/25: Re: FPGA Express Synthesis Problem
Jerry English:
    4656: 96/11/26: Re: How to use Xilinx ?
    8544: 98/01/07: Re: serial conf. PROMS
    10637: 98/06/08: Re: FPGA Conversion
    10638: 98/06/08: Re: FPGA Conversion
    10753: 98/06/16: Re: Wallace trees
    19927: 00/01/18: Re: Viterbi decoder in FPGA
    20073: 00/01/26: Re: Anyone changed an NT disk serial number?
    20974: 00/03/01: Re: Xilinx Tools Vs Altera tools
    21021: 00/03/03: Re:
    21183: 00/03/09: Re: Microprocessor architecture (6800, 4004? PA-RISC, PPC, MIPS, x86,
    22151: 00/04/27: AHDL to Verilog
    23455: 00/06/26: Re: How to speed it up?
    23990: 00/07/19: synthesizer memory useage
    24094: 00/07/26: Re: Variable shifting
    24126: 00/07/27: Re: End of my rope.
    24752: 00/08/17: Re: Board suggestion for high gate count FPGA board
    25163: 00/08/29: Re: largest fpga in the industry
    25469: 00/09/12: Anybody receiving Spartan II?
    26081: 00/10/03: Re: "Xilinx Adds FPGA Support to Free Web Design Tools"
    26111: 00/10/04: Re: Xilinx Licensing.
    26204: 00/10/08: Foundation iSE and Coregen limited devices
    26564: 00/10/20: Re: Virtex E development boards
    26877: 00/11/02: Re: Excellent Opportunity ASIC Engineers CA International Relocation
    26897: 00/11/02: Re: OT: Xilinx T-Shirt
    28404: 01/01/11: Xilinx's XST hanging
    28785: 01/01/24: Re: Xilinx's XST hanging
    29083: 01/02/05: Re: who wants to work in France ????
    29542: 01/02/26: Re: Spartan II power
    29603: 01/02/28: Re: Virtex ambit support
    29850: 01/03/13: bonding information
Jerry Francis:
    44025: 02/06/10: Virtex 2 Pro Board
    44087: 02/06/11: Visual SourceSafe and VHDL files
Jerry Greer:
    853: 95/03/13: Re: Questions of implementing asynchronous circu
Jerry Hicks:
    7758: 97/10/11: Re: FPGA News Resource Page
    7759: 97/10/11: Looking for CUPL, PALASM, etc. source
    7763: 97/10/12: Re: design sites
    7866: 97/10/25: Re: Anyone know of an I2C Controller design for an FPGA?
Jerry McGoveran:
    3803: 96/08/05: Re: Job posting
Jerry O'Keefe:
    9237: 98/03/03: Re: Survey - Proto Board for Xilinx FPGA
Jerry Pongstaporn:
    27760: 00/12/06: dual port ram for altera
Jerry Schroefter:
    28217: 01/01/01: Re: Virtex ROM ques.
Jerry Zdenek:
    11044: 98/07/14: Re: Dataio Chipwriter won't burn Altera EPC1 generated with Maxplus2 8.2 or greater???
    17196: 99/07/08: Re: Altera 10K I/O's
    17323: 99/07/21: Re: Solaris vs. NT
jerry1111:
    39923: 02/02/22: Re: Beginner Altera Questions
    40079: 02/02/26: Re: Beginner Altera Questions
    40184: 02/03/01: Re: Beginner Altera Questions
    40197: 02/03/01: Altera Excalibur
    40219: 02/03/02: Re: Altera Excalibur
    40221: 02/03/02: Re: Altera Excalibur
    40241: 02/03/03: Re: Altera Excalibur
    41626: 02/04/03: Re: powerpc in virtex2pro
    42861: 02/05/05: Re: Xilinx MicroBlaze, Opinion?
    42966: 02/05/08: Re: Xilinx MicroBlaze, Opinion?
    43791: 02/06/03: Re: fpga cpu
    43840: 02/06/04: Re: fpga cpu
    43841: 02/06/04: Re: fpga cpu
    43843: 02/06/04: Re: NIOS GNUPro tool chain + SDK for Linux
    43851: 02/06/04: Re: fpga cpu
    44585: 02/06/24: Re: Help!I can't use the programmer of Max-plus II on windows XP.
    49337: 02/11/09: Re: Compiling Altera Nios Designs
    49450: 02/11/12: Re: FPGA Size?
    54084: 03/04/02: Matrix multiply in FPGA
    54095: 03/04/02: Re: Matrix multiply in FPGA
    54181: 03/04/04: Re: Matrix multiply in FPGA
    54237: 03/04/05: Re: Matrix multiply in FPGA
    55341: 03/05/04: Re: 2.5V switching regulator for Spartan 2
    56281: 03/06/02: Re: NIOS-GERMS
    62563: 03/11/01: Nios & external RAM
    62566: 03/11/01: Re: Nios & external RAM
    64189: 03/12/19: Re: Spartan3 availability
    64215: 03/12/20: Re: Spartan3 availability
    64228: 03/12/21: Re: Spartan3 availability
    68819: 04/04/20: Re: NIOS: Run program from SDRAM
    68934: 04/04/22: Re: NIOS: Run program from SDRAM
<jerryjsy@hotmail.com>:
    89710: 05/09/23: Need help in Flash simulation module.
<jerryzy@gmail.com>:
    90627: 05/10/17: Newbie question: XC3S400 Gate Count
    90679: 05/10/18: Re: Newbie question: XC3S400 Gate Count
Jerzy:
    46675: 02/09/05: OFDM - looking for something more
    47199: 02/09/20: Re: Overheat with XCV-600E
    48721: 02/10/23: ngdbuild - command line in xilinx' ISE tools
    48775: 02/10/24: Re: ngdbuild - command line in xilinx' ISE tools
    49803: 02/11/21: Re: Xilinx programming and PCI printer port
    54089: 03/04/02: FFT 256pt on Spartan
    54140: 03/04/03: Re: Xilinx Divider Core
    54549: 03/04/14: Simulate Post-PAR VHDL Model - Error
    57944: 03/07/10: viterbi - SMU - trace back calculation
    69343: 04/05/07: Virtex2 (500) DCM Frequency Synthesize
    69368: 04/05/08: Re: Virtex2 (500) DCM Frequency Synthesize
Jerzy Gbur:
    43076: 02/05/13: Re: Duplicating IOB FFs Without I/O Pads Being Inserted in XST
    43245: 02/05/17: Re: Timing constraints on internal signals
    43410: 02/05/21: Off topic - a little
    44577: 02/06/24: CIC filter
    60409: 03/09/12: Re: DCM not locking in XC2V4000
    60491: 03/09/15: Re: DCM not locking in XC2V4000
    71397: 04/07/17: Re: Xilinx Virtex-II Configuration in Slave Serial
    83001: 05/04/21: Re: LVDS pin assignment
    83094: 05/04/23: Re: Xilinx multiplier out of slices
    86922: 05/07/09: Re: Rocket IO failure after power cycle.
    87481: 05/07/25: Re: DCM.
    93211: 05/12/16: Re: Parallel Cable III is not detected
    94102: 06/01/05: Re: Virtex2 I/O state in configure phase
    94501: 06/01/12: Re: Virtex2 I/O state in configure phase
    94492: 06/01/12: Re: Virtex2 I/O state in configure phase
    97451: 06/02/22: FPGA to ASIC migrate
    97642: 06/02/25: Re: FPGA to ASIC migrate
    113962: 06/12/31: Re: Memory controller design
jerzy.gbur@gmail.com:
    86636: 05/07/01: Re: interpolation in FPGA
    90700: 05/10/19: Re: which is Low power FPGA?
    90745: 05/10/20: Re: which is Low power FPGA?
    92824: 05/12/07: Re: A stupid question about constraints
    93852: 06/01/02: Re: basic DSP with FPGA
    93853: 06/01/02: Re: Start up condition of flip flops in FPGA?
    93976: 06/01/04: Re: DCM and buffers
    95688: 06/01/25: Re: Remapping from Virtex-II to Virtex-4
    94086: 06/01/05: Virtex2 I/O state in configure phase
    95964: 06/01/27: Re: SDRAM Controller
    98765: 06/03/16: Re: ADC Interleaving
    109683: 06/10/03: Re: Virtex 4 Configuration Pins
    114029: 07/01/03: Re: Memory controller design
    117563: 07/04/04: Re: Conceptos about VCCINT,VCCAUX,etc
    120017: 07/05/31: Re: Virtex4 Configuration Problem
    124384: 07/09/20: Re: Virtex-4 SELECT MAP configuration
    124755: 07/10/03: Tcl - Xilinx - ISE - WindowsXP
    124776: 07/10/04: Re: Tcl - Xilinx - ISE - WindowsXP
    124813: 07/10/05: Re: Tcl - Xilinx - ISE - WindowsXP
    126458: 07/11/23: Re: xilinx spartan 3 + 16 adc
    133847: 08/07/17: Re: What's wrong with this Virtex4 DCM?
    135097: 08/09/16: Re: Ultra low power FPGAs
    135288: 08/09/24: Re: OFDM band switch ...
    135322: 08/09/26: Re: OFDM band switch ...
    135368: 08/09/29: Re: OFDM band switch ...
    136053: 08/10/29: Re: Possibility of Driving FPGA clock from an other FPGA ?
    143626: 09/10/19: Re: Handwritten recognition using FPGA
    147736: 10/05/20: Availability of XC6SLX16-2CPG196C
jerzy.zielinski:
    107639: 06/08/30: xgpio_DiscreteRead
    107857: 06/09/01: Read from Microblaze
    109149: 06/09/21: Interrupts in Microblaze
    109256: 06/09/22: Re: Interrupts in Microblaze
    113539: 06/12/15: uClinux bootloader on Spartan-3e Starter Kit
Jesper Kristensen:
    45636: 02/07/30: How to generate correct Express Mode configuration bit stream for Spartan-XL...?
    68173: 04/03/28: C++ Runtime Error when using RTL View in ISE6.2i WebPack...
    152526: 11/09/03: Virtex-6 XC6VHX380T Master SPI Configuration Problems....
    152533: 11/09/06: Re: Virtex-6 XC6VHX380T Master SPI Configuration Problems....
<Jesper.Kristensen@tellabs.com>:
    105209: 06/07/17: Reuse a Speed Grade -8 Stratix image in Speed Grade -6 ...?
    113149: 06/12/06: Quartus II: Back-annotating bidir's gives two entries per pin...
    121469: 07/07/05: Spartan-3A: 200A & 400A Image problems / variance...
Jespr:
    132225: 08/05/18: Problem with Scheduler in Xilkernel.
    132268: 08/05/19: Re: Problem with Scheduler in Xilkernel.
    132302: 08/05/20: Re: Problem with Scheduler in Xilkernel.
Jess:
    19717: 00/01/09: Make thousands$$$$ form only $6!!!!!!!!!!!!!!!!!
jesse:
    31687: 01/06/02: QuickLogic programming HW for sale
    36384: 01/11/07: QuickLogic Programmer (s) for Sale
Jesse Bouwman:
    9107: 98/02/21: Re: Free FPGA tools???
jesse jenkins:
    57805: 03/07/07: Re: XPLA3 vs. MAX3000A
Jesse Kempa:
    40119: 02/02/27: Re: microblaze
    40192: 02/03/01: Re: microblaze
    42092: 02/04/15: Re: problems with Nios 2.0
    43814: 02/06/03: Re: ALtera SOPC Builder
    44320: 02/06/17: Re: MicroBlaze uClinux port?
    46467: 02/08/30: Re: Crashes while reading from memory with Nios
    47670: 02/10/01: Re: Nios interrupt latency?
    47757: 02/10/03: Re: TCP/IP in FPGA
    49197: 02/11/04: Re: 2-nios design using SOPC builder
    53099: 03/03/03: Re: Nios - > 8 bit Ram
    53636: 03/03/18: Re: LogicLock and SOPC Builder
    54437: 03/04/10: Re: Cheap(er) FPGA configuration?
    54809: 03/04/18: Re: Avalon Bus Master
    54947: 03/04/22: Re: NIOS 3.0 Spurious Interrupts
    54981: 03/04/23: Re: NIOS 3.0 Spurious Interrupts
    55923: 03/05/23: Re: Using GERMS monitor with NIOS CPU on non-Altera board
    56156: 03/05/29: Re: Any recommendation for an FPGA kit ?
    56298: 03/06/02: Re: NIOS-GERMS
    57511: 03/07/01: Re: Can Altera NIOS processor be syntheized on a Flex FPGA
    58540: 03/07/25: Re: Altera Nios 3: Using Interface To User Logic Problem
    58671: 03/07/30: Re: SRAM question in Cyclone Dev. Board
    58924: 03/08/04: Re: Tiny TCP/IP stack and tiny MAC controller on FPGA for direct download to S(D)RAM memory
    58945: 03/08/04: Re: Nios Ethernet Development Kit Problems
    59237: 03/08/12: Re: Nios Clock Frequency
    59348: 03/08/15: Re: Memory map in Altera NIOS
    60272: 03/09/09: Re: Suitable FPGA architecture for Robots..
    60274: 03/09/09: Re: system simulation and verification methods (NIOS)
    60611: 03/09/17: Re: fpga +cpu + wireless
    60620: 03/09/17: Re: Nios Quartus II Question...
    60647: 03/09/18: Re: mouse to Nios Development kit
    60691: 03/09/19: Re: mouse to Nios Development kit
    60786: 03/09/22: Re: Italy is out of FPGA world?
    61175: 03/09/29: Re: NIOS and OCI
    61429: 03/10/03: Re: Quartus II tutorial vs the real world
    61433: 03/10/03: Re: Xilinx courses
    61534: 03/10/06: Re: MicroBlaze size
    61536: 03/10/06: Re: large integer support in GNUPro for Altera Nios software development
    61947: 03/10/15: Re: mp3 project
    61966: 03/10/15: Re: Debugging software in an ACEX device with Nios 32 via JTAG
    62064: 03/10/17: Re: Xilinx Slice and Altera ...?
    62139: 03/10/20: Re: Debugging software in an ACEX device with Nios 32 via JTAG
    63006: 03/11/12: Re: Code for accessing CF cards on Cyclone dev.board
    63907: 03/12/08: Re: NIOS: Running code from flash
    63938: 03/12/09: Re: NIOS: Running code from flash
    64171: 03/12/18: Re: interfacing a WishBone IP core to a CoreConnect bus
    64474: 04/01/05: Re: Floating point in Nios SDK
    64481: 04/01/05: Re: dynamic memory allocation NIOS
    64899: 04/01/15: Re: yo, Mr. FPGA Engineer
    65741: 04/02/05: Re: Stratix II NIOS sizes ?
    65744: 04/02/05: Re: Differences between Xilinx ISE and Altera Quartus software
    65885: 04/02/09: Re: Is nobody using c++ and/or plugs-lib? was Re: nios c++ and ethernet [may by ot?]
    65904: 04/02/09: Re: Stratix II NIOS sizes ?
    66189: 04/02/13: Re: APEX fit problem
    66498: 04/02/20: Re: Dhrystone figures - Was: Microblaze instruction timings
    66826: 04/02/26: Re: Stratix 2 ALUT architecture patented ?
    68073: 04/03/25: Re: Altera NIOS SOPC Builder---- Can I edit a text file
    68402: 04/04/02: Re: Can't do a single byte read in Nios?
    69167: 04/04/28: Re: Error in SoPC Builder
    69285: 04/05/04: Re: Best way to handle multiple common data busses in Altera FPGA (and others)
    69300: 04/05/05: Re: Altera SoPC builder command line system generator
    69624: 04/05/16: Re: best fpga development board?
    69760: 04/05/19: Re: Nios II Going Live...
    69761: 04/05/19: Re: NIOS Board Stratix Edition - FPGA won't configure
    69812: 04/05/20: Re: Never right, always room for improvement
    69818: 04/05/20: Re: program flash memory through JTAG on FPGA
    69841: 04/05/21: Re: Never right, always room for improvement
    69914: 04/05/24: Re: NIOS Board Stratix Edition - FPGA won't configure
    70080: 04/06/01: Re: NIOS 2 memory limitations
    70304: 04/06/11: Re: Interfacing FPGA to on-board SRAM Stratix EP1S40F780C5
    70429: 04/06/16: Re: Using Altera libraries for Nios Dev Board
    70430: 04/06/16: Re: C Header files for User Design Logic in the Nios.
    70432: 04/06/16: Re: Interfacing FPGA to on-board SRAM Stratix EP1S40F780C5
    70865: 04/06/30: Re: Altera SOPC Master Peripheral Design?
    70870: 04/06/30: Re: Altera Nios Ethernet Development Kit: "spurious interrupt number: 0000 001C"
    71238: 04/07/12: Re: Nios - Ethernet Frame Format
    71243: 04/07/12: Re: NIOS 2 HAL, libraries, ...
    71276: 04/07/13: Re: Using gprof with Nios II
    71316: 04/07/14: Re: Altera SOPC SDRAM & CLK Input?
    71355: 04/07/15: Re: Altera SOPC SDRAM & CLK Input?
    72428: 04/08/18: Re: Nios II debugging with gdb
    72429: 04/08/18: Re: Nios II debugging with gdb
    72444: 04/08/18: Re: NIOS II memory devices on tristate bridges
    72466: 04/08/19: Re: NIOS II memory devices on tristate bridges
    72471: 04/08/19: Re: Nios II debugging with gdb
    72492: 04/08/20: Re: NIOS II Sim
    72495: 04/08/20: Re: NIOS II memory devices on tristate bridges
    73665: 04/09/27: Re: NIOS II / Cyclone II - Multiply, Barrel Shift and Divide
    73666: 04/09/27: Re: [ALTERA] NIOS-II + MMU + FPU
    74146: 04/10/04: Re: [NIOS-II SOPC] SDRAM Read Burst Cycle Length ...
    75841: 04/11/16: Re: Hello anyone! Does someone works with CS8900 under NIOSII? It's really works? Please, write works it with HAL? Thx.
    76441: 04/12/02: Re: NIOS II & CS8900?
jesse lackey:
    114772: 07/01/24: Re: Xilinx ISE 8.2
    115024: 07/01/29: Re: Global Clocks in Xilinx ISE
    119716: 07/05/25: Testbenches in C driving ISE simulator?
Jesse Newcomb:
    20536: 00/02/13: QuickLogic FPGA programmers for sale
    20538: 00/02/13: HP 16500B logic analyzer for sale
    21065: 00/03/05: QuickLogic programmers for sale
<jesse@jumboprawn.net>:
    24207: 00/07/29: QuickLogic programmer bits for sale
    26619: 00/10/22: QuickLogic programmer(s) for sale
<jesse@telematrix.com>:
    746: 95/02/22: ITC
<jessen@sgi.com>:
    12164: 98/10/02: Looking for QuickLogic programmer
Jessica Felix:
<jessiek@polbox.com>:
    18714: 99/11/09: Re: Frequency Division in Altera AHDL ?
    18727: 99/11/10: Re: Frequency Division in Altera AHDL ?
Jesus Jimenez:
    56224: 03/05/31: Re: Simulation in Altera Quartus II
    56225: 03/05/31: Is it possible to simulate Nios designs with Quartus?
    56484: 03/06/06: Re: Is it possible to simulate Nios designs with Quartus?
Jesus Molina:
    39828: 02/02/20: PCI/FPGA evaluation board
    39836: 02/02/20: Re: PCI/FPGA evaluation board
Jet Morgan:
    81881: 05/04/03: Re: problem in driving I2C bus through memory-mapped register
jetmarc:
    37955: 01/12/27: Atmel FPSLIC - Problem with concurrent statements
    37976: 01/12/28: Re: Atmel FPSLIC - Problem with concurrent statements
    39622: 02/02/14: Lean serial communication processor
    43111: 02/05/14: Bus arbiter with low latency
    43728: 02/05/31: LFSR with 2^n instead of (2^n)-1
    43755: 02/05/31: Re: LFSR with 2^n instead of (2^n)-1
    43768: 02/06/01: Clock double trigger problem
    43782: 02/06/02: Re: Clock double trigger problem
    43906: 02/06/05: Re: burning a design
    45206: 02/07/15: AT40K / FPSLIC - Place & Route tools (3rd party)?
    45228: 02/07/16: Re: AT40K / FPSLIC - Place & Route tools (3rd party)?
    45392: 02/07/22: Re: AT40K / FPSLIC - Place & Route tools (3rd party)?
    45393: 02/07/22: Delays in Leonardo
    45678: 02/07/31: Re: tone detection...
    45945: 02/08/12: Re: Programming bits reverse engineering
    46336: 02/08/26: Evaluation board recommendation?
    51324: 03/01/10: Re: External RAM...
    51325: 03/01/10: Re: shift register implementation
    51604: 03/01/17: Re: Multiple FPGA-boards integration issues
    51784: 03/01/21: Re: Atmel FPSLIC UART Code
    51786: 03/01/21: Re: FLEXlm
    51837: 03/01/23: Re: FLEXlm
    52322: 03/02/06: Re: low pass FIR filter in FPGA
    52665: 03/02/18: Re: About automatically programming my FPGA
    54870: 03/04/21: Re: Atmel FPSLIC BGA, real?
    56227: 03/05/31: Re: FPGA's an Flash
    56356: 03/06/03: Re: FPGA's an Flash
    56631: 03/06/10: Re: What's in a bitstream?
    57330: 03/06/27: Re: Partial reconfiguration of Vertex-2 devices.
    57600: 03/07/02: Re: Everything need a reset?
    59747: 03/08/27: Can SpartanIIE talk 3.3v and 1.8v at the same time?
    60612: 03/09/17: Re: platform flash as storage?
    60614: 03/09/17: Re: Digilent board
    60787: 03/09/22: Re: FPGA implementation in (V)HDL
    61227: 03/09/30: Timing constraint for BUFG?
    61287: 03/10/01: Re: Timing constraint for BUFG?
    61923: 03/10/15: Re: Electronic Dice ( 3 die ) In VHDL
    61957: 03/10/15: Re: Electronic Dice ( 3 die ) In VHDL
    62830: 03/11/09: Re: Building the 'uber processor'
<jetmarc@hotmail.com>:
    95006: 06/01/20: Security of Xilinx Virtex2 Pro
    100471: 06/04/10: Re: Compiler to FPSLIC
    100530: 06/04/11: Re: Atmel FPSLIC
    105986: 06/08/04: Re: 100m JTAG cable
    111219: 06/10/31: Re: Taking forever to synthesise (XILINX ISE 8.1i)
    111603: 06/11/06: ISE/EDK project on a file server?
    112031: 06/11/15: Share BRAM for data and instruction OCM?
    112556: 06/11/24: Re: Protecting netlist for Xilinx
    112827: 06/11/29: ISE on a cluster?
    113232: 06/12/08: Barrel shifter in Virtex4?
    113626: 06/12/18: FX12 ethernet resource usage
    113874: 06/12/27: Re: OPB master implementation
    114255: 07/01/09: V4FX PPC data cache behaviour?
    114848: 07/01/25: On-chip randomness (V4FX)
    115004: 07/01/29: Re: On-chip randomness (V4FX)
    115397: 07/02/09: Re: Need advice to help improve timing on V4 FX
    115954: 07/02/26: Re: Not power of two BRAM size problem
    116154: 07/03/02: Re: OPB-to-PLB bridge
    116423: 07/03/08: Load V4 bitstream encryption key with XSVF
    116449: 07/03/09: Re: Load V4 bitstream encryption key with XSVF
    116451: 07/03/09: Re: Load V4 bitstream encryption key with XSVF (solved)
    116674: 07/03/15: Re: Programming XCF from MicroBlaze over JTAG???
    116807: 07/03/19: Re: Programming XCF from MicroBlaze over JTAG???
    117111: 07/03/23: Re: FPGA with 5V and PLCC package
    118025: 07/04/16: Re: OPB To Wishbone Bridge
    118129: 07/04/18: Re: OPB To Wishbone Bridge
    118339: 07/04/24: Re: Slave PLB core interrupt
    118471: 07/04/27: Prope timing constraint for this pin?
    118722: 07/05/02: Re: ISE 8.2 Strange cache problem? Warning...
    118726: 07/05/02: Re: Read 64-bit value over PLB
    118753: 07/05/03: Re: OPB Master Peripheral
    118848: 07/05/04: Re: Select pullup, pulldown or none via embedded S/W
    118961: 07/05/08: Chipscope with custom cable?
    119092: 07/05/11: V4FX PPC ICU data transfer timeout?
    119851: 07/05/28: Atmel FPSLIC users out there?
    120749: 07/06/15: Re: booting a large V4 PPC program with a minimum of on chip bram
    121250: 07/06/29: Re: d-link router?
    122281: 07/07/25: Re: Xint64 ?
    122550: 07/07/31: Re: Looking for PLD with embedded memory
    122551: 07/07/31: Re: Looking for 2 simple Xilinx examples of FSL
    126018: 07/11/12: Re: Embedded Linux & Code Security
    129733: 08/03/04: Re: Software Defined Radio auf Xilinx Virtex 4
    129773: 08/03/05: Re: AES Bitstream Encryption in Virtex-4. How safe it is?
    133375: 08/06/26: Re: FPGA area use by module?
    133586: 08/07/04: Re: Processor Debug interface
    135129: 08/09/17: Re: SDRAM question
    135131: 08/09/17: Re: Random Mask Generation on FPGAs
    136992: 08/12/17: V4FX PPC405: DCR bus and synchronization
    137602: 09/01/23: Re: XPS PowerPC accessing DCR register
    138100: 09/02/06: Re: Xilinx Powerpc issue with custom peripherals
    140129: 09/04/29: ASIC from working FPGA design
    140255: 09/05/06: Re: some soft-processors
    140757: 09/05/25: Re: BSCAN_SPARTAN3 proper use with CAPTURE and UPDATE
jetq88:
    106660: 06/08/16: xilinx or altera?
    108441: 06/09/11: VHDL or Verilog or SystemC?
    109548: 06/09/28: Re: ISE DDR Memory Controller to write between RAM and FPGA
    109551: 06/09/28: Re: ISE DDR Memory Controller to write between RAM and FPGA
    109742: 06/10/04: Can I use MIG tool to generate memory controller for DIMM module of DDR SDRAM?
    114039: 07/01/03: Spartan3 XC3S400 won't work after upgrading ISE from ISE6.3 to ISE8.2
    114662: 07/01/22: Re: Xilinx doing a re-entry in non-volatile FPGA arena!!!
    115597: 07/02/14: Need fair opinions on choosing either Altera or Xilinx as main FPGA source
    117506: 07/04/02: Re: Does the XC3S250E-VQ100 exist?
    117522: 07/04/03: Re: Implementing a communication protocol for data transfer over TCP on an FPGA
    117632: 07/04/05: what is the best practice to exchange data between microblaze softcore and customer hardware writen in VHDL
jeung joon ee:
    26679: 00/10/24: ultra low cost Evaluation boards
    30641: 01/04/20: FREE SDRAM-controller core
jeverett@xilinx.com:
    98701: 06/03/14: Re: Why does Xilinx hate version control?
jey:
    128127: 08/01/16: Basic FPGA question about Reset
    128131: 08/01/16: Re: Basic FPGA question about Reset
    128133: 08/01/16: Re: Basic FPGA question about Reset
jeycrisis:
    83920: 05/05/09: Configuring an XC3S400 Spartan 3 with JTAG
    83961: 05/05/10: Re: Configuring an XC3S400 Spartan 3 with JTAG
    83974: 05/05/10: Re: Configuring an XC3S400 Spartan 3 with JTAG
Jez Smith:
    65834: 04/02/07: Xilinx webpack
<jez-smith@hotmail.co.uk>:
    112762: 06/11/28: Re: verilog 2 VHDL translator
    112778: 06/11/28: Re: Double buffering
    112811: 06/11/29: Re: FPGA application field
    112838: 06/11/29: Re: FPGA application field
    112858: 06/11/29: Re: ISE on a cluster?
    112899: 06/11/30: Re: DCM jitter (again)
    112902: 06/11/30: Re: DCM jitter (again)
Jezwold:
    77544: 05/01/10: Re: Configuration devices
    77558: 05/01/10: Re: San Jose job offer - need advice
    77595: 05/01/11: Re: (d)ram interface
    77641: 05/01/12: Re: Configuration devices
    77719: 05/01/15: Re: Questions from a beginner...
    77723: 05/01/15: Re: Questions from a beginner...
    77724: 05/01/15: Re: Cheap source for GAL's
    77962: 05/01/20: Re: lasy question about VHDL: logic between a bit and a vector
    78029: 05/01/23: Don't touch in altera maxplus 2
    78030: 05/01/23: Re: Microscope examination of a PLD
    78130: 05/01/25: Re: Don't touch in altera maxplus 2
    78308: 05/01/28: Re: How do I get the contents in FPGA
    78317: 05/01/29: Re: Sensitive List Question
    78318: 05/01/29: Re: Sensitive List Question
    78321: 05/01/29: Re: Quartus II megafunction
    78329: 05/01/29: Re: Sensitive List Question
    78330: 05/01/29: Re: Quartus II megafunction
    78338: 05/01/29: Re: i need xilinx edk
    78340: 05/01/29: Re: i need xilinx edk
    78370: 05/01/30: Re: OT: Design security
    78419: 05/01/31: Re: Design security
    78460: 05/02/01: Re: Evaluating EDIF netlist
    78501: 05/02/01: Re: MP3 Player Project
    78503: 05/02/01: Re: Design security
    78551: 05/02/03: Re: How to handle clock skew?
    78557: 05/02/03: Re: Q, compile option, mb-gcc
    78574: 05/02/03: Re: Help, i'm geting warnings :-(
    78646: 05/02/04: Re: Spartan-3 Starter Kit supplier in the UK?
    78853: 05/02/08: Re: .vho (Xilinx Core Generator) to .vhd ??
    78984: 05/02/10: Re: Sending text from fpga to printer
    78985: 05/02/10: Re: C program to big for microblaze?
    79025: 05/02/11: Re: Altera's Megafunction altaccumulator
    79030: 05/02/11: Re: ISE and IEEE.Fixed_pkg (fixed point math for synth?)
    79474: 05/02/19: Re: why to use FIFO on FPGA?
    79564: 05/02/20: Re: WYSIWYG option in xilinx webpack 6.3
    79772: 05/02/24: Re: Looking for some rules of thumb - migrating a discrete 74HCxxx design into an FPGA
    79900: 05/02/25: Re: Error in ISE 6.3
    79962: 05/02/27: Re: I2C protocol to communicate between FPGAs
    80875: 05/03/13: Re: Which HDL?
    80930: 05/03/14: Re: Which HDL?
    81091: 05/03/17: Re: Newbie: Slow FPGAs
    81099: 05/03/17: Re: Newbie: Slow FPGAs
Jezz:
    75376: 04/11/03: Re: FPGA for Game and Amusement
    75391: 04/11/04: Re: FPGA for Game and Amusement
jf hasson:
    45676: 02/07/31: logicore pci macro in virtex problem
jfh:
    34136: 01/08/15: Hysteresis behavior of an fpga buffer
    34807: 01/09/08: Powering up a multi virtex fpga board
    36835: 01/11/21: slew rate of virtex output buffers figures
    43235: 02/05/17: LOCKED signal of a DLL in a Virtex device questions
    87874: 05/08/03: RocketIO connexion to an optical transceiver
    87875: 05/08/03: Re: RocketIO connexion to an optical transceiver
    87879: 05/08/03: Re: RocketIO connexion to an optical transceiver
    87885: 05/08/03: Re: RocketIO connexion to an optical transceiver
    94902: 06/01/18: profiling with virtex4 powerpc
    99579: 06/03/26: Linux on ml403
    99766: 06/03/28: Re: Linux on ml403
    99928: 06/03/30: Re: Linux on ml403
    112777: 06/11/28: Hardware in the loop simulation for Altera design
    112856: 06/11/29: Re: Hardware in the loop simulation for Altera design
    139347: 09/03/27: PLL in Actel Igloo part
    139360: 09/03/27: Re: PLL in Actel Igloo part
    139365: 09/03/27: Re: PLL in Actel Igloo part
    144366: 09/12/01: PMC or XMC based on Altera parts (preferably Stratix)
    145423: 10/02/08: Progrmming a flash connected to a Stratix II GX
    146399: 10/03/15: Nested interrupts in Nios system and hung system
JFMAHER:
    1751: 95/08/24: For Sale: Chronology Package...
    2138: 95/10/19: For Sale:Chronology Docutime
JG:
    111547: 06/11/05: Spartan3E kit and BPI configuration problem.
    112681: 06/11/27: What's the status regarding MicroBlaze, Lynuxworks and uClinux 2.6?
-jg:
    114211: 07/01/07: Re: Problem with unused pin on Spartan 2E
    114212: 07/01/07: Re: First Picture of Craignell Modules
    114246: 07/01/08: Re: First Picture of Craignell Modules
    114305: 07/01/11: Re: Quick question on Coolrunner II IO voltages
    114334: 07/01/11: Re: inserting text into a video stream (from a pre-existing video source)
    114336: 07/01/11: Re: picoblaze RS-232 using 62.5 MHz
    114383: 07/01/13: Re: Will FPGAs suit my need?
    114427: 07/01/15: Re: ISE 9.1i and partial reconfiguration
    114465: 07/01/16: Re: interesting article FPGA routing field programmable nanowire interconnect (FPNI)
    114467: 07/01/16: Re: microcode in verilog?
    114587: 07/01/19: Re: Phasse Detector
    114609: 07/01/20: Re: Phasse Detector
    114681: 07/01/22: Re: Xilinx doing a re-entry in non-volatile FPGA arena!!!
    114835: 07/01/24: Re: Does xiling cpld's need a power supply bypass cap?
    114961: 07/01/27: Re: Minimal design for xilinx?
    114962: 07/01/27: Re: Minimal design for xilinx?
    115945: 07/02/26: Re: Spartan-3AN
    115965: 07/02/26: Re: Spartan-3AN
    116849: 07/03/19: Re: Altera introduces Cyclone III devices, ships 65nm
    116860: 07/03/19: Re: Altera introduces Cyclone III devices, ships 65nm
    117858: 07/04/11: =?iso-8859-1?q?Re:_CPLD_+_=B5C_with_reasonably-priced_tools=3F?=
    117859: 07/04/11: Re: Measuring the period of a signal
    117951: 07/04/14: Re: picoblaze C compiler download wanted
    118361: 07/04/24: Re: FPGA and DAC for wave generation
    127539: 08/01/01: Re: Where are the LCD or OLED bitmapped displays?
    127546: 08/01/01: Re: Where are the LCD or OLED bitmapped displays?
    127840: 08/01/09: Re: Real examples of metastability causing bugs
    127844: 08/01/09: Re: Low Power CPU Implementation
    127846: 08/01/09: Re: Processor in CPLD
    127986: 08/01/11: Re: Real examples of metastability causing bugs
    127995: 08/01/11: Re: Real examples of metastability causing bugs
    127998: 08/01/11: Re: Real examples of metastability causing bugs
    128012: 08/01/12: Re: Real examples of metastability causing bugs
    128014: 08/01/12: Re: Real examples of metastability causing bugs
    128030: 08/01/14: Re: Real examples of metastability causing bugs
    128075: 08/01/14: Re: Real examples of metastability causing bugs
    128089: 08/01/15: Re: Real examples of metastability causing bugs
    128116: 08/01/15: Re: Debbuging a RISC processor on an FPGA
    128266: 08/01/19: Re: Source of accurate frequency
    128275: 08/01/19: Re: Source of accurate frequency
    128283: 08/01/20: Re: Source of accurate frequency
    128316: 08/01/22: Re: Source of accurate frequency
    128353: 08/01/22: Re: Ballistic chronograph using a Spartan 3E starter board
    128408: 08/01/24: Re: Virtex-4 driving a 5V CMOS
    129824: 08/03/06: Re: Anyone to open "FPGA museum" ? Here is first item :)
    130433: 08/03/24: Re: counterfeit Xilinx ?
    131366: 08/04/20: Re: Problem writing quadrature decoder
    131389: 08/04/20: Re: Problem writing quadrature decoder
    131390: 08/04/21: Re: Problem writing quadrature decoder
    131461: 08/04/21: Re: Problem writing quadrature decoder
    131489: 08/04/22: Re: counterfeit Xilinx ?
    131616: 08/04/26: Re: Problem writing quadrature decoder
    131617: 08/04/26: Re: ATF750 for Proteus
    131636: 08/04/27: Re: Problem writing quadrature decoder
    131637: 08/04/27: Re: Problem writing quadrature decoder
    133395: 08/06/26: Re: Beginner : Rotary switch (quad sw)
    137619: 09/01/23: Re: Altera 3000A: Can I make a freq. generator (1 Hz to 2 kHz) ?
    137620: 09/01/23: Re: Altera 3000A: Can I make a freq. generator (1 Hz to 2 kHz) ?
    137633: 09/01/24: Re: Altera 3000A: Can I make a freq. generator (1 Hz to 2 kHz) ?
    137829: 09/01/30: Re: Spartan-6
    137934: 09/02/02: Re: Spartan-6
    137935: 09/02/02: Re: Why the second flip-flop in Virtex-6?
    137942: 09/02/02: Re: Spartan-6
    137950: 09/02/02: Re: Spartan-6
    138002: 09/02/03: Re: Why the second flip-flop in Virtex-6?
    138003: 09/02/03: Re: Spartan-6
    138004: 09/02/03: Re: Tabula - new kid on the FPGA block?
    138021: 09/02/04: Re: Sixteen serial ports ?
    138022: 09/02/04: Re: Spartan-6
    138023: 09/02/04: Re: Why the second flip-flop in Virtex-6?
    138025: 09/02/04: Re: Why the second flip-flop in Virtex-6?
    138052: 09/02/04: Re: Antti-Brain issue 5 released
    138053: 09/02/04: Re: Antti-Brain issue 5 released
    138344: 09/02/16: Re: cpld 9572 xilinx
    138420: 09/02/20: Re: Very fast counter in VirtexII
    138521: 09/02/25: Re: Very fast counter in VirtexII
    138599: 09/03/01: Re: New person to CPLD programming
    138830: 09/03/12: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
    138851: 09/03/12: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
    138871: 09/03/12: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
    138931: 09/03/15: Re: Getting started with FPGA
    138989: 09/03/17: Re: Zero operand CPUs
    139045: 09/03/19: Re: Documenting a simple CPU
    139049: 09/03/19: Re: Documenting a simple CPU
    139075: 09/03/19: Re: Documenting a simple CPU
    139076: 09/03/19: Re: Documenting a simple CPU
    139219: 09/03/23: Re: Silicon Blue last datesheet correct URL
    139220: 09/03/23: Re: Silicon Blue last datesheet correct URL
    139226: 09/03/23: Re: Silicon Blue last datesheet correct URL
    139227: 09/03/23: Re: Silicon Blue last datesheet correct URL
    139228: 09/03/23: Re: Silicon Blue last datesheet correct URL
    139247: 09/03/24: Re: Silicon Blue last datesheet correct URL
    139269: 09/03/24: Re: FPGAs in automotive apps (was Re: Silicon Blue last datesheet
    139271: 09/03/24: Re: Antti Processor
    139313: 09/03/26: Re: Looking for a low-cost development kit
    139371: 09/03/27: Re: best soft core(s) that have C compiler support
    139384: 09/03/27: Re: best soft core(s) that have C compiler support
    139388: 09/03/27: Re: best soft core(s) that have C compiler support
    139390: 09/03/28: Re: best soft core(s) that have C compiler support
    139409: 09/03/28: Re: What does Xilinx mean by "Real 6-input look-up (LUT) technology"?
    139437: 09/03/29: Re: best soft core(s) that have C compiler support
    139512: 09/04/01: Re: Switching an AC power socket from an FPGA
    139543: 09/04/02: Re: delays in XC95144XL CPLD
    139559: 09/04/03: Re: delays in XC95144XL CPLD
    139678: 09/04/08: Re: Two stage synchroniser,how does it work?
    139679: 09/04/08: Re: ANN: Antti-Brain March issue released
    139883: 09/04/18: Re: Dual-frequency quartz oscillator with a FPGA ?
    139904: 09/04/18: Re: Dual-frequency quartz oscillator with a FPGA ?
    139911: 09/04/18: Re: Dual-frequency quartz oscillator with a FPGA ?
    140203: 09/05/03: Re: High-speed signals crossing a split-ground
    140326: 09/05/08: Re: Can the complex DSP archetecture based on FPGA+DSP be replaced by
    140451: 09/05/13: Re: cheapest FPGA?
    140490: 09/05/14: Re: cheapest FPGA?
    140492: 09/05/14: Re: Xilinx 5V FPGA available from distributors again???
    140549: 09/05/16: Re: some soft-processors
    140561: 09/05/17: Re: some soft-processors
    140577: 09/05/18: Re: SD card bootstrap code in 55 instructions
    140578: 09/05/18: Re: XILINX license model restricts longtime availability
    140632: 09/05/20: Re: some soft-processors
    140634: 09/05/20: Re: Open source processors
    140867: 09/05/27: Re: Coolrunner II: what's wrong up here ?
    140878: 09/05/27: Re: Old School Altera MAX 7000
    140931: 09/05/29: Re: Coolrunner II: what's wrong up here ?
    140933: 09/05/30: Re: Has ST's FPGA project GOSPL transformed to Morpheus ?
    140992: 09/06/01: Re: phase locking a slow (2Mhz) signal.
    141224: 09/06/11: Re: Latest Xilinx Discontinuations
    141257: 09/06/12: Re: NTSC/PAL Encoder using FPGA and DAC
    141537: 09/06/26: Re: New feauture in Spartan-6 FPGA's: SELF DESTRUCT !!
    141549: 09/06/27: Re: New feauture in Spartan-6 FPGA's: SELF DESTRUCT !!
    141550: 09/06/27: Re: 6/6 infos
    141560: 09/06/27: Re: 6/6 infos
    141636: 09/07/01: Re: FPGA as FM RADIO transmitter
    142077: 09/07/23: Re: Strange FPGA behavior
    142087: 09/07/23: Re: How do you handle build variants in VHDL?
    142145: 09/07/26: Re: How to implementa an FSM in block ram
    142205: 09/07/28: Re: cool chart
    142232: 09/07/29: Re: cool chart
    142241: 09/07/30: Re: How to implementa an FSM in block ram
    142638: 09/08/23: Re: Soft Processor IP core report
    142660: 09/08/24: Re: Soft Processor IP core report
    142693: 09/08/26: Re: Reading from ADC and writing to DAC at same time
    143046: 09/09/17: Re: WARP PLD's are back in new shape
    143091: 09/09/19: Re: Actel dropped ARM7, when comes Xilinx ARM enabled silicon?
    143092: 09/09/19: Re: Actel dropped ARM7, when comes Xilinx ARM enabled silicon?
    143172: 09/09/23: Re: 8 phase clock output
    143214: 09/09/25: Re: Super Small MIPS-compatible Altera-Based Soft Processor and
    143229: 09/09/27: Re: USB programmable Open Source Hardware
    143231: 09/09/27: Re: USB programmable Open Source Hardware
    143238: 09/09/28: Re: USB programmable Open Source Hardware
    143255: 09/09/28: Re: USB programmable Open Source Hardware
    143258: 09/09/28: Re: USB programmable Open Source Hardware
    143269: 09/09/29: Re: USB programmable Open Source Hardware
    143370: 09/10/07: Re: Ideas for a pulse programmer needed
    143418: 09/10/10: Re: Development boards for CPU development ?
    143483: 09/10/12: Re: Implement ARM cores on a FPGA chip?
    143528: 09/10/14: Re: FPGA on-die LVDS termination issues
    143699: 09/10/21: Re: Can I use a crystal for the clock source for a Xilinx Spartan 3A
    143734: 09/10/22: Re: Time stability of clock on FPGA board
    143735: 09/10/22: Re: Time stability of clock on FPGA board
    143774: 09/10/24: Re: Generating delay using logic gates
    143910: 09/11/02: Re: 50+ pages fresh from Antti's brain
    143911: 09/11/02: Re: Need some help creating a ring oscillator on a Spartan-3AN
    143957: 09/11/04: Re: Cyclone IV announced
    143992: 09/11/06: Re: CPLD + MCU SoC from Cypress, free samples too!
    144010: 09/11/06: Re: CPLD + MCU SoC from Cypress, free samples too!
    144032: 09/11/08: Re: Sinewave generation
    144033: 09/11/08: Re: Sinewave generation
    144035: 09/11/08: Re: OK Xilinx users, it's time I was let in on the joke...
    144037: 09/11/09: Re: free software/open source projects and FPGA?
    144062: 09/11/09: Re: CPLD + MCU SoC from Cypress, free samples too!
    144066: 09/11/09: Re: XPLA3 coolrunner programming tool?
    144091: 09/11/10: Re: XPLA3 coolrunner programming tool?
    144094: 09/11/10: Re: XPLA3 coolrunner programming tool?
    144096: 09/11/11: Re: XPLA3 coolrunner programming tool?
    144110: 09/11/11: Re: OK Xilinx users, it's time I was let in on the joke...
    144115: 09/11/11: Re: OK Xilinx users, it's time I was let in on the joke...
    144116: 09/11/11: Re: XPLA3 coolrunner programming tool?
    144120: 09/11/11: Re: XPLA3 coolrunner programming tool?
    144121: 09/11/11: Re: XPLA3 coolrunner programming tool?
    144136: 09/11/12: Re: max. sinking current of XC95144xl cpld
    144299: 09/11/25: Re: 32KHz RTC for FPGA
    144301: 09/11/25: Re: 32KHz RTC for FPGA
    144306: 09/11/25: Re: 32KHz RTC for FPGA
    144308: 09/11/25: Re: 32KHz RTC for FPGA
    144312: 09/11/25: Re: 32KHz RTC for FPGA
    144313: 09/11/25: Re: 32KHz RTC for FPGA
    144317: 09/11/25: Re: 32KHz RTC for FPGA
    144328: 09/11/26: Re: some issues with canned oscillators (was Re: 32KHz RTC for FPGA)
    144330: 09/11/26: Re: some issues with canned oscillators (was Re: 32KHz RTC for FPGA)
    144495: 09/12/10: Re: A new approach to FPGA and PCB System Development Platform, Santa
    144753: 09/12/30: Re: Seeking some advice
    144827: 10/01/06: Serial Flash reaches 104MHz Quad IO speeds
    145020: 10/01/20: Re: Easy PC software tool - Bad experience
    145030: 10/01/20: Re: Easy PC software tool - Bad experience
    145040: 10/01/21: Re: Easy PC software tool - Bad experience
    145073: 10/01/24: Re: timing properties of fpga devices at sub-clock frequencies
    145166: 10/01/29: Re: synthesizing a completely empty design for an FPGA to measure
    145169: 10/01/30: Re: synthesizing a completely empty design for an FPGA to measure
    145171: 10/01/30: Re: synthesizing a completely empty design for an FPGA to measure
    145180: 10/01/30: Re: synthesizing a completely empty design for an FPGA to measure
    145467: 10/02/10: Re: To get higher clock frequencies at output using propagation
    145538: 10/02/13: Re: 28nm FPGAs are coming...
    145630: 10/02/16: Re: What is the basis on flip-flops replaced by a latch
    145715: 10/02/20: Re: Unpredictable design
    145736: 10/02/21: Re: Looking for Ultimate RISC/MISC that runs LINUX Website
    145846: 10/02/25: Re: antti alive message
    145886: 10/02/26: Re: Frustration with Vendors!
    145888: 10/02/26: Re: Frustration with Vendors!
    145891: 10/02/26: Re: Frustration with Vendors!
    145896: 10/02/26: Re: Frustration with Vendors!
    145912: 10/02/27: Re: Frustration with Vendors!
    145913: 10/02/27: Re: Frustration with Vendors!
    145937: 10/02/28: Re: Frustration with Vendors!
    145938: 10/02/28: Re: Frustration with Vendors!
    145943: 10/03/01: Re: Frustration with Vendors!
    145944: 10/03/01: Spice simulation of IBIS details - model examples
    145947: 10/03/01: Re: Spice simulation of IBIS details - model examples
    145957: 10/03/01: Re: Spice simulation of IBIS details - model examples
    145960: 10/03/01: Re: Spice simulation of IBIS details - model examples
    145963: 10/03/01: Re: Spice simulation of IBIS details - model examples
    145991: 10/03/02: Re: Spice simulation of IBIS details - model examples
    145995: 10/03/02: Re: Tabula. (FPGA start up)
    146000: 10/03/02: Re: Tabula. (FPGA start up)
    146042: 10/03/04: Re: Announce: 1 Pin Interface - FPGA and HW debug tool
    146044: 10/03/04: Re: Actel is now the only FPGA vendor with hard-core processor in the
    146052: 10/03/04: Re: Actel is now the only FPGA vendor with hard-core processor in the
    146058: 10/03/04: Re: Announce: 1 Pin Interface - FPGA and HW debug tool
    146059: 10/03/04: Re: Announce: 1 Pin Interface - FPGA and HW debug tool
    146063: 10/03/04: Re: Announce: 1 Pin Interface - FPGA and HW debug tool
    146067: 10/03/04: Re: Announce: 1 Pin Interface - FPGA and HW debug tool
    146068: 10/03/04: Re: Tabula. (FPGA start up)
    146075: 10/03/04: Re: Announce: 1 Pin Interface - FPGA and HW debug tool
    146118: 10/03/05: Re: Actel is now the only FPGA vendor with hard-core processor in the
    146137: 10/03/06: Re: FSM in BlockRAM
    146146: 10/03/06: Re: FSM in BlockRAM
    146206: 10/03/08: Re: Tabula. (FPGA start up)
    146275: 10/03/10: Re: Tier Logic introduces the world's first 3D FPGA
    146277: 10/03/10: Re: Tier Logic introduces the world's first 3D FPGA
    146281: 10/03/10: Re: Tier Logic introduces the world's first 3D FPGA
    146286: 10/03/10: Re: Tier Logic introduces the world's first 3D FPGA
    146293: 10/03/10: Re: Why doesn't this situation generate a latch?
    146313: 10/03/11: Re: Tier Logic introduces the world's first 3D FPGA
    146320: 10/03/11: Re: Tier Logic introduces the world's first 3D FPGA
    146321: 10/03/11: Re: Tier Logic introduces the world's first 3D FPGA
    146364: 10/03/14: Re: Tier Logic introduces the world's first 3D FPGA
    146431: 10/03/17: Re: Xilinx Spartan6 Virtex6 Rollout
    146437: 10/03/18: Re: Tabula. (FPGA start up)
    146457: 10/03/18: Re: Xilinx Spartan6 Virtex6 Rollout
    146461: 10/03/18: Re: Xilinx Spartan6 Virtex6 Rollout
    146463: 10/03/18: Re: Xilinx Spartan6 Virtex6 Rollout
    146647: 10/03/24: Re: Ring Oscillator -> counter differences
    146729: 10/03/26: Re: Ring Oscillator -> counter differences
    146730: 10/03/26: Re: PCB routing issues for sync SRAM
    146742: 10/03/26: Re: Ring Oscillator -> counter differences
    146743: 10/03/26: Re: Multipliers in CoolRunner Series?
    146758: 10/03/27: Re: Multipliers in CoolRunner Series?
    146873: 10/03/30: Re: Spartan 6 PLL - Why such a strict input jitter requirement?
    146897: 10/03/31: Re: Spartan 3E: MAX_STEPS as a function of CLKIN frequency
    147035: 10/04/10: Re: I'd rather switch than fight!
    147231: 10/04/19: Re: Need to run old 8051 firmware
    147293: 10/04/22: Re: Polmaddie Family CPLD and FPGA Teaching Boards
    147294: 10/04/22: Re: Polmaddie Family CPLD and FPGA Teaching Boards
    147365: 10/04/23: Re: Need to run old 8051 firmware
    147377: 10/04/24: Re: voltage divider calcs
    147525: 10/04/29: Re: xilinx arm finally announced
    147554: 10/05/01: Re: Cheap FPGAs for tutorial
    147713: 10/05/18: Re: New 'standard' compact programming header needed!
    147731: 10/05/19: Re: New 'standard' compact programming header needed!
    147887: 10/05/29: Re: Last Xilinx Webpack that was big-brother free?
    147910: 10/06/01: Re: Anyone else need bigger parts in small (low pin count) packages
    147923: 10/06/02: Re: Anyone else need bigger parts in small (low pin count) packages
    147929: 10/06/02: Re: Anyone else need bigger parts in small (low pin count) packages
    147948: 10/06/03: Re: Anyone else need bigger parts in small (low pin count) packages
    147954: 10/06/03: Re: Anyone else need bigger parts in small (low pin count) packages
    147958: 10/06/04: Re: Anyone else need bigger parts in small (low pin count) packages
    148052: 10/06/16: Re: How to detect a sync and start of a frame in an optimal way
    148167: 10/06/24: Re: Please suggest NON Volatile FPGA Devices
    148496: 10/07/27: Re: All Digital PLL
    148734: 10/08/18: Re: CPLD development board with 8-bit wide Flash/EEProm
    148909: 10/09/09: Re: PSOC3/5
    148911: 10/09/09: Re: Want to get into FPGA
    148915: 10/09/09: Re: PSOC3/5
    149668: 10/11/15: Re: Cypres PSoC devices - hdl entry for digital sections?
    149670: 10/11/15: Re: Maximum speed SPI on Spartan3a?
    150835: 11/02/15: Re: why an FSM is not a counter?!
    150836: 11/02/15: Re: lattice machXO2 VCCP pin
jg:
    153920: 12/06/29: Re: Replacement for XC4005E
    154306: 12/09/25: Re: Xilinx CPLD XC95144 for Driving Sigma Delta DAC
    154429: 12/10/28: Re: Using LVDS Input for Delta Sigma ADC
    154433: 12/10/29: Re: Using LVDS Input for Delta Sigma ADC
    154440: 12/11/02: Re: production life of Spartan3A ?
    154791: 13/01/10: Re: Lattice iCECube2 for iCE40 Devices
    154901: 13/02/10: Re: Idea Hunt, FPGA + ARM Cortex-M3
    154977: 13/03/07: Re: EPROM programmer erase
    155149: 13/04/30: Re: Low cost and/or small size CPU in an FPGA
    155570: 13/07/22: Re: Xilinx "Ultrascale" announcement leaves out low-cost devices
    155571: 13/07/22: Re: Xilinx "Ultrascale" announcement leaves out low-cost devices
    155704: 13/08/11: Re: Lattice Announces EOL for XP and EC/P Product Lines
    155731: 13/08/23: Re: Lattice Announces EOL for XP and EC/P Product Lines
    155747: 13/08/26: Re: Lattice Announces EOL for XP and EC/P Product Lines
    155748: 13/08/26: Re: Lattice Announces EOL for XP and EC/P Product Lines
    155749: 13/08/26: Re: Lattice Announces EOL for XP and EC/P Product Lines
    155765: 13/08/29: Re: Lattice Announces EOL for XP and EC/P Product Lines
    155813: 13/09/18: Re: Legal Issues Reproducing Old CPU
    155826: 13/09/24: Re: Legal Issues Reproducing Old CPU
    155845: 13/09/29: Re: Lattice diamond / MachXO2
    156145: 13/12/12: Re: MachXO breakout board as a programmer
    156746: 14/06/14: Re: 22V10 programmer
jg.campbell:
    20983: 00/03/02: Re: Bit Serial Arithmetic De-mystified
<jgais@ws.estec.esa.nl>:
    18204: 99/10/07: Free SPARC VHDL model available
    25112: 00/08/26: Vacancy at European Space Agency
jgarrigo:
    22922: 00/06/02: RE: Help with Coregen
<jgbreezer@gmail.com>:
    156897: 14/07/24: Re: Chisel as alternative HDL
jgjhg ghjg:
    16967: 99/06/21: XILINX PROG-PIN unconnected?
jgk2004:
    152060: 11/06/29: Virtex 5 Rocket IO design for reading in ADC data.
    152067: 11/06/30: Re: Virtex 5 Rocket IO design for reading in ADC data.
    152069: 11/06/30: Re: Virtex 5 Rocket IO design for reading in ADC data.
    152071: 11/06/30: Re: Virtex 5 Rocket IO design for reading in ADC data.
    152075: 11/06/30: Re: Virtex 5 Rocket IO design for reading in ADC data.
jgknowla1:
    84060: 05/05/11: Minimum circuit to get Spartan-3 running
    84084: 05/05/12: Re: Minimum circuit to get Spartan-3 running
jgraham:
    58959: 03/08/05: retiming with Synplify Pro
jhamz:
    133445: 08/06/29: I-map Websolution...turning possibility into reality...
<jhirbawi@yahoo.com>:
    10663: 98/06/09: Re: Multipliers on FPGA's
    11037: 98/07/14: Re: Howto: CRC's and PRBS in Parallel
    11086: 98/07/18: Re: Shift Invarient Bit Transform
    11110: 98/07/20: Re: Shift Invarient Bit Transform
    15384: 99/03/22: Re: Bit Error Rate Test
    18084: 99/09/28: Re: Altera 20KE LVDS IO
    19724: 00/01/10: Re: Decoding RSPC (Reed Solomon Product Code)
JHL:
    39937: 02/02/22: How can I disable clock buffer (BUFG) insertion in Xilinx Foundation F3.1i?
    39999: 02/02/24: Re: How can I disable clock buffer (BUFG) insertion in Xilinx Foundation F3.1i?
Jhlw:
    110874: 06/10/24: Bit order reversed in Xilinx post-translate simulation
    110989: 06/10/26: Re: Bit order reversed in Xilinx post-translate simulation
    111507: 06/11/03: Cleaning generated files in Xilinx 8.2 EDK and ISE
    111524: 06/11/04: Re: Cleaning generated files in Xilinx 8.2 EDK and ISE
    111549: 06/11/05: Re: Cleaning generated files in Xilinx 8.2 EDK and ISE
    111974: 06/11/13: Running an application from external memory in Xilinx
    112057: 06/11/15: Getting Xilinx DMA SG working with peripheral
    114496: 07/01/17: Re: running applications from external memory
    114503: 07/01/17: Re: running applications from external memory
    114537: 07/01/18: Re: running applications from external memory
    114538: 07/01/18: Re: running applications from external memory
<jhmccaskill@gmail.com>:
    116398: 07/03/08: Re: Introducing picosecond delay between two output signals
Jhoberg:
    116693: 07/03/15: Verilog DSP Examples (FFT With 32K-Point Transform Length, FIR, IIR, Discrete Cosine Transform (DCT), Convolution 2D)
    116801: 07/03/18: ADC capture with FPGA Spartan3 in Verilg
    118222: 07/04/19: Free Hardware
    118259: 07/04/20: Re: Free Hardware
    118312: 07/04/23: Re: Free Hardware
    118314: 07/04/23: free architecture
    118325: 07/04/23: Re: free architecture
jholley:
    88118: 05/08/09: Re: Hiding data inside a FPGA
<Jhon12@hotmail.com>:
    30795: 01/04/29: Speedup games, programs and get more FREE RAM
<jhon@geocities.com>:
    8558: 98/01/08: Parallel port interface
<jhouse@btmd.com>:
    105042: 06/07/12: Can't get my Verilog Peripheral to import into XPS! Any tricks?
    105070: 06/07/12: Re: Can't get my Verilog Peripheral to import into XPS! Any tricks?
    105089: 06/07/13: Re: Can't get my Verilog Peripheral to import into XPS! Any tricks?
jhuebner:
    57756: 03/07/05: Re: PC-104 dev Boards
Ji Soon Kim:
    120603: 07/06/11: Help with T-VPACK
Jialin:
    111651: 06/11/07: How to send data/program to the memory of a Spartan 3 starter kit board
    111713: 06/11/08: Re: How to send data/program to the memory of a Spartan 3 starter kit board
    111714: 06/11/08: Re: How to send data/program to the memory of a Spartan 3 starter kit board
Jian F. Weng:
    22897: 00/05/30: Implement LMS
    22898: 00/05/30: Implement LMS
Jian Ju:
    53773: 03/03/22: how to implement the bidir in Altera AHDL?
    63631: 03/11/27: overshoot problem of EPM7128S
Jian Liang:
    66827: 04/02/26: Question: size of Stratix??
Jian Lin:
    24280: 00/08/02: Category : Subject
Jian Shen:
    5957: 97/03/31: clock edge specification for Synopsys synthesis
Jian_Zhang:
    9285: 98/03/05: Using Java for PLI?
    9301: 98/03/05: Re: Using Java for PLI?
Jiang:
    62912: 03/11/11: Are modules that are not floorplanned still functional?
    62995: 03/11/12: Re: Are modules that are not floorplanned still functional?
jianghongtu@hotmail.com:
    52051: 03/01/29: problem with JTAG downloading
jianhuawow:
    152226: 11/07/24: About the setup time of BUFGMUX in Spartan6
Jianrong Wang:
    46478: 02/08/31: A little question
Jianyong Niu:
    27474: 00/11/23: survey of fpga application
    27930: 00/12/15: kalman filter
    45068: 02/07/11: Need a non-pipelined signed integer divider
    46301: 02/08/25: Re: I2C BUS
    46933: 02/09/12: Re: symplicity conv_integer problem
    55276: 03/05/02: Re: IP Core for CAN communication
    66481: 04/02/20: Power supply for the Xilinx Virtex Pro FF1152 Proto Board
    70291: 04/06/11: Re: Xilinx System Generator
JianYong Niu:
    28873: 01/01/26: what is the best FPGA development toolkit?
    29099: 01/02/06: Xilinx Implementation Error! need help urgently
    29113: 01/02/06: Re: Handel-C language.
    30519: 01/04/12: *help* how to count clock cycles in a design? how can i know its maximum clock frequency?
    32420: 01/06/26: Xilinx System Generator Simulation Problem
    32535: 01/06/29: Re: Xilinx System Generator Simulation Problem
    32536: 01/06/29: Error to execute vcom.do in ModelSim XE5.3d
    33097: 01/07/17: Xilinx System Generator V1.0 question
    33138: 01/07/18: Re: Project implementation
    36471: 01/11/09: How to convert unsigned integer into std_logic_vector in VHDL design?
    36560: 01/11/12: fixed-point number convert
    36801: 01/11/20: Implementation problem with the codes generated from Xilinx System Generator
    37516: 01/12/13: FPGA development board
JianyongNiu:
    28806: 01/01/24: can not start coregen
    28807: 01/01/24: Re: can not start coregen
    28855: 01/01/26: Re: can not start coregen
    46077: 02/08/16: Re: Divider in Xilinx System Generator
jicho:
    64299: 03/12/26: LVPECL_33 to LVPECL_25 (virtex-II pro)
<jidan1@hotmail.com>:
    106703: 06/08/17: Why is Spartan-3 more expensive than Cyclone?
    107675: 06/08/30: Bypass Caps : XAPP623 vs Spartan-3 Starter Kit Board
    108507: 06/09/12: Spartan-3: 5V -> 2.5V level shifting
    108536: 06/09/12: Re: Spartan-3: 5V -> 2.5V level shifting
    108593: 06/09/13: Re: Spartan-3: 5V -> 2.5V level shifting
    108629: 06/09/14: Re: Spartan-3: 5V -> 2.5V level shifting
    117207: 07/03/26: Minimal pins for JTAG configuration
    117212: 07/03/26: Re: Minimal pins for JTAG configuration
    117258: 07/03/27: Re: Minimal pins for JTAG configuration
    117324: 07/03/28: Problems with Xilinx Parallel III Cable
    117325: 07/03/28: Re: Minimal pins for JTAG configuration
    117329: 07/03/28: Re: Problems with Xilinx Parallel III Cable
    117332: 07/03/28: Re: Problems with Xilinx Parallel III Cable
    117337: 07/03/28: Re: Problems with Xilinx Parallel III Cable
    117338: 07/03/28: Re: Problems with Xilinx Parallel III Cable
    117342: 07/03/28: Re: Problems with Xilinx Parallel III Cable
    117346: 07/03/28: Re: Problems with Xilinx Parallel III Cable
    117364: 07/03/29: Re: Problems with Xilinx Parallel III Cable
    117365: 07/03/29: Re: Problems with Xilinx Parallel III Cable
    117377: 07/03/29: Re: Problems with Xilinx Parallel III Cable
    120205: 07/06/03: Microcontrollers have a better predictable time behaviour than FPGAs
    120251: 07/06/04: Re: Microcontrollers have a better predictable time behaviour than FPGAs
    125893: 07/11/08: Maximum current drive according to datasheet ?!
    125897: 07/11/08: Re: Maximum current drive according to datasheet ?!
    125930: 07/11/08: Re: Maximum current drive according to datasheet ?!
    132464: 08/05/28: JTAG + PROM error!
    132673: 08/06/05: Re: JTAG + PROM error!
    132771: 08/06/06: Re: JTAG + PROM error!
    132777: 08/06/06: Re: JTAG + PROM error!
    132778: 08/06/06: Re: JTAG + PROM error!
<jigarmori@gmail.com>:
    156386: 14/03/26: Re: Initializing color bars on CH7301
Jihan Zhu:
    54449: 03/04/11: Dynamic Reconfigurable FPGAs
Jihoon:
    92827: 05/12/07: Re: ML402 DDR SDRAM
    92828: 05/12/07: Re: ML402 DDR SDRAM
Jila Nazari:
    28207: 00/12/29: selecting tools a newbi question.
Jim:
    4814: 96/12/17: How to get MORE ORDERS for ANYTHING you SELL!!!
    14910: 99/02/24: JTAG HANG UP......
    14937: 99/02/25: Re: JTAG HANG UP......
    15006: 99/03/02: VECTORS FROM MEMEORY STRUCTURE
    15150: 99/03/09: Re: Startup issues with 24c04 eeprom and I2C interface
    15173: 99/03/10: Re: Startup issues with 24c04 eeprom and I2C interface
    23252: 00/06/19: Does anyone know of a PC Card macro for Xilinx Spartan series?
    35971: 01/10/25: Re: memory dump for Xilinx block ram
    36235: 01/11/02: Re: XC6000
    36236: 01/11/02: Re: JTAG problem
    36351: 01/11/07: Re: Encoder timin question
    36521: 01/11/10: Re: Can Xilinx recognize the critical path in the design
    36532: 01/11/11: Re: Reconfigrable Routers
    36599: 01/11/13: Re: Incrementing counter from state-machine
    36698: 01/11/16: Re: jtag programming xilinx cpld
    36744: 01/11/19: Re: jtag programming xilinx xc9572 cpld
    44435: 02/06/20: Help!I can't use the programmer of Max-plus II on windows XP.
    44619: 02/06/25: Re: Help!I can't use the programmer of Max-plus II on windows XP.
    47259: 02/09/21: Re: Cheap development package for beginner?
    52613: 03/02/16: Re: Help wanted on Installing Xilinx on Win NT
    52773: 03/02/21: Re: Modelsim warnings about Spartan2 Block RAM read/write
    52945: 03/02/26: Xilinx Coolrunner-II Dev Kit
    52972: 03/02/27: Re: Xilinx Coolrunner-II Dev Kit
    59210: 03/08/12: Re: Webpack sees 2 clocks when there is only one
    66684: 04/02/25: Basic jitter from a CPLD (XC7500XL)
    66697: 04/02/25: Re: Basic jitter from a CPLD (XC7500XL)
    66701: 04/02/25: Re: Basic jitter from a CPLD (XC7500XL)
    66702: 04/02/25: Re: Basic jitter from a CPLD (XC7500XL)
    66709: 04/02/25: Re: Basic jitter from a CPLD (XC7500XL)
    66753: 04/02/26: Re: Basic jitter from a CPLD (XC7500XL)
    66800: 04/02/26: Re: Basic jitter from a CPLD (XC7500XL)
    66834: 04/02/27: Re: Basic jitter from a CPLD (XC7500XL)
    67409: 04/03/11: Re: Answering Machine RAM
    67584: 04/03/15: Programmed ground pins v physical grounding (Xilinx CPLD)
    69240: 04/05/02: frequency multiplication
    70707: 04/06/24: DPLL in CPLD
    70753: 04/06/26: Re: DPLL in CPLD
    75801: 04/11/15: Help with Virtex II and 5v TTL
    75811: 04/11/15: Re: Help with Virtex II and 5v TTL
    103051: 06/05/25: ISE sends sensitive information to Xilinx site!
    103211: 06/05/28: Specifying a non connected port
    103356: 06/05/31: Using part of CPLD to Invert Own Clock
    103412: 06/06/01: Using version control for Xilinx 8.1i ISE projects and source files
    103434: 06/06/01: Re: Using part of CPLD to Invert Own Clock
    103444: 06/06/01: Re: Using version control for Xilinx 8.1i ISE projects and source files
    103475: 06/06/03: Re: FPGA board for USB experiments?
    109277: 06/09/22: Re: Altera configuring/programming for FLEX10KE with EPC2 - sof or pof?
    143220: 09/09/26: Re: ChipScope Pro, storing stimuli in ILA core
    143223: 09/09/27: Re: ChipScope Pro, storing stimuli in ILA core
    143262: 09/09/28: Re: ChipScope Pro, storing stimuli in ILA core
    143371: 09/10/07: Re: Virtx 4 and FPGA programming
    143480: 09/10/12: Re: integrating chipscope pro in EDK
    152584: 11/09/15: clock enable for fixed interval
    152597: 11/09/16: Re: clock enable for fixed interval
    153265: 12/01/21: clock enable question
    153268: 12/01/22: Re: clock enable question
jim:
    29538: 01/02/25: answer
    77694: 05/01/14: Configuring FPGA with AT91 (GNUarm settings)
    113173: 06/12/07: testbench help
    115936: 07/02/26: Virtex 4, how do I generate 100khz clock
Jim Antone:
    49340: 02/11/10: PCI core
Jim Banks:
    1291: 95/05/29: Design debug with Xilinx extra fine pitch parts
    3102: 96/04/02: Re: XACT5.2 bit file length count changes
    3095: 96/04/01: XACT5.2 bit file length count changes
Jim Bittman:
    36572: 01/11/12: Re: Virtex 2 parts shipping = receiving
    36574: 01/11/12: Xilinx s/w upgrade 4.1 problems
    36635: 01/11/13: Re: Xilinx s/w upgrade 4.1 problems
    36654: 01/11/14: Re: Xilinx s/w upgrade 4.1 problems
Jim Bock:
    1605: 95/07/26: Lattice:pds+/Viewlogic Comments please
    1784: 95/09/01: Re: VHDL Savy editors under UNIX?
Jim Brain:
    76835: 04/12/14: Need help with CUPL
    76983: 04/12/18: Re: Need help with CUPL
Jim Burnham:
    8490: 97/12/22: Better Digital library for Visio 4
Jim Burns:
    4375: 96/10/22: Re: Xilinx xchecker.exe and Windows NT
Jim Carlock:
    69363: 04/05/07: Re: How to remove an unintended Right-click menu?
Jim Chase:
    7283: 97/08/21: Re: Unbonded Pad Resources
    7629: 97/09/29: FS Advin Pilot U84 Universal Programmer
    7630: 97/09/29: FS Corelis PCI Probe Card
Jim Cohoon:
    5031: 97/01/14: Design Automation Conference Scholarships
Jim Drew:
    2719: 96/01/29: Re: GAL programming for hobby use...Is there no hope?
    2740: 96/01/31: Re: GAL programming for hobby use...Is there no hope?
    2741: 96/01/31: Re: GAL programming for hobby use...Is there no hope?
    2745: 96/02/01: Re: GAL programming for hobby use...Is there no hope?
    2758: 96/02/02: Re: GAL programming for hobby use...Is there no hope?
Jim E:
    34555: 01/08/29: Re: Urgent Help Needed
    34599: 01/08/30: Re: Urgent Help Needed
    34600: 01/08/30: Re: Urgent Help Needed
Jim English:
    61492: 03/10/05: Re: Spartan 2e implementation
Jim Flanagan:
    58195: 03/07/16: Altera ByteBlaster Standalone Programming Utility
    132934: 08/06/10: Dram Refresh Controller Tutorial wanted
    133030: 08/06/14: Old Mits Dram Datasheet Search
    133430: 08/06/28: Missing the simplest things - Active HDL - Beginners Questions
    136335: 08/11/11: CPLD newbie questions
Jim Frenzel:
    159: 94/09/02: Xilinx and 8.4 -- not!
    176: 94/09/09: Re: Xilinx and 8.4 -- not!
    515: 94/12/16: Industry FPGA Applications?
    1132: 95/05/03: Re: Web/FTP site for FPGA based research
    10727: 98/06/12: XC6000 VHDL models?
    17445: 99/07/28: Partial Reconfiguration?
Jim George:
    64145: 03/12/18: FIR Filter cores for Virtex-][
    64177: 03/12/18: Re: FIR Filter cores for Virtex-][
    64236: 03/12/21: Re: FIR Filter cores for Virtex-][
    76797: 04/12/12: LUT and MUXF5 placement
    76799: 04/12/12: Re: PLLs on biphase mark signals
    76803: 04/12/12: Re: LUT and MUXF5 placement
    76822: 04/12/13: Re: LUT and MUXF5 placement
    77126: 04/12/23: Re: Using low-core-voltage devices in industrial applications
    78498: 05/02/01: Virtex II Slice Design - ARGH!
    78537: 05/02/02: Re: Virtex II Slice Design - ARGH!
    80162: 05/03/02: Suppressing extra XST messages
    80164: 05/03/02: Timing Error large enough to cause problems?
    80165: 05/03/02: Re: Xilinx ISE7.1
    80191: 05/03/02: Re: Xilinx ISE7.1
    80193: 05/03/02: Re: PLL code
    80755: 05/03/10: Re: RPM creation
    80756: 05/03/10: Re: FIR Filter On FPGA
    80757: 05/03/10: Re: low speed FIR filter in FPGA
    80887: 05/03/13: Re: Xilinx ISE and IP cores
    81950: 05/04/05: Re: ISE
    81951: 05/04/05: Re: IBUFG and BUFG +xilinx
    81953: 05/04/05: Re: Stupid question
    82030: 05/04/05: Re: IBUFG and BUFG +xilinx
    82180: 05/04/07: Linux VHDL Simulator
    82822: 05/04/18: Re: LUT in fpga
    83236: 05/04/26: ISE wishlist
    83280: 05/04/26: Re: ISE wishlist
    83403: 05/04/29: Map Error: "RLOC not supported for simple gates"
    83454: 05/04/29: Re: Map Error: "RLOC not supported for simple gates"
    83739: 05/05/05: Re: including components, i.e. SRL16
    84597: 05/05/22: GHDL under x86_64 Linux
    84778: 05/05/26: Async FIFO coregen wizard
    84911: 05/05/31: Re: Magical Mystery Tour of ISE environment variables
    84912: 05/05/31: Re: JTAG Programming Problem
    85583: 05/06/11: Re: computer upgrade time.
    86039: 05/06/20: Re: Xilinx MacFir5.0 - Block Ram requirenments
    86278: 05/06/24: Re: DC Offset removal in FPGA
    86279: 05/06/24: Re: using GUI and batch mode produces different results !
jim granville:
    5059: 97/01/17: Re: ANNOUNCE 8051/8052 microcontroller model now available for FPGA
    5060: 97/01/17: Re: Any PEEL22CV10A replacements with more capacity?
    5256: 97/02/01: Re: Steven K. Knapp - no such article
    5327: 97/02/07: Re: FPGA power dissipation
    5791: 97/03/14: Re: Galileo... Leonardo... Renoir... ?
    6092: 97/04/11: Re: Sole source
    5992: 97/04/02: Re: New Technology
    5999: 97/04/03: Re: 8051 core for XC40xx
    7181: 97/08/11: Re: Price of Serial EPROM is Outrageous - Better Explanation
    7245: 97/08/18: Re: Price of Serial EEPROM is Outrageous
    7259: 97/08/19: Re: ISP Stories
    7267: 97/08/19: Re: Price of Serial EEPROM is Outrageous
    7270: 97/08/20: Re: 89c2051 Price & Capability (was Ourtageous Serial EEPROM $$)
    7276: 97/08/20: Re: ISP Stories
    7451: 97/09/11: SYNC RAM in XCilinx/Altera...
    7491: 97/09/16: Re: Choosing a good pin assignment for multiple-xilinx prototype.
    7509: 97/09/18: Re: 6809 discontinued
    7540: 97/09/19: Re: Atmel 17256 serial config EEPROMs
    7601: 97/09/25: HEX format prom files wanted
    7899: 97/10/28: Re: Counter Problem
    8185: 97/11/26: Re: Need Digital PLL in a Flex 10
    8292: 97/12/06: Re: A suggestion for Xilinx
    8486: 97/12/22: Re: Schmitt Trigger on ISP
    8813: 98/01/28: Re: Opinions wanted on PLD selection
    9023: 98/02/15: Re: Altera 5032 programming problems
    9035: 98/02/17: Re: Why some CPLDS are slow to power-up?
    9037: 98/02/17: Re: Why altera CPLDS are slow to power-up?
    9162: 98/02/26: Re: Altera CPLD power-up procedure?
    9668: 98/03/30: Re: USB bus interface (12 mbit/sec) in an FPGA - how difficult?
    9704: 98/04/01: Re: Digital PLL's or Manual Synching?
    10136: 98/04/29: Re: How to implement a UART use FPGA with less cells.
    10364: 98/05/15: Re: vga gen
    10402: 98/05/16: Re: vga gen
    10844: 98/06/25: Re: Q: I squared C on an FPGA
    11202: 98/07/25: Re: Silicore VHDL 8-bit RISC uC core for FPGA
    11385: 98/08/09: Re: Radiation and Relaibility
    11680: 98/08/31: Re: A Johnson counter
    12080: 98/09/28: Re: A Johnson counter
    12128: 98/10/01: Re: Simple programmable device suggestions please?
    12416: 98/10/12: Re: Need 100MHz Counter with 3 Comparators
    12450: 98/10/13: Re: Digital Sine Generator
    12451: 98/10/13: Re: Processor Cores
    13715: 98/12/20: Re: Fast *Industrial* 22V10?
    13737: 98/12/22: Re: Atmel's PLD
    13738: 98/12/22: Re: Fast *Industrial* 22V10?
    13875: 98/12/31: Re: 22V10 Metastability - help please
    13877: 98/12/31: Re: 22V10 Metastability - help please
    14354: 99/01/27: Re: Hysteresis on PLD Clock Inputs
    14359: 99/01/27: Re: Hysteresis on ALL PLD Inputs
    17149: 99/07/04: Re: FW: Xilinx Acquisition of CoolRunners
    17747: 99/08/30: Re: Smallest Configurator for Xilinx
    17748: 99/08/30: AMD Athlon CPU Speed at Simulates
    18251: 99/10/10: Re: Altera 10K50V in-rush/temp problem...
    19029: 99/11/25: Re: Obselete processor substitutes
    19260: 99/12/09: Re: constraints between clock domains: can't advance
    19620: 00/01/05: Re: Design security
    19689: 00/01/08: Re: Design security
    19713: 00/01/09: Re: Design security
    20778: 00/02/22: Re: Generating a Higher Frequency Clock from a Lower One in FPGA
    20848: 00/02/24: Re: IEC 1131-3 i NEED HELP
    64313: 03/12/28: Re: [Spartan-IIE] Exeeding max. input rise/fall time of signals ??
    64319: 03/12/28: Re: [Spartan-IIE] Exeeding max. input rise/fall time of signals ??
    64614: 04/01/09: Re: spartan 3 sample
    64615: 04/01/09: Re: Anybody know what the REAL story is? Play it again? Sam? Oh
    64647: 04/01/10: Re: min propagation delay in xilinx cpld
    64648: 04/01/10: Re: Large/Fast static RAM
    64817: 04/01/15: Re: ASMBL - hmmm ---- hmmmm -- Wow? -- "Hard-tocopy" rant -- skip
    64818: 04/01/15: Re: translating .jed files to equations
    64847: 04/01/15: Re: Altera Cyclone data is incomplete or messy
    64848: 04/01/15: Re: Gray encoding for FSM
    64956: 04/01/17: Re: Gray encoding for FSM
    65073: 04/01/20: Re: WTD: info on AMD palce22v10
    65127: 04/01/21: Re: BIST FPGA testing - Applying a test vector
    65128: 04/01/21: Re: changing values in a fifo
    65192: 04/01/22: Re: WTD: info on AMD palce22v10
    65193: 04/01/22: Re: Soft failures (?) 9536XL
    65194: 04/01/22: Re: xilinx 70% tracking rule
    65301: 04/01/24: Re: Spirit on Mars, upsets on Earth -- does your vendor know? How?
    65317: 04/01/25: Re: Spirit on Mars, upsets on Earth -- does your vendor know? How?
    65346: 04/01/26: Re: changing values in a fifo
Jim Granville:
    21047: 00/03/04: Re: New name: DLLs, PLLs and videotape...
    21208: 00/03/10: Re: pal design using GAL22V10 and PROTEL
    21514: 00/03/24: SPLD Usage ?
    21629: 00/03/27: Re: Anyone using Philips (now Xilinx) Coolrunner PLDs?
    21648: 00/03/28: Re: FPGA & single point failure
    22194: 00/05/01: Re: How to Prevent theft of FPGA design
    22280: 00/05/04: Re: How to Prevent theft of FPGA design
    22281: 00/05/04: Re: Why are there no "cheap" FPGAs?
    22324: 00/05/05: Re: How to Prevent theft of FPGA design
    22366: 00/05/06: Re: How to Prevent theft of FPGA design
    22417: 00/05/09: Re: How to Prevent theft of FPGA design
    22754: 00/05/23: Re: Xilinx tools
    22883: 00/05/30: Re: Design of Phase-Locked Loop (PLL) - 2 alternatives
    22954: 00/06/06: Re: PLA to ABEL converter?
    22973: 00/06/07: Re: 3.3V I/O TO 5V LOGIC?
    22993: 00/06/08: TTL device Libraries
    23012: 00/06/09: Re: TTL device Libraries
    23021: 00/06/09: Re: TTL device Libraries
    23123: 00/06/15: Re: PAR Times for XILINX Foundation Express Student Edition 1.5
    23234: 00/06/19: Re: Problem copying text from the Spartan II data sheet
    23262: 00/06/20: Re: cpld
    23283: 00/06/21: Re: Problem copying text from the Spartan II data sheet
    23508: 00/06/28: Re: I cant stand it any more.
    23528: 00/06/29: Re: How to do ...?
    23811: 00/07/11: Re: Xilinx buys LavaLogic
    23817: 00/07/11: Re: phase lock different frequencies
    24026: 00/07/24: Re: Q: PAL22V10 JEDEC file-toVHDL translators?
    24526: 00/08/12: OPAL sw ex natsemi ?
    24551: 00/08/14: Re: Virtex 2.5V part with 5V IO problems
    24554: 00/08/14: Re: Virtex 2.5V part with 5V IO problems
    24852: 00/08/21: Re: Metastability measurement
    24863: 00/08/21: Re: Metastability measurement
    24953: 00/08/23: Re: Some notes on metastability
    25095: 00/08/26: Re: Why Aren't Anti-Fuse FPGAs The Biggest FPGAs In The World?
    25124: 00/08/27: Re: Why Aren't Anti-Fuse FPGAs The Biggest FPGAs In The World?
    25133: 00/08/27: Re: Balls!
    25138: 00/08/28: Re: FPGA power pins decoupling <-> PCB autorouting
    25157: 00/08/29: Re: Using a FPGA as I/O expansion on embedded PC ??
    25522: 00/09/13: Re: Clock skew in XILINX CPLD
    25934: 00/09/27: Re: hdl
    25979: 00/09/29: Re: ABEL truth table for 8-1 Mux (The solution)
    26126: 00/10/05: Re: Whoa, Noise on a digital output pin?, and Minor rant on XC9500 S/W, was Re: Simon,Floating Inputs
    26044: 00/10/02: Re: Migrating PAL/TTL design to FPGA
    26069: 00/10/03: Re: Synthesis failures
    26315: 00/10/12: Re: palasm
    26408: 00/10/15: Re: Sinusoidal PWM on Xilinx FPGA
    26451: 00/10/17: Re: Low power cpld?
    26582: 00/10/21: Re: CoolRunner news :(
    26748: 00/10/27: Re: How safe is the algorithm implemented with FPGA?
    26666: 00/10/24: Re: RS422 interfacing to a FPGA ?
    26991: 00/11/07: Re: CoolRunner news :(
    27610: 00/11/30: Re: Xilinx Coolrunner going on last time buy?
    28126: 00/12/22: Re: really fast counter in SpartanXL?
    28144: 00/12/23: Re: Virtex and metastability
    28506: 01/01/16: Re: Virtex-II officially launched
    28705: 01/01/22: Re: xc95108 funny behaviour
    29010: 01/02/02: Re: 64-bit counter @ 200 MHz on FPGA?
    29050: 01/02/04: Re: Encryption is supported in new Virtex II but.....
    29127: 01/02/07: Re: Switching matrix, FPGA or CPLD? -
    29263: 01/02/12: Re: any idea ?
    29531: 01/02/26: Re: cpul vs vhdl
    29591: 01/02/28: Re: cpul vs vhdl
    30146: 01/03/26: Re: No inputs on XC9536XL
    29671: 01/03/05: Re: Metastability, Asynchronous Signals, & Asynchronous design
    29677: 01/03/05: Re: Metastability, Asynchronous Signals, & Asynchronous design
    29710: 01/03/06: Re: Metastability, Asynchronous Signals, & Asynchronous design
    29734: 01/03/07: Re: Parallel Port EPP
    29851: 01/03/14: Re: 64 simultan A/D Converters in an SPARTAN-II
    29859: 01/03/14: Re: 64 simultan A/D Converters in an SPARTAN-II
    30086: 01/03/23: Re: frequency measurement?
    30233: 01/03/29: Re: Recommended Oscillators for DLL's at 25 MHz
    30320: 01/04/03: Re: pseudo random numbers
    30382: 01/04/05: Re: High Speed PLA/FPGA
    30411: 01/04/07: Re: Why FPGA/CPLDs draw a lot current?
    30429: 01/04/08: Re: Why FPGA/CPLDs draw a lot current?
    30491: 01/04/11: Re: Why FPGA/CPLDs draw a lot current?
    30576: 01/04/18: Re: compression
    30603: 01/04/19: Re: compression
    30627: 01/04/20: Re: clocking on both edges
    30656: 01/04/22: Re: WinCUPL still alive?
    31299: 01/05/18: Re: interfacing:keyboard/displays
    31451: 01/05/25: Re: frequency ramp
    31518: 01/05/29: Re: Want to buy: Old copy of ABEL, Synario or ViewPLD
    31543: 01/05/30: Re: Want to buy: Old copy of ABEL, Synario or ViewPLD
    31853: 01/06/07: Re: one state machine
    31899: 01/06/08: Re: Help in FIFO design
    32554: 01/06/30: Re: clock speed in XC95288XL
    32720: 01/07/06: Re: 8031 microcontroller on FPGA development board :-)
    32721: 01/07/06: Re: XC9500 drive capability
    33118: 01/07/18: Re: Working Design - Anyone
    33119: 01/07/18: Re: Coolrunner: availability
    33120: 01/07/18: Re: conditional expression optimization
    33179: 01/07/19: Re: Working Design - Anyone
    33531: 01/07/30: Re: finite defect statistics
    33614: 01/08/01: Re: finite defect statistics
    34003: 01/08/11: Re: Low Cost FPGA or PLD
    34051: 01/08/13: Re: FPGA or CPLD data compression
    34124: 01/08/15: Re: Building a clock out of a PLD
    34139: 01/08/15: Re: Building a clock out of a PLD
    34170: 01/08/16: Re: Building a clock out of a PLD
    34253: 01/08/18: Re: Atmel CPLD - JEDEC to ABEL
    34286: 01/08/19: Re: Atmel CPLD - JEDEC to ABEL
    34338: 01/08/22: Re: protecting pins on xilinx xc95 cpld
    34524: 01/08/29: Re: FPGA : USB in an FPGA, has anyone done it before?
    34547: 01/08/29: Re: Version Control
    34572: 01/08/30: Re: Version Control
    34721: 01/09/05: Re: Clock Multiplication
    34884: 01/09/13: Re: Programming Delays in ABEL
    34917: 01/09/14: Re: configuration latency for PCI bridge in FPGA
    35090: 01/09/21: Re: Maximum clock rate of various Xilinx families?
    35095: 01/09/21: Re: Maximum clock rate of various Xilinx families?
    35146: 01/09/24: Re: Clockin on rising AND falling edge
    35506: 01/10/09: Re: ROM based FSMs
    35567: 01/10/11: Re: Synplicity/Leonardo License Agreement Information
    35674: 01/10/13: Re: Lattice discontinues all smaller MACH circuits and other devices
    35766: 01/10/17: Re: LUT Glitches
    35793: 01/10/18: Re: Recommended Newsgroup
    35914: 01/10/24: Re: Are there any Coolrunner P5Z22V10 (PLCC) devices left anywhere?
    35957: 01/10/25: Re: CPLD with built-in oscillator?
    36001: 01/10/26: Re: GAL compiler
    36002: 01/10/26: Re: GAL compiler
    36378: 01/11/08: Re: Quadrature Encoder Sampling Time
    36510: 01/11/10: Re: 18V8Z and Philips SNAP compiler
    36542: 01/11/12: Re: Quadrature Encoder Sampling Time
    36676: 01/11/15: Re: High Speed PWM?
    36973: 01/11/28: Re: Creating a jitter free clock
    37021: 01/11/29: Re: Creating a jitter free clock
    37040: 01/11/29: Re: maximum output current on Spartan2
    37051: 01/11/29: Re: maximum output current on Spartan2
    37105: 01/11/30: Re: FPGA startup current
    37464: 01/12/12: Re: ISP by JTAG using a microcontroller
    37504: 01/12/13: Re: Initialization of RAM
    37653: 01/12/19: Re: ISP by JTAG using a microcontroller
    37807: 01/12/21: Re: Best-case timing?
    37823: 01/12/21: Re: annoying problem and "simple and clever solution"
    38121: 02/01/06: Re: Suitability of Atmel for project?
    38131: 02/01/07: Re: Suitability of Atmel for project?
    38162: 02/01/08: Re: Suitability of Atmel for project?
    38296: 02/01/11: Re: EXPAL language ?
    38397: 02/01/14: Re: Homebrew computers using FPGA?
    38603: 02/01/19: Re: Audio time delay circuit
    38955: 02/01/29: Re: FPGA or Micro-controller in Lowpower designs?
    38957: 02/01/29: Re: Xilinx webpack
    38960: 02/01/29: Re: Xilinx webpack
    38963: 02/01/29: Soft errors climb in 0,13u SRAM
    39001: 02/01/30: Re: The LUT puzzle, Iam on the way
    39054: 02/01/31: Re: FPGA or Micro-controller in Lowpower designs?
    39065: 02/01/31: Re: The LUT puzzle, Iam on the way
    39168: 02/02/03: Re: LARGE ultra low power FPGA/CPLD recommendation
    39230: 02/02/05: Re: Destroying a CPLD by JTAG
    39231: 02/02/05: Re: Destroying a CPLD by JTAG
    39244: 02/02/05: Re: FPGA or Micro-controller in Lowpower designs?
    39245: 02/02/05: Re: LARGE ultra low power FPGA/CPLD recommendation
    39306: 02/02/06: Re: Programming Altera PGAs.
    39458: 02/02/11: Re: Multiple clock domein synchronization.
    39585: 02/02/14: Re: Atmel CPLD chip design software?
    39624: 02/02/15: Re: Lean serial communication processor
    39790: 02/02/20: Re: Few pins but more gates
    39905: 02/02/22: Re: Need largest CPLD devices?
    39910: 02/02/22: Re: Coolrunner and ISP
    39964: 02/02/23: Re: Coolrunner and ISP
    39986: 02/02/23: Re: Coolrunner and ISP
    39998: 02/02/24: Re: Coolrunner and ISP
    40107: 02/02/28: Re: PAL to JEDEC convertor
    40204: 02/03/02: Re: Beginner Altera Questions
    40257: 02/03/04: Re: max3000a odd behavior -- is the bug in my vhdl code? help!
    40287: 02/03/05: Re: max3000a odd behavior -- is the bug in my vhdl code? help!
    40345: 02/03/06: Re: digital video PLL
    40413: 02/03/07: Re: FPGA or DSP in a power supply?
    40432: 02/03/07: Re: high active and low active reset signal mixed in a design
    40437: 02/03/07: Re: FPGA or DSP in a power supply?
    40493: 02/03/08: Re: Converting old Mach 5 project from DSL to VHDL
    40587: 02/03/12: Re: Newbie choosing a language - Verilog, VHDL, or ABEL
    40635: 02/03/12: Re: Mystery two wire interface, or am I being dense?
    40761: 02/03/15: Re: Newbie choosing a language - Verilog, VHDL, or ABEL/CUPL
    41109: 02/03/21: Re: FPGA or Micro-controller in Lowpower designs?
    41219: 02/03/23: Re: Poor availability problems on Coolrunner
    41236: 02/03/23: Re: Poor availability problems on Coolrunner
    41373: 02/03/27: Re: Help with Xilinx CoolRunner Problem
    41374: 02/03/27: Re: clock multiplier
    41416: 02/03/28: Re: I2C complexity
    41627: 02/04/04: Re: powerpc in virtex2pro
    41677: 02/04/05: Re: hand placement
    41725: 02/04/06: Re: Help: Design a crystal oscillator in a Xilinx XCR3256XL
    41736: 02/04/06: Re: 32 bit accumulator/comparator PWM?
    41773: 02/04/08: Re: 32 bit accumulator/comparator PWM?
    41777: 02/04/08: Re: 32 bit accumulator/comparator PWM?
    41814: 02/04/09: Re: 32 bit accumulator/comparator PWM?
    42062: 02/04/15: Re: FPGA config without boot PROM???
    42144: 02/04/17: Re: Synario v2.3
    42231: 02/04/19: Re: 8051 Core for Motor Electronics
    42476: 02/04/25: Re: Using PAL/GAL/FPGA to replace CPU's (correct news group?)
    42507: 02/04/26: Re: Using PAL/GAL/FPGA to replace CPU's (correct news group?)
    42517: 02/04/26: Re: Xilinx Easypath- Selling parts with known defects
    42546: 02/04/27: Re: 8051 Core for Motor Electronics
    42573: 02/04/28: Re: SpartanII design considerations...
    42577: 02/04/28: Re: SpartanII design considerations...
    42672: 02/05/01: Re: Xilinx Easypath- Selling parts with known defects
    42674: 02/05/01: Re: power supply sequencer for Virtex II
    42681: 02/05/01: Re: power supply sequencer for Virtex II
    42682: 02/05/01: Re: Xilinx Easypath- Selling parts with known defects
    42794: 02/05/03: Re: simultaneous switching of LVPECL outputs
    42795: 02/05/03: Re: Frequency synthesiser
    42797: 02/05/03: Re: simultaneous switching of LVPECL outputs
    42868: 02/05/06: Re: Frequency synthesiser
    42911: 02/05/07: Re: max 7000
    42988: 02/05/09: Re: OP-AMP in FPGA
    42996: 02/05/09: Re: More C things
    43053: 02/05/11: Re: altera 7000's
    43088: 02/05/14: Re: Architecture for high-level reconfigurable computing
    43100: 02/05/14: Re: Architecture for high-level reconfigurable computing
    43147: 02/05/15: Re: Architecture for high-level reconfigurable computing
    43154: 02/05/15: Re: Architecture for high-level reconfigurable computing
    43161: 02/05/15: Re: Frequency synthesiser
    43187: 02/05/16: Re: Architecture for high-level reconfigurable computing
    43287: 02/05/18: Re: Building a relaxation oscillator with a Xilinx 9536XL
    43320: 02/05/19: Re: HardPath
    43383: 02/05/21: Re: Using Impact with XCR5064 coolrunner?
    43394: 02/05/21: Re: Spartan2 on a Compact Flash card
    43408: 02/05/21: Re: fpga cpu
    43463: 02/05/22: Re: What properties has FPGA?
    43467: 02/05/22: Re: XST since ISE 4.x can actually generate an EDIF netlist!!!
    43484: 02/05/22: Re: What properties has FPGA?
    43653: 02/05/29: Re: Frequency synthesiser
    43661: 02/05/29: Re: Frequency synthesiser
    43779: 02/06/03: Re: Clock double trigger problem
    43825: 02/06/04: Re: divide by 5
    44011: 02/06/10: Re: Do you know a e-mail list where I can make questions about Handel-C?
    44092: 02/06/12: Re: fpga and ultra highspeed counters
    44112: 02/06/12: Re: Searching for high performance PLD
    44162: 02/06/13: Re: Searching for high performance PLD
    44204: 02/06/14: Re: Power supply caps on PCB
    44213: 02/06/14: Re: Power supply caps on PCB
    44324: 02/06/18: Re: Internal oscillator in CPLD?
    44337: 02/06/18: Re: Seeking CPLD/FPGA recomendation
    44378: 02/06/19: Re: Seeking CPLD/FPGA recomendation
    44428: 02/06/20: Re: ATMEL CPLD
    44520: 02/06/22: Re: Logic Minimization in Max+Plus II compiler
    44545: 02/06/23: Re: Xilinx's 4.1i's Lastest webpack
    44575: 02/06/24: Re: [Newbie] Help with 20L8 PAL
    44679: 02/06/27: Re: 5V tolerance
    44705: 02/06/28: Re: 32KHz oscilator in CPLD
    44748: 02/06/29: Re: State machine and syncronous inputs
    44752: 02/06/29: Re: Altera equivalent for GAL 16V8
    44779: 02/07/01: Re: Timed Licenses and version control ( was 5V tolerance )
    44857: 02/07/03: Re: Converting to Altera Quartus
    44864: 02/07/03: Re: Converting to Altera Quartus
    44921: 02/07/06: Re: Xpower accuracy (is there anybody from Xilinx out there ?)
    44939: 02/07/07: Re: Converting to Altera Quartus
    44977: 02/07/09: Re: Are these design guideline safe ?
    45382: 02/07/22: Re: TMS 1000
    45462: 02/07/24: Re: Field Programmable SoC's
    45507: 02/07/25: Re: 8bit Magnitude Comparator
    45513: 02/07/25: Re: Another way to simulate
    45587: 02/07/28: Re: can 555 be used as clock input to cplds
    45709: 02/08/02: Re: Safe design speed
    45823: 02/08/07: Re: CUPL S/N?
    45857: 02/08/08: Re: CUPL S/N?
    45930: 02/08/12: Re: articles about FPGA based DSP design
    46131: 02/08/20: Re: "flip flop" and "register"
    46139: 02/08/20: Re: Good documentation on CPLD
    46214: 02/08/22: Re: I2C License
    46227: 02/08/22: Re: to reduce the circuit design
    46357: 02/08/27: Re: Anyone already on QUARTUS II V2.1 ?
    46383: 02/08/28: Re: Any FSM optimizer?
    46388: 02/08/28: Re: Any FSM optimizer?
    46408: 02/08/29: Re: Any FSM optimizer?
    46414: 02/08/29: Re: WebPack FSM woes...
    46540: 02/09/03: Re: C/C++ to Verilog/VHDL ?!
    46544: 02/09/03: Re: Actel Proto Boards
    46651: 02/09/05: Re: What's wrong with clearLogic?
    46652: 02/09/05: Re: What's wrong with clearLogic?
    46695: 02/09/06: Re: question about quiescent current
    46782: 02/09/09: Re: Metastability numbers
    46783: 02/09/09: Re: Metastability numbers, even better!
    46789: 02/09/09: Re: Metastability numbers
    46815: 02/09/10: Re: XCR3384XL availability
    46820: 02/09/10: Re: Metastability numbers
    46823: 02/09/10: Re: Altera Stratix DSP Performance
    46830: 02/09/10: Re: Are Xilinx CoolRunners / Atmel ATF15xx CPLD's flash-based?
    46835: 02/09/10: Re: XCR3384XL availability
    46842: 02/09/10: Re: XCR3384XL availability
    46851: 02/09/10: Re: 555 schematic or vhdl for xilinx or other clock circuit ?
    46889: 02/09/11: Re: XCR3384XL availability
    46892: 02/09/11: Re: C/C++ to Verilog/VHDL ?!
    46894: 02/09/11: Re: FPGA comes with a DAC?
    46895: 02/09/11: Re: XCR3384XL availability
    46916: 02/09/12: Re: atmel CPLD documentation
    46950: 02/09/13: Re: QUARTUS II V2.1 LINUX (C) ALTERA
    46994: 02/09/14: Re: 2-D resistor array
    47001: 02/09/14: Re: 2-D resistor array
    47025: 02/09/15: Re: Clcok divison : Rational clock divider
    47046: 02/09/16: Re: 1.8V regulator needed for Spartan IIE
    47071: 02/09/17: Re: Virtex II packaging, why no QFP?
    47138: 02/09/19: Re: using CPLD's inverter in oscillator circuit
    47267: 02/09/22: Re: external switch to CPLD input
    47274: 02/09/22: Re: Can a fpga replace external inverters in a crystal osc ?
    47321: 02/09/24: Re: external switch to CPLD input
    47337: 02/09/24: Re: querries regarding cpld
    47341: 02/09/24: Re: upcoming trened: analogue Fpga's?
    47360: 02/09/25: Re: FPGA fail when Electrostatic discharge Occurs
    47377: 02/09/25: Re: Altera Cyclone low-cost FPGA chips?
    47397: 02/09/25: Re: Altera Cyclone low-cost FPGA chips?
    47409: 02/09/25: Re: FPGA fail when Electrostatic discharge Occurs
    47491: 02/09/27: Re: CPCNG project : website updated
    47503: 02/09/27: Re: Is it possible to build a Ring Oscillator in an FPGA chip?
    47511: 02/09/27: Re: Is it possible to build a Ring Oscillator in an FPGA chip?
    47660: 02/10/02: Re: USB2 in FPGA?
    47685: 02/10/02: Re: Implementing Delta-Sigma ADC and DAC in Spartan IIE
    47770: 02/10/04: Re: Need advice wiring up a CPLD
    47771: 02/10/04: Re: ANN: Embedded processor for Tcl language
    47865: 02/10/06: Re: DDS in PLD?
    47877: 02/10/07: Re: Implementing Delta-Sigma ADC and DAC in Spartan IIE
    48045: 02/10/10: Re: Why can Xilinx sw be as good as Altera's sw?
    48089: 02/10/11: Re: Why can Xilinx sw be as good as Altera's sw?
    48237: 02/10/15: Re: Why can Xilinx sw be as good as Altera's sw?
    48302: 02/10/16: Re: xilinx: VirtexII in a pqfp208 or pqfp240 ?
    48360: 02/10/17: Re: Xilinx microblaze vs. picoblaze
    48529: 02/10/19: Re: FPGA breadboard with a SmartMedia Card to store the bit file.
    48560: 02/10/21: Re: 6502 core available
    48673: 02/10/23: Re: slow slew rate signal...
    48702: 02/10/23: Re: LCD driver implement with FPGA
    48749: 02/10/24: Re: slow slew rate signal...
    48753: 02/10/24: Re: How do I measure power consumption?
    48804: 02/10/25: Re: Xilinx POS Power On Surge Current
    48923: 02/10/27: Re: cpld I/O modes
    49060: 02/10/31: Chip for fine delays
    49097: 02/11/01: Re: Concepts: What is "Clock Edge"?
    49104: 02/11/01: Re: Concepts: What is "Clock Edge"?
    49106: 02/11/01: Re: XC18VXX PROM Corruption
    49112: 02/11/01: Re: XC18VXX PROM Corruption
    49120: 02/11/01: Re: Metastability results are finally posted
    49148: 02/11/02: Re: XC18VXX PROM Corruption
    49191: 02/11/05: Re: C\C++ to HDL Converter, why not HDL -> C instead
    49392: 02/11/12: Re: Silly FPGA Arch question...
    49462: 02/11/13: Re: jedec
    49610: 02/11/18: Re: CoolBlaze and PicoBlaze
    49648: 02/11/19: Re: Metastability in FPGAs
    49650: 02/11/19: Re: Metastability in FPGAs
    49662: 02/11/19: Re: Metastability in FPGAs
    49688: 02/11/19: Re: Metastability in FPGAs
    49844: 02/11/22: Re: Metastability in FPGAs
    49931: 02/11/26: Re: How do I measure power consumption?
    49971: 02/11/27: Re: count based Frequency generator
    49995: 02/11/28: Re: count based Frequency generator
    49997: 02/11/28: Re: count based Frequency generator
    50112: 02/12/03: Re: ESD problems
    50148: 02/12/04: Re: ISA bus VGA
    50166: 02/12/04: Re: ESD problems
    50196: 02/12/05: Re: ESD problems
    50326: 02/12/09: Re: Pierce Crystal Oscillator in Cypress 37128 CPLD
    50450: 02/12/11: Re: Tiny Forth Processors
    50481: 02/12/12: Re: Tiny Forth Processors
    50499: 02/12/12: Re: Power consumption question
    50507: 02/12/12: Re: Power consumption question
    50585: 02/12/13: Re: JVM/.NET on FPGA (was Tiny Forth Processors)
    50659: 02/12/16: Re: what makes an implementation a patent?
    50746: 02/12/19: Re: A/D converter in FPGA
    50748: 02/12/19: Re: How to asynchronously reset a flip-flop?
    50758: 02/12/19: Re: A/D converter in FPGA
    50798: 02/12/20: Re: A/D converter in FPGA
    50801: 02/12/20: Re: Async RAM on an FPGA board
    50890: 02/12/22: Re: Xmas Wish Lists ( was stupid rookie timing question )
    50902: 02/12/23: Re: thermal issues on FPGA
    51066: 02/12/30: Re: thermal issues on FPGA
    51100: 03/01/01: Re: shift register implementation
    51236: 03/01/08: Re: Co-simulation of Spice and Vhdl
    51286: 03/01/10: Re: conversions and some assistance please
    51289: 03/01/10: Re: Virtex-II Pro misfire?
    51326: 03/01/11: Re: Virtex-II Pro misfire?
    51327: 03/01/11: Re: Virtex-II Pro misfire?
    51332: 03/01/11: Re: Virtex-II Pro misfire?
    51335: 03/01/11: Re: Virtex-II Pro misfire?
    51355: 03/01/12: Re: Help for Generating Video Clock synchronous to Hsync of the Video..........
    51511: 03/01/15: Re: Open FPGA please!
    51528: 03/01/16: Re: Open FPGA please!
    52005: 03/01/29: Re: frequency matching of ring oscillators
    52172: 03/02/04: Re: Voltage Creep ( was 3.3 Volt tolerance in Virtex II Pro...)
    52532: 03/02/13: Re: Coolrunner II I/O speeds?
    52563: 03/02/14: Re: Coolrunner II I/O speeds?
    52698: 03/02/20: Re: ABEL Help!
    52858: 03/02/25: Re: FPGA's at High Temperatures
    52950: 03/02/27: Re: configuring xilinx fpga with nand flash
    53176: 03/03/06: Re: EP310
    53265: 03/03/09: Re: Implementation of latch in FPGA
    53317: 03/03/11: Re: Altera Clock
    53350: 03/03/12: Re: Cyclone power up problem
    53367: 03/03/12: Re: Cyclone power up problem
    53391: 03/03/13: Re: Cyclone power up problem
    53393: 03/03/13: Re: Cyclone power up problem
    53412: 03/03/13: Re: Cyclone power up problem
    53450: 03/03/14: Re: Cyclone power up problem
    53546: 03/03/16: Re: Cyclone power up problem - Summery
    53552: 03/03/16: Re: Cyclone power up problem - Summery
    53603: 03/03/18: Re: Help understanding 7408 and gate chip
    53606: 03/03/18: Re: Cheapest Spartan II/IIE configuration flash EEPROM!
    53613: 03/03/18: Re: new XC95xx global clock
    53637: 03/03/19: Re: Low Power CPLD suggestion request...
    53730: 03/03/21: Re: Altera ACEX 1K
    53933: 03/03/28: Re: Differential LVPECL Inteface of Spartan IIE
    53945: 03/03/28: Re: Differential LVPECL Inteface of Spartan IIE
    54040: 03/04/01: Re: Xilinx announces 90nm sampling today!
    54041: 03/04/01: Re: What would it take?
    54051: 03/04/01: Re: What would it take?
    54302: 03/04/08: Re: Coolrunner 2 's 16 pins output effect
    54311: 03/04/08: Re: Spartan-3 in docsan Webpack release notes... a joke???
    54606: 03/04/15: Re: 2.5V switching regulator for Spartan 2
    54673: 03/04/16: Re: request for simple UART
    54733: 03/04/17: Re: 2.5V switching regulator for Spartan 2
    54907: 03/04/22: Re: Boycott All Xilinx products untill they correct all ISE software errors
    54908: 03/04/22: Re: Very low pin count FPGA
    54998: 03/04/24: Re: Very low pin count FPGA
    55114: 03/04/28: Re: Low pin count SOC
    55174: 03/04/30: Re: Low pin count SOC
    55222: 03/05/01: Re: Low power, high temperature CPLD
    55227: 03/05/01: Re: Low power, high temperature CPLD
    55230: 03/05/01: Re: Low power, high temperature CPLD
    55273: 03/05/02: Thermal Data for Logic Devices
    55274: 03/05/02: Re: Low power, high temperature CPLD
    55293: 03/05/03: Re: Thermal Data for Logic Devices
    55343: 03/05/05: Re: PLL chips
    55399: 03/05/07: Re: I want a 800 k gates FPGA in 40 pin DIL
    55411: 03/05/07: Re: PLL chips
    55435: 03/05/08: Re: I want a 800 k gates FPGA in 40 pin DIL
    55465: 03/05/09: Re: Price of CPLDs
    55488: 03/05/10: Re: Price of CPLDs
    55570: 03/05/13: Re: Atmel, just another case of bad support?
    55577: 03/05/13: Re: Atmel, just another case of bad support?
    55643: 03/05/15: Re: how to calculate the gate count required for a FPGA design
    55644: 03/05/15: Re: OK I am pissed off with Xilinx webpack.
    55684: 03/05/16: Re: Low power, high temperature CPLD
    55685: 03/05/16: Re: CollRunner-II EVB problems
    55696: 03/05/16: Re: Low power, high temperature CPLD
    55699: 03/05/16: Re: smallest embedded cpu.
    55862: 03/05/22: Re: Asynchronous State Machines and HDLs
    56003: 03/05/27: Re: Why is there a large gulf between CPLD and FPGA?
    56009: 03/05/27: Re: Why is there a large gulf between CPLD and FPGA?
    56040: 03/05/28: Re: Why is there a large gulf between CPLD and FPGA?
    56100: 03/05/29: Re: FIFO Controller
    56101: 03/05/29: Re: 5v TTL to 3.3v 2.5v 1.8v 1.2v LVTTL solution
    56164: 03/05/30: Re: New version,Low Speed
    56166: 03/05/30: Re: FIFO Controller
    56167: 03/05/30: Re: FIFO Controller
    56169: 03/05/30: Re: smallest embedded cpu....and the most pain?
    56170: 03/05/30: Re: FPGA's an Flash
    56193: 03/05/30: Re: smallest embedded cpu....and the most pain?
    56104: 03/05/29: Re: 5v TTL to 3.3v 2.5v 1.8v 1.2v LVTTL solution
    56307: 03/06/03: Re: FPGA's an Flash
    56308: 03/06/03: Re: FPGA's an Flash
    56309: 03/06/03: Re: New version,Low Speed
    56424: 03/06/05: Re: FPGA's an Flash
    56567: 03/06/10: Re: Controlling FPGA speed with VCCINT
    56575: 03/06/10: Re: Balls! (676 of them)
    56648: 03/06/11: Re: Controlling FPGA speed with VCCINT
    56650: 03/06/11: Re: Cheap development tools
    56708: 03/06/12: Re: DVI with a Virtex-II - summary
    56733: 03/06/13: Re: Analog signals connected to xilinx spartan2
    56739: 03/06/13: Re: How to Capture a VGA display EXTERNALLY
    56777: 03/06/15: Re: Power consumed in a non configured FPGA?
    56823: 03/06/17: Re: Power consumed in a non configured FPGA?
    56829: 03/06/17: Re: An All Digital Phase Lock Loop
    56909: 03/06/19: Re: FPGA to Custom ASIC ??
    56910: 03/06/19: Re: Cyclone vs. Acex consumption?
    56931: 03/06/19: Re: Power consumed in a non configured FPGA?
    56967: 03/06/20: Re: Dr. Leaky responds
    57107: 03/06/24: Re: Programmable Delay (not clock driven)
    57108: 03/06/24: Re: Q: regarding I2C protocols
    57171: 03/06/25: Re: PALs, GALs and ABEL
    57219: 03/06/26: Re: GAL16V8 reverse compilation
    57284: 03/06/27: Re: Xilinx Webpack bugs bugs bugs
    57288: 03/06/27: Re: Free PAL synth tools (ABEL, PALASM, VHDL, etc.)?
    57292: 03/06/27: Re: Low-power FPGA
    57294: 03/06/27: Re: Abel et al Flows
    57372: 03/06/29: Re: why so many problems Xilinx ?
    57373: 03/06/29: Re: why so many problems Xilinx ?
    57380: 03/06/29: Re: why so many problems Xilinx ?
    57381: 03/06/29: Re: why so many problems Xilinx ?
    57382: 03/06/29: Re: Xilinx Webpack bugs bugs bugs
    57384: 03/06/29: Re: why so many problems Xilinx ?
    57521: 03/07/02: Re: Cyclone vs Spartan-3
    57596: 03/07/03: Re: Xilinx ISE drops support for more parts
    57613: 03/07/03: Re: XPLA3 vs. MAX3000A
    57692: 03/07/04: Re: XPLA3 vs. MAX3000A
    57693: 03/07/04: Re: XPLA3 vs. MAX3000A
    57734: 03/07/05: Re: XPLA3 vs. MAX3000A
    57754: 03/07/06: Re: XPLA3 vs. MAX3000A
    57758: 03/07/06: Re: XPLA3 vs. MAX3000A
    57769: 03/07/07: Re: What About CPLD Standardization ?
    57815: 03/07/08: Re: XPLA3 vs. MAX3000A
    57872: 03/07/09: Re: phase noise in NCO
    58281: 03/07/19: Re: Graduation Day: My first 4-layer PCB
    58321: 03/07/21: Re: Phase / frequency detector types
    58494: 03/07/25: Re: Pricing question....
    58898: 03/08/04: Re: 5 volt tolerant Xilinx parts
    58994: 03/08/06: Re: Design fits XC9536 but not XC9536XL
    59002: 03/08/06: Re: 'Virtual Grounds'
    59029: 03/08/07: Re: Design fits XC9536 but not XC9536XL
    59081: 03/08/08: Re: Patent granted for "system on a chip" framework?
    59090: 03/08/08: Re: Size does matter
    59194: 03/08/12: Re: Upgrading OS or WebPack
    59454: 03/08/20: Re: 22V10, ABEL & Current Design Tools?
    59502: 03/08/21: Re: 22V10, ABEL & Current Design Tools?
    59503: 03/08/21: Re: 22V10, ABEL & Current Design Tools?
    59504: 03/08/21: Re: Legacy 4005 series and current Xilinx ISE offerings?
    59506: 03/08/21: Re: Xilinx XC3000 with Xilinx ISE student edition 4.2i
    59531: 03/08/21: Re: 22V10, ABEL & Current Design Tools?
    59533: 03/08/21: Re: Legacy 4005 series and current Xilinx ISE offerings?
    59569: 03/08/22: Re: 22V10, ABEL & Current Design Tools?
    59570: 03/08/22: Re: 22V10, ABEL & Current Design Tools?
    59669: 03/08/26: Re: Thinking out loud about metastability
    59725: 03/08/27: Re: Thinking out loud about metastability
    59819: 03/08/29: Re: Thinking out loud about metastability
    59904: 03/09/01: Re: Thinking out loud about metastability
    60041: 03/09/04: Re: Measuring metastability.
    60088: 03/09/05: Re: New to FPGA, seeking advice
    60196: 03/09/08: Re: CMOS camera w/ USB2 -- crazy?
    60288: 03/09/10: Re: opinions are OK
    60331: 03/09/11: Re: Metatstable Modeling
    60334: 03/09/11: Re: Embedded/Microcontroller FPGA and Software Defined Radio
    60351: 03/09/11: Re: Metatstable Modeling
    60376: 03/09/12: Re: Metatstable Modeling
    60401: 03/09/12: Re: Metatstable Modeling
    60527: 03/09/16: Re: Original (5V) Xilinx Spartan ? ( Philip ? )
    60633: 03/09/18: Re: opinions are OK
    60724: 03/09/20: Re: Some question about using FPGA
    60725: 03/09/20: Re: opinions are OK
    60924: 03/09/25: Re: ISE 6.1 and Redhat 9
    61319: 03/10/02: Re: Ask the hotline, you may be surprised and pleased
    61409: 03/10/03: Re: CUPL documentation?
    61411: 03/10/03: Re: Ask the hotline, you may be surprised and pleased
    61468: 03/10/05: Re: Interesting article about FPGAs
    61488: 03/10/06: Re: Interesting article about FPGAs
    61886: 03/10/15: Re: Electronic Dice ( 3 die ) In VHDL
    61889: 03/10/15: Re: FPGA/CPLD With Analog Functions?
    61890: 03/10/15: Re: Pass transistor logic in a FPGA
    61898: 03/10/15: Re: SpartanXL
    61900: 03/10/15: Re: How to program an XC5210
    61908: 03/10/15: Re: Electronic Dice ( 3 die ) In VHDL
    61967: 03/10/16: Re: SpartanXL
    61968: 03/10/16: Re: Electronic Dice ( 3 die ) In VHDL
    61969: 03/10/16: Re: Power on problems
    61971: 03/10/16: Re: FPGA/CPLD With Analog Functions?
    62019: 03/10/17: Re: wincupl, winsim documentation?
    62021: 03/10/17: Re: Electronic Dice ( 3 die ) In VHDL
    62022: 03/10/17: Re: SpartanXL
    62033: 03/10/17: Re: Spartan-3 non-ES availability, and misleading pricing info
    62197: 03/10/22: Re: 74 logic to CPLD. how easy for a Newbie?
    62393: 03/10/29: Re: Electronic Dice VHDL Program
    62398: 03/10/29: Re: Are clock and divided clock synchronous?
    62595: 03/11/03: Re: Minimalist RS232 on Cyclone
    62815: 03/11/08: 0.13u device with 5V I/O
    62828: 03/11/09: Re: 0.13u device with 5V I/O
    62851: 03/11/11: Re: 0.13u device with 5V I/O
    62880: 03/11/11: Re: 0.13u device with 5V I/O
    62881: 03/11/11: Re: Home grown CPU core legal?
    62955: 03/11/12: Re: Implementing a very fast counterin VirtexII
    62960: 03/11/12: Re: Implementing a very fast counterin VirtexII
    62965: 03/11/12: Re: Home grown CPU core legal?
    62972: 03/11/12: Re: Home grown CPU core legal?
    62973: 03/11/12: Re: Home grown CPU core legal?
    63077: 03/11/14: Re: Frequency Doubler - VHDL/Verilog
    63193: 03/11/18: Re: Do I need to connect all Vref in a bank together?
    63259: 03/11/19: Re: Do I need to connect all Vref in a bank together?
    63265: 03/11/19: Re: Thank you all for the replays.
    63333: 03/11/20: Re: Small PLD choices
    63334: 03/11/20: Re: Anyone use HDL as design tool for PCBs?
    63340: 03/11/20: Re: State Machines....
    63398: 03/11/21: Re: State Machines....
    63423: 03/11/21: Re: Xilinx legacy situation
    63516: 03/11/25: Re: Reconstructing source code from JED file
    63520: 03/11/25: 5V I/O with 1.8V Core
    63526: 03/11/25: Re: 5V I/O with 1.8V Core
    63541: 03/11/25: Re: Slightly unmatched UART frequencies
    63572: 03/11/26: Re: Slightly unmatched UART frequencies
    63573: 03/11/26: Re: 5V I/O with 1.8V Core
    63578: 03/11/26: Re: 5V I/O with 1.8V Core
    63581: 03/11/26: Re: 5V I/O with 1.8V Core
    63626: 03/11/27: Re: 5V I/O with 1.8V Core
    63671: 03/11/28: Re: 5V I/O with 1.8V Core
    63696: 03/12/01: Re: Slightly unmatched UART frequencies
    63702: 03/12/01: Re: XC9500 design does not fit into Coolrunner
    63942: 03/12/10: ASMBL - hmmm
    63948: 03/12/10: Re: ASMBL - hmmm ---- hmmmm -- Wow?
    63952: 03/12/10: Re: ASMBL - hmmm ---- hmmmm -- Wow?
    63981: 03/12/11: Re: ASMBL - hmmm ---- hmmmm -- Wow?
    64125: 03/12/18: Re: What is this ASMBL thing from Xilinx?
    64166: 03/12/19: Re: www.fpga-faq.com
    65405: 04/01/28: Re: FPGA Config Readback while run, gotchas etc
    65536: 04/02/02: Re: Differences between Xilinx ISE and Altera Quartus software
    65579: 04/02/03: Re: ASMBL
    65582: 04/02/03: Re: ASMBL anxiety
    65635: 04/02/04: Re: Stratix II NIOS sizes ?
    65636: 04/02/04: Re: Is it possible that a Virtex II device performs below its spec?
    65847: 04/02/08: Re: Pricing, 101, and sales seeding, and designers' radar modifiers...
    65848: 04/02/08: Re: Stratix II NIOS sizes ?
    65987: 04/02/11: Re: Pricing, 101
    66044: 04/02/12: Re: negative hold time (Typ/max)
    66045: 04/02/12: Re: Pricing, 101
    66055: 04/02/12: Re: negative hold time (Typ/max)
    66115: 04/02/13: Re: negative hold time
    66116: 04/02/13: Re: Peter's 1Hz-640MHz Synth project
    66123: 04/02/13: Re: Peter's 1Hz-640MHz Synth project
    66134: 04/02/13: Re: Peter's 1Hz-640MHz Synth project
    66138: 04/02/13: Re: Peter's 1Hz-640MHz Synth project
    66140: 04/02/13: Re: Peter's 1Hz-640MHz Synth project
    66197: 04/02/14: Re: Peter's 1Hz-640MHz Synth project
    66198: 04/02/14: Re: Pricing, 101
    66255: 04/02/16: Re: Dual-stack (Forth) processors
    66289: 04/02/17: Re: 74ls193 in coolrunner
    66297: 04/02/17: Re: 74ls193 in coolrunner
    66440: 04/02/20: Re: Can FPGA bootstrap itself?
    66566: 04/02/23: Re: Spartan 3 - avaliable in small quantities?
    66594: 04/02/24: Re: Spartan 3 - avaliable in small quantities?
    66598: 04/02/24: Re: Dual-stack (Forth) processors
    66603: 04/02/24: Re: Spartan 3 - avaliable in small quantities?
    66712: 04/02/26: Re: Basic jitter from a CPLD (XC7500XL)
    66730: 04/02/26: Re: Stratix 2 / MAX II
    66790: 04/02/27: Re: Altera ACEX chip wide reset
    66793: 04/02/27: Re: Basic jitter from a CPLD (XC7500XL)
    66803: 04/02/27: Re: Basic jitter from a CPLD (XC7500XL)
    66995: 04/03/03: Re: Need to speed up Stratix compiles.
    67015: 04/03/04: Re: Need to speed up Stratix compiles.
    67128: 04/03/06: Re: PWM, PLD programming ,(up/down ramp frequency)
    67139: 04/03/06: Re: PWM, PLD programming ,(up/down ramp frequency)
    67173: 04/03/08: lattice metastable info
    67175: 04/03/08: Re: Release asynchrounous resets synchronously
    67180: 04/03/08: Re: Release asynchrounous resets synchronously
    67212: 04/03/09: Re: NEWS: Xilinx announces acquisition of Triscend
    67213: 04/03/09: Re: NEWS: Xilinx announces acquisition of Triscend
    67214: 04/03/09: Re: HOW to Increase jitter in ALTERA PLL ?
    67216: 04/03/09: Re: Release asynchrounous resets synchronously
    67221: 04/03/09: Re: Release asynchrounous resets synchronously
    67293: 04/03/10: Re: HOW to Increase jitter in ALTERA PLL ?
    67294: 04/03/10: Re: Release asynchrounous resets synchronously
    67367: 04/03/11: Re: copy protection on FPGA using embedded serial number
    67492: 04/03/13: Re: PWM, PLD programming ,(up/down ramp frequency)
    67511: 04/03/13: Re: PWM, PLD programming ,(up/down ramp frequency)
    67512: 04/03/13: Re: PWM, PLD programming ,(up/down ramp frequency)
    67543: 04/03/14: Re: PWM, PLD programming ,(up/down ramp frequency)
    67607: 04/03/16: Re: low power Oscillator for Xilinx CoolrunnerII
    67625: 04/03/16: Re: low power Oscillator for Xilinx CoolrunnerII
    67666: 04/03/17: Re: ISE 6.2 (w/ SP#1) is 10+ times slower than 6.1
    67872: 04/03/22: Re: Why It Is not Recommended to Infer latches in VLSI Design...
    67946: 04/03/23: Re: Fried a XC2S200!
    67961: 04/03/24: Re: How many times can I burn an FPGA?
    67964: 04/03/24: Re: How many times can I burn an FPGA?
    68032: 04/03/25: Re: Time measurement with Xilinx Spartan-3 - Help
    68072: 04/03/26: Re: PWM, PLD programming ,(up/down ramp frequency)
    68074: 04/03/26: Re: Clock divider preserving duty-cycle ?
    68093: 04/03/26: Re: CPLD: assign pins first, or design content first?
    68132: 04/03/27: Re: CPLD: assign pins first, or design content first?
    68354: 04/04/02: Re: AHDL, VERILOG or VHDL??
    68416: 04/04/04: Re: The Logic Behind License Renewal
    68440: 04/04/05: Re: Which HVL is the most popular?
    68464: 04/04/06: Re: ATMEL support / Are they serious ?
    68465: 04/04/06: Re: ATMEL support / Are they serious ?
    68790: 04/04/19: Re: DDS-Based PLL
    68823: 04/04/20: Re: Clock Enables and Power
    68869: 04/04/21: Re: calculate the number of logic gate in FPGA
    68884: 04/04/21: Re: Issues on Shift Register in a Clockless UART
    68913: 04/04/22: Re: cpld in plcc84 package
    68927: 04/04/22: Re: Issues on Shift Register in a Clockless UART
    68953: 04/04/23: Time domain/Delay line UARTs - high speeds
    68986: 04/04/24: Re: OT - Generating a 20MHz clock that can be adjusted by +- 2%
    68994: 04/04/24: Re: OT - Generating a 20MHz clock that can be adjusted by +- 2%
    69000: 04/04/24: Re: transport applications
    69009: 04/04/25: Re: Help implementing a 74273 flip flop in a 9536 cpld
    69030: 04/04/26: Re: Looking for a USB-enabled flash-based microcontroller with CPLD/FPGA
    69035: 04/04/26: Re: Xilinx CPLD - FSM - one hot - lost token...
    69070: 04/04/27: Re: CPLD input
    69071: 04/04/27: Re: Stretch Inc
    69073: 04/04/27: Re: Stretch Inc
    69124: 04/04/28: Re: Strange message from Xilinx 6.2.01i
    69135: 04/04/28: Re: Altera EP320 to PAL16V8
    69228: 04/05/01: Re: Correction
    69238: 04/05/02: Re: Connecting a crystal to a Cyclone or Max PLD
    69476: 04/05/12: Re: FPGA wanted
    69494: 04/05/12: Re: Easypath
    69516: 04/05/13: Re: Looking for Synario 3.0 (Lattice)
    69520: 04/05/13: Re: Decompiler for GAL JEDEC fusemap
    69537: 04/05/13: Re: Looking for Synario 3.0 (Lattice)
    69557: 04/05/14: Re: Looking for Synario 3.0 (Lattice)
    69570: 04/05/14: Re: Looking for Synario 3.0 (Lattice)
    69639: 04/05/17: Re: Phase relationship management
    69669: 04/05/18: Re: How to replace Triscend - Xilinx plans for the future
    69671: 04/05/18: Atmel Zigbee solutions
    69719: 04/05/19: Re: How to replace Triscend - Xilinx plans for the future
    69735: 04/05/19: Re: Nios II Going Live...
    69779: 04/05/20: Re: Nios II Going Live...
    69780: 04/05/20: Re: Nios II Going Live...
    69781: 04/05/20: Re: Nios II Going Live...
    69783: 04/05/20: Re: How to replace Triscend - Xilinx plans for the future
    69811: 04/05/21: Re: Nios II Going Live...
    69850: 04/05/22: Re: Never right, always room for improvement
    69890: 04/05/24: Re: strange behaviour of the design
    69927: 04/05/25: Re: Driving fpga pin out over long cable
    70006: 04/05/27: Re: What can I do if my chip can't meet timing?
    70025: 04/05/28: Re: Driving fpga pin out over long cable
    70028: 04/05/28: Re: Driving fpga pin out over long cable
    70096: 04/06/03: Re: FPGA + A/D converter
    70104: 04/06/03: Re: FPPTA?
    70275: 04/06/11: Re: Avoid action on very short peak on input signal (Xilinx Spartan
    70377: 04/06/15: Re: Atmel WinCupl
    70407: 04/06/16: Progress in FPGA static Icc timeline degrade
    70409: 04/06/16: Re: pulse generation using SRL16E on a Virtex-II
    70488: 04/06/18: Re: compressing Xilinx bitstreams
    70492: 04/06/18: Re: compressing Xilinx bitstreams
    70502: 04/06/18: Re: compressing Xilinx bitstreams
    70513: 04/06/18: Re: compressing Xilinx bitstreams
    70544: 04/06/20: Re: CPLD mistery. Help.
    70651: 04/06/23: Re: CPLD mistery. Problem Found... and is an interesting one !
    70652: 04/06/23: Re: Family Photo Album
    70658: 04/06/23: Re: Family Photo Album
    70726: 04/06/25: Re: DPLL in CPLD
    70759: 04/06/27: Re: DPLL in CPLD
    70777: 04/06/28: Re: How to add clock delay in CPLD?
    70799: 04/06/29: Re: Battle of the Vapours
    70807: 04/06/29: Re: Family Photo Album
    70809: 04/06/29: Re: Battle of the Vapours
    70922: 04/07/02: Re: reduced power =?ISO-8859-1?Q?Xilinx=AE_Spartan-3=28TM=29_?=
    70939: 04/07/02: Re: Does Xilinx have the worst web site on the planet?
    70981: 04/07/04: Re: Multi-phase Motor Controller?
    71016: 04/07/06: Re: FPGAs starting with incorrect bitstream !?
    71088: 04/07/08: Re: FSM in illegal state
    71096: 04/07/08: Re: FSM in illegal state
    71097: 04/07/08: Re: RC Servo PWM Digital Capture in a Xilinx xc9500 CPLD?
    71099: 04/07/08: Re: FSM in illegal state
    71128: 04/07/09: Re: FSM in illegal state
    71447: 04/07/19: Re: FPGAs starting with incorrect bitstream !?
    71511: 04/07/21: Re: Low Power Applications - enumerate
    71554: 04/07/22: Re: FPGA Selection--
    71625: 04/07/26: Re: 1GHz FPGA counters
    71630: 04/07/26: Re: 1GHz FPGA counters
    71653: 04/07/27: Re: 1GHz FPGA counters
    71654: 04/07/27: Re: 1GHz FPGA counters
    71669: 04/07/27: Re: 1GHz FPGA counters
    71690: 04/07/28: Re: 1GHz FPGA counters
    71701: 04/07/28: Re: On-Chip Oscillator
    71731: 04/07/29: Re: FPGA vs CPLD
    71732: 04/07/29: Re: configuration SRAM cells in Xilinx/Altera FPGAs
    71805: 04/07/31: Re: On-Chip Oscillator
    71810: 04/07/31: Re: On-Chip Oscillator
    71834: 04/08/02: Re: Fast Memories
    71844: 04/08/02: Re: 1GHz FPGA counters
    71859: 04/08/03: Re: DDR or SDR ? Memory controller in FPGA
    71861: 04/08/03: Re: Compact FPGA Board?
    71918: 04/08/04: Re: FPGA and RS422
    71976: 04/08/05: Re: Choosing FPGAs: Xilinx vs Altera vs Actel vs Lattice
    72012: 04/08/06: Re: Choosing FPGAs: Xilinx vs Altera vs Actel vs Lattice
    72021: 04/08/06: Re: Comparing Quality of Results of FPGA CAD Tools
    72067: 04/08/07: Re: Compact FPGA Board?
    72075: 04/08/08: Re: ABEL support for legacy chips
    72093: 04/08/09: Re: ABEL support for legacy chips
    72142: 04/08/10: Re: Now I am really confused!
    72143: 04/08/10: Re: ABEL support for legacy chips
    72187: 04/08/11: Re: ABEL support for legacy chips
    72233: 04/08/12: Re: new XILINX 9500XL datasheets
    72443: 04/08/19: Re: Announcing JOLT - Yet Another Xilinx Programming Tool
    72564: 04/08/25: Re: Altera MAX II
    72588: 04/08/26: Re: ring oscillator calibration
    72618: 04/08/27: Re: Altera MAX II
    72639: 04/08/27: Re: ring oscillator calibration
    72640: 04/08/27: Re: Altera MAX II
    72814: 04/09/03: Re: Completed my first Virtex4 design
    73724: 04/09/29: Re: NV on-chip memory?
    73820: 04/09/30: Re: NV on-chip memory?
    73821: 04/09/30: Re: DISCLOSURE : NV on-chip memory?
    73836: 04/09/30: Re: ELABORATED DISCLOSURE and continued discussion : NV on-chip
    73905: 04/10/01: Re: MicroBlaze is no available as Open-Source!! (from independant
    73912: 04/10/01: Re: MicroBlaze is no available as Open-Source!! (from independant
    73999: 04/10/02: Re: JOP on Spartan-3 Starter Kit
    74005: 04/10/02: Re: FPGA vs ASIC area
    74042: 04/10/03: Re: JOP on Spartan-3 Starter Kit
    74058: 04/10/03: Re: FPGA vs ASIC area
    72843: 04/09/05: Re: CPLD : Is there a way
    72911: 04/09/08: Re: 1GHz FPGA counters
    72948: 04/09/09: Re: 1GHz FPGA counters
    73053: 04/09/13: Re: Need some help with some technical claims...
    73077: 04/09/14: Re: Need some help with some technical claims...
    73079: 04/09/14: Re: Virtex 4 released today
    73081: 04/09/14: Re: Virtex 4 released today
    73158: 04/09/15: Re: Virtex 4 released today
    73208: 04/09/16: Re: Virtex 4 released today
    73209: 04/09/16: Re: I/O state of max7000s during power-up?
    73215: 04/09/16: Re: Xilinx DCMs
    73254: 04/09/17: Re: beginner's question
    73676: 04/09/28: Re: NV on-chip memory?
    73681: 04/09/28: Re: Spartan-3 VCCIO ramp up time
    74940: 04/10/22: Re: Async reset
    75055: 04/10/26: Re: Assembler for PicoBlaze in Perl
    75056: 04/10/26: Re: Low-power FPGAs?
    75066: 04/10/26: Re: Low-power FPGAs?
    75067: 04/10/26: Re: Assembler for PicoBlaze in Perl
    75137: 04/10/27: Re: Low-power FPGAs?
    75163: 04/10/28: Re: Low-power FPGAs?
    75170: 04/10/28: Re: Low-power FPGAs?
    75180: 04/10/28: Re: Low-power FPGAs?
    75229: 04/10/30: Re: Low-power FPGAs?
    75243: 04/10/31: Re: Low-power FPGAs?
    75261: 04/11/01: Re: Low-power FPGAs?
    75346: 04/11/03: Re: Low-power FPGAs?
    74079: 04/10/04: Re: NV on-chip memory?
    74080: 04/10/04: Re: M*Blaze in Cyclone ! End of What? ;)
    74148: 04/10/05: Re: JOP on Spartan-3 Starter Kit
    74262: 04/10/07: Re: DCM and CLKFX - is this allowed?
    74321: 04/10/08: Re: DCM and CLKFX - is this allowed?
    74364: 04/10/09: Re: Flex10K10A, I2C, MultiVolt IO, pull-ups
    74371: 04/10/09: Re: PLL lock usage into Altera Stratix devices
    74402: 04/10/11: Re: JOP on Spartan-3 Starter Kit
    74404: 04/10/11: Re: JOP on Spartan-3 Starter Kit
    74445: 04/10/12: Re: Temperature considerations of inactive logic blocks
    74490: 04/10/13: Re: Actel Fusefile Reverse Engineering
    74492: 04/10/13: Re: level converter for high frequencies
    74600: 04/10/15: Re: Xilinx to Make Image Processing FPGA
    74736: 04/10/18: Re: Open-Source MicroBlaze IP-Core working in FPGA :)
    74781: 04/10/19: Re: Open-Source MicroBlaze IP-Core working in FPGA :)
    74931: 04/10/22: Re: Async reset
    75442: 04/11/06: Re: Number of FPGA users?
    75444: 04/11/06: Re: Low-power FPGAs?
    75527: 04/11/09: Re: Low-power FPGAs?
    75591: 04/11/11: Re: Advice on Contemporary Low cost, Medium Density CPLDs
    75600: 04/11/11: Re: Xilinx Tshirts in football package.....
    75657: 04/11/12: Re: C Compiler for Picoblaze !!!!!
    75659: 04/11/12: Re: Low-power FPGAs?
    75668: 04/11/12: Re: asynchronous bus transfers
    75712: 04/11/13: Re: Obsolete processors resurected in FPGAs
    75745: 04/11/14: Re: Obsolete processors resurected in FPGAs
    75751: 04/11/14: Re: Obsolete processors resurected in FPGAs
    75753: 04/11/14: Re: Obsolete processors resurected in FPGAs
    75909: 04/11/19: Re: 5V inputs with series resistor on Spartan-3
    75939: 04/11/20: Re: NIOSII problems?
    76050: 04/11/24: TSMC release 40V 0.18u process, MTP comming
    76073: 04/11/24: Re: Spartan 3L - misleading info to potential customers
    76106: 04/11/25: Re: Hierarchical PCB design.
    76220: 04/11/29: Re: CPLD + CAN bus
    76246: 04/11/30: Re: CPLD + CAN bus
    76262: 04/11/30: Re: CPLD + CAN bus
    76334: 04/12/01: Re: Pin connection doubts
    76335: 04/12/01: Re: CMOS capacitive loads, transition probabilities and FPGAs
    76352: 04/12/01: Re: CMOS capacitive loads, transition probabilities and FPGAs
    76371: 04/12/01: Re: Stupid tools question...
    76596: 04/12/07: Re: how to speed up my accumulator ??
    76599: 04/12/07: Re: how to speed up my accumulator ??
    76678: 04/12/09: Re: Open source FPGA EDA Tools
    76854: 04/12/15: Re: Need help with CUPL
    76985: 04/12/18: Re: Need help with CUPL
    76991: 04/12/19: Re: GAL/PAL - Read the UES/AND-Array with burned Security Fuse???
    77010: 04/12/20: Low Power FPGAs, Vcc control
    77054: 04/12/21: Re: Using low-core-voltage devices in industrial applications
    77071: 04/12/22: Re: Using low-core-voltage devices in industrial applications
    77102: 04/12/23: Re: Using low-core-voltage devices in industrial applications
    77547: 05/01/11: Re: Configuration devices
    77634: 05/01/13: Re: Programming and copyright
    77713: 05/01/15: Re: I2C --> SPI or Parallel Port Concentrator
    77746: 05/01/16: Re: I2C --> SPI or Parallel Port Concentrator
    77902: 05/01/20: Re: Comparison of LEON2, Microblaze and Openrisc processors
    77939: 05/01/21: Re: Comparison of LEON2, Microblaze and Openrisc processors
    78016: 05/01/23: Re: Microscope examination of a PLD
    78056: 05/01/24: Re: How to get 1.8432 MHz out of 24 MHz with Sparten-3?
    78096: 05/01/25: Re: 60Hz clock on XC9572
    78117: 05/01/25: Re: 60Hz clock on XC9572
    78186: 05/01/26: Re: 60Hz clock on XC9572
    78196: 05/01/26: Re: Copying/Reverse Engineering PAL
    78229: 05/01/27: Re: 60Hz clock on XC9572
    78236: 05/01/27: Re: lowest-cost FPGA and CPLD
    78241: 05/01/27: Re: =?ISO-8859-1?Q?ProASIC=A7_Released?=
    78242: 05/01/27: Re: =?ISO-8859-1?Q?ProASIC=A7_Released?=
    78246: 05/01/27: Re: =?ISO-8859-1?Q?ProASIC=A7_Released?=
    78307: 05/01/29: New code FLASH memory
    78438: 05/02/01: Re: could I drive Altera MAX II CPLD with LSTTL outputs?
    78496: 05/02/02: Re: LVDS without termination
    78506: 05/02/02: Re: See Peter's High-Wire Act next Tuesday
    78597: 05/02/04: Re: See Peter's High-Wire Act next Tuesday
    78603: 05/02/04: Re: See Peter's High-Wire Act next Tuesday
    78605: 05/02/04: Re: See Peter's High-Wire Act next Tuesday
    78615: 05/02/04: Re: See Peter's High-Wire Act next Tuesday
    78640: 05/02/05: Re: See Peter's High-Wire Act next Tuesday
    78649: 05/02/05: Re: Xilinx Virtex4 / Spartan3 High Speed Designs
    78690: 05/02/06: Re: See Peter's High-Wire Act next Tuesday
    78709: 05/02/07: Re: See Peter's High-Wire Act next Tuesday
    78710: 05/02/07: Re: See Peter's High-Wire Act next Tuesday
    78715: 05/02/07: Re: See Peter's High-Wire Act next Tuesday
    78725: 05/02/07: Re: See Peter's High-Wire Act next Tuesday
    78765: 05/02/08: Re: See Peter's High-Wire Act next Tuesday
    78782: 05/02/08: Re: See Peter's High-Wire Act next Tuesday
    78986: 05/02/11: Re: SimmStick FPGA module
    79145: 05/02/15: Re: SimmStick FPGA module
    79146: 05/02/15: Re: See the next high-wire act, this time on power consumption
    79208: 05/02/16: Re: See the next high-wire act, this time on power consumption
    79234: 05/02/16: Re: See the next high-wire act, this time on power consumption
    79284: 05/02/17: Re: What do future FPGA's need?
    79339: 05/02/18: Re: Updated Stratix II Power Specs & Explanation
    79418: 05/02/19: Re: DNL and INL calculation
    79531: 05/02/21: Re: hdl:lament
    79553: 05/02/21: Re: difficult to build counter, some help please : (
    79597: 05/02/22: Re: Reconfigure your dreams: fully reconfigurable computer in DIP40
    79602: 05/02/22: Re: Reconfigure your dreams: fully reconfigurable computer in DIP40
    79603: 05/02/22: Re: Reconfigure your dreams: fully reconfigurable computer in DIP40
    79646: 05/02/23: Re: SD Card and FPGA
    79669: 05/02/23: Re: Is Altera Cyclone a good choice ?
    79730: 05/02/24: Re: Hardcopy Vs ASIC
    79820: 05/02/25: Re: cheapest CPLD
    79838: 05/02/25: Re: Nios performance
    79985: 05/02/28: Re: Prescalable counter
    79990: 05/02/28: Re: I2C protocol to communicate between FPGAs
    80028: 05/03/01: Re: Prescalable counter
    80328: 05/03/04: Re: programming ATF750 in ABEL
    80329: 05/03/04: Re: making an fpga hot - addendum
    80400: 05/03/05: Re: Genlock
    80439: 05/03/06: Re: using atmel fit2500 fitter for a atf750
    80463: 05/03/07: Re: Help with 22v10 and WinCupl :(
    80502: 05/03/08: Re: Asynchronous processor !?!
    80510: 05/03/08: Re: Help with 22v10 and WinCupl :(
    80511: 05/03/08: Re: state encoding in FSM for simple cases ?
    80512: 05/03/08: Re: Surge in S2? ~3 amperes at cold for a millisecond
    80578: 05/03/09: Re: Asynchronous processor !?!
    80749: 05/03/11: Re: programing an ATF750 from VHDL
    80860: 05/03/13: Re: (Stupid/Newbie) Question on UART
    80886: 05/03/14: Re: (Stupid/Newbie) Question on UART
    80929: 05/03/15: Re: XC3000 non-recoverable lockup problem
    80955: 05/03/15: Re: (Stupid/Newbie) Question on UART
    80983: 05/03/16: Re: XC3000 non-recoverable lockup problem
    80988: 05/03/16: Re: XC3000 non-recoverable lockup problem
    81087: 05/03/18: Re: XC3000 non-recoverable lockup problem
    81121: 05/03/18: Re: Newbie: Slow FPGAs
    81188: 05/03/19: Re: XC3000 non-recoverable lockup problem
    81189: 05/03/19: Re: XC3000 non-recoverable lockup problem
    81277: 05/03/21: Re: PAL problems (again)
    81380: 05/03/23: Re: XC3000 non-recoverable lockup problem
    81381: 05/03/23: Re: XC3000 non-recoverable lockup problem
    81398: 05/03/23: Re: XC3000 non-recoverable lockup problem
    81444: 05/03/24: Re: XC3000 non-recoverable lockup problem
    81454: 05/03/24: Re: XC3000 non-recoverable lockup problem
    81462: 05/03/24: Re: OT: EDA tools
    81483: 05/03/25: Re: XC3000 non-recoverable lockup problem
    81626: 05/03/29: Re: XC3000 non-recoverable lockup problem
    81628: 05/03/29: Re: free 8 Channel Frequency meter for all FPGA owners :)
    81629: 05/03/29: Re: some +. for Altera
    81860: 05/04/03: Re: Achieving required speed in Virtex-II Pro FPGA
    81932: 05/04/05: Re: XC3000 non-recoverable lockup problem
    82026: 05/04/06: Re: ISA vs. patent/trademark
    82119: 05/04/07: Re: Xilinx ISE 7.1i / stuck down XCR3064 outputs
    82169: 05/04/08: Re: Slow rising strobe used to clock IOB's, can it cause trouble?
    82436: 05/04/13: Re: General question about soft CPUs
    82536: 05/04/14: Re: "The ISE 7.1 Experience"
    82765: 05/04/18: Re: Xilinx tools from the commandline
    82880: 05/04/19: Re: Soft CPU vs Hard CPU's
    82937: 05/04/20: Re: College Project
    82978: 05/04/21: Re: Charge-pumps in FPGAs? Not Since 1998
    83603: 05/05/04: Re: Patent issues in implementing embedded fpgas
    83907: 05/05/10: Re: Altera: Maxplus rules!
    84116: 05/05/13: Re: Virtex4 running at 360Mhz DDR
    84137: 05/05/13: Re: V4 vs. Stratix-II...
    84218: 05/05/15: Re: Stupid Question on the Urination Contest... Re: V4 vs. Stratix-II...
    84233: 05/05/16: Re: Update Picoblaze Code in Bitstream
    84353: 05/05/18: Re: V4 vs. Stratix-II...
    84550: 05/05/21: Re: Bullshit Achieves Literary Status
    84791: 05/05/27: Re: ISE 7.1 small advice about project files (.ISE extension)
    85310: 05/06/08: Re: Lattice and Mentor seminar info pieces... & ST's new 'uC'+FPGA
    85320: 05/06/08: Re: Great Tutorial on Signal Integrity, SSOs, Ground Bounce etc
    85321: 05/06/08: Re: Pissed off with Xilinx - Spartan 3
    85329: 05/06/08: Re: Great Tutorial on Signal Integrity, SSOs, Ground Bounce etc
    85347: 05/06/08: Re: Lattice and Mentor seminar info pieces... & ST's new 'uC'+FPGA
    85380: 05/06/09: Re: ISE/EDK 6.3 vs 7.1...
    85382: 05/06/09: Re: General gripe session ....
    85386: 05/06/09: Re: Great Tutorial on Signal Integrity, SSOs, Ground Bounce etc
    85577: 05/06/11: Re: computer upgrade time.
    85610: 05/06/12: Re: Best Practices for Hardware Designers
    85734: 05/06/15: Re: Somewhat OT - falling behind the times ...
    85857: 05/06/17: Re: AbusivepPricing information in marketing publications
    85910: 05/06/18: Re: AbusivepPricing information in marketing publications
    85938: 05/06/19: Re: CPLD fusemap data - why the secrecy?
    85943: 05/06/19: Re: CPLD fusemap data - why the secrecy?
    85983: 05/06/20: Re: Interesting question on CPLD
    85985: 05/06/20: Re: FPGAs: Where will they go?
    85986: 05/06/20: Re: Retrieving code from an old PAL
    86095: 05/06/22: Re: FPGAs: Where will they go?
    86126: 05/06/22: Re: FPGAs: Where will they go?
    86129: 05/06/22: Re: FPGAs: Where will they go?
    86195: 05/06/23: Re: FPGAs: Where will they go?
    86196: 05/06/23: Re: FYI: Spartan-3 XC3S50 through XC3S1500 Back on Xilinx Online
    86271: 05/06/24: Re: Xilinx webshop
    86314: 05/06/25: Re: Xilinx webshop
    86360: 05/06/27: Re: Xilinx webshop
    86361: 05/06/27: Re: Chess & FPGAs
    86368: 05/06/27: Re: Xilinx webshop
    86546: 05/06/30: Re: Small FPGA
    86614: 05/07/01: Re: Direct audio output from FPGA pins
    86878: 05/07/08: Stacked Die devices
    86934: 05/07/10: Re: Altera QII WE Tutorials
    87546: 05/07/26: Re: OnChip Oscillator for Xlinx FPGA's (Spartan-3 available now)
    87550: 05/07/26: Re: Free 8 bit micro for fpga
    87596: 05/07/27: Re: OnChip Oscillator for Xlinx FPGA's (Spartan-3 available now)
    87598: 05/07/27: Re: OnChip Oscillator for Xlinx FPGA's (Spartan-3 available now)
    87616: 05/07/27: Re: OnChip Oscillator for Xlinx FPGA's (Spartan-3 available now)
    87658: 05/07/28: Re: isplever and GAL
    87699: 05/07/29: Re: Delay Generators in FPGAs
    87860: 05/08/03: Re: 5V non-volatile reprogrammable FPGA/CPLD
    87861: 05/08/03: Re: Programmable frequency synthesizer with Xilinx DCM
    87868: 05/08/03: Re: Programmable frequency synthesizer with Xilinx DCM
    87930: 05/08/04: Re: Programmable frequency synthesizer with Xilinx DCM
    87990: 05/08/05: Re: Programmable frequency synthesizer with Xilinx DCM
    88044: 05/08/08: AS Assembler support for Lattice Mico8
    88166: 05/08/11: Re: Generating 44.1 kHz clock from 98.304 MHz crystal on FPGA ?
    88174: 05/08/11: Re: Generating 44.1 kHz clock from 98.304 MHz crystal on FPGA ?
    88299: 05/08/15: Re: ISE 7.1 'improvements' plus meandering....
    88302: 05/08/15: Re: ISE 7.1 'improvements' plus meandering....
    88305: 05/08/15: Re: ISE 7.1 'improvements' plus meandering....
    88331: 05/08/16: Re: Peter Alfke's SPDT Switch Debouncer
    88339: 05/08/16: Re: AHDL Abandoned in Quartus?
    88345: 05/08/16: Re: Peter Alfke's SPDT Switch Debouncer
    88380: 05/08/17: Re: Antti's last comp.arch.fpga posting
    88418: 05/08/18: Re: super fast divide-by-N
    88426: 05/08/18: Re: super fast divide-by-N
    88833: 05/08/30: Re: CPLD Jitter
    88835: 05/08/30: Re: Best FPGA for floating point performance
    88838: 05/08/30: Re: Array of slope A/Ds in FPGA?
    89024: 05/09/03: Re: gal16v8 CUPL problems
    89030: 05/09/03: Re: CPLD CoolRunner-II - IO current limited to 8mA?
    89046: 05/09/04: Re: High baud rate chips for RS232 protocol
    89075: 05/09/05: Re: I2C "SCL" line problem
    89164: 05/09/07: Re: Cyclone conf flash - 25p10 !
    89197: 05/09/08: Re: Cyclone conf flash - 25p10 !
    89238: 05/09/09: Re: Cyclone conf flash - 25p10 !
    89366: 05/09/14: Re: Reading a PAL fusemap with a microscope
    89368: 05/09/14: Re: 24 Counters on one board
    89380: 05/09/14: Re: Is a CPLD appropriate for this triple PWM application?
    89423: 05/09/15: Re: Is a CPLD appropriate for this triple PWM application?
    89469: 05/09/16: Re: Is a CPLD appropriate for this triple PWM application?
    89540: 05/09/19: Re: Reading a PAL fusemap with a microscope
    89569: 05/09/20: Re: Is a CPLD appropriate for this triple PWM application?
    89757: 05/09/25: Re: Question on Metastability
    89791: 05/09/27: Re: Question on Metastability
    89796: 05/09/27: Re: Question on Metastability
    89845: 05/09/28: Re: Small C Compiler for Picoblaze
    89917: 05/09/30: Re: Antti is back
    90311: 05/10/10: Re: 16-bit microprocessor dore for Actel
    90346: 05/10/11: Re: Virtex-4 FX20 PPC405 Startup Issue
    90466: 05/10/14: Re: Distributed microcontroller computing
    90493: 05/10/15: Re: How to Reduce Interconnects (VDD and VSS)
    90546: 05/10/17: Re: Best Async FIFO Implementation
    90552: 05/10/17: Re: Best Async FIFO Implementation
    90567: 05/10/17: Re: ADC implementation on fpga? Information and procudures wanted.
    90594: 05/10/18: Re: ADC implementation on fpga? Information and procudures wanted.
    90595: 05/10/18: Re: Best Async FIFO Implementation
    90599: 05/10/18: Re: Best Async FIFO Implementation
    90603: 05/10/18: Re: Best Async FIFO Implementation
    90629: 05/10/18: Re: Newbie question: XC3S400 Gate Count
    90727: 05/10/20: Re: which is Low power FPGA?
    90763: 05/10/21: Re: which is Low power FPGA?
    90781: 05/10/21: Re: MAC Architectures
    90881: 05/10/25: Re: SoC Processor design at gate level for edu
    90990: 05/10/27: Re: state machine with 2 clock's
    91041: 05/10/28: Re: another FPGA/asic vendor dead :(
    91047: 05/10/28: Re: another FPGA/asic vendor dead :(
    91048: 05/10/28: Re: another FPGA/asic vendor dead :(
    91053: 05/10/28: Re: another FPGA/asic vendor dead :(
    91055: 05/10/28: Re: 24 to 32 8-bit PWM outputs
    91076: 05/10/29: Re: Cost to go from FPGA to ASIC
    91131: 05/10/31: Re: ISE 8.1, EDK 8.1 any pre-release info available?
    91160: 05/11/01: Re: Sigma-Delta A/D
    91176: 05/11/01: Re: Sigma-Delta A/D
    91177: 05/11/01: Re: Spartan-3E starter kit
    91216: 05/11/02: Re: Antti's Logic Assembler ( was Spartan-3E starter kit )
    91292: 05/11/03: Re: FPGA C Compiler on sourceforge.net (TMCC derivative)
    91297: 05/11/03: Re: Xilinx trouble opening ml40x_emb_ref_xx
    91298: 05/11/03: Re: Xilinx trouble opening ml40x_emb_ref_xx
    91309: 05/11/03: Re: FPGA C Compiler on sourceforge.net (TMCC derivative)
    91333: 05/11/04: Re: FPGA C Compiler on sourceforge.net (TMCC derivative)
    91345: 05/11/04: Re: FPGA C Compiler on sourceforge.net (TMCC derivative)
    91347: 05/11/04: Re: Spartan-3E starter kit
    91391: 05/11/05: Re: FPGA C Compiler on sourceforge.net (TMCC derivative)
    91398: 05/11/05: Re: Spartan-3E starter kit
    91431: 05/11/07: Re: FPGA C Compiler on sourceforge.net (TMCC derivative)
    91441: 05/11/07: Re: Why Spartan-3e is the best
    91606: 05/11/10: Re: Best Case Timing Parameters
    91681: 05/11/11: Re: fpga speed logic/density MIPS/FLOPS as compared to general purpose
    91694: 05/11/11: Re: open-sourced FPGA (vhdl, verilog, C variants) design libraries,
    91705: 05/11/11: Re: open-sourced FPGA (vhdl, verilog, C variants) design libraries,
    91715: 05/11/11: Re: open-sourced FPGA (vhdl, verilog, C variants) design libraries,
    91716: 05/11/11: Re: open-sourced FPGA (vhdl, verilog, C variants) design libraries,
    91906: 05/11/17: Re: RoHS
    91907: 05/11/17: Re: Rise time/fall time for Spartan3 clock inputs
    92197: 05/11/24: Re: Case expression?
    92251: 05/11/25: Re: XC2000
    92264: 05/11/25: Re: FPGA ARM IP Core
    92325: 05/11/28: Re: Virtex 4 Tapped Delay Lines
    92427: 05/11/30: Re: Slow FIFO using external SRAM
    92504: 05/12/01: Re: Virtex 4 Tapped Delay Lines
    92678: 05/12/05: Re: Power Optimization NetSeminar: Wedesday, Dec. 7 at 11 am PST
    92732: 05/12/06: Re: Is it legal to write an logical equation for a FPGA LUT in claims
    92785: 05/12/07: Re: ISE 8.1 release delayed?
    92841: 05/12/08: Re: I2C controller chipset to interface with FPGA
    92846: 05/12/08: Re: I2C controller chipset to interface with FPGA
    92890: 05/12/09: Re: I2C controller chipset to interface with FPGA
    92893: 05/12/09: Re: I2C controller chipset to interface with FPGA
    93002: 05/12/12: Re: Important BRAM safety tip ( was: Adding "super-LUTs" to FPGA,
    93059: 05/12/13: Re: mixed signal flash FPGAs launched!
    93095: 05/12/14: Re: Future of Microchip Development Tools?
    93164: 05/12/15: Re: Hello PPl, is there a way of locking a design (NGC) to a particular
    93372: 05/12/21: Re: Patents and (possible) Plagiarism, Anyone ever been in a similarsituation?
    93417: 05/12/22: Re: Place and Route Algorithms
    93440: 05/12/22: Re: Place and Route Algorithms: where's the fat?
    93443: 05/12/22: Xilinbx Online store XC2C32A, XC2C64A missing ?
    93474: 05/12/23: Re: Going insane - Xilinx VGA controller...
    93479: 05/12/23: Re: Place and Route Algorithms: where's the fat?
    93480: 05/12/23: Re: Place and Route Algorithms: where's the fat?
    93798: 05/12/31: Re: Power Optimization: can the routing and placement really save
    93799: 05/12/31: Re: Power Optimization: can the routing and placement really save
    93822: 06/01/01: Re: Brute Force Examination of a PLD
    93963: 06/01/04: Re: RTL for Z8000 series CPU?
    94063: 06/01/05: Re: Xilinx new year Puzzle: binary counter 0,5,2,3,4,1,6,7...
    94040: 06/01/05: Re: [ANNOUNCE] MyHDL 0.5 released
    94116: 06/01/06: Re: [ANNOUNCE] MyHDL 0.5 released
    94037: 06/01/05: Re: Schematic Entry, Xilinx or Altera?
    94041: 06/01/05: Re: Schematic Entry, Xilinx or Altera?
    94048: 06/01/05: Re: Schematic Entry, Xilinx or Altera?
    94128: 06/01/06: Re: Schematic Entry, Xilinx or Altera?
    94104: 06/01/06: Re: What kind of cpu is suit for me?
    94105: 06/01/06: Re: Beginner help with VHDL, Xilinx 9536XL, and ISE7.1
    94125: 06/01/06: Re: Beginner help with VHDL, Xilinx 9536XL, and ISE7.1
    94197: 06/01/07: Re: Beginner help with VHDL, Xilinx 9536XL, and ISE7.1
    94321: 06/01/10: Re: Beginner help with VHDL, Xilinx 9536XL, and ISE7.1
    94208: 06/01/08: Re: FPGA -> ASIC`
    94324: 06/01/10: Re: "failed to create empty document"
    94812: 06/01/18: Re: Samples
    94500: 06/01/13: Re: DSP soft processors
    94632: 06/01/15: Re: DSP soft processors
    94498: 06/01/13: Re: FPGA Journal Article
    94647: 06/01/16: Re: FPGA Journal Article
    94651: 06/01/16: Re: FPGA Journal Article
    94720: 06/01/17: Re: FPGA Journal Article
    94588: 06/01/14: Re: OT: RoHS and Lead?
    94611: 06/01/14: Re: OT: RoHS and Lead?
    94586: 06/01/14: Re: Attack of the clones
    94630: 06/01/15: Re: Caution, Rant follows
    94633: 06/01/15: Re: Caution, Rant follows
    94786: 06/01/18: Re: Just want to program Xilinx CPLD device from JEDEC file using
    94873: 06/01/19: Re: Selling Microblaze based Machines
    94875: 06/01/19: Re: clock generation with DOPPLER shift
    94959: 06/01/20: Re: Xilinx padding LC numbers, how do you feel about it?
    94983: 06/01/20: Re: Quadrature Encoder ::
    94990: 06/01/20: Re: Quadrature Encoder ::
    95093: 06/01/21: Re: Just want to program Xilinx CPLD device from JEDEC file usingISE8.1
    95569: 06/01/25: Re: Creating Multiple Configuration PROM File
    95615: 06/01/25: Re: Creating Multiple Configuration PROM File
    95455: 06/01/24: Re: Reconfigurable Array of Array
    95461: 06/01/24: Re: Xilinx padding LC numbers, how do you really feel about it?
    95497: 06/01/24: Re: Xilinx padding LC numbers, how do you really feel about it?
    95756: 06/01/26: Re: Xilinx padding LC numbers, how do you really feel about it?
    95617: 06/01/25: Re: Xilinx padding LC numbers, how do you really feel about it?
    95534: 06/01/24: Re: Xilinx padding LC numbers, how do you really feel about it?
    95485: 06/01/24: =?ISO-8859-1?Q?Re=3A_obtaining_ABEL_code_from_schemati?=
    95537: 06/01/24: Re: ISE8.1 Service Packs Schedule
    95643: 06/01/25: Re: help:dual-edge flip-flop possible using Verilog?
    95740: 06/01/26: Re: help:dual-edge flip-flop possible using Verilog?
    95775: 06/01/26: Re: help:dual-edge flip-flop possible using Verilog?
    95757: 06/01/26: Re: So what happened to JHDLBits?
    95895: 06/01/27: Re: So what happened to JHDLBits?
    95898: 06/01/27: Re: Spartan-3 Starter Board
    95796: 06/01/26: Re: Stop. Go. Yield.
    95892: 06/01/27: Re: So Xilinx, is XDL and related libraries an available open source
    96011: 06/01/28: Re: Impact 8.1 problems with non xilinx device in chain
    96012: 06/01/28: Re: Lattice high end FPGAs to be announced soon
    96108: 06/01/31: Re: Xilinx Legal
    96287: 06/02/02: Re: Back to max thermal and power for XC4VLX200's
    96299: 06/02/02: Re: Back to max thermal and power for XC4VLX200's
    96298: 06/02/02: Re: Back to max thermal and power for XC4VLX200's
    96310: 06/02/02: Re: Back to max thermal and power for XC4VLX200's
    96312: 06/02/02: Re: Back to max thermal and power for XC4VLX200's
    96332: 06/02/02: Re: Back to max thermal and power for XC4VLX200's
    96360: 06/02/03: Re: Die Area
    96333: 06/02/02: Re: Spartan3 pullups
    96387: 06/02/03: Re: BGA central ground matrix
    96439: 06/02/04: Re: BGA central ground matrix
    96442: 06/02/04: Re: BGA central ground matrix
    96574: 06/02/07: Re: BGA central ground matrix
    96663: 06/02/09: Re: MicroBlaze in Spartan 3 playing tuxchess :)
    96664: 06/02/09: Re: MicroBlaze in Spartan 3 playing tuxchess :)
    96676: 06/02/09: Async Processors
    96677: 06/02/09: Re: NMEA Decoder/Display
    96691: 06/02/09: Re: Async Processors
    96702: 06/02/09: Re: BGA central ground matrix
    96703: 06/02/09: Re: BGA central ground matrix
    96736: 06/02/10: Re: Parallel NCO (DDS) in Spartan3 for clock synthesis - highest
    96743: 06/02/10: Re: Async Processors
    96753: 06/02/10: Re: Async Processors
    96755: 06/02/10: Re: Parallel NCO (DDS) in Spartan3 for clock synthesis - highest
    96797: 06/02/11: Re: Async Processors
    96818: 06/02/11: Re: Async Processors
    96824: 06/02/11: Re: Altera EPLD
    96846: 06/02/12: Re: Async Processors
    96875: 06/02/13: Re: Microblaze using SPI flash as instruction memory
    96886: 06/02/13: Re: Parallel NCO (DDS) in Spartan3 for clock synthesis - highest
    96926: 06/02/14: Re: Altera RoHS Irony
    96946: 06/02/14: Re: I2C and posedge sampling
    97005: 06/02/15: Re: SCHEMATICS ... Is anybody as frustrated as I am with the software?
    97021: 06/02/15: Re: Altera RoHS Irony
    97127: 06/02/17: Maxim anounce MAX3421E SPI-USB Host/Peri
    97131: 06/02/17: Re: User masks in HardCopy and HardCopy II
    97393: 06/02/22: Re: FPGA - software or hardware -2-
    97398: 06/02/22: Re: Is FPGA code called gateware?
    97412: 06/02/22: Re: Is FPGA code called gateware?
    97466: 06/02/23: Re: Input stage for VHF frequency counter in an FPGA?
    97531: 06/02/24: Re: News from Embedded World in Nurnber
    97548: 06/02/24: Re: 8051 IP core with JTAG debugger for FPGA?
    97678: 06/02/26: Re: fpga to 5v ttl logic
    97718: 06/02/27: Re: fpga to 5v ttl logic
    97777: 06/02/28: Re: The 95108 cpld is getting heated when connected by CRO
    97778: 06/02/28: Re: fpga to 5v ttl logic
    97783: 06/02/28: Re: tricks to make large PLAs fast?
    97804: 06/02/28: Re: tricks to make large PLAs fast?
    97812: 06/02/28: Re: tricks to make large PLAs fast?
    97861: 06/03/01: Re: FPGA communication, I2C and DAC
    97864: 06/03/01: Re: tricks to make large PLAs fast?
    97905: 06/03/02: Re: problem with ISE versions
    97913: 06/03/02: Re: fpga to 5v ttl logic
    97925: 06/03/02: Re: Pulse Shape in a functional simulation
    98118: 06/03/06: Re: why use an FPGA when a CPLD will do ??
    98174: 06/03/07: Re: Pullup questions on Spartan3
    98253: 06/03/08: Re: Questions about counter in VHDL
    98343: 06/03/09: Re: for all those who believe in ASICs....
    98350: 06/03/09: Re: Questions about counter in VHDL
    98352: 06/03/09: Re: for all those who believe in ASICs....
    98417: 06/03/10: Re: a problem with coolrunner CPLD (XC2C256) GCK0 pin
    98420: 06/03/10: Re: a problem with coolrunner CPLD (XC2C256) GCK0 pin
    98427: 06/03/10: Re: for all those who believe in ASICs....
    98428: 06/03/10: Re: for all those who believe in ASICs....
    98462: 06/03/11: Re: for all those who believe in ASICs....
    98465: 06/03/11: Re: a problem with coolrunner CPLD (XC2C256) GCK0 pin
    98476: 06/03/11: Re: for all those who believe in ASICs....
    98483: 06/03/11: Re: for all those who believe in ASICs....
    98485: 06/03/11: Re: for all those who believe in ASICs....
    98496: 06/03/11: Re: for all those who believe in ASICs....
    98538: 06/03/13: Re: fpga to 5v ttl logic
    98539: 06/03/13: Re:Low Icc FPGAs
    98540: 06/03/13: Re: Low Icc FPGAs
    98554: 06/03/13: Re: Combinatorial Division?
    98620: 06/03/14: Re: Why does Xilinx hate version control?
    98635: 06/03/14: Re: Why does Xilinx hate version control?
    98686: 06/03/15: Re: Why Xilinx does not specify clock to output MINIMUM time???
    98694: 06/03/15: Re: fpga to 5v ttl logic
    98698: 06/03/15: Re: Why does Xilinx hate version control?
    98705: 06/03/15: Re: Why does Xilinx hate version control?
    98751: 06/03/16: Re: fpga to 5v ttl logic
    98752: 06/03/16: Re: fpga to 5v ttl logic
    98759: 06/03/16: Re: CoolRunner 2 CPLD
    98800: 06/03/17: Re: for all those who believe in ASICs....
    98802: 06/03/17: Re: Where are FPGA heading?
    98828: 06/03/17: Re: Where are FPGA heading?
    98902: 06/03/18: Re: for all those who believe in ASICs....
    98920: 06/03/18: Re: Where are FPGA heading?
    98922: 06/03/18: Re: fpga to 5v ttl logic
    98961: 06/03/18: Re:Disk/LCD defect tolerant models for FPGA sales
    99018: 06/03/19: Re: Disk/LCD defect tolerant models for FPGA sales
    99058: 06/03/20: Re: for all those who have stopped listening, and are ranting now...
    99142: 06/03/21: Re: PacoBlaze with multiply and 16-bit add/sub instructions
    99158: 06/03/21: Re: PacoBlaze with multiply and 16-bit add/sub instructions
    99159: 06/03/21: Re: PacoBlaze with multiply and 16-bit add/sub instructions
    99161: 06/03/21: Re: Disk/LCD defect tolerant models for FPGA sales
    99167: 06/03/21: Re: Disk/LCD defect tolerant models for FPGA sales
    99221: 06/03/22: Re: for all those who believe in ASICs....
    99240: 06/03/22: Smarter Power supplies arrive
    99249: 06/03/22: Re: OpenSPARC released
    99304: 06/03/23: Re: this JTAG thing is a joke
    99381: 06/03/24: Re: this JTAG thing is a joke
    99386: 06/03/24: Re: for all those who believe in ASICs....
    99395: 06/03/24: Re: this JTAG thing is a joke
    99405: 06/03/24: Re: for all those who believe in (structured) ASICs....
    99406: 06/03/24: Re: Xilinx hi-speed interconnect/routing question
    99416: 06/03/24: Re: this JTAG thing is a joke
    99418: 06/03/24: Re: Xilinx hi-speed interconnect/routing question
    99468: 06/03/25: Re: Lattice FPGA
    99481: 06/03/25: Re: Lattice FPGA
    99484: 06/03/25: Re: Xilinx hi-speed interconnect/routing question
    99553: 06/03/27: Re: a problem with coolrunner CPLD (XC2C256) GCK0 pin
    99570: 06/03/27: Re: Xilinx hi-speed interconnect/routing question
    99585: 06/03/27: Re: Altera web site inaccessible
    99602: 06/03/27: Re: Altera web site inaccessible
    99637: 06/03/28: Re: Altera web site (in)accessible
    99638: 06/03/28: Re: deglitching a clock
    99659: 06/03/28: Re: deglitching a clock
    99678: 06/03/28: Re: Microblaze using SPI flash as instruction memory
    99739: 06/03/29: Re: Quartus Compiler as Quailty Check for WebPack
    99831: 06/03/30: Re: deglitching a clock
    99903: 06/03/31: Re: FpgaC developers wanted :)
    99993: 06/04/01: Re: Atmel microcontroller
    99994: 06/04/01: Re: deglitching a clock
    100006: 06/04/01: Re: Atmel microcontroller
    100066: 06/04/03: Re: Configuration pins on Spartan-3
    100114: 06/04/04: Want HiSpeed USB on your FPGA ?
    100169: 06/04/05: Re: How does the DCM phase shifting circuitry work? Xilinx Spartan
    100178: 06/04/05: Re: How does the DCM phase shifting circuitry work? Xilinx Spartan
    100197: 06/04/05: Re: interesting note -- altera C to hardware :)
    100256: 06/04/06: Re: How does the DCM phase shifting circuitry work? Xilinx Spartan
    100259: 06/04/06: Re: How does the DCM phase shifting circuitry work? Xilinx Spartan3
    100266: 06/04/06: Re: LVDS in Cyclone-II
    100279: 06/04/06: Re: LVDS in Cyclone-II
    100330: 06/04/07: Re: USB Interface to Virtex-4
    100331: 06/04/07: Re: Bizarre behaviour by Quartus?
    100333: 06/04/07: Re: USB Interface to Virtex-4
    100424: 06/04/09: Re: Compiler to FPSLIC
    100450: 06/04/10: Re: Compiler to FPSLIC
    100451: 06/04/10: Re: Compiler to FPSLIC
    100452: 06/04/10: Re: Compiler to FPSLIC
    100507: 06/04/11: Re: C-Compiler for free VHDL controller core ?
    100517: 06/04/11: Re: Configuration Rate with multiple .bit files
    100518: 06/04/11: Re: Configuration Rate with multiple .bit files
    100520: 06/04/11: Re: very slow pull-up with CPLD design
    100555: 06/04/12: Re: State Machine and Area Estimate Question
    100618: 06/04/14: Re: Spartan3E readback, SPI programming
    100657: 06/04/15: Re: humble suggestion for Xilinx
    100665: 06/04/15: Re: humble suggestion for Xilinx
    100679: 06/04/16: Re: Spartan 3 chips in power up
    100682: 06/04/16: Re: Where is the xilinx online store gone?
    100683: 06/04/16: Re: Where is the xilinx online store gone?
    100684: 06/04/16: Re: Where is the xilinx online store gone?
    100748: 06/04/18: Re: PLD610
    100750: 06/04/18: Re: Which is the best way to measure low frequencies?
    100835: 06/04/19: Re: PLD610
    101118: 06/04/26: Re: Heating problem of the CPLD
    101121: 06/04/26: Re: Simulated Quartus II delays are much greater than measured
    101122: 06/04/26: Async FPGA ~2GHz
    101126: 06/04/26: Re: Async FPGA ~2GHz
    101154: 06/04/27: Re: Async FPGA ~2GHz
    101157: 06/04/27: Re: Async FPGA ~2GHz
    101172: 06/04/27: Re: Async FPGA ~2GHz
    101179: 06/04/27: Re: The use of analog switches as level translators
    101180: 06/04/27: Re: Picoblaze C Compiler
    101185: 06/04/27: Re: Async FPGA ~2GHz
    101229: 06/04/28: Re: LED Driver
    101231: 06/04/28: Re: Picoblaze C Compiler
    101251: 06/04/28: Re: LED Driver
    101253: 06/04/28: Re: Async FPGA ~2GHz
    101317: 06/04/29: Re: Xilinix SPI programming with USB Platform Cable
    101322: 06/04/29: Re: Pull up resistors on Spartan 3 mode pins
    101329: 06/04/29: Re: Working Altera USB-Blaster compatible design published underGPL
    101377: 06/04/30: Re: Pull up resistors on Spartan 3 mode pins
    101384: 06/04/30: Re: FPGA Single LED Demos: FPGA board for a good ideas/suggestions
    101387: 06/04/30: Re: Pull up resistors on Spartan 3 mode pins
    101388: 06/04/30: Re: Pull up resistors on Spartan 3 mode pins
    101413: 06/05/01: Re: FPGA Single LED Demos: FPGA board for a good ideas/suggestions
    101414: 06/05/01: Re: design optimization
    101428: 06/05/01: Re: Pull up resistors on Spartan 3 mode pins
    101469: 06/05/02: Re: Async FPGA ~2GHz
    101470: 06/05/02: Re: ISE 8.1 Comment Bug, Very hideous
    101478: 06/05/02: Re: Async FPGA ~2GHz
    101541: 06/05/03: Re: Chaining multiple Xilinx "Six Easy Pieces" Clock Doubler
    101543: 06/05/03: Re: bizzare unexplained random errors w/ Lattice 4256V CPLD
    101547: 06/05/03: Re: ISE 8.1 Comment Bug, Very hideous
    101569: 06/05/03: Re: Chaining multiple Xilinx "Six Easy Pieces" Clock Doubler
    101606: 06/05/04: Re: Measuring Light with LED and FPGA
    101613: 06/05/04: Re: Interfacing Spartan 3 board to PC parallel port??
    101614: 06/05/04: Re: Unreactive Output Pins on Xilinx Virtex-II
    101621: 06/05/04: Re: Measuring Light with LED and FPGA
    101632: 06/05/04: Re: Interfacing Spartan 3 board to PC parallel port??
    101678: 06/05/05: Re: 87C52 & 87C51 core
    101694: 06/05/05: Re: LVDS inputs on Cyclone II
    101695: 06/05/05: Re: LVDS inputs on Cyclone II
    101705: 06/05/05: Re: LVDS inputs on Cyclone II
    101758: 06/05/06: Re: Xilinx SelectMAP Question
    101802: 06/05/07: Re: Spartan 3e starter kit & Multimedia
    101809: 06/05/07: Re: Measuring Light with LED and FPGA
    101811: 06/05/07: Re: flashing a led
    101838: 06/05/08: Re: Funky experiment on a Spartan II FPGA
    101840: 06/05/08: Re: Xilinx 3s8000?
    101843: 06/05/08: Re: Funky experiment on a Spartan II FPGA
    101845: 06/05/08: Re: Funky experiment on a Spartan II FPGA
    101854: 06/05/08: Re: Xilinx 3s8000?
    101933: 06/05/09: Putting the Ring into Ring oscillators
    101934: 06/05/09: Re: Can an FPGA be operated reliably in a car wheel?
    101962: 06/05/09: Re: Xilinx 3s8000?
    101964: 06/05/09: Re: Xilinx 3s8000?
    101974: 06/05/09: Re: Xilinx 3s8000?
    101975: 06/05/09: Re: Putting the Ring into Ring oscillators
    102017: 06/05/10: Re: Putting the Ring into Ring oscillators
    102047: 06/05/10: Re: Superscalar Out-of-Order Processor on an FPGA
    102112: 06/05/11: Re: CoolRunner XPLA3 getting axed?
    102113: 06/05/11: Re: CoolRunner XPLA3 getting axed?
    102114: 06/05/11: Re: Altera Equiv.
    102121: 06/05/11: Re: Superscalar Out-of-Order Processor on an FPGA
    102123: 06/05/11: Re: CoolRunner XPLA3 getting axed?
    102127: 06/05/11: Re: CoolRunner XPLA3 thriving for many years to come
    102144: 06/05/11: Re: Interrupt signal sampling (Level or edge?)
    102219: 06/05/12: Re: reverse engineering ?
    102379: 06/05/16: Re: Virtex 5 announced
    102381: 06/05/16: Re: Virtex 5 announced and sampling ... and real!
    102396: 06/05/16: Re: Power for Spartan 3
    102398: 06/05/16: Re: Virtex 5 announced and sampling
    102404: 06/05/16: Re: Virtex 5 announced and sampling ... and real!
    102410: 06/05/16: Re: Virtex 5 announced and sampling
    102466: 06/05/17: Re: Actel Fusion FPGAs
    102467: 06/05/17: Re: Actel Fusion FPGAs
    102575: 06/05/18: Re: disappointing 550Mhz performance of V5 DSP slices
    102613: 06/05/18: Re: Make a signal free for glitches?
    102630: 06/05/18: Re: ADC implementation on FPGA ?
    102666: 06/05/19: Re: Virtex 5 announced and sampling: apologia for FX woes on V4
    102751: 06/05/20: Re: CPLD (CoolRunner failures)
    102769: 06/05/20: Re: CPLD (CoolRunner failures)
    102789: 06/05/21: Re: Why do the electronics manufacturers have to spam me?
    102791: 06/05/21: Re: Virtex 5 announced and sampling: apologia for FX woes on V4
    102797: 06/05/21: Re: CPLD (CoolRunner failures)
    102802: 06/05/21: Re: CPLD (CoolRunner failures)
    102888: 06/05/23: Re: CPLD (CoolRunner failures)
    102937: 06/05/24: Re: ISE 8.1SP4 PN doesnt start
    103028: 06/05/25: Re: Most expensive 8051 in DIP40? here on my desk, labelled Virtex-4
    103038: 06/05/25: Re: ISE 8.1SP4 PN doesnt start
    103118: 06/05/26: Re: ISE sends sensitive information to Xilinx site!
    103119: 06/05/26: Re: ISE sends sensitive information to Xilinx site!
    103120: 06/05/26: Re: Remote Application delivery for EDA
    103128: 06/05/26: Re: ISE sends sensitive information to Xilinx site!
    103171: 06/05/27: Potential of the CELL Processor for Scientific Computing
    103178: 06/05/27: Re: ISE sends sensitive information to Xilinx site!------ Only if
    103256: 06/05/30: Re: Fast Serial I/O on Virtex-5
    103315: 06/05/31: Re: Virtex 5 announced and sampling ... and real!
    103323: 06/05/31: Re: How do I scale a 9-b signed 2's complement data by 17/sqrt(21)?
    103427: 06/06/02: Re: clockless arbiters on fpgas?
    103613: 06/06/07: Re: Who's dying?
    103617: 06/06/07: Re: Who's dying?
    103661: 06/06/08: Re: Who's dying?
    103670: 06/06/08: Re: STOP IT :)
    103677: 06/06/08: Re: Rumor Control:: Will Quartus phase out supporting AHDL?
    103687: 06/06/08: Re: IOBDELAY's delay value
    103699: 06/06/09: Re: Rumor Control:: Will Quartus phase out supporting AHDL?
    103771: 06/06/11: Re: Anyone with Xilinx SP305-board ?
    103822: 06/06/13: Re: Rumor Control:: Will Quartus phase out supporting AHDL?
    103834: 06/06/13: Re: Looking for patent attorney specialized in programmable logic
    103917: 06/06/15: Re: Time for a new "Largest FPGA with free tool support"?
    103945: 06/06/16: Re: ARM cores in FPGA ?
    103956: 06/06/16: Re: How to get lowest price for a ModelSim license?
    103963: 06/06/16: Re: XPLA3 bidirectional bus
    103973: 06/06/16: Re: ARM cores in FPGA ?
    104026: 06/06/17: Re: Time for a new "Largest FPGA with free tool support"?
    104035: 06/06/17: Re: Anyone get a Pictiva OLED to work?
    104036: 06/06/17: Re: Anyone get a Pictiva OLED to work?
    104179: 06/06/21: Re: FSM State Minimization on FPGAs
    104182: 06/06/21: Re: FSM State Minimization on FPGAs
    104293: 06/06/23: Re: keys to the Kingdom
    104295: 06/06/23: Re: keys to the Kingdom
    104324: 06/06/24: Re: keys to the Kingdom
    104393: 06/06/27: Re: PicoBlaze and DDR Ram
    104403: 06/06/27: Re: ISE WebPack 8.2
    104489: 06/06/29: Re: Preserve patent materials through a notary
    104522: 06/06/29: Re: keys to the Kingdom
    104562: 06/06/30: Re: How to evaluate the space efficiency of a historic design.
    104563: 06/06/30: Re: Stopping the clock for power management
    104671: 06/07/04: Re: Chaos in FF metastability
    104771: 06/07/06: Re: Chaos in FF metastability
    104813: 06/07/07: Re: Chaos in FF metastability
    104814: 06/07/07: Re: debouncing a switch (in hardware)
    104827: 06/07/07: Re: Chaos in FF metastability
    104832: 06/07/07: Re: debouncing a switch (in hardware)
    104837: 06/07/07: Re: debouncing a switch (in hardware)
    104875: 06/07/08: Re: Chaos in FF metastability
    105202: 06/07/18: Re: ISE 8.2 WebPack does not support Virtex-5 at all?
    105216: 06/07/18: Re: 2048 input or gate ?
    105245: 06/07/19: Re: JED file translator
    105252: 06/07/19: Re: ISE 8.2 - time to crash 20 minutes
    105256: 06/07/19: Re: ISE 8.2 - time to crash 20 minutes
    105301: 06/07/20: Re: corrupted data when accessing dual port bram in Cyclone II
    105354: 06/07/21: Re: Virtex-5: SoftCore processors at 200MHz !
    105373: 06/07/21: Re: Virtex-5: SoftCore processors at 200MHz !
    105438: 06/07/23: Re: Using BUS'es in ISE WebPACK 3.3WP8.1 ???
    105550: 06/07/26: Re: 2Khz clock signal from 50Hz main frequency with ADPLL
    105557: 06/07/26: Re: 2Khz clock signal from 50Hz main frequency with ADPLL
    105595: 06/07/27: Re: 2Khz clock signal from 50Hz main frequency with ADPLL
    105598: 06/07/27: Re: 2Khz clock signal from 50Hz main frequency with ADPLL
    105638: 06/07/28: Re: 2Khz clock signal from 50Hz main frequency with ADPLL
    105649: 06/07/28: Re: Guided MAP/PAR in ISE
    105782: 06/08/01: Re: 100m JTAG cable
    105838: 06/08/02: Re: 100m JTAG cable
    105846: 06/08/02: Re: 100m JTAG cable
    105854: 06/08/02: Re: Programmable pulse generator
    105856: 06/08/02: Re: 100m JTAG cable
    105870: 06/08/02: Re: Programmable pulse generator
    105921: 06/08/03: Re: generating sine-like waveforms
    106117: 06/08/08: Re: Microblaze, EDK, Spartan 3 and Webpack
    106182: 06/08/09: Re: 100 Mbit manchester coded signal in FPGA
    106183: 06/08/09: Re: 100 Mbit manchester coded signal in FPGA
    106184: 06/08/09: Re: 100 Mbit manchester coded signal in FPGA
    106211: 06/08/09: Re: 100 Mbit manchester coded signal in FPGA
    106324: 06/08/12: Re: (uc)Linux support for Xilinx FPGAs is going to next level
    106326: 06/08/12: Re: Embedded clocks
    106332: 06/08/12: Re: Embedded clocks
    106390: 06/08/13: Re: Embedded clocks
    106406: 06/08/13: Re: Embedded clocks
    106410: 06/08/13: Re: Embedded clocks
    106419: 06/08/13: Re: Maximum Current Draw of FPGA
    106449: 06/08/14: Re: Embedded clocks
    106450: 06/08/14: Re: Embedded clocks
    106461: 06/08/14: Re: Embedded clocks
    106471: 06/08/14: Re: Embedded clocks
    106478: 06/08/14: Re: Embedded clocks
    106517: 06/08/15: Re: Embedded clocks
    106518: 06/08/15: Re: Crystal input for FPGA
    106521: 06/08/15: Re: Crystal input for FPGA
    106524: 06/08/15: Re: Crystal input for FPGA
    106535: 06/08/15: Re: Embedded clocks
    106646: 06/08/17: Re: Simple state machine in CUPAL
    106669: 06/08/17: Re: Simple state machine in CUPAL
    106681: 06/08/17: Re: Simple state machine in CUPAL
    106722: 06/08/18: Re: S3 starter kit, command-line
    106741: 06/08/18: Re: Simple state machine in CUPAL
    106744: 06/08/18: Re: Using an FPGA as USB HOST without PHY
    106799: 06/08/20: Re: S3 starter kit, command-line
    106803: 06/08/20: Re: S3 starter kit, command-line
    106829: 06/08/21: Re: CPU design
    106835: 06/08/21: Re: CPU design
    106841: 06/08/21: Re: CPU design
    106874: 06/08/22: Re: CPU design
    106877: 06/08/22: Re: CPU design
    106932: 06/08/23: Re: CPU design
    106934: 06/08/23: Re: CPU design
    106946: 06/08/23: Re: Running DDR below the min frequency
    106950: 06/08/23: Re: CPU design
    107025: 06/08/24: Re: CPU design
    107116: 06/08/25: Re: Why No Process Shrink On Prior FPGA Devices ?
    107150: 06/08/25: Re: fastest FPGA
    107165: 06/08/25: Re: fastest FPGA
    107263: 06/08/26: Re: fastest FPGA
    107268: 06/08/26: Re: FPGA -> SATA?
    107270: 06/08/26: Re: fastest FPGA
    107286: 06/08/26: Re: fastest FPGA
    107335: 06/08/27: Re: What is the truth about the Virtex5 ?
    107336: 06/08/27: Re: fastest FPGA
    107339: 06/08/27: Re: fastest FPGA
    107416: 06/08/28: Re: Spartan-4 ?
    107458: 06/08/29: Re: Spartan-4 ? - Igloo ?
    107522: 06/08/30: Re: Undergrad project-8051 specifications??
    107527: 06/08/30: Re: placing addiional caps across existing caps to reduce noise
    107528: 06/08/30: Re: placing addiional caps across existing caps to reduce noise
    107530: 06/08/30: Re: CPU design
    107575: 06/08/30: Re: Spartan-4 ?
    107903: 06/09/02: Re: Higher voltages input, quick check....
    107906: 06/09/02: Re: Higher voltages input, quick check....
    107908: 06/09/02: Re: Higher voltages input, quick check....
    107937: 06/09/03: Re: Impossible to download WebPACK?
    107942: 06/09/03: Re: Forth-CPU design
    107954: 06/09/03: Re: Forth-CPU design
    107996: 06/09/04: Re: Here are the URLs (was Re: Impossible to download WebPACK?)
    108005: 06/09/04: Re: Forth-CPU design
    108083: 06/09/05: Re: Forth-CPU design
    108212: 06/09/07: Re: Forth-CPU design
    108375: 06/09/10: Re: Can a FPGA work like a microprocessor ?
    108540: 06/09/13: Re: Spartan-3: 5V -> 2.5V level shifting
    108549: 06/09/13: Re: Spartan-3: 5V -> 2.5V level shifting
    108568: 06/09/13: Re: SoC Development Board
    108673: 06/09/15: Re: Spartan3 driving mosfets
    108751: 06/09/16: Re: XIlinx Spartan 2E stuck in configuration mode
    108752: 06/09/16: Re: Spartan3 driving mosfets
    108757: 06/09/16: Re: XIlinx Spartan 2E stuck in configuration mode
    108791: 06/09/17: Re: XIlinx Spartan 2E stuck in configuration mode
    108792: 06/09/17: Re: XPLA3 going obsolete?
    108798: 06/09/17: Re: XIlinx Spartan 2E stuck in configuration mode
    108823: 06/09/18: Re: XIlinx Spartan 2E stuck in configuration mode
    108882: 06/09/19: Re: New Lattice 32-bit Embedded Microprocessor Available Through
    108885: 06/09/19: Re: Virtex4 Configuration ROM?
    109554: 06/09/29: Re: Driving a 30 bit wide LVTTL bus at 160MHz
    109947: 06/10/09: Re: An implementation of a clean reset signal
    109963: 06/10/09: Re: Antifuse, lower cost?
    109964: 06/10/09: Re: Spartan3A - internal flash configuration or not?
    110010: 06/10/10: Re: Just a matter of time
    110030: 06/10/10: Re: An implementation of a clean reset signal
    110098: 06/10/11: Re: Antifuse, lower cost?
    110162: 06/10/12: Re: Antifuse, lower cost?
    110169: 06/10/12: Re: longest webcase record -- understandably so
    110204: 06/10/12: Re: longest webcase record -- understandably so
    110246: 06/10/13: Re: longest webcase record -- understandably so
    110279: 06/10/13: Re: Last ISE version that supports XC95xxXL ?
    110387: 06/10/15: Re: Xilinx FPGAs in battery-powered scenarios
    110400: 06/10/15: Re: Xilinx FPGAs in battery-powered scenarios
    110436: 06/10/16: Re: how to change cclk frequency ?
    110438: 06/10/16: Re: Xilinx FPGAs in battery-powered scenarios
    110453: 06/10/16: Re: virtex-5 sysmon, really nice to monitor supply and temp
    111041: 06/10/28: Re: Survey: simulator usage
    111055: 06/10/28: Re: A pre-emptive strike against blaming the chip
    111061: 06/10/28: Re: A pre-emptive strike against blaming the chip
    111068: 06/10/28: Re: Survey on Quartus SOPC/Nios-II
    111093: 06/10/29: Re: Survey on Quartus SOPC/Nios-II
    111120: 06/10/30: Re: Survey: simulator usage
    111172: 06/10/31: Re: On the Futility of Documentation Webcases ( Was: Xilinx documentation
    111189: 06/10/31: Re: How stable is the internal clock of a Xilinx CPLD?
    111281: 06/11/01: Re: Dual Port RAM
    111402: 06/11/03: Re: Spectre of Metastability Update
    111420: 06/11/03: Re: Need just a few 5V Spartan
    111432: 06/11/03: Re: Spectre of Metastability Update
    111487: 06/11/04: Re: Spectre of Metastability Update
    111490: 06/11/04: Re: Spectre of Metastability Update
    111497: 06/11/04: Re: Spectre of Metastability Update
    111528: 06/11/05: Re: Spectre of Metastability Update
    111606: 06/11/07: Re: Spectre of Metastability Update
    111827: 06/11/11: Re: Stratix-III announced
    111864: 06/11/12: Re: Stratix-III announced
    111912: 06/11/13: Re: Stratix-III announced
    111913: 06/11/13: Re: Stratix-III announced
    111915: 06/11/13: Re: Stratix-III announced
    112076: 06/11/16: Re: 8080 FSGA model in an FPGA
    112077: 06/11/16: Re: how to filter glitches and mutliple transitions?
    112087: 06/11/16: Re: 8080 FSGA model in an FPGA
    112138: 06/11/17: Re: Warnings in Xilinx 8.2i
    112154: 06/11/17: Re: combinatorical divide by 2 in FPGA
    112217: 06/11/18: Re: memory init in Altera bitfiles, (like data2mem) is it possible?
    112257: 06/11/19: Re: memory init in Altera bitfiles, (like data2mem) is it possible?
    112263: 06/11/19: Re: memory init in Altera bitfiles, (like data2mem) is it possible?
    112274: 06/11/19: Re: memory init in Altera bitfiles, (like data2mem) is it possible?
    112292: 06/11/20: Re: board - T562.jpg
    112646: 06/11/27: Re: run a counter without a clock
    112703: 06/11/28: Re: run a counter without a clock
    112753: 06/11/29: Re: run a counter without a clock
    112895: 06/12/01: Re: FPGA application field
    113080: 06/12/06: Re: Altera starter kits
    113120: 06/12/07: Re: Altera starter kits
    113122: 06/12/07: Re: Spartan-3A launched
    113136: 06/12/07: Re: Free Anydivider, Divide clock by any number
    113292: 06/12/11: Re: approximation of an exponential ramp?
    113397: 06/12/13: Re: Tarfessock1
    113460: 06/12/14: Re: what are your current SoC design for ?
    113493: 06/12/15: Re: abel to vhdl converter
    113644: 06/12/19: Re: solder mask for fpga dissipation
    113693: 06/12/20: Re: ANN: PicoBlaze C: compile to bitstream!
    113806: 06/12/23: Re: Virtex-5 Webpack?
    113809: 06/12/23: Re: Virtex-5 Webpack?
    115082: 07/01/31: Re: 1 Gbps - state of the art?
    115336: 07/02/08: Re: question about power dissipation
    115451: 07/02/12: Re: CLOCK GENERATOR
    115456: 07/02/12: Re: Weird problem with WP 9.1sp1 and XC95144XL
    115514: 07/02/13: Re: Which is your favorite FPGA language?
    115526: 07/02/13: Re: Building Coaxial transmission line on PCB?
    115556: 07/02/14: Re: Which is your favorite FPGA language?
    115557: 07/02/14: Re: Typical clock frequencies of FPGA designs
    115561: 07/02/14: Re: Building Coaxial transmission line on PCB?
    115564: 07/02/14: Re: Typical clock frequencies of FPGA designs
    115569: 07/02/14: Re: Typical clock frequencies of FPGA designs
    115640: 07/02/16: Re: Need fair opinions on choosing either Altera or Xilinx as main
    115643: 07/02/16: Re: Do you like Virtex-5 ?
    115702: 07/02/17: Re: Do you like Virtex-5 ?
    115732: 07/02/19: Re: Do you like Virtex-5 ?
    115758: 07/02/20: Re: ACTEL ProAsic Plus
    115832: 07/02/22: Re: Determine error in asynchronous signal
    115837: 07/02/22: Re: Determine error in asynchronous signal
    115844: 07/02/22: Re: Determine error in asynchronous signal
    115847: 07/02/22: Re: Determine error in asynchronous signal
    115878: 07/02/23: Re: Structured ASIC players
    115881: 07/02/23: Re: Structured ASIC players
    116001: 07/02/28: Re: Spartan-3AN
    116057: 07/03/01: Re: what does a 'blank check' do exactly
    116063: 07/03/01: Re: Spartan-3AN
    116114: 07/03/02: Re: Bypass caps, X2Y and 'puddles'.
    116121: 07/03/02: Re: what does a 'blank check' do exactly
    116122: 07/03/02: Re: XC3S400 and XC3S500E in PQ208
    116195: 07/03/05: Re: Large power planes vs. power islands vs. slits for decoupling
    116201: 07/03/05: Re: Large power planes vs. power islands vs. slits for decoupling
    116248: 07/03/06: Re: Large power planes vs. power islands vs. slits for decoupling
    116258: 07/03/06: Re: Large power planes vs. power islands vs. slits for decoupling
    116310: 07/03/07: Re: Ideas for Masters Project.
    116351: 07/03/08: Re: Spartan3AN - Roadmap
    116358: 07/03/08: Re: Spartan3AN - Roadmap
    116368: 07/03/08: Re: Spartan3AN - Roadmap - bigger questions may prevail...
    116427: 07/03/09: Re: Spartan3AN - Roadmap
    116470: 07/03/10: Re: Xilin X-Fest Lunacy
    116472: 07/03/10: Re: Spartan3AN - Roadmap
    116497: 07/03/11: Re: Are FPGAs go enough for clock dstribution
    116612: 07/03/14: Re: WTF? - Spartan-3E starter kit with no printed board manual?
    116853: 07/03/20: Re: Altera introduces Cyclone III devices, ships 65nm
    116902: 07/03/21: Re: FPGA with 5V and PLCC package
    116912: 07/03/21: Re: FPGA with 5V and PLCC package
    116914: 07/03/21: Re: softcore CPU tools
    116918: 07/03/21: Re: Why is Xilinx's WebPACK so inferior?
    116927: 07/03/21: Re: Why is Xilinx's WebPACK so inferior?
    116934: 07/03/21: Re: Off topic: what is the purpoe of XST?
    116994: 07/03/22: Re: FPGA with 5V and PLCC package
    117003: 07/03/22: Re: FPGA with 5V and PLCC package
    117005: 07/03/22: Re: softcore CPU tools
    117008: 07/03/22: Re: Off topic: what is the purpoe of XST?
    117026: 07/03/22: Re: FPGA with 5V and PLCC package
    117027: 07/03/22: Re: Off topic: what is the purpoe of XST?
    117082: 07/03/23: Re: FPGA with 5V and PLCC package
    117089: 07/03/23: Re: Altera introduces Cyclone III devices, 'ships' 65nm
    117092: 07/03/23: Re: Off topic: what is the purpoe of XST?
    117148: 07/03/24: Re: FPGA with 5V and PLCC package
    117173: 07/03/26: Re: Where is Open Source for FPGA development?
    117178: 07/03/26: Re: Where is Open Source for FPGA development?
    117239: 07/03/27: Re: Open-source CPU-core for standard-cell ASIC?
    117240: 07/03/27: Re: Open-source CPU-core for standard-cell ASIC?
    117286: 07/03/28: Re: Lattice "Open IP" license is GPL-compatible?
    117381: 07/03/30: Re: FPGA with 5V and PLCC package
    117388: 07/03/30: Re: RISC implementation questions
    117394: 07/03/30: Re: RISC implementation questions
    117448: 07/03/31: Re: Help with a face recognition system
    117547: 07/04/04: Re: FPGA with 5V and PLCC package
    117619: 07/04/05: Re: having a state machine in a datapath element a bad design practice?
    118165: 07/04/19: Re: 80000 Bit Shift Register
    118260: 07/04/21: Re: DARNAW! - PGA Style FPGA Module
    118261: 07/04/21: Re: FPGA Newbie
    118277: 07/04/21: Re: FPGA Newbie
    118291: 07/04/23: Re: Lattice pricing
    118310: 07/04/24: Re: FPGA Newbie
    118324: 07/04/24: Re: Ouputs during startup and Programming
    118518: 07/04/29: Re: physical chip size
    118521: 07/04/29: Re: driving Spartan-3 input from 74LS TTL
    118539: 07/04/30: Re: debounce state diagram FSM
    118567: 07/04/30: Re: driving Spartan-3 input from 74LS TTL
    118609: 07/05/01: Re: debounce state diagram FSM
    118666: 07/05/02: Re: debounce state diagram FSM
    118691: 07/05/02: Re: DDR2 with Spartan-3A anybody having success??
    118858: 07/05/05: Re: Spartan 3A Starter Kit Multiboot Demo Config 4 Display Problem
    118864: 07/05/05: Re: Atom HDL
    118865: 07/05/05: Re: Select pullup, pulldown or none via embedded S/W
    118866: 07/05/05: Re: Select pullup, pulldown or none via embedded S/W
    118941: 07/05/08: Re: Help with ATF750CL and WinCUPL
    118943: 07/05/08: Re: V5 LVPECL Inputs
    118945: 07/05/08: Re: Xilinx software quality - how low can it go ?!
    119029: 07/05/10: Re: An Open-Source suggestion for Xilinx
    119034: 07/05/10: Re: An Open-Source suggestion for Xilinx
    119108: 07/05/12: =?ISO-8859-1?Q?Re=3A_power_consumption_of_integrated_c?=
    119136: 07/05/13: Re: driving Spartan-3 input from 74LS TTL
    119185: 07/05/15: Re: An Open-Source suggestion for Xilinx
    119186: 07/05/15: Re: Xilinx software quality - how low can it go ?!
    119187: 07/05/15: Re: An Open-Source suggestion for Xilinx
    119188: 07/05/15: Re: An Open-Source suggestion for Xilinx
    119251: 07/05/16: Re: How low DDR2 Clock Frequency can be? To make it work on FPGA.
    119263: 07/05/16: Re: Power Consumption near Timing Failure Point
    119328: 07/05/17: Re: Power Consumption near Timing Failure Point
    119329: 07/05/17: Re: how to delay a signal in virtex FPGA
    119330: 07/05/17: Re: how to delay a signal in virtex FPGA
    119443: 07/05/19: Re: releasing some FPGA tools-ip as open-source
    119515: 07/05/22: Atmel release Metal Programmable Cell Fabric uC ARM9
    119518: 07/05/22: Re: Atmel release Metal Programmable Cell Fabric uC ARM9
    119575: 07/05/23: Re: LVCMOSS33 I/O sink current
    119604: 07/05/24: Re: LVCMOSS33 I/O sink current
    119635: 07/05/24: Re: Altera Cyclone II - used in 100USD Laptop
    119639: 07/05/24: Re: 6502 and CPU licences in general
    119651: 07/05/24: Re: 6502 and CPU licences in general
    119704: 07/05/25: Re: Altera Cyclone II - used in 100USD Laptop
    119790: 07/05/26: Re: low speed communication
    119820: 07/05/27: Re: Spartan3 LVCMOS33 Slew rate
    119824: 07/05/27: Re: 6502 FPGA core
    119827: 07/05/27: Re: 6502 FPGA core
    119841: 07/05/28: Re: 6502 FPGA core
    119869: 07/05/29: Re: 6502 FPGA core
    119875: 07/05/29: Re: 6502 FPGA core
    119884: 07/05/29: Re: PacoBlaze 2.2
    119936: 07/05/30: Re: PacoBlaze 2.2
    120055: 07/06/01: Re: LVDS termination scheme to nonstandard ribbon cable
    120105: 07/06/01: Re: Actel Cortex M1, any info on license fee?
    120207: 07/06/04: Re: Microcontrollers have a better predictable time behaviour than
    120283: 07/06/05: Re: Lattice XP2 finally announced
    120286: 07/06/05: Re: Power on Spartan 90nm process node
    120289: 07/06/05: Re: Power on Spartan 90nm process node
    120352: 07/06/06: Re: Lattice XP2 finally announced
    120356: 07/06/06: Re: Lattice XP2 finally announced
    120413: 07/06/07: Re: Virtex4 CLKX2 DCM Jitter
    120426: 07/06/07: Re: asynchronous circuit design
    120480: 07/06/08: Re: Lattce SC Purspeed I/O
    120498: 07/06/08: Re: LVPECL output skew
    120555: 07/06/10: Re: Lattice's Online Store Now Sells Silicon - No Minimum Order Quantity
    120614: 07/06/12: Re: Power consumption problem
    120646: 07/06/13: Re: Power consumption problem
    120815: 07/06/18: Re: anyone know a FPGA designer?
    120948: 07/06/21: Achronix Async FPGA Silicon available when ?
    121150: 07/06/27: Re: Can FPGAs inputs detect low currents?
    121193: 07/06/28: Re: another Forth CPU design
    121198: 07/06/28: Re: Xilinx FPGA to interface to special I/O
    121203: 07/06/28: Re: another Forth CPU design
    121209: 07/06/28: Re: Analogue like signal interaction within cpld possible ????
    121228: 07/06/29: Re: Analogue like signal interaction within cpld possible ????
    121230: 07/06/29: Re: Xilinx FPGA to interface to special I/O
    121241: 07/06/29: Execute from SPI flash
    121242: 07/06/29: Re: Execute from SPI flash
    121254: 07/06/29: Re: Execute from SPI flash
    121343: 07/07/03: Re: high voltage input on SPARTAN-3 FPGAs: MTBF reduction?
    121346: 07/07/03: Re: Analogue like signal interaction within cpld possible ????
    121347: 07/07/03: Re: high voltage input on SPARTAN-3 FPGAs: MTBF reduction?
    121354: 07/07/03: Re: high voltage input on SPARTAN-3 FPGAs: MTBF reduction?
    121421: 07/07/04: Re: high voltage input on SPARTAN-3 FPGAs: MTBF reduction?
    121539: 07/07/07: Re: Xilinx ISE, EDK and some ground roules in software development
    121607: 07/07/10: Re: Revisit: Altera vs Xilinx (NIOS II vs Microblaze)
    121653: 07/07/11: Re: Anyone really use those opensource CPUs (OR1K, Lattice Mico32,
    121697: 07/07/12: Re: Anyone really use those opensource CPUs (OR1K, Lattice Mico32,
    121698: 07/07/12: Re: Virtex-II Pro Flip-Flop Setup time
    121701: 07/07/12: Altera MAX III Status ?
    121706: 07/07/12: Re: Revisit: Altera vs Xilinx (NIOS II vs Microblaze)
    121713: 07/07/12: Re: Virtex-II Pro Flip-Flop Setup time
    121729: 07/07/12: Re: Altera MAX III Status ?
    121758: 07/07/13: Re: Revisit: Altera vs Xilinx (NIOS II vs Microblaze)
    121762: 07/07/13: Re: Altera MAX III Status ?
    121765: 07/07/13: Re: Anyone really use those opensource CPUs (OR1K, Lattice Mico32,
    121774: 07/07/13: Re: Anyone really use those opensource CPUs (OR1K, Lattice Mico32,Leon)?
    121861: 07/07/14: Re: Counter ?
    121862: 07/07/14: Re: Counter ?
    121864: 07/07/14: Re: Counter ?
    121867: 07/07/14: Re: Revisit: Altera vs Xilinx (NIOS II vs Microblaze)
    121880: 07/07/14: Re: Image Resolution Rescaling
    121903: 07/07/15: Re: ESR Meter - design contest
    121905: 07/07/15: Re: ESR Meter - design contest
    121909: 07/07/15: Re: ESR Meter - design contest
    121983: 07/07/17: Re: Revisit: Altera vs Xilinx (NIOS II vs Microblaze)
    121995: 07/07/17: Re: Xilinx XC9536 current draw ?
    122022: 07/07/18: Re: Xilinx XC9536 current draw ?
    122040: 07/07/18: Re: Xilinx XC9536 current draw ?
    122041: 07/07/18: Re: Xilinx XC9536 current draw ?
    122070: 07/07/19: Re: Revisit: Altera vs Xilinx (NIOS II vs Microblaze)
    122201: 07/07/24: Re: On I2C protocol
    122253: 07/07/25: Re: On I2C protocol
    122340: 07/07/26: Re: Documentation/leds/simulation
    122347: 07/07/26: Re: Altera or Xilinx
    122399: 07/07/27: Re: Problem with X_FF primitive acting as a latch instead of a fliflop
    122558: 07/07/31: Re: Looking for PLD with embedded memory
    122581: 07/08/01: Re: Looking for PLD with embedded memory
    122830: 07/08/08: Re: New Xilinx forum.
    122831: 07/08/08: Re: New Xilinx forum.
    122974: 07/08/13: Re: Xilinx 13th August opportunity
    123038: 07/08/15: Re: Delaying a pulse train
    123039: 07/08/15: Re: Delaying a pulse train
    123045: 07/08/15: Re: Delaying a pulse train
    123074: 07/08/16: Re: Delaying a pulse train
    123081: 07/08/16: Re: Delaying a pulse train
    123134: 07/08/17: Re: Delaying a pulse train
    123258: 07/08/22: Re: Voltage translation question
    123294: 07/08/23: Re: Power Reduction Strategy
    123300: 07/08/23: Re: Power Reduction Strategy
    123327: 07/08/24: Re: Voltage translation question
    123608: 07/08/31: Re: An FPGA startup is seeking testcase from potential customers
    123663: 07/09/01: Re: Die size, pitch size?
    123775: 07/09/05: Re: Multiple CPLDs on a PCB.
    123791: 07/09/05: Re: Multiple CPLDs on a PCB.
    123924: 07/09/07: Re: VCCAUX too high on a Spartan 3 design
    123982: 07/09/10: Re: Minimize power consumption
    123985: 07/09/10: Re: Minimize power consumption
    124024: 07/09/11: Re: Uses of Gray code in digital design
    124039: 07/09/11: Re: Uses of Gray code in digital design
    124041: 07/09/11: Re: Uses of Gray code in digital design
    124088: 07/09/12: Re: Uses of Gray code in digital design
    124090: 07/09/12: Re: Uses of Gray code in digital design
    124106: 07/09/12: Re: Uses of Gray code in digital design
    124251: 07/09/17: Re: Beginner Advice (Languages, tools etc.)
    124252: 07/09/17: Re: Physical Design Contribution to FPGA/CPLD success
    124280: 07/09/18: Re: Guess: what is the largest number of state machines in a current
    124328: 07/09/19: Re: Guess: what is the largest number of state machines in a current
    124330: 07/09/19: Re: Altera / Lattice / Xilinx CPLDs ?
    124331: 07/09/19: Re: Altera / Lattice / Xilinx CPLDs ?
    124335: 07/09/19: Re: Guess: what is the largest number of state machines in a current
    124494: 07/09/25: Re: Actel Cortex FPGAs, real change of ARM licensing - 0.000 cost
    124544: 07/09/26: Re: Never buy Altera!!!!
    124731: 07/10/02: Re: 2 leg crystal on FPGA: Lattice vs Xilinx
    124732: 07/10/02: Re: 2 leg crystal on FPGA: Lattice vs Xilinx
    124747: 07/10/03: Re: Test and Measurements - Large FPGA
    124829: 07/10/06: Re: 2 leg crystal on FPGA: Lattice vs Xilinx
    124830: 07/10/06: Re: Virtex 13?
    124888: 07/10/10: Re: Legacy support of a Max 7000S
    125033: 07/10/16: Re: FPGA quiz: what can be wrong
    125056: 07/10/16: Re: FPGA quiz: what can be wrong
    125067: 07/10/16: Re: FPGA quiz: what can be wrong
    125075: 07/10/16: Re: FPGA quiz: what can be wrong
    125145: 07/10/17: Re: FPGA quiz: what can be wrong
    125149: 07/10/17: Re: FPGA quiz: what can be wrong
    125168: 07/10/17: Re: FPGA quiz: what can be wrong
    125188: 07/10/18: Re: FPGA quiz: what can be wrong
    125189: 07/10/18: Re: FPGA quiz 1&2, we have the answers and winners
    125222: 07/10/18: Re: FPGA quiz3, or where Antti did give up and does not know answer
    125265: 07/10/19: Re: FPGA pin swapping utility
    125266: 07/10/19: Re: FPGA quiz3, or where Antti did give up and does not know answer
    125275: 07/10/19: Re: mess around with supply voltage to cyclone III
    125406: 07/10/25: Re: Changing refresh rate for DRAM while in operation?
    125452: 07/10/26: Re: Signetics N82F101F
    125506: 07/10/27: Re: Signetics N82F101F
    125507: 07/10/27: Re: is Quartus 7.1 really that S*** !?
    125547: 07/10/29: Re: Power supply filter capacitors
    125551: 07/10/29: Re: Power supply filter capacitors
    125589: 07/10/30: Re: Power supply filter capacitors
    125600: 07/10/30: Re: Signetics N82F101F
    125678: 07/11/01: Re: Ping Jim: The PFD is dead!
    125679: 07/11/01: Re: Capability of a FPGA device.
    125681: 07/11/01: Re: Ping Jim: The PFD is dead!
    125712: 07/11/02: Re: can i use dual edge or two clocks?
    125713: 07/11/02: Re: Another way to handle floating inputs.
    125723: 07/11/02: Re: can i use dual edge or two clocks?
    125753: 07/11/03: Re: Another way to handle floating inputs.
    125811: 07/11/06: Re: not totally repulsive
    125841: 07/11/07: Re: not totally repulsive
    125849: 07/11/07: Re: not totally repulsive
    125875: 07/11/08: Re: Non-volatile FPGA in a small package
    125931: 07/11/09: Re: Maximum current drive according to datasheet ?!
    125981: 07/11/11: Re: newbie to 16v8
    125988: 07/11/12: Re: newbie to 16v8
    125993: 07/11/12: Re: newbie to 16v8
    125994: 07/11/12: Re: newbie to 16v8
    126091: 07/11/15: Re: FPGA for hobby use
    126121: 07/11/15: Re: Xilinx Virtex-II Newbie
    126125: 07/11/15: Re: Xilinx Virtex-II Newbie
    126128: 07/11/15: Re: Xilinx Virtex-II Newbie
    126152: 07/11/16: Re: Xilinx Virtex-II Newbie
    126237: 07/11/18: Re: Coolrunner in system programming - XAPP0058 - viable?
    126242: 07/11/18: Re: Coolrunner in system programming - XAPP0058 - viable?
    126262: 07/11/19: Re: Coolrunner in system programming - XAPP0058 - viable?
    126270: 07/11/19: Re: Coolrunner in system programming - XAPP0058 - viable?
    126275: 07/11/19: Re: Coolrunner in system programming - XAPP0058 - viable?
    126281: 07/11/19: Re: Coolrunner in system programming - XAPP0058 - viable?
    126311: 07/11/20: Re: Coolrunner in system programming - XAPP0058 - viable?
    126319: 07/11/20: Re: Coolrunner in system programming - XAPP0058 - viable?
    126321: 07/11/20: Re: Coolrunner in system programming - XAPP0058 - viable?
    126324: 07/11/20: Re: Coolrunner in system programming - XAPP0058 - viable?
    126325: 07/11/20: Re: Coolrunner in system programming - XAPP0058 - viable?
    126330: 07/11/20: Re: Coolrunner in system programming - XAPP0058 - viable?
    126333: 07/11/20: Re: Coolrunner in system programming - XAPP0058 - viable?
    126336: 07/11/20: Re: Coolrunner in system programming - XAPP0058 - viable?
    126346: 07/11/20: Re: Coolrunner in system programming - XAPP0058 - viable?
    126385: 07/11/21: Re: Coolrunner in system programming - XAPP0058 - viable?
    126387: 07/11/21: Re: Coolrunner in system programming - XAPP0058 - viable?
    126388: 07/11/21: Re: Coolrunner in system programming - XAPP0058 - viable?
    126420: 07/11/22: Re: Measuring setup and hold time in Lab
    126422: 07/11/22: Re: Measuring setup and hold time in Lab
    126491: 07/11/25: Re: using fpga as programmable connection
    126526: 07/11/27: Re: xilinx spartan 3 + 16 adc
    126562: 07/11/28: Re: CPU design uses too many slices
    126576: 07/11/28: Re: VHDL language is out of date! Why? I will explain.
    126586: 07/11/28: Re: I/O short circuit protection?
    126709: 07/11/30: Re: lossless compression in hardware: what to do in case of uncompressibility?
    126857: 07/12/05: Re: XILINX XABEL
    127062: 07/12/11: Re: GAL16V8
    127088: 07/12/12: Re: Craignell and Darnaw1 Website Updates
    127273: 07/12/17: Re: Why the core dynamic power isn't 0 when the toggle=?ISO-8859-1?Q?_rate_is_0??=
    127334: 07/12/19: Re: VCCIO issue on Xilinx Spartan3E !
    128630: 08/02/01: Re: Why use small resistor for Vcco voltage regulator
    128657: 08/02/02: Re: Why use small resistor for Vcco voltage regulator
    128661: 08/02/02: Re: Why use small resistor for Vcco voltage regulator
    128668: 08/02/03: Re: Why use small resistor for Vcco voltage regulator
    128682: 08/02/04: Re: My first Flash FPGA
    128965: 08/02/12: Re: how to implement this...
    129004: 08/02/13: Re: My first verilog/cpld project
    129055: 08/02/14: Re: When are FPGAs the right choice?
    129063: 08/02/14: Re: Newbie looking for guidance
    129067: 08/02/14: Re: When are FPGAs the right choice?
    129115: 08/02/15: Re: Rom Implementation in a CPLD
    129124: 08/02/15: Re: Virtex-4 input pad failures
    129209: 08/02/19: Re: Ballpark PLB frequency
    129312: 08/02/21: Re: Using Lattice ispLEVER with VHDL libraries
    129315: 08/02/21: Re: MicroBlaze simulator, software ownership rights for SALE
    129318: 08/02/21: Re: FPGA Programming solution
    129355: 08/02/22: Re: Random Number Generation in VHDL
    129528: 08/02/27: Re: Convert some table into combinatorial circuit + optimization
    129529: 08/02/27: Re: Picoblaze enhencement and assembler
    129843: 08/03/07: Re: Blast from the past
    129867: 08/03/08: SiliconBlue enters the FPGA fray
    129871: 08/03/08: Re: SiliconBlue enters the FPGA fray
    129911: 08/03/10: Re: XC3S50-4VQ100C fpga chip
    130008: 08/03/13: Re: SiliconBlue enters the FPGA fray
    130009: 08/03/13: Re: SiliconBlue enters the FPGA fray
    130154: 08/03/17: Re: Designing CPU
    130193: 08/03/18: Re: Designing CPU
    130199: 08/03/18: Re: Designing CPU
    130266: 08/03/19: Re: Optimizing an inferred counter
    130269: 08/03/19: Re: A Challenge for serialized processor design and implementation
    130292: 08/03/20: Re: A Challenge for serialized processor design and implementation
    130302: 08/03/20: Re: A Challenge for serialized processor design and implementation
    130306: 08/03/20: Re: A Challenge for serialized processor design and implementation
    130463: 08/03/25: Re: A Challenge for serialized processor design and implementation
    130464: 08/03/25: Re: A Challenge for serialized processor design and implementation
    130507: 08/03/26: Re: counterfeit Xilinx ?
    130590: 08/03/28: Re: A Challenge for serialized processor design and implementation
    130665: 08/03/30: Re: async clk input, clock glitches
    130666: 08/03/30: Re: async clk input, clock glitches
    130667: 08/03/30: Re: async clk input, clock glitches
    130669: 08/03/30: Re: async clk input, clock glitches
    130670: 08/03/30: Re: ISE 10.1 - Initial experience
    130696: 08/03/31: Re: async clk input, clock glitches
    130704: 08/03/31: Re: async clk input, clock glitches
    130705: 08/03/31: Re: async clk input, clock glitches
    130747: 08/04/01: Re: ISE 10.1 - Initial experience
    130762: 08/04/01: Re: ISE 10.1 - Initial experience
    130801: 08/04/02: Re: now I can talk about it...
    130826: 08/04/03: Re: counterfeit Xilinx ?
    130830: 08/04/03: Re: counterfeit Xilinx ?
    130864: 08/04/04: Re: A Challenge for serialized processor design and implementation
    130883: 08/04/04: Re: A Challenge for serialized processor design and implementation
    130910: 08/04/05: Re: Xilinx FPGA + SMPS
    130915: 08/04/05: Re: Conterfeit parts guidance
    130916: 08/04/05: Re: counterfeit Xilinx ?
    130926: 08/04/05: Re: PLA datasheet - PLS161
    130927: 08/04/05: Re: PLA datasheet - PLS161
    130934: 08/04/06: Re: A Challenge for serialized processor design and implementation
    130950: 08/04/07: Re: Xilinx inferred FIFOs
    130956: 08/04/07: Re: Conterfeit parts guidance
    130977: 08/04/08: Re: counterfeit Xilinx ?
    131030: 08/04/09: Re: Intel plans to tackle cosmic ray threat (actually they have beenworking
    131031: 08/04/09: Re: Modify POF with new ESB (ROM) content?
    131039: 08/04/09: Re: A Challenge for serialized processor design and implementation
    131048: 08/04/09: Re: 32 bit multiplier
    131049: 08/04/09: Re: Disable optimisation - Ring oscillator
    131076: 08/04/10: Re: A Challenge for serialized processor design and implementation
    131084: 08/04/10: Re: 32 bit multiplier
    131135: 08/04/12: Re: Xilinx tech Xclusive
    131139: 08/04/12: Re: Xilinx tech Xclusive
    131680: 08/04/29: Re: Problem writing quadrature decoder
    131921: 08/05/08: Re: ANNC: FPGA Design Software Webcast
    131924: 08/05/08: Re: Problem writing quadrature decoder
    131937: 08/05/08: Re: Problem writing quadrature decoder
    131965: 08/05/09: Re: ANNC: FPGA Design Software Webcast
    132003: 08/05/10: Re: 5 V oscillator output to GCLK
    132013: 08/05/10: Re: 5 V oscillator output to GCLK
    132015: 08/05/10: Re: 5 V oscillator output to GCLK
    132022: 08/05/10: Re: 5 V oscillator output to GCLK
    132023: 08/05/10: Re: Problem writing quadrature decoder
    132039: 08/05/11: Re: Problem writing quadrature decoder
    132045: 08/05/12: Re: Problem writing quadrature decoder
    132049: 08/05/12: Re: Problem writing quadrature decoder
    132054: 08/05/12: Re: Problem writing quadrature decoder
    132073: 08/05/13: Re: Problem writing quadrature decoder
    132077: 08/05/13: Re: Problem writing quadrature decoder
    132078: 08/05/13: Re: Problem writing quadrature decoder
    132079: 08/05/13: Re: Problem writing quadrature decoder
    132080: 08/05/13: Re: Problem writing quadrature decoder
    132082: 08/05/13: Re: Programming XCR3064xl - voltage at output stuck at 0
    132084: 08/05/13: Re: Problem writing quadrature decoder
    132085: 08/05/13: Re: Problem writing quadrature decoder
    132088: 08/05/13: Re: Problem writing quadrature decoder
    132091: 08/05/13: Re: Problem writing quadrature decoder
    132096: 08/05/14: Re: Problem writing quadrature decoder
    132104: 08/05/14: Re: Problem writing quadrature decoder
    132106: 08/05/14: Re: Problem writing quadrature decoder
    132111: 08/05/14: Re: Problem writing quadrature decoder
    132113: 08/05/14: Re: Yay! We're done with the quadrature encoder!
    132124: 08/05/15: Re: Programming XCR3064xl - voltage at output stuck at 0
    132250: 08/05/20: Re: Resetting FPGA Without watch dog timer
    132255: 08/05/20: Re: Stratix IV Announced
    132292: 08/05/21: Re: bizarre state machine behavior
    132321: 08/05/22: Re: Stratix IV Announced
    132322: 08/05/22: Re: Every newbie's favorite project: the Quadrature Rotary Encoder
    132331: 08/05/22: Re: bizarre state machine behavior
    132450: 08/05/28: Mathstar plans to discontinue FPOA development
    132455: 08/05/28: Re: 'Nother one bites the dust
    132490: 08/05/29: Re: Sequentially syncrhronous
    132491: 08/05/29: Re: Sequentially syncrhronous
    132492: 08/05/29: Re: Sequentially syncrhronous
    132500: 08/05/29: Re: Are FPGAs headed toward a coarse granularity?
    132654: 08/06/05: Re: Xilinx vs Altera
    132657: 08/06/05: Re: Xilinx vs Altera
    132659: 08/06/05: Re: Xilinx cuts 250 jobs.
    132660: 08/06/05: A new FPGA company comes out of Stealth mode - SiliconBlue
    132725: 08/06/06: Re: ANNOUNCE:-- TimingAnalyzer Free Version -- Draw timing diagrams
    132727: 08/06/06: Re: A new FPGA company comes out of Stealth mode - SiliconBlue
    132730: 08/06/06: Re: A new FPGA company comes out of Stealth mode - SiliconBlue
    132735: 08/06/06: Re: Xilinx vs Altera
    132750: 08/06/06: Re: ANNOUNCE: SiliconBlue Pioneers New FPGA Technology for Handheld,
    132764: 08/06/06: Re: xilinx and jtag
    132800: 08/06/07: Re: A new FPGA company comes out of Stealth mode - SiliconBlue
    132807: 08/06/07: Re: ANNOUNCE:-- TimingAnalyzer Free Version -- Draw timing diagrams
    132925: 08/06/11: Re: Cheating the FPGA clock speed
    133007: 08/06/13: Re: HELP: a Funny asynchronous input design
    133016: 08/06/14: Re: CPLD beginner questions
    133020: 08/06/14: Re: CPLD beginner questions
    133027: 08/06/14: Re: HELP: a Funny asynchronous input design
    133029: 08/06/14: Re: CPLD beginner questions
    133040: 08/06/15: Re: FPGA IO Pin Unwanted Coupling
    133133: 08/06/19: Re: =?windows-1252?Q?NVIDIA=92s_Tesla_T10P_Blurs_Some_?=
    133400: 08/06/27: Re: NVRAM design in CPLD
    133418: 08/06/28: Re: Standard forms for Karnaugh maps?
    133424: 08/06/28: Re: Standard forms for Karnaugh maps?
    133433: 08/06/29: Re: Standard forms for Karnaugh maps?
    133500: 08/07/02: Re: Nintendo DS Screenshots / Video Capture
    133512: 08/07/02: Re: How do I program an fpga once it has been designed and layout
    133589: 08/07/05: Re: Single ended interface at 70Mhz for FPGAs
    133634: 08/07/08: Re: Virtex 4 expected production end-of-life
    133966: 08/07/21: Re: The littlest CPU
    134142: 08/07/28: Re: vhdl code for debouncing push button
    134178: 08/07/29: Re: vhdl code for debouncing push button
    134179: 08/07/29: Re: vhdl code for debouncing push button
    134189: 08/07/30: Re: vhdl code for debouncing push button
    134294: 08/08/05: Altera sues Zilog - signs of desperation from Programmable Vendor
    134341: 08/08/07: Re: Altera sues Zilog - signs of desperation from Programmable Vendor
    134342: 08/08/07: Re: Downsizing Verilog synthesization.
    134364: 08/08/08: Re: Downsizing Verilog synthesization.
    134369: 08/08/08: Re: Downsizing Verilog synthesization.
    134373: 08/08/08: Re: Downsizing Verilog synthesization.
    134399: 08/08/09: Re: Downsizing Verilog synthesization.
    134401: 08/08/09: Re: Downsizing Verilog synthesization.
    134408: 08/08/09: Re: Coolrunner programming - best way?
    134418: 08/08/10: Re: Downsizing Verilog synthesization.
    134419: 08/08/10: Re: Downsizing Verilog synthesization.
    134437: 08/08/11: Re: Downsizing Verilog synthesization.
    134445: 08/08/11: Re: Altera question - MAX3000 vs MAX7000
    134458: 08/08/12: Re: Downsizing Verilog synthesization.
    134707: 08/08/27: Re: need fast FPGA suggestions
    134720: 08/08/28: Re: need fast FPGA suggestions
    134722: 08/08/28: Re: need fast FPGA suggestions
    134752: 08/08/29: Re: need fast FPGA suggestions
    134754: 08/08/29: Re: need fast FPGA suggestions
    134759: 08/08/29: Re: crazy patent
    134847: 08/09/04: Re: XST bug on illigal states of a FSM ?
    135019: 08/09/11: Re: WinCupl Problem(s)
    135064: 08/09/13: Re: Ultra low power FPGAs
    135066: 08/09/13: Re: Seeking several async. SRAMs at 8ns ( IS61LV51216-8T or GS74116TP-8)
    135085: 08/09/15: Re: Ultra low power FPGAs
    135140: 08/09/18: Re: Random Mask Generation on FPGAs
    135465: 08/10/03: Re: Standalone Altera production programmer
    135641: 08/10/11: Re: Lattice vs Altera (Mico32 / NIOS)....or?
    135701: 08/10/13: Re: Lattice vs Altera (Mico32 / NIOS)....or?
    135777: 08/10/16: Re: free cpu 8051 verilog code
    135779: 08/10/16: Re: sensitive fpga
    135803: 08/10/16: Re: A couple of CPLD design challenges for the group
    135804: 08/10/16: Re: A couple of CPLD design challenges for the group
    135820: 08/10/17: Re: A couple of CPLD design challenges for the group
    135823: 08/10/17: Re: A couple of CPLD design challenges for the group
    135831: 08/10/17: Re: Using GCK pin as both clock and signal (Spartan 2)
    135855: 08/10/18: Re: Using GCK pin as both clock and signal (Spartan 2)
    135866: 08/10/19: Re: A couple of CPLD design challenges for the group
    135873: 08/10/20: Re: Field update
    136006: 08/10/27: Re: Learning WinCUPL; Tried Atmel Suppport but no solution!
    136045: 08/10/29: Re: Learning WinCUPL; Tried Atmel Suppport but no solution!
    136256: 08/11/08: Re: Tilera multicore replaces FPGA?
    136407: 08/11/15: Re: What happened to the Cyclone IV?
    136424: 08/11/16: Re: What happened to the Cyclone IV?
    136658: 08/11/29: Re: EPLD - FPGA - Is there a difference
    151370: 11/03/28: Re: MAX II CPLD and I2S Clock divider jitter
    151372: 11/03/28: Re: MAX II CPLD and I2S Clock divider jitter
    151603: 11/04/25: Re: Lattice Breakout Boards
    152096: 11/07/05: Re: Delta-Sigma in an FPGA
    152118: 11/07/10: Re: VHDL rollover of counter
    152128: 11/07/11: Re: VHDL rollover of counter
    152508: 11/08/29: Re: Very cheap Spartan3 board that can be configured by simple USB
    152509: 11/08/29: Re: A free lunch
    152512: 11/08/29: Re: Very cheap Spartan3 board that can be configured by simple USB
    152563: 11/09/14: Re: Xilinx Tin Whiskers ?
    152730: 11/10/13: Re: Spartan changes in glitch sensitivity
    153137: 11/12/09: Re: Lattice buys SiBlue for $62 million
    153445: 12/02/26: Re: What is a PLD/FPGA with serial or Ethernet port logic or block
    153451: 12/02/27: Re: What is a PLD/FPGA with serial or Ethernet port logic or block
Jim Hamblen:
    22086: 00/04/20: Re: VGA interface and VHDL
    22095: 00/04/21: Re: MaxPlus9.5 License and Fitter problems
Jim Hearne:
    11178: 98/07/23: Logic Lab Gal Programmer
Jim Horn:
    159195: 16/08/30: Altera USB Blaster clone driver for STM32F1xx
Jim Hwang:
    31771: 01/06/05: Re: XtremeDSP Ready for prime time?
    43660: 02/05/28: Re: Addressable shift register
Jim Jones:
    153649: 12/04/09: FPGAs directly plugged into CPU socket
Jim Kapcio:
    2394: 95/11/28: Checksum from .pof file
Jim Kearney:
    38979: 02/01/29: Re: The LUT puzzle, Iam on the way
    39516: 02/02/12: Re: Spartan Program/Verify
    39540: 02/02/13: Re: Spartan Program/Verify
    39581: 02/02/13: Re: Altera's new family Stratix
    40561: 02/03/10: Re: Xilinx Download Cable Connectors
    40611: 02/03/11: Re: Xilinx Download Cable Connectors
    45199: 02/07/15: Re: Which is best method for register with settable and clearable bits
    54336: 03/04/08: Re: Xilinx Impact and USB/LPT ports
    54362: 03/04/09: Re: Xilinx Impact and USB/LPT ports
    59639: 03/08/25: Re: Reusing CCLK line after configuration for Spartan-II
    59670: 03/08/25: Re: Reusing CCLK line after configuration for Spartan-II
Jim King:
    14095: 99/01/13: Re: Problems with processes
    14096: 99/01/13: Re: Problems with processes
    14115: 99/01/14: Ratings for Synplicity Synplify
    14120: 99/01/14: Re: Problem with reducing bus width / Foundation Series v1.5
    14140: 99/01/15: General FPGA introduction needed
    14656: 99/02/09: Re: Benchmarks: Schematic vs Synthesis (Exemplar vs Synplicity)
    14503: 99/02/02: Re: FPGA Express Evaluation...
Jim Kipps:
    15958: 99/04/23: Re: fpga express stripping out Viewlogic busses
    15959: 99/04/23: Re: Viewlogic FPGA Express vs Xilinx FPGA Express....any difference?
    16184: 99/05/07: Re: [Q]Do you recommend Altera MAXPLUS II9.01 as a VHDL compiler for
    16286: 99/05/13: Re: How synthesize tools concern with size of the design?
    16313: 99/05/14: Re: How synthesize tools concern with size of the design?
    16356: 99/05/18: Case study: Viewlogic's IntelliFlow
    16409: 99/05/20: Re: Foundation FPGA Express
    16410: 99/05/20: Re: Case study: Viewlogic's IntelliFlow
    16467: 99/05/24: Re: How synthesize tools concern with size of the design?
    16872: 99/06/15: Re: FPGA Express 3.00
    16941: 99/06/18: Re: vhdl and viewlogic problem
    17011: 99/06/24: Re: Viewdraw + Foundation Express design flow
    17012: 99/06/24: Re: Synopsys FPGA Express vs. Compiler II
    17013: 99/06/24: Re: Synopsys DC & FPGA Compiler
Jim Kruse:
    553: 94/12/30: Re: LPM Docs & Resources
Jim LaLone:
    294: 94/10/14: Re: Xilinx configuration
Jim Lewis:
    13997: 99/01/06: Re: VHDL Bit String Literals
    15989: 99/04/26: VHDL Class, May 26-27, Portland Or.
    50164: 02/12/03: Re: register OR latch ? (source code)
    50286: 02/12/07: Re: Warnings in FPGA express
    50784: 02/12/19: Re: How to asynchronously reset a flip-flop?
    50858: 02/12/20: Re: FPGA Supercomputing opportunity
    51450: 03/01/13: Re: How to coerce a list of discrete signals to an array in VHDL
    51770: 03/01/21: Re: A Request: VHDL Source of a 32bit Floating Point ALU - Still
    54671: 03/04/15: Re: synthesis of a VHDL module in Xilinx
    59338: 03/08/15: Re: Synthesisable fixed-point arithmetic package
    61551: 03/10/06: Re: Implementing multiple registers with one single input output
    62146: 03/10/20: Re: Subroutine in VHDL?
    62184: 03/10/21: Re: 74 logic to CPLD. how easy for a Newbie?
    62560: 03/11/01: Re: simulation stops preliminarily
    62683: 03/11/04: Re: Video Scan Conversion Rate - Camera Input to DVI Display Output
    62894: 03/11/10: Re: Reverse engineering an EDIF file?
    64520: 04/01/06: Re: How do you initialize signals in VHDL?
    64695: 04/01/11: Re: Synthesis in VHDL vs. Verilog
    64696: 04/01/11: Re: Synthesis in VHDL vs. Verilog
    64740: 04/01/12: Re: Synthesis in VHDL vs. Verilog
    64783: 04/01/13: Re: Synthesis in VHDL vs. Verilog
    64788: 04/01/13: Re: Synthesis in VHDL vs. Verilog
    64931: 04/01/16: Re: Please help with Xilinx ISE Schematic question
    65195: 04/01/21: Re: Soft failures (?) 9536XL
    65262: 04/01/22: Re: Synthesizing pipelined multipliers in Synplify Pro
    65351: 04/01/25: Re: VHDL newbie
    65460: 04/01/29: Re: FPGA basics
    65528: 04/02/01: Re: Syn. warning
    67209: 04/03/08: Re: strange error
    67347: 04/03/10: Re: very strange error
    68030: 04/03/24: Re: study verilog or vhdl?
    68059: 04/03/25: Re: study verilog or vhdl?
    68143: 04/03/27: Re: study verilog or vhdl?
    68187: 04/03/29: Re: study verilog or vhdl?
    68451: 04/04/05: Re: VHDL: Use of literal '1' on an input port ?
    68492: 04/04/06: Re: Which HVL is the most popular?
    68534: 04/04/07: Re: VHDL: Use of literal '1' on an input port ?
    68744: 04/04/16: Re: Bus interface?
    68880: 04/04/20: Re: reading files in vhdl
    69187: 04/04/29: Re: good starter kit
    69306: 04/05/05: Re: How to drive record fields from procedure AND testbench?
    69335: 04/05/06: Re: How to drive record fields from procedure AND testbench?
    69337: 04/05/06: Re: How to drive record fields from procedure AND testbench?
    69348: 04/05/07: Re: How to drive record fields from procedure AND testbench?
    69401: 04/05/10: RAM inference and Standards
    69402: 04/05/10: Re: Easypath question (was "Hard-tocopy" rant)
    69408: 04/05/10: Re: Monolithic state machine or structured state machine?
    69412: 04/05/10: Re: Monolithic state machine or structured state machine?
    69617: 04/05/15: Re: One issue about free hardware
    71292: 04/07/13: Re: FSM in illegal state (conclusion)
    71314: 04/07/14: Re: FSM in illegal state (conclusion)
    71325: 04/07/14: Re: FSM in illegal state (conclusion)
    73774: 04/09/29: Re: Clock Edge notation
    73449: 04/09/21: Re: combinatorial loops / feedback paths discussion
    73603: 04/09/24: Re: Getting info from a digital line
    75295: 04/11/01: Re: XST: suppressing incorrect optimizations in VHDL code
    75329: 04/11/02: Re: "frying" FPGAs
    75349: 04/11/02: Re: "frying" FPGAs
    74751: 04/10/18: Re: VHDL code for Type and Components
    74843: 04/10/20: Re: VHDL help needed ($)
    75382: 04/11/03: Re: XILINX Webpack VHDL synthesis question (unnecessary MUX infered)
    75405: 04/11/04: Re: XILINX Webpack VHDL synthesis question (unnecessary MUX infered)
    75568: 04/11/09: Re: xilinx webpack simulation problem (latch in place of logic)
    76197: 04/11/28: Re: dual-write port BRAM with XST/Webpack
    76628: 04/12/07: Re: Verilog Book Recommendation
    76643: 04/12/07: Re: "Hello World" project for an FPGA (on a Spartan3 board)
    77076: 04/12/21: Re: low cost Altera MAX II development kit with more I/O pins?
    77283: 05/01/03: Re: Recover FPGA Verilog or VHDL source from .SOF file
    77335: 05/01/04: Re: Procedure exit on global signal
    79053: 05/02/11: Re: ISE and IEEE.Fixed_pkg (fixed point math for synth?)
    90431: 05/10/12: Re: VHDL : Use concatenation on port mapping
    109278: 06/09/22: Call for Participation Accellera VHDL Verification Features
    111987: 06/11/14: Re: Nested Generate Statement in VHDL
    113986: 07/01/01: Re: Matlab (.m) to VHDL
    114156: 07/01/05: Re: DC timing violation, what to do first?
    115434: 07/02/10: Re: Setting VHDL standard in Xilinx ISE
    116266: 07/03/05: Re: VHDL and Latch
    116402: 07/03/08: Re: How to implement pipeline in this case?
    116411: 07/03/08: Re: VHDL and Latch
    116435: 07/03/08: Re: VHDL and Latch
    116437: 07/03/08: Re: VHDL and Latch
    117222: 07/03/26: Re: A suggestion for a new input interface for functions in VHDL:
    117263: 07/03/27: Re: A suggestion for a new input interface for functions in VHDL:
    117277: 07/03/27: Re: A suggestion for a new input interface for functions in VHDL:
    117339: 07/03/28: Re: A suggestion for a new input interface for functions in VHDL:
    117383: 07/03/29: RFC: Enhancing VHDL for OO, Randomization, Functional Coverage
    117434: 07/03/30: Re: A suggestion for a new input interface for functions in VHDL:
    117531: 07/04/03: RFC: VHDL testbench enhancements
    117538: 07/04/03: Re: RFC: VHDL testbench enhancements
    118733: 07/05/02: Re: debounce state diagram FSM - topical
    119498: 07/05/21: Re: VHDL newbie: building sequential circuits with basic gates
    119507: 07/05/21: Re: VHDL newbie: building sequential circuits with basic gates
    123463: 07/08/28: Re: Null statement in VHDL
    123465: 07/08/28: Re: New keyword 'orif' and its implications
    123478: 07/08/28: Re: New keyword 'orif' and its implications
    123576: 07/08/30: Re: New keyword 'orif' and its implications
    123577: 07/08/30: Re: New keyword 'orif' and its implications
    123594: 07/08/30: Re: New keyword 'orif' and its implications
    123600: 07/08/30: Re: New keyword 'orif' and its implications
    123601: 07/08/30: Re: New keyword 'orif' and its implications
    123639: 07/08/31: Re: New keyword 'orif' and its implications
    123672: 07/08/31: Re: New keyword 'orif' and its implications
    123850: 07/09/05: Re: New keyword 'orif' and its implications
    123851: 07/09/05: Re: New keyword 'orif' and its implications
    124357: 07/09/19: Re: Guess: what is the largest number of state machines in a current
    129465: 08/02/25: Re: Seed Values
    129497: 08/02/26: Re: Seed Values
    131322: 08/04/18: Re: Which to learn: Verilog vs. VHDL?
    131323: 08/04/18: Re: Which to learn: Verilog vs. VHDL?
    131777: 08/05/01: Re: sobel in vhdl
    136480: 08/11/18: Re: Aligned PLL clocks in RTL simulation
    136504: 08/11/19: Re: Aligned PLL clocks in RTL simulation
    137526: 09/01/21: Re: Digilent USB Cable supported Devices
    138389: 09/02/18: Re: VHDL long elsif state machine
    156356: 14/03/17: Re: full functional coverage
    156357: 14/03/17: Re: full functional coverage
    156366: 14/03/19: Re: full functional coverage
    156371: 14/03/19: Re: full functional coverage
    156372: 14/03/19: Re: full functional coverage
    156379: 14/03/20: Re: full functional coverage
    157106: 14/10/13: Re: looking for systemC/TLM 2.0 courses
Jim Lewis, ASIC and HDL Consultant:
    3865: 96/08/12: Technical Job posting ( and ads) not related to the newsgroup.
    3866: 96/08/12: Technical Job posting ( and ads) not related to the newsgroup.
Jim Lyke:
    15827: 99/04/15: subscribe
    47380: 02/09/25: Where can I get XC6200 series FPGAs
Jim M.:
    54597: 03/04/14: NIOS 3.0 Fmax and other Issues
    54659: 03/04/15: Re: NIOS 3.0 Fmax and other Issues
    54749: 03/04/17: Re: NIOS 3.0 Fmax and other Issues
    54751: 03/04/17: Avalon Bus Master
    54901: 03/04/21: Re: Avalon Bus Master
    54902: 03/04/21: NIOS 3.0 Spurious Interrupts
    54934: 03/04/22: Re: NIOS 3.0 Fmax and other Issues
    54968: 03/04/23: Re: NIOS 3.0 Spurious Interrupts
    55012: 03/04/24: Re: NIOS 3.0 Spurious Interrupts
    55022: 03/04/24: Declaring variables with NIOS and GNUPro Tools
    55024: 03/04/24: Re: NIOS 3.0 Fmax and other Issues
    55128: 03/04/28: NIOS Development Board and Flash Protection
    55163: 03/04/29: Re: NIOS Development Board and Flash Protection
    55256: 03/05/01: Re: Schmitt Trigger an a Virtex
    55387: 03/05/06: Re: MJL Stratix Dev Kit
    57795: 03/07/07: Re: Problem with user defined logicinterface in Nios
Jim McCloskey:
    10219: 98/05/05: 3.3V design conversion
Jim McGinnis:
    45383: 02/07/21: Re: TMS 1000
Jim McGrath:
    8873: 98/02/03: combining Altera .sof files
Jim McManus:
    5407: 97/02/13: Re: PCI Prototyping board with a XC4013E or XC4013EX
    6084: 97/04/10: Re: PCI and DRAM control - Xilinx 4000 -Verilog
    7307: 97/08/24: Re: Xilinx PCI simulation problem...
    17207: 99/07/08: Re: PCI interface
    17222: 99/07/10: Re: PCI interface
    17276: 99/07/15: Re: PCI interface
    17277: 99/07/15: Re: PCI interface
    18215: 99/10/07: Re: Virtex and PCI 5V?
    18214: 99/10/07: Re: HOT II PCI Development System
    19966: 00/01/20: Re: which PLD support Hot-swap
    21094: 00/03/06: Re: PCI reflected wave switching spec ???
    25101: 00/08/25: Re: PCI macros
Jim Mrowca:
    5698: 97/03/07: Re: Introducing Renoir
Jim Patterson:
    22521: 00/05/11: Info on using Reconfig feature of Virtex?
    26788: 00/10/29: help on a simple ALU
    26792: 00/10/29: Re: help on a simple ALU
    46384: 02/08/28: Re: Anyone already on QUARTUS II V2.1 ?
    46385: 02/08/28: Re: Stratix Experience
Jim Pennell:
    28050: 00/12/19: Re: 3V -> 5V clock signal level conversion
Jim Peterson:
    2977: 96/03/07: Re: Reconfigurable Computing Languages
    9462: 98/03/15: Xilinx could gaurd its secrets better (Re: Strange Xilinx question?)
    11524: 98/08/20: Re: half full flag in a xilinx async fifo?
    11544: 98/08/21: Re: Big FPGA on PCI card with Linux support?
Jim Poder:
    30926: 01/05/03: Re: Serial UART
Jim Ranlett:
    55859: 03/05/21: Asynchronous State Machines and HDLs
Jim Raynor:
    41949: 02/04/11: Price List ?
    42084: 02/04/15: FPGA parameters
    42299: 02/04/19: XC9500XL problem
    44039: 02/06/10: Spartan II E -- BUFGDLL
    44044: 02/06/10: BUFGDLL again
    44090: 02/06/11: Multi Pass PAR
    44737: 02/06/28: Re: blank CPLD
    44975: 02/07/08: loading Spartan 2E configuration
    45044: 02/07/11: Re: FPGA/CPLD Decision help?
    45490: 02/07/24: vhdl dll question....help please
    45499: 02/07/24: XST vs FPGA Express???
    46417: 02/08/28: Problem: Spartan 2 E CCLK
    51422: 03/01/13: Simulate Virtex Primitive using ModelSim
    51435: 03/01/13: Re: Simulate Virtex Primitive using ModelSim
    52324: 03/02/07: HELP NEEDED
Jim Robinson:
    58407: 03/07/22: Re: Synplify syn_direct_enable doesn't work for me.
    58497: 03/07/24: Re: Synplify syn_direct_enable doesn't work for me.
    67919: 04/03/22: Free trial of Identify Lite RTL Debugger for Xilinx
Jim Roehn:
    5348: 97/02/09: Re: X84 board VHDL examples
Jim Sackman:
    3594: 96/07/02: Re: Need recommendation for PCI interface on 68332
Jim Stewart:
    21089: 00/03/06: Stupid Foundation question
    37259: 01/12/05: Re: For Sale: Huge Xilinx FPGA lots
    44273: 02/06/15: Stupid WebPack question
    44275: 02/06/15: Re: Stupid WebPack question
    44277: 02/06/15: Re: Stupid WebPack question
    44313: 02/06/17: Another stupid WebPack question
    44627: 02/06/24: Re: too hot fpga device
    54414: 03/04/10: Webpack 5.2 and Win98se
    54428: 03/04/10: Re: Webpack 5.2 and Win98se
    54436: 03/04/10: Re: Webpack 5.2 and Win98se
    54494: 03/04/11: Re: Buying FPGAs from parts brokers
    54874: 03/04/21: Re: Webpack 5.2 Install problems?
    54878: 03/04/21: Re: Webpack 5.2 Install problems?
    54974: 03/04/23: Re: Webpack 5.2 Install problems?
    55144: 03/04/28: Re: Low pin count SOC
    55209: 03/04/30: Re: Boycott All Xilinx products untill they correct all ISE softwareerrors
    55250: 03/05/01: Re: Boycott All Xilinx products untill they correct all ISE softwareerrors
    55449: 03/05/08: Re: Software and hardware monopoly is bad
    55552: 03/05/12: Re: Price of CPLDs
    73508: 04/09/22: Re: [ALTERA] NIOS-II + MMU + FPU
    73649: 04/09/27: Re: embedded linux on FPGA?
    74868: 04/10/20: Re: Introducing MANIK - a 32 bit Soft-Core RISC Processor
    95539: 06/01/23: Re: OT:Shooting Ourselves in the Foot
    95554: 06/01/23: Re: OT:Shooting Ourselves in the Foot
    107531: 06/08/29: Re: September training?
    108137: 06/09/05: Re: Please help me with (insert task here)
    108217: 06/09/06: Re: Please help me with (insert task here)
    108224: 06/09/06: Re: Please help me with (insert task here)
    125360: 07/10/23: Re: Changing refresh rate for DRAM while in operation?
    146539: 10/03/22: Re: Finally, selling my old Xilinx/Viewlogic software package
Jim Stockton:
    55221: 03/04/30: Re: Low power, high temperature CPLD
Jim Sung:
    3856: 96/08/09: An incompatible problem of ALTERA MAXPLUS2 Ver6.2, Ver 6.1 -- need your help
    3877: 96/08/13: Re: An incompatible problem of ALTERA MAXPLUS2 Ver6.2, Ver 6.1 -- need your help
Jim Ternus:
    8384: 97/12/11: Royalties Agreement
Jim Thomas:
    43423: 02/05/21: Re: SDRAM pricing
    109266: 06/09/22: Re: Dell Laptop for Embedded Work
Jim Thompson:
    64377: 03/12/31: Re: SOS : 4-bit binary divider circuit PLEASE!!!!!!!
    64414: 04/01/02: Re: SOS : 4-bit binary divider circuit PLEASE!!!!!!!
    87908: 05/08/03: Re: System Engineering in the R/D World
    87958: 05/08/04: Re: System Engineering in the R/D World
    87959: 05/08/04: Re: System Engineering in the R/D World
    93196: 05/12/15: Re: Xilinx' encrypted HPICE models in PSPICE
    95587: 06/01/24: Re: Very OT: Americanized family names
    95009: 06/01/20: Re: OT:Shooting Ourselves in the Foot
    95010: 06/01/20: Re: OT:Shooting Ourselves in the Foot
    95032: 06/01/20: Re: OT:Shooting Ourselves in the Foot
    95033: 06/01/20: Re: OT:Shooting Ourselves in the Foot
    95037: 06/01/20: Re: OT:Shooting Ourselves in the Foot
    95047: 06/01/20: Re: OT:Shooting Ourselves in the Foot
    95049: 06/01/20: Re: OT:Shooting Ourselves in the Foot
    95079: 06/01/20: Re: OT:Shooting Ourselves in the Foot
    95109: 06/01/20: Re: OT:Shooting Ourselves in the Foot
    95110: 06/01/20: Re: OT:Shooting Ourselves in the Foot
    95118: 06/01/20: Re: OT:Shooting Ourselves in the Foot
    95128: 06/01/20: Re: OT:Shooting Ourselves in the Foot
    95136: 06/01/20: Re: OT:Shooting Ourselves in the Foot
    95139: 06/01/20: Re: OT:Shooting Ourselves in the Foot
    95149: 06/01/20: Re: OT:Shooting Ourselves in the Foot
    95281: 06/01/21: Re: OT:Shooting Ourselves in the Foot
    95341: 06/01/22: Re: OT:Shooting Ourselves in the Foot
    95404: 06/01/23: Re: OT:Shooting Ourselves in the Foot
    95447: 06/01/23: Re: OT:Shooting Ourselves in the Foot
    99879: 06/03/30: Re: deglitching a clock
    99885: 06/03/30: Re: deglitching a clock
    107655: 06/08/30: Re: Performance Appraisals
    107656: 06/08/30: Re: Performance Appraisals
    108098: 06/09/05: Re: Please help me with (insert task here)
    112290: 06/11/19: Re: board - T562.jpg
    112593: 06/11/25: Re: board - T562.jpg
    112600: 06/11/25: Re: board - T562.jpg
    112619: 06/11/26: Re: board - T562.jpg
    112628: 06/11/26: Re: board - T562.jpg
    112674: 06/11/27: Re: Was: board - T562.jpg, Now: Switched cap voltage regulator
    114205: 07/01/07: Re: Basic questions about digital phase locked loop
    129560: 08/02/27: Re: ADC to FPGA Interface Webcast
    145461: 10/02/10: Re: Tieing Off Unused Pins in Quartus II Blocks
Jim Toerresen:
    3331: 96/05/14: Evolvable HW
    3369: 96/05/22: Re: Evolvable HW
    3408: 96/05/25: Re: Evolvable HW
Jim Tompkins:
    53: 94/08/04: Intel iFX questions
    199: 94/09/19: PLD for async state machine?
    1808: 95/09/05: FPGA to masked gate array conversion
Jim Wang:
    72257: 04/08/12: Can PPC in V2P reconfig the FPGA slices?
    72265: 04/08/12: Re: Attention Xilinx: command line tools would be useful [Was: Re: why?]
Jim Watts:
    28772: 01/01/24: Re: APEX
    28773: 01/01/24: Re: Fixing pins on Spartan II
    28774: 01/01/24: Re: About programming cables
    28775: 01/01/24: Re: VHDL question
Jim Weir:
    2730: 96/01/31: Re: GAL programming for hobby use...Is there no hope?
    11570: 98/08/24: Re: New Evolutionary Electronics Book
Jim West:
    3283: 96/05/09: Re: What EPLD system to buy ?
Jim Wu:
    52617: 03/02/16: Re: VITAL_primitives Library in Xilinx WebPack
    52640: 03/02/17: Re: Measuring die temperature
    52653: 03/02/18: Re: Xilinx Filter
    52703: 03/02/19: Re: WebPack 4.2i and Block RAM instantiation
    52705: 03/02/19: Re: crc implementation
    52832: 03/02/24: Re: Program a Serial Data Flash - SPI - Interface through a CPLD via JTAG
    52884: 03/02/25: Re: Program a Serial Data Flash - SPI - Interface through a CPLD via JTAG
    53082: 03/03/03: Re: Bus Functional Model
    53083: 03/03/03: Re: Startup latency...
    53170: 03/03/05: Re: Startup latency
    53172: 03/03/05: Re: Bus Functional Model
    53231: 03/03/07: Re: JTAG
    58566: 03/07/26: Re: Simple circuit / good design?
    58943: 03/08/04: Re: how to protect own IP in Xilinx ISE
    58981: 03/08/05: Re: model sim block ram sim
    59024: 03/08/06: Re: How to use EAB in Altera FPGA?
    59027: 03/08/06: Re: How to use EAB in Altera FPGA?
    59032: 03/08/06: Does Xilinx Webpack 5.2 work on WinNT SP6?
    59033: 03/08/06: Re: power saving condition test ?
    59054: 03/08/07: Re: power saving condition test ?
    59066: 03/08/07: Re: How to find the intersection of two vectors?
    59151: 03/08/10: Re: a quick searching problem
    59166: 03/08/11: Re: Upgrading OS or WebPack
    59191: 03/08/11: Re: a quick searching problem
    59197: 03/08/12: Data Structure Viewer
    59251: 03/08/13: Re: Error please Help
    59261: 03/08/13: Re: Error please Help
    59363: 03/08/16: Re: xilinx PAR removing Logic
    59378: 03/08/17: Re: custom memory array implementaion
    59762: 03/08/28: Re: Help ! compxlib Error " mti_se not found" while Bulding XILINX libraries for ModelSim SE
    59779: 03/08/28: Re: Implementing FIFO in Spartan-II
    59943: 03/09/02: Re: how to design this datapath unit for DSP using VHDL/Verilog?
    61624: 03/10/08: Re: ASIC/FPGA programming
    63089: 03/11/14: Re: Reading back SRAM content via JTAG?
    63139: 03/11/16: Re: Reading back SRAM content via JTAG?
    67854: 04/03/21: Re: How do I read the INIT values in blockRAM?
    67875: 04/03/22: Re: How do I read the INIT values in blockRAM?
    68556: 04/04/08: Re: how to use a .ucf file?
    68640: 04/04/12: Re: Problems installing ISE 6.2 under Linux
    68915: 04/04/22: Re: Compiling library problem in Xilinx ISE4.0?
    69314: 04/05/06: Re: bitgen progarm in ISE
    69357: 04/05/07: Re: Error while simulation with XILINX DCM
    69358: 04/05/07: Re: ChipScope Core Generator Flow
    69554: 04/05/13: Re: program flash memory through JTAG on FPGA
    69562: 04/05/14: Re: instantiate an edf module with ise
    69870: 04/05/23: Re: Reg learning FPGA backend
    71132: 04/07/09: Re: Synthesis failure Xilinx WebPack XST
    71521: 04/07/21: Re: Area constraint on a sub-module
    72245: 04/08/12: Looking for suggestions/recommendations on 64-bit Linux machine
    72710: 04/08/29: Re: Floorplanner RPM question
    72742: 04/08/31: Re: Installing Xilinx ISEWebPack under Wine
    72784: 04/09/01: Re: Floorplanner RPM question
    72831: 04/09/03: Re: Fanout Xilinx
    73907: 04/09/30: Re: Xilinx Timing Constraints
    73911: 04/09/30: Re: luts are optimized away
    75868: 04/11/17: Re: Setup violation warning with constant signal in Modelsim/Webpack
    75872: 04/11/17: Re: Xilinx, VHDL, Verilog, ModelSim, BMP
    75873: 04/11/17: Re: Xilinx, VHDL, Verilog, ModelSim, BMP
    75878: 04/11/17: Re: Xilinx, VHDL, Verilog, ModelSim, BMP
    75879: 04/11/17: Re: Xilinx, VHDL, Verilog, ModelSim, BMP
    75901: 04/11/18: Re: Xilinx, VHDL, Verilog, ModelSim, BMP
    75927: 04/11/19: Re: Xilinx, VHDL, Verilog, ModelSim, BMP
    76420: 04/12/01: Re: Stupid tools question...
    78393: 05/01/31: Re: Listing unrouted nets in FPGA Editor
    78591: 05/02/03: Re: Modifying a post PAR xilinx design
    79265: 05/02/16: Re: How to display synplify_pro version in tcl command
    79267: 05/02/16: Re: Orcad schematic and footprint libraries for Xilinx Spartan 3 FPGA's
    79398: 05/02/18: Re: Input Timing Specification
    79788: 05/02/24: Re: How to synthesize the xilinx ip core?
    80966: 05/03/15: Re: Calling netlist module in a design
    81074: 05/03/17: Re: Using XC2V6000 to send/receive test vectors.
    81157: 05/03/18: Re: Using XC2V6000 to send/receive test vectors.
    81604: 05/03/28: Re: Xilinx- Extract a pin layout
    81605: 05/03/28: Re: using (verilog) reg as memory
    81719: 05/03/30: Re: using (verilog) reg as memory
    81720: 05/03/30: Re: Xilinx- Extract a pin layout
    82108: 05/04/06: Re: Modelsim simulations without ISE
    82250: 05/04/09: Re: ISE 7.1 for 64 bit Linux ???
    82251: 05/04/09: Re: rules to assign pins to FPGA?
    82283: 05/04/10: Re: ISE 7.1 for 64 bit Linux ???
    82715: 05/04/16: Re: Xilinx tools from the commandline
    83126: 05/04/24: Re: how to put an FIR in an FPGA?
    84614: 05/05/23: Re: FSM stops working
    86649: 05/07/01: Re: vhdl source code cross reference tool
    86835: 05/07/07: Re: Has anybody run Virtex-4 FPGAs at 300MHz+ interface speed?
    87374: 05/07/22: Re: DDR SDRAM on ML401
    87614: 05/07/27: Re: Xilinx Foundation ISE and WinXP/x64?
    87669: 05/07/27: Re: chipscope/impact Virtex4 problem
    87706: 05/07/28: Re: XST and TCL support?
    88428: 05/08/18: Re: Xilinx ISE on remtoe Display
    89328: 05/09/13: Re: ISE 7.1i & Linux / reg code question
    89330: 05/09/13: Re: reducing the number of IOBS in a design
    91774: 05/11/12: Re: Add files to Xilinx ISE Project w/script
    92674: 05/12/04: Re: Virtex 4 IDELAY implementation
    93568: 05/12/24: Re: edif to vhd black box
    94205: 06/01/07: Re: How to keep the design from Synplify or XST optimizing
    94644: 06/01/15: Re: Directed routing in Xilinx V2PRO.
    98444: 06/03/10: Re: Virtex-4 DCM CLKFX jitter
    98445: 06/03/10: Re: since xilinx ise 8.1 support linux red hat 4.0 (with device Spartan-3 400k)
    102122: 06/05/10: Re: Routing problem in PAR.
    102194: 06/05/11: Re: Xilinx ISE 8.1 Makefile
    102235: 06/05/12: Re: How to check IOB register packing?
    102319: 06/05/15: Re: Assigning MGT's in sample Aurora Design
    102562: 06/05/17: Re: Hold Time Violations in Virtex4
    103529: 06/06/05: Re: Multi place and route
    103543: 06/06/05: Re: Webpack larger than CDs
    103598: 06/06/06: Re: ISE8.1 on OpenSUSE 64bit
    103640: 06/06/07: Re: Problems with ISE logic optimization
    103641: 06/06/07: Re: ISE8.1 on OpenSUSE 64bit
    103984: 06/06/16: Re: Virtex2-Pro local clocking...
    104774: 06/07/05: Re: Incorporating CoreGen files in EDK 8.1 peripheral
    104828: 06/07/06: Re: Can a BUFGMUX drive a global clock in the Spartan-3?
    104937: 06/07/10: Re: LUT4 INIT value to implement 2:1 MUX ?
    105047: 06/07/12: Re: Diffenrential I/Os in Virtex-4
    105672: 06/07/28: Re: 4VSX35 LOC placements?
    105698: 06/07/28: Re: 4VSX35 LOC placements?
    105757: 06/07/31: Re: Core Generator
    105820: 06/08/01: Re: Usage of DDR IOBs
    105988: 06/08/04: Re: RocketIO simulation in VCS
    106068: 06/08/07: Re: How do I treat "default" case which is useless?
    106507: 06/08/14: Re: RocketIO MGT Tile/Column Question
    106769: 06/08/18: Re: Problem Instantiating a DSP48E or RAMB36 for a Virtex5 in ISE 8.2 SP2
    106773: 06/08/18: Re: Problem Instantiating a DSP48E or RAMB36 for a Virtex5 in ISE 8.2 SP2
    106780: 06/08/18: Re: Problem Instantiating a DSP48E or RAMB36 for a Virtex5 in ISE 8.2 SP2
    106912: 06/08/22: Re: ModelSim SE PLUS 6.1B. Problem to simulate RocketIO in GT_CUSTOM mode
    107601: 06/08/30: Re: Location of Virtex4 ASCII pinout tables
    108695: 06/09/15: Re: General Tips of reading Verilog Code
    108731: 06/09/15: Re: Critcal path in XILINX ISE (XST)
    109698: 06/10/03: Re: How to create a library for a Xilinx project
    109724: 06/10/04: Re: How to create a library for a Xilinx project
    110929: 06/10/25: Re: Supported bus widths for RLDRAM on Virtex4?
    111644: 06/11/07: Re: ISE/EDK project on a file server?
    111760: 06/11/09: Re: Xilinx ISE ucf management
    111761: 06/11/09: Re: tri0 GSR = glbl.GSR;
    111958: 06/11/13: Re: MPMC2: MPMC2 with DDR2 SDRAM
    111959: 06/11/13: Re: How to control the running of NC-Sim and Xilinx ISE under Unix?
    111960: 06/11/13: Re: Xilinx ISE ucf management
    112965: 06/12/02: Re: LUT input order
    112967: 06/12/02: Re: LUT input order
    113100: 06/12/06: Re: Clock phase shift
    113132: 06/12/06: Re: Usage of BUFIO in Virtex 4?
    113133: 06/12/06: Re: Usage of BUFIO in Virtex 4?
    113187: 06/12/07: Re: Xilinx PAR crashing with 'make'
    113223: 06/12/08: Re: source synchronous timing (Xilinx)
    113653: 06/12/18: Re: jtag reset seq
    113877: 06/12/27: Re: assigned a special pins in ISE
    114189: 07/01/06: Re: dynamically created blockRAM contents?
    114884: 07/01/25: Re: Any UK mirror for ISE 8.2i SP2?
    114901: 07/01/25: Re: OrCAD symbol for the Xilinx V5LX50 FF676 device
    114927: 07/01/26: Re: Forcing a LUT to not be optimized
    115792: 07/02/20: Re: How to get the area/time results without IO mapping
    115909: 07/02/24: Re: How to specify ISE INST constraint with GENERATE statements?
    116127: 07/03/01: Re: Regional Clock Network and Large Designs
    116157: 07/03/02: Re: Potential problem in batch files for Xilinx [was SCons build tool as an alternative to makefiles]
    116256: 07/03/05: Re: Multiple devices within one ISE project
    116293: 07/03/06: Re: Potential problem in batch files for Xilinx
    116785: 07/03/18: Re: init of FPGA's Block-RAMs.
    117045: 07/03/22: Re: Manual LUT - AND function mapping problem
    117133: 07/03/23: Re: Xilinx Virtex-4 Embedded Ethernet Wrapper IP Core - HELP with UCF
    119536: 07/05/22: Re: SelectIO banking rules
    119818: 07/05/26: Re: IOSTANDARD user constrain
    120432: 07/06/06: Re: How many OSERDES per bufio
    120485: 07/06/07: Re: How many OSERDES per bufio
    120824: 07/06/18: Re: Xilinx FPGA Pinout spreadsheets
    120892: 07/06/19: Re: .xco file and vcs verilog compiler
    121631: 07/07/10: Re: DDR SDRAM simulation model, ML300, Infineon
    123101: 07/08/16: Re: Virtex 4 IBUFG to DCM routing question
    123127: 07/08/16: Re: Virtex 4 IBUFG to DCM routing question