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Messages from 39925

Article: 39925
Subject: QPRO questions
From: dottavio@ised.it (Antonio)
Date: 21 Feb 2002 23:25:12 -0800
Links: << >>  << T >>  << A >>
For my Thesis I'm interested to propose a FPGA to use for a QPSK
modulator instead of an ASIC, I would want to know if the V1000
BG560-4 is the top for the QPRO series or there are QPRO version of
VIRTEX_E or VIRTEX_2, another question is to know if the performance I
can obtain on standard V1000 BG560-4 are the same I can obtain on the
QPRO version. The last question is if do you know of FPGA already
mounted on a Satellite for a critical service like modulation.  Thanks

Antonio

P.S. Another question, there are available board to test the QPRO
VIRTEX or is the same to test on a board with a standard V1000 BG560-4
 ?

Article: 39926
Subject: OT - Programmer war stories
From: "Christopher Duncan" <Chris@ShowProgramming.com>
Date: Fri, 22 Feb 2002 02:27:59 -0500
Links: << >>  << T >>  << A >>
Hi, folks.

I'm trying to reach as many seasoned programmers
as I can, hope you don't mind the off topic post.
As part of the research I'm doing for a follow up
to my recent book, "The Career Programmer:
Guerilla Tactics for an Imperfect World" (Apress),
I'm compiling a book of war stories from those of
you who have been out there dealing with all the
insanity that Corporate America has to offer.

In The Career Programmer, I talked about
overcoming the real world obstacles we run into
trying to get decent software out the door
(arbitrary deadlines, clueless management,
Marketing, fuzzy requirements, never any time for
testing, corporate politics - all that stuff they
never taught us in school). I've had tremendous
feedback to the book, and one of the things that
struck me was that as I told stories about the
ridiculous situations I've had to cope with in
my own career, everyone asked if I was looking
over their cubicle walls because they were
dealing with the same things in their shop. So,
if figured it would be fun to do a follow up
book relating the war stories that some of you
have been through. None of my books are tied to
a particular programming language, operating
system or platform, so it doesn't matter what
kind of coding you do. We all deal with the
same sort of craziness.

I'll paraphrase the stories, and of course I
won't use any real names (personal or company) -
we get enough grief from management as it is, no
point inviting any more. I'll be happy to include
your name in the Acknowledgements, but of course
will omit it if you prefer your story to be
anonymous. This book will be in the same, er,
conversational style (that's what my publishers
told me was the politically correct phrase for
being a wise guy) as The Career Programmer was.
I try not to take myself too seriously in this
business - keeps my antacid bills down. But then,
if you've read the last book you probably figured
that out about the time you encountered the
night watchman's attack Chihuahua...

Anyway, if you've got a good war story about
programming in Corporate America, I'd love to
hear it. I may change the format of how I gather
& organize the stories on my web site, so just go
to www.ShowProgramming.com/TheCareerProgrammer.asp
and look for the link on War Stories. That gives
me the flexibility to reorganize the database &
data input page whenever I want without leaving dead
links. And of course, you know I'll have to rewrite
the UI at least a couple of times. There's always
one more tweak.

Oh, by the way, since I get emails from programmers
all over the world, I get teased a little here &
there about my use of "Corporate America", since
programming is obviously an international community.
And from what I've heard, the business world is equally
insane in every country. However, America is the only
one I have experience with. And besides, it was easier
to write than Corporate <Insert Your Country Here>.
Hey, I got lazy, what can I say?

Anyway, if you've got a good story about how crazy this
business can get and wouldn't mind me sharing it with
others, please drop by and add it to the database.
Make sure you leave me an email address that will still
be good when the book comes out (these things tend to
take months to get out the door - sound familiar?).

And thanks very much for taking the time, I truly
appreciate it.

Happy Coding!

Christopher Duncan







Article: 39927
Subject: Tristate meets mux
From: hmurray-nospam@megapathdsl.net (Hal Murray)
Date: Fri, 22 Feb 2002 07:38:22 -0000
Links: << >>  << T >>  << A >>
>Remember that the Virtex internal T/S is not really a
>tristate bus.  That is why it is so fast and uses minimal
>power.

I see comments like that occasionally, but I don't really
understand the issues yet.

Is there a good paper describing the tradeoffs?
If I have a regular structure, like an FPGA, how do I
build and layout a big mux to make it go fast?

Is the result predictable if I enable two drivers
at the same time?

I'm an old-timer.  I've used tristate busses often
enough that they live near the top of my toolbox.  (There
is probably a chicken and egg problem here.)  I'm just
used to turning problems into microcoded state machines,
often with a tristate bus in the middle.  How do you
transform that type or solution into one that is
more mux-friendly?

-- 
These are my opinions, not necessarily my employer's.  I hate spam.


Article: 39928
Subject: Re: INIT on XC2S30
From: "Mark van de Belt" <mvandebelt@NOSPAM.roax.nl>
Date: Fri, 22 Feb 2002 08:49:56 +0100
Links: << >>  << T >>  << A >>
That's it. I was not using the pin at all.
Thanks

"Peter Alfke" <peter.alfke@xilinx.com> wrote in message
news:3C757918.7011049D@xilinx.com...
> The INIT pin description in the data sheet, table 55, says:
> "..After the I/O go active"   ( i.e. after the end of configuration)
"INIT is a
> user-programmable I/O pin."
> What are you using this pin for?
>
> Peter Alfke, Xilinx Applications
> =============================
> Mark van de Belt wrote:
>
> > Hello,
> >
> > I'm trying to configure a XC2S30 FPGA from the ISA bus in a PC
(embedded).
> > The configuration file generation is no problem and I'm following the
> > datasheet and application note for 'Parallel slave' programming:
> > (as seen from the processor)
> > WRITE# = '0' (always)
> > PROGRAM# = '1'
> > INIT# = input with pull up
> > DONE = input with pull up
> > CCLK = IOW#
> > CS# = CS# from ISA bus (0x360)
> > DATA = DATA
> >
> > To start I pulse the PROGRAM# low and wait for INIT# to come high.
> > Then I start writing to addres 0x360.
> > After the last byte the DONE line is high, but the INIT line is low.
> > According to the datasheet this line should be high aswell. The content
of
> > the FPGA is correct, I can access the internal registers.
> > Why is the INIT# pin low?
> >
> > Thanks in advance
>



Article: 39929
Subject: Re: Linux tools
From: "Jan Pech" <j.pech@ieee.org>
Date: Fri, 22 Feb 2002 08:49:59 +0100
Links: << >>  << T >>  << A >>
> > I was away for a while from the NG, is there any word on FPGA vendors
> > offering (or planning to) Linux toolchains (in the same config and
> > pricing as their Win tools) ?
> >
> > Thanks,
> >
> > Zoltan
> >
>
> http://www.xilinx.com/prs_rls/software/0225_Em_Linux.html

But it's not native Linux application.... It's only Windows version that can
be used under Wine:(



Article: 39930
Subject: Re: Here is an argument and can anyone help me out
From: thomas.stanka@tesat.de (Thomas Stanka)
Date: 22 Feb 2002 09:16:53 GMT
Links: << >>  << T >>  << A >>
HI,

"Madhu" <pp_madhavi@yahoo.com> wrote:
>   here is an argument with one of my friend who is a mechanical engineer
> and writing S/W.

Ooch, I *like* those kind of experts.

>   He argues that if the input and output waveforms are given he can
> write a tool which generates a digital circuit for those inputs and
> outputs. He knows about truth tables and gates.

He is right. Given a Computer with endless RAM to store such cirquits.

>   He is not convinced when I told all digital circuits are not just
> combinational.

thats ok, a generic cirquit could also use register.

>   Then I asked him whether he can generate a C program if the inputs and
> outputs are given. But he says that it is obsurd that I am comparing a
> language with digital design.

Thats wrong. There are differences between HDL and programming language, 
but not that much.

Well, It is really no Problem to think about a generic cirquit doing the 
same as your AMD/Pentium/Sparc....
(Given endless number of gates per die and a technologie without gatedelay)
But we had to do a lot work getting _small_ and _fast_ cirquits for given 
Problems. And there are a lot of designers earning their money with 
developing smaller and faster cirquits. 

During study we had to develop a 1 bit ALU for a few simple operations. One 
student started with a truth table and ended with a very complex cirquit.
- to complex for debugging
- more gates than every other solution
- worse delay
- unfortunately a simple error due to missing one inverter.

all other students need a fulladder, one inverter, one and, one or and some 
multiplexer. Got the problem?

bye Thomas

-- 
Thomas Stanka TE/EMD4
Space Communications Systems
Tesat Spacecom GmbH & Co KG
thomas.stanka@tesat.de

Article: 39931
Subject: Re: Problem While Downloading to Spartan 2 FPGA using JTAG
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Fri, 22 Feb 2002 10:29:50 +0000
Links: << >>  << T >>  << A >>


Ray Andraka wrote:

> Check to make sure the power connections on the cable are connected to the board.  IIRC, Parallel cable III needs a 5v
> supply.  If it is not powered, the cable won't be recognized.
>

The Parallel-III uses  'HC125s as the PP signal buffers which can be powered from a supply as low as 2V.  The '125s power is
supplied from the Parallel-III through a 1N5817 Schottky diode with a voltage drop of 0.3V => the min voltage is 2.3 =>
there should be a decent supply for the cable even for XC95XV devices

On a side note: We implemented the Parallel-III schems on our boards some time ago but replaced the HC parts with ordinary
LS125s powered from 5V. All was well when there were only CPLDs in the chain but when I added an XC18V04 at the front we
started to get a lot of programming failures for this serial EEPROM. Changing to HC125s powered from 3.3V has made that
problem go away ?!


Article: 39932
Subject: Re: Here is an argument and can anyone help me out
From: Christopher.Saunter@durham.ac.uk (Christopher Saunter)
Date: Fri, 22 Feb 2002 10:40:57 +0000 (UTC)
Links: << >>  << T >>  << A >>
Theron Hicks (hicksthe@egr.msu.edu) wrote:

Hi Theron:
: I think I had the same lab back in the 70's.  I guess we are both showing
: our ages.
Speak for yourself ;-)))  I am <30, it's just we did some stuff with them
in our labs a few years back.  Actually quite interesting.

I am working on implementing a control algortithim in programmable logic,
and the way things are working out, the design has much more in common
with the way it would have been done once (and it has been...) in an
analogue computer, than it does the current CPU implementations - as with
an AC the FPGA allows large scale parallelism, and all the digital data
flowing arround in busses through processing blocks is rather like
voltages being processed by op amps etc.

That analogy works quite well for the DSP side of the design, it kind of
falls flat when it comes to the processor parts mind ;-)

Cheers,
	Chris Saunter



Article: 39933
Subject: Re: Linux tools
From: Claudio <lancos@nientespam.libero.it>
Date: Fri, 22 Feb 2002 12:12:24 +0100
Links: << >>  << T >>  << A >>
Jan Pech wrote:

>>>I was away for a while from the NG, is there any word on FPGA vendors
>>>offering (or planning to) Linux toolchains (in the same config and
>>>pricing as their Win tools) ?
>>>
>>>Thanks,
>>>
>>>Zoltan
>>>
>>>
>>http://www.xilinx.com/prs_rls/software/0225_Em_Linux.html
>>
> 
> But it's not native Linux application.... It's only Windows version that can
> be used under Wine:(
> 


"This offering makes ISE the first programmable logic solution available 
that supports Linux OS, with later versions of ISE moving to native 
Linux in 2003"

We have to wait untill 2003 for native Linux ISE. However a great news!!

Claudio


Article: 39934
Subject: Re: Xilinx (ise4.1) is screwed up! SCREAM LOUD!!
From: Jonas Weiss <jweiss@kontronmedical.ch>
Date: Fri, 22 Feb 2002 12:21:24 +0100
Links: << >>  << T >>  << A >>
Glad to hear I'm not alone!
For my part I now use an adapted version of the async. FIFO that comes with
XILINX app. Note 258. This works for me but of course maintainability compared
to the CoreGen part is rather poor.

And here I'll join you with your  "...scream _really_ loud..."


Jonas Weiss


Article: 39935
Subject: Re: Problem While Downloading to Spartan 2 FPGA using JTAG
From: yatiks@yahoo.com (Kumar)
Date: 22 Feb 2002 03:54:00 -0800
Links: << >>  << T >>  << A >>
I have connected 5V supply before trying to program the device ,but
the same setup works fine in other PC but not in My PC .

yathish 

Ray Andraka <ray@andraka.com> wrote in message news:<3C75D343.4F83DE41@andraka.com>...
> Check to make sure the power connections on the cable are connected to the board.  IIRC, Parallel cable III needs a 5v
> supply.  If it is not powered, the cable won't be recognized.
> 
> Kumar wrote:
> 
> > "Mark van de Belt" <mark@nijenrode.demon.nl.spam.invalid> wrote in message news:<u7apohsnbc79e2@corp.supernews.com>...
> > > I think the problem is with the BIOS setting for the parallel port. You have
> > > to set it to EPP (or was it ECP, i'm not sure).
> > >
> > > This could solve your problem
> >
> >       No Mark ,I changed the BIOS settings from "Bidirectional" to
> > "EPP" .
> > The result is same not able to connect . I connected the printer to
> > same port ,it worked properly .My IO address is 0378 and Interrupt
> > request 07.
> > There is no DMA Or one more IO range .Mother Board chipset 850D .Here
> > is some information of log file
> > which may help in solving the problem
> >
> > Device #1 selected
> > AutoDetecting cable. Please wait.
> > CB_PROGRESS_START - Starting Operation.
> > Connecting to cable (USB Port).
> > Cable connection failed.
> > Connecting to cable (Parallel Port - LPT1).
> > Connecting to cable (Parallel Port - LPT2).
> > Connecting to cable (Parallel Port - LPT3).
> > Connecting to cable (COM1 Port).
> > Cable connection failed.
> > Connecting to cable (COM2 Port).
> > Cable connection failed.
> > Connecting to cable (COM3 Port).
> > Cable connection failed.
> > Connecting to cable (COM4 Port).
> > Cable connection failed.
> > Elapsed time =     23 sec.
> > Cable autodetection failed.
> > WARNING:iMPACT:547 - Can not find cable, please check cable setup !
> > =>
> >
> > Thank u
> > yathish
> 
> --
> --Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email ray@andraka.com
> http://www.andraka.com
> 
>  "They that give up essential liberty to obtain a little
>   temporary safety deserve neither liberty nor safety."
>                                           -Benjamin Franklin, 1759

Article: 39936
Subject: Re: Linux tools
From: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Date: 22 Feb 2002 12:07:29 GMT
Links: << >>  << T >>  << A >>
Jan Pech <j.pech@ieee.org> wrote:
:> > I was away for a while from the NG, is there any word on FPGA vendors
:> > offering (or planning to) Linux toolchains (in the same config and
:> > pricing as their Win tools) ?
:> >
:> > Thanks,
:> >
:> > Zoltan
:> >
:>
:> http://www.xilinx.com/prs_rls/software/0225_Em_Linux.html

: But it's not native Linux application.... It's only Windows version that can
: be used under Wine:(

Where's the difference?

The Windows API is a library like Motif, lesstif, qt, gnome. Is a Motif
program  compiled on Win32 not a native Windows application? Is a Gnome
programm running on you KDE Desktop not a native Linux programm?

Understand the concept of Wine.

Bye

-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Article: 39937
Subject: How can I disable clock buffer (BUFG) insertion in Xilinx Foundation F3.1i?
From: "JHL" <jaehwanida@orgio.net>
Date: Fri, 22 Feb 2002 21:13:00 +0900
Links: << >>  << T >>  << A >>
Hello everyone!

I now program virtex(XCV50-4BG256) using VHDL.
Because I use many clock signal in my design, when I make my VHDL source
synthesized into the chip, I often receive some error messages, which say to
me that it is impossible to map
my source to this chip because of lack of CLK buffer resource.

How can I disable clock buffer insertion in Xilinx Foundation F3.1i?




Article: 39938
Subject: Re: Problem While Downloading to Spartan 2 FPGA using JTAG
From: "Tim" <tim@rockylogic.com.nooospam.com>
Date: Fri, 22 Feb 2002 12:38:13 -0000
Links: << >>  << T >>  << A >>
At this point I would go for a cheap add-on parallel card for your PC.
This should solve (most) signal level and timing problems.

Kumar wrote

> I have connected 5V supply before trying to program the device ,but
> the same setup works fine in other PC but not in My PC .

<rest trimmed>





Article: 39939
Subject: Re: Linux tools
From: Petter Gustad <newsmailcomp1@gustad.com>
Date: Fri, 22 Feb 2002 13:04:04 GMT
Links: << >>  << T >>  << A >>
Claudio <lancos@nientespam.libero.it> writes:

> "This offering makes ISE the first programmable logic solution available 
> that supports Linux OS, with later versions of ISE moving to native 
> Linux in 2003"
> 
> We have to wait untill 2003 for native Linux ISE. However a great news!!

I've heard that Quartus II 2.0 supports Linux (Red Had 6.2), however I
don't know its release date, or if it has been released.

Petter
-- 
________________________________________________________________________
Petter Gustad   8'h2B | (~8'h2B) - Hamlet in Verilog   http://gustad.com

Article: 39940
Subject: Re: Problem While Downloading to Spartan 2 FPGA using JTAG
From: sanket@insight.memec.co.in (Xilinx FAE from Insight SANKET)
Date: 22 Feb 2002 05:06:32 -0800
Links: << >>  << T >>  << A >>
Hi,
(1)Try all the Parallel port settings in the BIOS.
(2)Re-install Impact.
(3)Check with a Insight JTAG cable if you have one.If it works then
definitely it is a problem with the cable length.

SANKET.

Ray Andraka <ray@andraka.com> wrote in message news:<3C75D343.4F83DE41@andraka.com>...
> Check to make sure the power connections on the cable are connected to the board.  IIRC, Parallel cable III needs a 5v
> supply.  If it is not powered, the cable won't be recognized.
> 
> Kumar wrote:
> 
> > "Mark van de Belt" <mark@nijenrode.demon.nl.spam.invalid> wrote in message news:<u7apohsnbc79e2@corp.supernews.com>...
> > > I think the problem is with the BIOS setting for the parallel port. You have
> > > to set it to EPP (or was it ECP, i'm not sure).
> > >
> > > This could solve your problem
> >
> >       No Mark ,I changed the BIOS settings from "Bidirectional" to
> > "EPP" .
> > The result is same not able to connect . I connected the printer to
> > same port ,it worked properly .My IO address is 0378 and Interrupt
> > request 07.
> > There is no DMA Or one more IO range .Mother Board chipset 850D .Here
> > is some information of log file
> > which may help in solving the problem
> >
> > Device #1 selected
> > AutoDetecting cable. Please wait.
> > CB_PROGRESS_START - Starting Operation.
> > Connecting to cable (USB Port).
> > Cable connection failed.
> > Connecting to cable (Parallel Port - LPT1).
> > Connecting to cable (Parallel Port - LPT2).
> > Connecting to cable (Parallel Port - LPT3).
> > Connecting to cable (COM1 Port).
> > Cable connection failed.
> > Connecting to cable (COM2 Port).
> > Cable connection failed.
> > Connecting to cable (COM3 Port).
> > Cable connection failed.
> > Connecting to cable (COM4 Port).
> > Cable connection failed.
> > Elapsed time =     23 sec.
> > Cable autodetection failed.
> > WARNING:iMPACT:547 - Can not find cable, please check cable setup !
> > =>
> >
> > Thank u
> > yathish
> 
> --
> --Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email ray@andraka.com
> http://www.andraka.com
> 
>  "They that give up essential liberty to obtain a little
>   temporary safety deserve neither liberty nor safety."
>                                           -Benjamin Franklin, 1759

Article: 39941
Subject: Re: Whether an FPGA & CPLD device has been spoiled.
From: sanket@insight.memec.co.in (Xilinx FAE from Insight SANKET)
Date: 22 Feb 2002 05:16:24 -0800
Links: << >>  << T >>  << A >>
Hi,
Frankly speaking  the life of your device has considerably reduced
even though it must be working perfectly.I suggest, that once a FPGA
or CPLD is given over voltage, it should be discarded AS YOU DO NOT
WANT TO INCREASE VARIABLES WHILE TESTING.
regds.
SANKET.


Ray Andraka <ray@andraka.com> wrote in message news:<3C754198.DC1D01F5@andraka.com>...
> Don't use it in a production setting if you exceeded the absolute maximum
> ratings listed in the DC specifications part of the data sheet.  You may have
> stressed it enough that it may fail after  a short time in service, or may not
> meet all the timing  even though it may still work correctly.
> 
> Eric Smith wrote:
> 
> > "X. Q." <qijun@okigrp.com.sg> writes:
> > > Last time I purchased a XC9572 CPLD and an SC2S100 Spartan-II chip.
> > > I applied a 5V to it's VCCO. I want to know how to decide whether the chip
> > > has been spoiled.
> >
> > Try using it correctly.  If it works, it isn't *completely* broken.
> 
> --
> --Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email ray@andraka.com
> http://www.andraka.com
> 
>  "They that give up essential liberty to obtain a little
>   temporary safety deserve neither liberty nor safety."
>                                           -Benjamin Franklin, 1759

Article: 39942
Subject: Re: Altera library problems.
From: "Wolfgang Loewer" <wolfgang.loewer@elca.de>
Date: Fri, 22 Feb 2002 14:28:40 +0100
Links: << >>  << T >>  << A >>
Paul,

just don't include the Megawizard generated file from you input list in
LeonardoSpectrum and everything should work fine. Quartus will read and
analyze the Megawizard file together with the EDIF netlist from
LeonardoSpectrum

- Wolfgang

"Paul" <nospam@nospamplease.com> schrieb im Newsbeitrag
news:D26c8.72648$as2.12565761@news6-win.server.ntlworld.com...
> I've generated an altclklock using the Altera megafunction wizard and
> Quartus 2 1.1 SP2 is happy to synthesise and P&R.
>
> However the same file is not at all happy in Leonardo (2001_1d Altera
> edition). Synthesis should create a black box but then P&R back with
Quartus
> 2 doesn't work.
>
> I believe this was working fine last time I tried with a similar P&R, but
my
> Quartus 2 version has incremented (previously used version probably Q2 1.0
> SP2 or 1.1 no SP)
>
>
> I suspect that the library altera_mf used to be something else???
>
> Can someone with an earlier version of Q2 try generating a simple PLL (I
> used a clock 1 @ 133MHz PLL x1 with a 'locked' output but this was an
> arbitrary choice) and compare the included library to that below.
>
>
> Here's an extract from the generated file:
>
> LIBRARY ieee;
> USE ieee.std_logic_1164.all;
>
> LIBRARY altera_mf;
> USE altera_mf.altera_mf_components.all;
>
> ENTITY plltest IS
>  PORT
>  (
>   inclock  : IN STD_LOGIC ;
>   locked  : OUT STD_LOGIC ;
>   clock1  : OUT STD_LOGIC
>  );
> END plltest;
>
>
> ARCHITECTURE SYN OF plltest IS
> <snipped>
> END SYN;
>
> ---------------------------------------
> Not sure that use of altera_mf is the same as before....
>
> Any insights appreciated.
>
> Paul
>
>



Article: 39943
Subject: Pin assignments in QUARTUS
From: guiducci@cern.ch (Luigi)
Date: 22 Feb 2002 05:41:39 -0800
Links: << >>  << T >>  << A >>
Hi,
I'm developing a design under QUARTUS (I'll switch to QUARTUS II
soon). I have to assign I/O signals to specific pins in my device (to
organize them in a useful way for the board design). What I wasn't
able to find is if there's a different way to do it than using the
boring interface of the "Assignment organizer". I cannot assign 500
pins clicking with my mouse! I saw that these assignments are into a
file .csf. Can I edit the pin locations directly in this file? Is it
used by the fitter? This file contains also the logic locations into
LAB etc. If I edit the pin locations only, then the fitter
redistribute in an optimal way (According to the new pin locations)
the logic cells, or it uses that half-edited .csf file?
Just to let you understand: what would be perfect for me, is something
like: "ok, put these I/Os on these pins, and then do your best by
yourself on everything else, my dear fitter".
Sorry if it's a silly question, but I didn't find anything useful in
the quartus help or on altera web site.
Thank you,

Luigi

Article: 39944
Subject: Re: Linux tools
From: Veli-Matti Karppinen <veli-matti.karppinen@rem_obvious.pigroup.fi>
Date: Fri, 22 Feb 2002 15:48:22 +0200
Links: << >>  << T >>  << A >>
Petter Gustad wrote:
> 
> Claudio <lancos@nientespam.libero.it> writes:
> 
> > "This offering makes ISE the first programmable logic solution available
> > that supports Linux OS, with later versions of ISE moving to native
> > Linux in 2003"
> >
> > We have to wait untill 2003 for native Linux ISE. However a great news!!
> 
> I've heard that Quartus II 2.0 supports Linux (Red Had 6.2), however I
> don't know its release date, or if it has been released.
> 

Hi,

We just got info that beta version could be available now and 
the official release appr. week 12. It will be nice to try it out.

Regards,

Veli-Matti

Article: 39945
Subject: Re: cross clock domain signals
From: sanket@insight.memec.co.in (Xilinx FAE from Insight SANKET)
Date: 22 Feb 2002 05:48:40 -0800
Links: << >>  << T >>  << A >>
Hi,


Convert your binary addresses to Gray code and pipeline them.Gray-code
addresses are used so that the registered Full and Empty flags  are
not in an unknown state due to the async. relationship of  Read and
Write clocks.
Check out XAPP175 on www.xilinx.com

This pdf may give you some new ideas though a quite different from
your query.
http://www.xilinx.com/company/consultants/flancter.pdf

regds.
SANKET.



jaiphen_interqos@yahoo.com.hk (starpanda) wrote in message news:<64c11999.0202212013.3b6b7e56@posting.google.com>...
> Hi,
> Right now I am developing a design which has to use a Asyn FIFO. Due
> to resource limitation, I have to use a dual port RAM to implement
> this Asyn FIFO (Read in one clock domain, write in another clock
> domain). I have to implement my own "Full" and "Empty" signals, but
> both signals involves signals in both clock domain (head and tail
> pointers). What should I do to avoid metastability problem when I try
> to calculate the data size of the FIFO?
> Thanks!
> 
> Jaiphen

Article: 39946
Subject: CPLD PROJECT
From: yoram@puc.cl (Yoram Rovner)
Date: 22 Feb 2002 05:59:17 -0800
Links: << >>  << T >>  << A >>
Hi:

I am a newbie on fpga issues and I need some recomendations. I am
planning to develop a cpu in a cpld. I have XESS XS95 board v.1.3 and
the student edition of Xilinx Foundation 1.5. I had some experiences
in programing with verilog so i will like to do this cpu in that
language. I have heard that Xilinx foundation student edition do not
provide a good tool for developing with verilog (i mean error reports,
etc). Would be better to use Webpack ise?, is there another
software(maybe free or low cost) that is recommended to use?


Thanks,


Yoram Rovner

Article: 39947
Subject: Re: Beginner Altera Questions
From: "Peter Ormsby" <faepete.deletethis@mediaone.net>
Date: Fri, 22 Feb 2002 14:02:36 GMT
Links: << >>  << T >>  << A >>

Al Williams <alw@al-williams.com> wrote in message
news:a9835df1.0202212119.6cf9dcaf@posting.google.com...
> I'm just getting accustomed to using the MAX3000A using Max PLUS II
> and Leonardo Spectrum. A few questions...
>
> 1) Is there any way to parameterize your Verilog so that once you
> bring the edif into MAX PLUS II you can still change the parameters?
> It looks like the parameters get fixed after passing it through LS. My
> guess is this is how it has to be, but that makes the MPII's inability
> to do Verilog (for free, at least) a disadvantage.

If you're using any of theMegaWizard functions, they can still be
parameterized in MP2 without resynthesizing your verilog in Leo Spec (since
Leo Spec just black-boxes the functions anyway).  Otherwise, you pretty much
have to run Leo Spec any time you change your verilog code.

Note that the MAX3000A (and MAX7000, for that matter) are now supported in
Quartus II Web Edition (the free downloadable version).  In Quartus II, you
can use the Nativelink feature to call up Leo Spec in the background and
synthesize your verilog without leaving the Quartus II GUI.

>
> 2) I tried to put MPII and LS on my laptop. I disconnected from the
> network and MPII still works, but LS complains I don't have a valid
> license. Of course, LS won't even try to work from an HD serial port
> license. I haven't tried it connected to the network, but ipconfig can
> still see my adapter and apparently so can MPII. Any ideas?
>

I think there's an issue with some versions of Windows reporting some NIC
ID's as 00-00-00-00-00-00 if you unplug them from the network
(http://www.altera.com/support/solutions/rd01242001_575.html).  It also
looks like there are several other reasons why Windows may report an invalid
NIC ID under certain conditions.  Do a search on "NIC" in the Altera
solutions database
(http://www.altera.com/support/solutions/spt-search_solutions.html) and see
if any of these apply to your situation.

-Pete-



Article: 39948
Subject: Re: Beginner Altera Questions
From: alw@al-williams.com (Al Williams)
Date: 22 Feb 2002 06:25:12 -0800
Links: << >>  << T >>  << A >>
"jerry1111" <jerry1111@wp.pl> wrote in message news:<a54qbe$b0j$1@news.tpi.pl>...
> > 2) I tried to put MPII and LS on my laptop. I disconnected from the
> > network and MPII still works, but LS complains I don't have a valid
> > license. Of course, LS won't even try to work from an HD serial port
> > license. I haven't tried it connected to the network, but ipconfig can
> > still see my adapter and apparently so can MPII. Any ideas?
> 
> If it's protected by NIC (network interface card) number it
> may not work when net is unplugged.
> 

Well, that seemed to be the case with a USB NIC. I tried the HD serial
number (not serial port -- sorry) and of course, LS isn't supposed to
work with that. So then I put in a PCMCIA NIC. That solved the MPII
(yes, I switched the license to the new NIC ID), so it seems that MPII
can read the number, but LS can't -- that's what makes it puzzling. Oh
well, thanks just the same.

Article: 39949
Subject: Re: Pin assignments in QUARTUS
From: "Jean-Baptiste Monnard" <jmonnard@horizon-tech.fr>
Date: Fri, 22 Feb 2002 15:08:03 -0000
Links: << >>  << T >>  << A >>
The only solution to add pin assignment without using the quartus interface
is to edit the .csf file.

1 - Close your current project
2 - open your project_name.csf file
3 - add your pin assignment  under the chip(name_chip) line :
for example :
MY_NODE : LOCATION = Pin_J1;
4 - save the new csf file and compile your project
...

Hope this helps



--
Jean Baptiste MONNARD
Ingénieur
HorizonTechnologies
01 60 92 10 15
"Luigi" <guiducci@cern.ch> a écrit dans le message news:
235ed672.0202220541.3bb1e381@posting.google.com...
> Hi,
> I'm developing a design under QUARTUS (I'll switch to QUARTUS II
> soon). I have to assign I/O signals to specific pins in my device (to
> organize them in a useful way for the board design). What I wasn't
> able to find is if there's a different way to do it than using the
> boring interface of the "Assignment organizer". I cannot assign 500
> pins clicking with my mouse! I saw that these assignments are into a
> file .csf. Can I edit the pin locations directly in this file? Is it
> used by the fitter? This file contains also the logic locations into
> LAB etc. If I edit the pin locations only, then the fitter
> redistribute in an optimal way (According to the new pin locations)
> the logic cells, or it uses that half-edited .csf file?
> Just to let you understand: what would be perfect for me, is something
> like: "ok, put these I/Os on these pins, and then do your best by
> yourself on everything else, my dear fitter".
> Sorry if it's a silly question, but I didn't find anything useful in
> the quartus help or on altera web site.
> Thank you,
>
> Luigi





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