Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarApr2017

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search

Messages from 39900

Article: 39900
Subject: Re: INIT on XC2S30
From: Peter Alfke <peter.alfke@xilinx.com>
Date: Thu, 21 Feb 2002 14:47:52 -0800
Links: << >>  << T >>  << A >>
The INIT pin description in the data sheet, table 55, says:
"..After the I/O go active"   ( i.e. after the end of configuration)  "INIT is a
user-programmable I/O pin."
What are you using this pin for?

Peter Alfke, Xilinx Applications
=============================
Mark van de Belt wrote:

> Hello,
>
> I'm trying to configure a XC2S30 FPGA from the ISA bus in a PC (embedded).
> The configuration file generation is no problem and I'm following the
> datasheet and application note for 'Parallel slave' programming:
> (as seen from the processor)
> WRITE# = '0' (always)
> PROGRAM# = '1'
> INIT# = input with pull up
> DONE = input with pull up
> CCLK = IOW#
> CS# = CS# from ISA bus (0x360)
> DATA = DATA
>
> To start I pulse the PROGRAM# low and wait for INIT# to come high.
> Then I start writing to addres 0x360.
> After the last byte the DONE line is high, but the INIT line is low.
> According to the datasheet this line should be high aswell. The content of
> the FPGA is correct, I can access the internal registers.
> Why is the INIT# pin low?
>
> Thanks in advance


Article: 39901
Subject: Re: EDIF to .bit file conversion for Xilinx Spartan XCS10
From: Johann Glaser <Johann.Glaser@gmx.at>
Date: Thu, 21 Feb 2002 23:54:08 +0100
Links: << >>  << T >>  << A >>
Hi!

> Ain't gonna happen.  They are not going to spend even the tiniest amount
> of money and effort to support new designs using the original Spartan
> family with free tools.  The only way you're going to get what you need
> for those parts is to buy the real software or the student edition.

Hmm, I found two different packages at Amazon:
 - Xilinx Student Edition, Version 1.5
 - Xilinx Student Edition 2.1i

The first one is suggested at the Xilinx web page but out of print. The
second one is cheaper ($55 instead of $70) but is not mentioned at the
Xilinx web page.

But do they really support my XCS10?

I ordered an eval board with a SpartanIIE  XC2S200E FPGA on it. This must
be supported by the student's version too. And: I want to build an 80MSps
DSO with a Xilinx FPGA, so perhaps I need more that 20k gates.

> Save yourself a bunch of hassle and switch to the Spartan II.

I don't want to throw away my DigiLab. It has nice things on it to play
with.

Bye
  Hansi

Article: 39902
Subject: Re: How can I do a Verilog/VHDL mixed language design in ISE WebPACK 4.1
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Thu, 21 Feb 2002 23:42:12 +0000
Links: << >>  << T >>  << A >>


Kevin Brace wrote:

>         I am wondering if someone has done a Verilog/VHDL mixed language
> design in ISE WebPACK 4.1 with XST.
> I have a top module written in Verilog, and a lower module written in
> VHDL.
> What I want to do here is to instantiate the lower module written in
> VHDL from the top module written in Verilog, and implement the design
> (Implementing a design means going through NGDBUILD -> MAP -> PAR.).
> However, the problem with ISE WebPACK 4.1 is that when I create a
> project, I have to select a Verilog flow, a VHDL flow, or an EDIF flow,
> and there is no support for mixed Verilog/VHDL flow.
> I know my question sounds like a real beginner's question, but should I
> create two different projects, one for the Verilog top module and
> another one for VHDL lower module, declare a blackbox in the Verilog top
> module, synthesize them separately with XST, and glue them together with
> NGDBUILD?
> Also, in addition to the VHDL module, can I also attach an EDIF module
> to the Verilog top module in NGDBUILD?
> Has anyone done any of these, and are there things I should watch out
> for?
>
> Thanks,
>
> Kevin Brace (Don't respond to me directly, respond within the
> newsgroup.)

Answer is basically yes you can do it but its a lot easier if you dump the
GUI ``projects' & go command line + makefile, in anything other than the
short term you won't regret it..



Article: 39903
Subject: Re: Need largest CPLD devices?
From: "X. Q." <qijun@okigrp.com.sg>
Date: Fri, 22 Feb 2002 08:35:04 +0800
Links: << >>  << T >>  << A >>
Well, the problem is that the group who wants this design knows nothing
about FPGA. I need to make it such that when they plug in the power
supply, the correct signals come out of the board. They need these signals
for testing their chips.

I am still not pretty sure about Actel and QuickLogic. Does it take lot of
time and labor to change my toolset from Xilinx to Actel or QuickLogic?

For EEPROM stuff, what do I need in order to save my configuration files
into a EEPROM? I found that in my iMPACT window I only see the FPGA
device, not so much EEPROM device, even though there is one PROM on the
board.

Thanks.
XQ.






"Falk Brunner" <Falk.Brunner@gmx.de> wrote in message
news:a53d2g$4agru$2@ID-84877.news.dfncis.de...
> "X. Q." <qijun@okigrp.com.sg> schrieb im Newsbeitrag
> news:3c746c0c@news.starhub.net.sg...
> > I built my design with Spartan-II. Now the research centre in another
> > country
> > needs my design. Let's pressume they don't have any expertise in FPGA
and
>
> So why dont you send
>
> a) the HDL code
> b) the netlist
>
> ?? So they can use it.
>
> > such, while they want my design. How can I transport my design to them?
My
> > design is 10K gates in ASIC. Can I get any CPLD which can hold this
> design?
>
> AFAIK there is no such big CPLD around. 1024 macrocells is the maximum.
>
> > I understand FPGA dies after I unplug the power.
>
> They dont ;-), They just lose their configuration, because it is stored in
> SRAM. But ACTEL sells FLASH and Antifuse based devices, they keep their
> programming after power OFF.
> Anyway, I dont quite see your problem. IF the "other" gus have a board
with
> a FPGA, (maybe same familie as you have) then they can easyly recompile
the
> code and are done.
>
> --
> MfG
> Falk
>
>
>
>



Article: 39904
Subject: Re: Problems : INOUT not allowed, alternatives
From: "Tim" <tim@rockylogic.com.nooospam.com>
Date: Fri, 22 Feb 2002 00:36:22 -0000
Links: << >>  << T >>  << A >>
Remember that the Virtex internal T/S is not really a
tristate bus.  That is why it is so fast and uses minimal
power.

Jason LaPenta wrote

> I'm not sure how to classify this problem so here's my best
> explaination. I'm using a Xilinx part, and in order to use LVDS, LVPECL,
> or 5V outputs, I need to specify the IOBUFs manually. Xilinx does not
> have an IOBUF that takes inout data from the internal FPGA, so I'm
> required to breakout the internal tristate buffers into an input,
> output, and tristate signals. This is turning my code into a real mess.




Article: 39905
Subject: Re: Need largest CPLD devices?
From: Jim Granville <jim.granville@designtools.co.nz>
Date: Fri, 22 Feb 2002 14:10:58 +1300
Links: << >>  << T >>  << A >>
X. Q. wrote:
> 
> Well, the problem is that the group who wants this design knows nothing
> about FPGA. I need to make it such that when they plug in the power
> supply, the correct signals come out of the board. They need these signals
> for testing their chips.
> 
> I am still not pretty sure about Actel and QuickLogic. Does it take lot of
> time and labor to change my toolset from Xilinx to Actel or QuickLogic?

Yes, way more time than learning about EE Configurators and their SW :-)
 
> For EEPROM stuff, what do I need in order to save my configuration files
> into a EEPROM? I found that in my iMPACT window I only see the FPGA
> device, not so much EEPROM device, even though there is one PROM on the
> board.

Most companies have download SW for configuration PGM. 
 eg Atmel uses i2c to pgm their AT17 family.

If your customer has a std device programmer, they can also pgm the EE
devices, then plug it into a socket - then you just email them a new
file,
and they can label each device, if they need PC-free tester operation. 

-jg

Article: 39906
Subject: Re: Coolrunner and ISP
From: rickman <spamgoeshere4@yahoo.com>
Date: Thu, 21 Feb 2002 20:15:17 -0500
Links: << >>  << T >>  << A >>
That is not the problem.  My problem is that the wiring for the JTAG
chain gets very complex.  I have two processors and two PLDs in the
chain.  I need to run in five different modes; 

1) All four devices in one Boundary Scan chain. 

2) DSP as alone as I can get it for emulation. 

3) MCU totally alone for emulator that does not work in a chain. 

4) CPLD driven by MCU for in-system and in-field change to bit file. 

5) (optional maybe) CPLD in chain driven from header for factory load of
bit file. 
This one might be done in mode 1) or in mode 4)

I have not figured out exactly how to connect the parts in mode 2 and 4
at the same time without jumpers since both have to be supported for
customer use.  I may be able to have mode 4) as the default and have the
user change jumpers to get to mode 2.  But I don't have room on the
board for a lot of jumpers.  We also have to support mode 1 with jumpers
and 3 with a header soldered for our debug use. 

If I give up on mode 1 (boundary scan) it gets a lot simpler.  Mode 2
has it's own connector.  Mode 3 and 4 can be suppored by a temp fixture
for factory test and programming.  A jumper will connect them for field
updates to the CPLD.  But the boundary scan seems like it is a VERY
useful tool.  

The real problem is the lousy support of scan chains by the emulation
tool vendors.  They don't seem to understand that JTAG ports are for
anything other than emulation.  



Alan Nishioka wrote:
> 
> rickman wrote:
> 
> >That may sound easy, but there are four devices on the board in the scan
> >chain; a DSP chip, the MCU, an XC2Se FPGA and the XCR3256XL CPLD. I had
> >planned to program the CPLD and FPGA via the DSP rather than directly
> >from the MCU (the MCU can access the entire DSP memory map via the DSP
> >host port). There are no extra pins on the MCU to directly control the
> >CPLD. Also, with the CPLD in the scan chain, I don't see how the TDI pin
> >can be driven by a device on the board unless the CPLD is the first
> >device in the chain. But even then, when the CPLD is driven by the MCU,
> >all the other devices in the scan chain will be clocked on their JTAG
> >port including the MCU!
> >
> JTAG should operate completely independently from the function of any
> chip.  You should be able to put all the other chips in JTAG bypass
> (while they are running or not) and only affect the single chip you want
> (the CPLD).  JTAG CPU emulators work this way.  They allow the CPU to
> run at full speed and still allow access to the CPU internals via the
> JTAG port.
> 
> Alan Nishioka
> alann@accom.com

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 39907
Subject: Re: Problems : INOUT not allowed, alternatives
From: Muzaffer Kal <muzaffer@dspia.com>
Date: Thu, 21 Feb 2002 17:22:50 -0800
Links: << >>  << T >>  << A >>
Jason LaPenta <S_PAM_lapenta_jm@yahoo.com_spam> wrote:

>Hello,
>
>I'm not sure how to classify this problem so here's my best
>explaination. I'm using a Xilinx part, and in order to use LVDS, LVPECL,
>or 5V outputs, I need to specify the IOBUFs manually. Xilinx does not
>have an IOBUF that takes inout data from the internal FPGA, so I'm
>required to breakout the internal tristate buffers into an input,
>output, and tristate signals. This is turning my code into a real mess. 
>
>Has anyone run into this problem and found an elegant solution?
>
>Thanks
>Jason
>s_p_a_m_lapenta_jm@yahoo.com_spam

You have a more basic problem in that you can't transfer tri-state
signals across buffers anyway. IOW, tri-state signals only make sense
at the intersection of two tri-state buffers with a single wire. You
can't take the output of a tri-state buffer with a wire to another
driver. You have to bring out your in, out, and enable signals to the
IO pin. There is no other way.


Article: 39908
Subject: Re: FPGA choices and questions
From: rickman <spamgoeshere4@yahoo.com>
Date: Thu, 21 Feb 2002 20:27:20 -0500
Links: << >>  << T >>  << A >>
Ulf Samuelsson wrote:
> 
> >
> > Does that mean that the JTAG-ICE will support debug with the device in a
> > scan chain? I am interested in using the AVR ATmega64 or 128 in a design
> > with boundary scan and a couple of FPGAs. But I am being told even
> > though the ATmega chips support boundary scan and JTAG debug, the
> > software doesn't support JTAG debug with the chip in a scan chain!!!
> > Boundary scan without a scan chain does not make a lot of sense.
> >
> > It would make some sense that when they change the software to handle
> > the two devices in one chip, they might fix the software to handle a
> > chip in a scan chain as well...
> >
> 
> Current "normal" AVR parts needs to be the  first part in the scan chain for
> it to work
> for boundary scan.
> I hope to see some development here in the future :-)
> 
> --
> Best Regards

I am not clear on what you are saying.  Are you saying that the JTAG-ICE
emulator will work with the ATmega if it is the first device in the
chain?  This is different from what I have been told so far which is
"JTAG-ICE was not designed to work in a scan chain", period.  

If that is the only requirement, I can do that!!!


-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 39909
Subject: Re: Linux tools
From: "B. Joshua Rosen" <bjrosen@polybus.com>
Date: Thu, 21 Feb 2002 20:59:10 -0500
Links: << >>  << T >>  << A >>
In <m31ykmpnq6.fsf@tade.bendor.com.au>, Zoltan Kocsi wrote:

> I was away for a while from the NG, is there any word on FPGA vendors
> offering (or planning to) Linux toolchains (in the same config and
> pricing as their Win tools) ?
> 
> Thanks,
> 
> Zoltan
> 

http://www.xilinx.com/prs_rls/software/0225_Em_Linux.html

Article: 39910
Subject: Re: Coolrunner and ISP
From: Jim Granville <jim.granville@designtools.co.nz>
Date: Fri, 22 Feb 2002 15:28:32 +1300
Links: << >>  << T >>  << A >>
rickman wrote:
> 
> That is not the problem.  My problem is that the wiring for the JTAG
> chain gets very complex.  I have two processors and two PLDs in the
> chain.  I need to run in five different modes;
> 
> 1) All four devices in one Boundary Scan chain.
> 
> 2) DSP as alone as I can get it for emulation.
> 
> 3) MCU totally alone for emulator that does not work in a chain.
> 
> 4) CPLD driven by MCU for in-system and in-field change to bit file.
> 
> 5) (optional maybe) CPLD in chain driven from header for factory load of
> bit file.
> This one might be done in mode 1) or in mode 4)
> 
> I have not figured out exactly how to connect the parts in mode 2 and 4
> at the same time without jumpers since both have to be supported for
> customer use.  I may be able to have mode 4) as the default and have the
> user change jumpers to get to mode 2.  But I don't have room on the
> board for a lot of jumpers.  We also have to support mode 1 with jumpers
> and 3 with a header soldered for our debug use.
> 
> If I give up on mode 1 (boundary scan) it gets a lot simpler.  Mode 2
> has it's own connector.  Mode 3 and 4 can be suppored by a temp fixture
> for factory test and programming.  A jumper will connect them for field
> updates to the CPLD.  But the boundary scan seems like it is a VERY
> useful tool.
> 
> The real problem is the lousy support of scan chains by the emulation
> tool vendors.  They don't seem to understand that JTAG ports are for
> anything other than emulation.

 What about a SPLD like a 16V8, to klude what's needed ?

- jg

Article: 39911
Subject: cross clock domain signals
From: jaiphen_interqos@yahoo.com.hk (starpanda)
Date: 21 Feb 2002 20:13:16 -0800
Links: << >>  << T >>  << A >>
Hi,
Right now I am developing a design which has to use a Asyn FIFO. Due
to resource limitation, I have to use a dual port RAM to implement
this Asyn FIFO (Read in one clock domain, write in another clock
domain). I have to implement my own "Full" and "Empty" signals, but
both signals involves signals in both clock domain (head and tail
pointers). What should I do to avoid metastability problem when I try
to calculate the data size of the FIFO?
Thanks!

Jaiphen

Article: 39912
Subject: Re: Problem While Downloading to Spartan 2 FPGA using JTAG
From: yatiks@yahoo.com (Kumar)
Date: 21 Feb 2002 20:23:09 -0800
Links: << >>  << T >>  << A >>
"Falk Brunner" <Falk.Brunner@gmx.de> wrote in message news:<a53d2h$4agru$3@ID-84877.news.dfncis.de>...
> "Kumar" <yatiks@yahoo.com> schrieb im Newsbeitrag
> news:b479edf8.0202202254.58dbda7e@posting.google.com...
> 
> > Then I connected the same Board to other PC with less speed( config
> > --366 Mhz Celeron ) I have not faced any problem in programming the
> > FPGA ( XC2s200-5PQ208 ) through JTAG with same cable (length = appr 5
> > feet).
> >
> >   Can anybody tell what is causing the problem (is the speed of the PC
> > or something else)  and also how can I solve this problem ????????
> 
> Looks like a driver problem.

 I dont think its a driver problem because when I connected the
printer to this port ,Printer worked properly.

Yathish

Article: 39913
Subject: what's different between Foundation series and FPGA express
From: "rick" <ooo@yahoo.com>
Date: Fri, 22 Feb 2002 04:58:43 GMT
Links: << >>  << T >>  << A >>
Does anybody still use the Foundation series 2.1? Do you do synthesize,
simulation and verification(post simulation) within "the Project Manager"?
The 2.1i package includes "the FPGA Express", does it have the simulation
function? Thanks.







Article: 39914
Subject: Re: Handel-C, System-C, Formal verification ???
From: Phil Hays <spampostmaster@attbi.com.com>
Date: Fri, 22 Feb 2002 05:00:40 GMT
Links: << >>  << T >>  << A >>
glen herrmannsfeldt wrote:

> If you are going to completely rewrite the algorithm, it doesn't seem
> that it will help your problem.

Yes, and it's not clear to me how much rewrite is involved.


-- 
Phil Hays

Article: 39915
Subject: Re: Handel-C, System-C, Formal verification ???
From: Phil Hays <spampostmaster@attbi.com.com>
Date: Fri, 22 Feb 2002 05:03:34 GMT
Links: << >>  << T >>  << A >>
Kelly Hall wrote:

> (www.proceler.com).  They advertise a system that automatically
> partitions your C code into hardware and software, targetting the
> hardware to an FPGA and the software to a CPU.

The size of our system is a lot bigger than what they claim to target, but
thanks for the pointer.


-- 
Phil Hays

Article: 39916
Subject: Re: Problem While Downloading to Spartan 2 FPGA using JTAG
From: yatiks@yahoo.com (Kumar)
Date: 21 Feb 2002 21:05:32 -0800
Links: << >>  << T >>  << A >>
"Mark van de Belt" <mark@nijenrode.demon.nl.spam.invalid> wrote in message news:<u7apohsnbc79e2@corp.supernews.com>...
> I think the problem is with the BIOS setting for the parallel port. You have
> to set it to EPP (or was it ECP, i'm not sure).
> 
> This could solve your problem

      No Mark ,I changed the BIOS settings from "Bidirectional" to
"EPP" .
The result is same not able to connect . I connected the printer to
same port ,it worked properly .My IO address is 0378 and Interrupt
request 07.
There is no DMA Or one more IO range .Mother Board chipset 850D .Here
is some information of log file
which may help in solving the problem

Device #1 selected
AutoDetecting cable. Please wait.
CB_PROGRESS_START - Starting Operation.
Connecting to cable (USB Port).
Cable connection failed.
Connecting to cable (Parallel Port - LPT1).
Connecting to cable (Parallel Port - LPT2).
Connecting to cable (Parallel Port - LPT3).
Connecting to cable (COM1 Port).
Cable connection failed.
Connecting to cable (COM2 Port).
Cable connection failed.
Connecting to cable (COM3 Port).
Cable connection failed.
Connecting to cable (COM4 Port).
Cable connection failed.
Elapsed time =     23 sec.
Cable autodetection failed.
WARNING:iMPACT:547 - Can not find cable, please check cable setup !
=>

Thank u
yathish

Article: 39917
Subject: Re: Problem While Downloading to Spartan 2 FPGA using JTAG
From: Ray Andraka <ray@andraka.com>
Date: Fri, 22 Feb 2002 05:08:14 GMT
Links: << >>  << T >>  << A >>
Check to make sure the power connections on the cable are connected to the board.  IIRC, Parallel cable III needs a 5v
supply.  If it is not powered, the cable won't be recognized.

Kumar wrote:

> "Mark van de Belt" <mark@nijenrode.demon.nl.spam.invalid> wrote in message news:<u7apohsnbc79e2@corp.supernews.com>...
> > I think the problem is with the BIOS setting for the parallel port. You have
> > to set it to EPP (or was it ECP, i'm not sure).
> >
> > This could solve your problem
>
>       No Mark ,I changed the BIOS settings from "Bidirectional" to
> "EPP" .
> The result is same not able to connect . I connected the printer to
> same port ,it worked properly .My IO address is 0378 and Interrupt
> request 07.
> There is no DMA Or one more IO range .Mother Board chipset 850D .Here
> is some information of log file
> which may help in solving the problem
>
> Device #1 selected
> AutoDetecting cable. Please wait.
> CB_PROGRESS_START - Starting Operation.
> Connecting to cable (USB Port).
> Cable connection failed.
> Connecting to cable (Parallel Port - LPT1).
> Connecting to cable (Parallel Port - LPT2).
> Connecting to cable (Parallel Port - LPT3).
> Connecting to cable (COM1 Port).
> Cable connection failed.
> Connecting to cable (COM2 Port).
> Cable connection failed.
> Connecting to cable (COM3 Port).
> Cable connection failed.
> Connecting to cable (COM4 Port).
> Cable connection failed.
> Elapsed time =     23 sec.
> Cable autodetection failed.
> WARNING:iMPACT:547 - Can not find cable, please check cable setup !
> =>
>
> Thank u
> yathish

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 39918
Subject: Re: Problem While Downloading to Spartan 2 FPGA using JTAG
From: yatiks@yahoo.com (Kumar)
Date: 21 Feb 2002 21:08:20 -0800
Links: << >>  << T >>  << A >>
"Tim" <tim@rockylogic.com.nooospam.com> wrote in message news:<1014321889.1479.0.nnrp-12.9e9832fa@news.demon.co.uk>...
> "Falk Brunner" wrote
> 
> > "Kumar" <yatiks@yahoo.com> schrieb im Newsbeitrag
> > news:b479edf8.0202202254.58dbda7e@posting.google.com...
> >
> > > Then I connected the same Board to other PC with less speed( config
> > > --366 Mhz Celeron ) I have not faced any problem in programming the
> > > FPGA ( XC2s200-5PQ208 ) through JTAG with same cable (length = appr 5
> > > feet).
> > >
> > >   Can anybody tell what is causing the problem (is the speed of the PC
> > > or something else)  and also how can I solve this problem ????????
> >
> > Looks like a driver problem.
> 
> Or inadequate signal levels from the PC?

May be 
How can we check that or How to solve ?

Thank u 
Yathish

Article: 39919
Subject: Re: Handel-C, System-C, Formal verification ???
From: Phil Hays <spampostmaster@attbi.com.com>
Date: Fri, 22 Feb 2002 05:10:18 GMT
Links: << >>  << T >>  << A >>
"z.karim" wrote:

> As far as determining what speed at which the design runs,
> you have to place and route the design immediately to get the speed at
> which it will run.  Handel-C has all the constructs to allow you to dictate
> the architecture; it just takes a couple days to get the feel for how it
> generates hardware.  I have used it and have been happy with the
> results: easily passing 100MHz in Spartan II and 200MHz in Virtex II.

Thanks for the input.  It's nice to hear from real users before spending time
and effort evaluating something new.  I'm going to get the crippleware
(evaluation) version, and if that looks ok I'm going to get a full evaluation
version and try some code.

> It does have the capability of spitting out VHDL so you can simulate your 
> result;

Is the feature usable for design debug on a large problem?  Or is the generated
VHDL so fragmented that it's hard to use?


-- 
Phil Hays

Article: 39920
Subject: Re: Handel-C, System-C, Formal verification ???
From: Phil Hays <spampostmaster@attbi.com.com>
Date: Fri, 22 Feb 2002 05:11:36 GMT
Links: << >>  << T >>  << A >>
Thomas Stanka wrote:

> What you need is a tool for model checking
> between C and VHDL. I don't think, you might find such a tool.

I'm dropping the idea of formal verification between C and VHDL.  Thanks.


-- 
Phil Hays

Article: 39921
Subject: Re: Coolrunner and ISP
From: Ray Andraka <ray@andraka.com>
Date: Fri, 22 Feb 2002 05:12:08 GMT
Links: << >>  << T >>  << A >>
Ayup,  I've been on a number of projects where they finally threw up their
hands and said forget trying to put the DSP and FPGA/CPLD JTAG on the same
chain because the emulators had a nasty habit of really screwing up the
FPGA/CPLD.  When faced with the question, the emulator vendors said "well,
don't do that".

rickman wrote:

> The real problem is the lousy support of scan chains by the emulation
> tool vendors.  They don't seem to understand that JTAG ports are for
> anything other than emulation.
>
>

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 39922
Subject: Beginner Altera Questions
From: alw@al-williams.com (Al Williams)
Date: 21 Feb 2002 21:19:03 -0800
Links: << >>  << T >>  << A >>
I'm just getting accustomed to using the MAX3000A using Max PLUS II
and Leonardo Spectrum. A few questions...

1) Is there any way to parameterize your Verilog so that once you
bring the edif into MAX PLUS II you can still change the parameters?
It looks like the parameters get fixed after passing it through LS. My
guess is this is how it has to be, but that makes the MPII's inability
to do Verilog (for free, at least) a disadvantage.

2) I tried to put MPII and LS on my laptop. I disconnected from the
network and MPII still works, but LS complains I don't have a valid
license. Of course, LS won't even try to work from an HD serial port
license. I haven't tried it connected to the network, but ipconfig can
still see my adapter and apparently so can MPII. Any ideas?

3) Anyone have any good references to some of the obscure design
doctor messages I've been getting? In particular, I keep getting a
delay warning on a reset line that makes no sense to me.

Just groping around for now. Any advice is welcome.

Al W.

Article: 39923
Subject: Re: Beginner Altera Questions
From: "jerry1111" <jerry1111@wp.pl>
Date: Fri, 22 Feb 2002 08:03:05 +0100
Links: << >>  << T >>  << A >>
> 2) I tried to put MPII and LS on my laptop. I disconnected from the
> network and MPII still works, but LS complains I don't have a valid
> license. Of course, LS won't even try to work from an HD serial port
> license. I haven't tried it connected to the network, but ipconfig can
> still see my adapter and apparently so can MPII. Any ideas?

If it's protected by NIC (network interface card) number it
may not work when net is unplugged.

jerry



Article: 39924
Subject: init RAM in VirtexII
From: "Seb" <no@valid.address.com>
Date: Fri, 22 Feb 2002 08:20:41 +0100
Links: << >>  << T >>  << A >>
I want to initialise the memory core that i made with CoreGen. This can be
done by making a .coe file before building the core. So if i want to change
the initialisation data, i have to rebuild the core...again and again.

My question: is it possible to construct the core with a pointer to the .coe
file, so that the content is included in a later stage (by ISE)...this way
it would be possible to change the .coe file without having to rebuild the
memory core.

thanx.
cheers,
Seb





Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarApr2017

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search