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Messages from 35850

Article: 35850
Subject: what is carry mode INC-F-CI ?
From: "Marc Battyani" <Marc.Battyani@fractalconcept.com>
Date: Sat, 20 Oct 2001 15:03:43 +0200
Links: << >>  << T >>  << A >>
While compiling a design (Spartan XL, ISE4.1 SP1) I get this:

WARNING:OldMap:929 - Signal `N_Debug6' on pin A1 of CY4 symbol "C82/C3/C2"
   (output signal=C82/C3/cout0_net) is not required by carry mode INC-F-CI.
The signal is being removed.

Well why not, but Debug6 is an external pin of the device and I need this
signal outside....
I also need this signal inside. It's a clock and when it is removed like
this, the mapper decides that half of the chip can be removed.

So what is the problem with carry mode INC-F-CI ?
Any ideas ?

Marc



Article: 35851
Subject: Xilinx Libraries
From: ramnathgoenka@yahoo.com (Ramnath)
Date: 20 Oct 2001 09:47:45 -0700
Links: << >>  << T >>  << A >>
Hi,

    We have got a xilinx Foundation Series 1.5v in our college
department. It supports all devices upto virtex 2.5.

    Lately i have download the free " WEBPACK ISE " from the Xilinx
website. That pack supports for all virtex products ( including the
virtex II).

   Now my question is, can i make use of the virtex II library of "
Free WEbPack ISE" in my Foundation Series 1.5v. If so how.

     Thanks is advance

 Ramnath

Article: 35852
Subject: Fpga Synthesis Process
From: ramnathgoenka@yahoo.com (Ramnath)
Date: 20 Oct 2001 11:50:45 -0700
Links: << >>  << T >>  << A >>
hi,

    I am a newbie to this area and slowly picking up things. I am
using Xilinx foundation series v 1.5 and Model sim.

    Alothough i have all these and even using these things, i do not
fully understand the concept of all.

   Could any one tell me what are the various stages in the synthesis
of FPGA.

To be exact what is done in the synthesis process, implementation
process, simulation and verification.

   What is the difference between simulation done in ModelSim and the
simulation done in Xilinx itself.

  Some one told me Modelsim is for simulation the testbeches ( still
not clear, please through some light)

       Thanks a lot in advance and expecting the reply.

Ramnath

Article: 35853
Subject: Verilog vs. VHDL
From: "AME" <AME3141592@yahoo.com>
Date: Sat, 20 Oct 2001 15:12:56 -0700
Links: << >>  << T >>  << A >>
The intention behind this message isn't to spark a war as much as it is to
ask for help in deciding between these two languages on my own.

I'm sure that this question has been asked a million times over.  I searched
through Google groups and read through a few threads on the same subject.
It seems there is not easy answer.  Only opinion.

Here's my context.  Fluent in C, C++, Forth, APL, Lisp, various machine
languages.  Used PAL's sporadically years ago with PALASM/CUPL  (I remember
using Intel's 5C060 / 5C090's to build a digital video test signal
generator).  I don't remember much of that, but I still have my
documentation, manuals and software.
Also, I've done lots of analog/digital/power hardware design work.

Goal:  I need to get going with a project that requires an FPGA at the heart
of the system.  I downloaded Xilinx Webpack and started to excercise it.
Looks good.  I have a lot to learn and need to buy some books.

So, then, how do I decide which branch to take?  VHDL or Verilog?  I want to
learn both eventually, but now, for this project, I need to pick one.  My
first impulse is to go with Verilog.  VHDL looks painful right now.  But,
then
again, that may be 'cause I'm comfortable with C.  And I certainly don't
want to decide based on something that superficial.

I just got done with the excellent free Aldec tutorials (www.aldec.com).
Thanks Aldec!!!
They gave me a good first pass view of the options.  Next, once I decide on
which language, I need to get a good book or two and dive in.  Any
recommendations?

FWIW, here's my opinion, oversimplified, I know:

Verilog:  No-nonsense, practical, easy to get into, can bite you due to
looseness with regards to data types.  It seems like a language that was
designed to get work done.  The Aldec tutorial says that Verilog "lacks the
constructs needed for system level specification".  I'm not smart enough at
this point to fully understand this statement and know the reasons why this
is so.  Does it apply to a board with a single FPGA?.

VHDL:  Designed as a documentation language and can describe just about
anything.  It seems that the designers decided to ignore tried and true
convention and come-up with their own cumbersome notation for things,
example:  (7 downto 0) instead of [7:0], indexing with paranthesis instead
of brackets, etc.  In some cases the same symbology is used for totally
differnt purposes.  Because it is a documentation language, as a novice, I
think that so much effort has to go into learning to write "proper English"
that you very quickly loose sight of what the heck you were trying to solve.
Coming from a very deep APL (not AHPL) background, I have a strong dislike
for notation that seriously removes you from the problem-solving
process --so I'm biased, but I'll try to not let it cloud my evaluation.

Care to share any opinion, links, book recommendations for an FPGA newbie?

Thank you,

-Martin Euredjain
Los Angeles, CA, USA




Article: 35854
Subject: Re: Verilog vs. VHDL
From: rafael plonka <rafael.plonka@gmx.de>
Date: Sun, 21 Oct 2001 03:23:48 +0200
Links: << >>  << T >>  << A >>
A quite good online service to learn some vhdl is the http://www.vhdl-online.de
page from the university Erlangen/Nürnberg in Germany (also there exist some
mirrors, I think). And somehow, I think I am also quite new to the stuff, but
until now I never had the feeling that I need to learn both VHDL AND Verilog...
Maybe I do a mistake, but in the moment it seems to be enough with just VHDL ;-)

Rafael


Article: 35855
Subject: Re: Verilog vs. VHDL
From: "AME" <AME3141592@yahoo.com>
Date: Sat, 20 Oct 2001 18:57:27 -0700
Links: << >>  << T >>  << A >>
> And somehow, I think I am also quite new to the stuff, but
> until now I never had the feeling that I need to learn both VHDL AND
Verilog.

I have a feeling that in the US it might be useful to have command of one
and a good familiarity with the other.  Also, if you plan on using any IP it
might be important to not be locked into any one language.

-Martin




Article: 35856
Subject: Re: I search a free 8086 core...
From: "Jan Gray" <jsgray@acm.org>
Date: Sat, 20 Oct 2001 20:19:01 -0700
Links: << >>  << T >>  << A >>
I've never heard of a free one.  There are some non-free ones at
http://vautomation.com/Product.htm.  See also the FPGA CPU links at
www.fpgacpu.org/links.html.

Jan Gray, Gray Research LLC




Article: 35857
Subject: Re: Verilog vs. VHDL
From: hamish@cloud.net.au
Date: 21 Oct 2001 07:39:29 GMT
Links: << >>  << T >>  << A >>
AME <AME3141592@yahoo.com> wrote:
> VHDL:  Designed as a documentation language and can describe just about
> anything.  It seems that the designers decided to ignore tried and true
> convention and come-up with their own cumbersome notation for things,
> example:  (7 downto 0) instead of [7:0], indexing with paranthesis instead
> of brackets, etc.  In some cases the same symbology is used for totally
> differnt purposes.  

Can you give an example of this last point?

Personally I don't see why VHDL is perceived as difficult to learn.
Yes VHDL doesn't use square brackets for indexing, for example,
but I don't think that makes it difficult, only different.
I use perl regularly, and C/C++ sometimes, and don't have
any trouble switching.


regards,
Hamish
-- 
Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>

Article: 35858
Subject: Interpolating in QPSK with f_IF = f_clk/4
From: "Antonio D'Ottavio" <etantonio@jumpy.it>
Date: Sun, 21 Oct 2001 10:16:45 +0200
Links: << >>  << T >>  << A >>
Good Morning,
I'm arranging a QPSK bandpass modulator having   f_clk = 165MHz   and
f_IF =  f_clk/4 = 41,25MHz
this means that for the I use :
cosine  = 1 ,   0 , -1 , 0 , ...
sine     =  0 , -1 ,   0 , 1 , ...
these arrive to the multipliers at a rate of 165MHz, on the other inputs of
the multipliers there are the output
of two SRRC filters interpolating by 6 a symbol rate of 27,5MSpS to 165MHz.
Until now this work fine, now there is a change in the project, it must be
possible to serve also a Symbol rate
of 13,75MSpS this seems possible using the zeroes in the sine and cosine so
the idea is to use :
cosine  =   1 , -1 ,   1 , -1 , ...
sine     =  -1 ,   1 , -1 ,   1 , ...
that always arrive at the multipliers at a rate of 165MHz while the SRRC
always interpolate 6.
My question is :
1) Do you think that this is correct especially regarding the fact that for
example the 1 arrive to the multiplier
    of the cosine in the same istant that the -1 arrive to the multiplier of
the sine, in fact I think that sine and
    cosine form an orthogonal base but not in this latest form, what do you
think about ???

2) If you think that this is correct do you think that I must use 2 filters
following the 2 multipliers to take in
    account that an interpolator is formed by an upsampler and a filter, in
this case how you suggest me to
    design this filter ??

Thanks for your interest ..

                                                           Antonio D'Ottavio





Article: 35859
Subject: FPGA based IPv6 router -- hi
From: ramnathgoenka@yahoo.com (Ramnath)
Date: 21 Oct 2001 02:36:55 -0700
Links: << >>  << T >>  << A >>
hai Everybody,

   I am a postgraduate student from Indian Institiute of technology
India. My project topic is

   "  Desgin and implementation of FPGA based Ipv6 router "

   As the topic more complex i plan to make a packet forwader with the
routing table being maintained by some other process.

   I expect some guidelines and other comments from the experienced
guru's

   Expecting a positive reply and advance thanks

   Ramnath
   M.Tech CSE
   IIT Guwahati
   ramnathgoenka@yahoo.com

Article: 35860
Subject: Re: Verilog vs. VHDL
From: Brian Drummond <brian@shapes.demon.co.uk>
Date: Sun, 21 Oct 2001 13:54:29 +0100
Links: << >>  << T >>  << A >>
On Sat, 20 Oct 2001 15:12:56 -0700, "AME" <AME3141592@yahoo.com> wrote:

>The intention behind this message isn't to spark a war as much as it is to
>ask for help in deciding between these two languages on my own.
>
>I'm sure that this question has been asked a million times over.  I searched
>through Google groups and read through a few threads on the same subject.
>It seems there is not easy answer.  Only opinion.
>
>Here's my context.  Fluent in C, C++, Forth, APL, Lisp, various machine
>languages.  

Not Pascal, not Modula-[2|3], not ADA, no pure OO languages like
Smalltalk or Eiffel?

>So, then, how do I decide which branch to take?  VHDL or Verilog? 

>VHDL:  Designed as a documentation language and can describe just about
>anything.  It seems that the designers decided to ignore tried and true
>convention and come-up with their own cumbersome notation for things,

Not designed as a documentation language but derived from a type-safe
language from a high-reliability environment, based on its own tried and
true convention. The designers apparently thought such things might be
important in hardware design.

>example:  (7 downto 0) instead of [7:0], indexing with paranthesis instead
>of brackets, etc.  

(7 downto 0) is different from (7 to 0) and (0 to 7). 
Now (7 to 0) clearly means nothing sensible, (a zero width bus), but
what about (a to b)?

What does [7:0] actually mean? [0:7]? 

How about [a:b]? Does Verilog start to look vague and ill-defined?

> Because it is a documentation language, as a novice, I
>think that so much effort has to go into learning to write "proper English"
>that you very quickly loose sight of what the heck you were trying to solve.

I find that it makes you think about what you mean, and catches many
things that could become niggling bugs if left to themselves. Sure, you
have to type a few extra characters (or let the tools generate them) but
I've not found myself losing sight of the problem.

>Coming from a very deep APL (not AHPL) background, I have a strong dislike
>for notation that seriously removes you from the problem-solving
>process --so I'm biased, but I'll try to not let it cloud my evaluation.

I'm sure that with C experience, and apparently not the more formal
languages - you will be more comfortable with Verilog, at least
initially. 

However I suspect that if you expend the effort to learn VHDL, you will
find it lets you use notation to keep you close to the problem-solving
process. Of course, you may have to _build_ much of that notation
yourself, but to do that you need good abstraction mechanisms - the
ability to step back from the details - for example, to define your own
set of operators - and that's what VHDL can provide.


(The short form: C programmers prefer Verilog becaue it more closely
resemble C than Pascal. I prefer VHDL for _precisely_ the same reason
:-)

Cheers, 
- Brian

Article: 35861
Subject: Re: I search a free 8086 core...
From: Philipp Krause <pkk@spth.de>
Date: Sun, 21 Oct 2001 17:59:30 +0200
Links: << >>  << T >>  << A >>
Radó Zoltán wrote:

> Someone can help me?
> 
> Thanks for all,
> Zoltan Rado
> 
> 
> 

There is a free 8080 core. Maybe you can use it as a starting point.
There once was a 8086 clone produced in the sovied union. Maybe you can 
find out something about that.


Article: 35862
Subject: Virtex II powerdown
From: "rs" <remi-seglie@infonie.fr>
Date: Sun, 21 Oct 2001 18:07:19 +0200
Links: << >>  << T >>  << A >>
It's not very clear in the data sheet : does the PWRDWN_B must at 1 or 0 for
powerdown ?



Article: 35863
Subject: Re: how to dublicate logic?
From: vasunews@rediffmail.com (Vasudeva Kamath)
Date: 21 Oct 2001 10:19:03 -0700
Links: << >>  << T >>  << A >>
Jens-Christian Lache <lache@tu-harburg.de_removeTheUnderscore> wrote in message news:<3BB2DFB8.BA6A9116@tu-harburg.de_removeTheUnderscore>...
> John_H wrote:
> 
> > >
> > > Hi!
> > > To reduce the fanout of a tristate signal leading to 64 iobs I
> > > tried dublicate this signal. How do I tell
> > > the synthesis tool now not to remove my dublicated logic?
> > > ( I tried to use a BUFG as well, but that didn't work at all)
> > > thanks for your help,
> > > -jc-
> 
> The synthesis tool is synopsis fpga express.
> -jc-

You can try the "dont touch" option in fpga express, to prevent the
synthesis tool from removing any logic.

--Vasudeva

Article: 35864
Subject: Re: Virtex II powerdown
From: Eric Crabill <eric.crabill@xilinx.com>
Date: Sun, 21 Oct 2001 10:23:57 -0700
Links: << >>  << T >>  << A >>

Hello,

I believe the "_B" indicates that the signal is active low.

Eric

rs wrote:
> 
> It's not very clear in the data sheet : does the PWRDWN_B must at 1 or 0 for
> powerdown ?

Article: 35865
Subject: Re: Verilog vs. VHDL
From: "AME" <AME3141592@yahoo.com>
Date: Sun, 21 Oct 2001 11:55:02 -0700
Links: << >>  << T >>  << A >>
<hamish@cloud.net.au> wrote in message
news:3bd27bb1$0$26089$afc38c87@news.optusnet.com.au...

> > ...  In some cases the same symbology is used for totally
> > differnt purposes.
>
> Can you give an example of this last point?

Sure.   "<=" used for "assignment" as well as "less than or equal to".

Of course, you might say that the context differntiates which is meant.
Well, take, for example:

a <= b <= c;

1-  Does this mean "evaluate b less-than-or-equal-to c and assign this to
a"?
2-  Or, does it mean, "c to both b and an"?

As I understand the language now, you need to know whether a is a signal or
a variable.  I could be wrong on this, but I think that if a is a signal
then then the above statement functions per 1 above.  If a is a variable
then it works per 2 above.


> Personally I don't see why VHDL is perceived as difficult to learn.
> Yes VHDL doesn't use square brackets for indexing, for example,
> but I don't think that makes it difficult, only different.

The bracket vs. parenthesis example I gave wasn't meant to be the basis for
establishing difficulty, it was just an example.

BTW, I am not trying to put down either Verilog or VHDL.  I'm just trying to
figure out how to decide which one to dive into at this point in time.

Thanks for your input.

-Martin




Article: 35866
Subject: Re: Verilog vs. VHDL
From: kevinbraceusenet@hotmail.com (Kevin Brace)
Date: 21 Oct 2001 13:50:33 -0700
Links: << >>  << T >>  << A >>
Although I have less than a year experience using Verilog, I will like
to chip in my two cents.
A little less than a year ago, I also had to decide whether or not I
wanted to use Verilog or VHDL.
I picked Verilog because the language seemed somewhat simpler than
VHDL, and seemed like there is less unnecessary writing than VHDL to
do the same thing.
Although I do have three things I don't like about Verilog.
The first thing will be that keywords "begin" and "end."
I think they should instead be "{" and "}" like in C language.
The second thing will be that Verilog has weak conditional compilation
support.
For example, compiler directive "`ifdef" can only check to if a text
macro is defined, and can't check a value (in other words, "`if"
doesn't exist in Verilog).
The third thing will be type checking.
Yes, VHDL has stricter type checking, and Verilog's is less
restrictive.
I personally think type checking should be strict.
        Regardless of what Aldec says about Verilog from what I read
(like EE Times), most ASIC designs done in the US uses Verilog, not
VHDL.
Aldec claims that Verilog "lacks the constructs needed for system
level specification," but if so, is VHDL any better? (I don't know. I
don't use VHDL.)
        There seems to be more VHDL books out there compared to
Verilog (for example, in Borders or Barns & Noble).
One thing I think is a problem of almost all HDL (Verilog and VHDL)
books out there is that the books don't clearly define which element
of the language is synthesizable by the synthesis tool and which is
not.
Instead, almost all books mixes up the stuff that no one uses, the
stuff that can't be synthesized, and the stuff that can be
synthesized.
A beginner has no idea of the concept of what is synthesizable, so
that person will waste time learning stuff no one uses, and less of
the stuff that is important now (the synthesizable part of the
language).
        Although I don't know if you have the hardware (prototype
board with an FPGA) already, but if you don't have any, I recommend
visiting Insight Electronics' Xilinx prototype board website
(http://www.insight-electronics.com/solutions/kits/xilinx/index.shtml).
Especially the ones that use Spartan-II are pretty affordable (I own
Insight Electronics Spartan-II PCI board which costs only $145).
        One thing you should have in mind that PLD vendors lie about
the gate count the chip has.
For example, Xilinx calls its Spartan-II XC2S150 part as 150,000
"system gates", but if you drop the "system" part of it, the
realistically achievable gate count will drop to about 25,000 gates
from my experience using that part.
The Xilinx's "system gates" inflates the realistically achievable gate
count by 6 times, so before selecting a device for your application,
you should know the gate count that the device can achieve
realistically.



Regards,



Kevin Brace (don't respond to me directly, respond within the
newsgroup)



"AME" <AME3141592@yahoo.com> wrote in message news:<9qssve01g4e@enews2.newsguy.com>...
> The intention behind this message isn't to spark a war as much as it is to
> ask for help in deciding between these two languages on my own.
> 
> I'm sure that this question has been asked a million times over.  I searched
> through Google groups and read through a few threads on the same subject.
> It seems there is not easy answer.  Only opinion.
> 
> Here's my context.  Fluent in C, C++, Forth, APL, Lisp, various machine
> languages.  Used PAL's sporadically years ago with PALASM/CUPL  (I remember
> using Intel's 5C060 / 5C090's to build a digital video test signal
> generator).  I don't remember much of that, but I still have my
> documentation, manuals and software.
> Also, I've done lots of analog/digital/power hardware design work.
> 
> Goal:  I need to get going with a project that requires an FPGA at the heart
> of the system.  I downloaded Xilinx Webpack and started to excercise it.
> Looks good.  I have a lot to learn and need to buy some books.
> 
> So, then, how do I decide which branch to take?  VHDL or Verilog?  I want to
> learn both eventually, but now, for this project, I need to pick one.  My
> first impulse is to go with Verilog.  VHDL looks painful right now.  But,
> then
> again, that may be 'cause I'm comfortable with C.  And I certainly don't
> want to decide based on something that superficial.
> 
> I just got done with the excellent free Aldec tutorials (www.aldec.com).
> Thanks Aldec!!!
> They gave me a good first pass view of the options.  Next, once I decide on
> which language, I need to get a good book or two and dive in.  Any
> recommendations?
> 
> FWIW, here's my opinion, oversimplified, I know:
> 
> Verilog:  No-nonsense, practical, easy to get into, can bite you due to
> looseness with regards to data types.  It seems like a language that was
> designed to get work done.  The Aldec tutorial says that Verilog "lacks the
> constructs needed for system level specification".  I'm not smart enough at
> this point to fully understand this statement and know the reasons why this
> is so.  Does it apply to a board with a single FPGA?.
> 
> VHDL:  Designed as a documentation language and can describe just about
> anything.  It seems that the designers decided to ignore tried and true
> convention and come-up with their own cumbersome notation for things,
> example:  (7 downto 0) instead of [7:0], indexing with paranthesis instead
> of brackets, etc.  In some cases the same symbology is used for totally
> differnt purposes.  Because it is a documentation language, as a novice, I
> think that so much effort has to go into learning to write "proper English"
> that you very quickly loose sight of what the heck you were trying to solve.
> Coming from a very deep APL (not AHPL) background, I have a strong dislike
> for notation that seriously removes you from the problem-solving
> process --so I'm biased, but I'll try to not let it cloud my evaluation.
> 
> Care to share any opinion, links, book recommendations for an FPGA newbie?
> 
> Thank you,
> 
> -Martin Euredjain
> Los Angeles, CA, USA

Article: 35867
Subject: To Christoph Hauze
From: "Dan" <daniel.deconinck@sympatico.ca>
Date: Sun, 21 Oct 2001 16:56:03 -0400
Links: << >>  << T >>  << A >>
Hello Christoph,

I would like to read your firewire thesis.

Is it on the web or can it be emailed ?

When I was an engineering student I designed an analog frame grabber. Now I
would like to try a firewire frame grabber.

Sincerely
Daniel DeConinck






Article: 35868
Subject: Re: Verilog vs. VHDL
From: "AME" <AME3141592@yahoo.com>
Date: Sun, 21 Oct 2001 19:35:25 -0700
Links: << >>  << T >>  << A >>
"Kevin Brace" <kevinbraceusenet@hotmail.com> wrote in message

> The first thing will be that keywords "begin" and "end."
> I think they should instead be "{" and "}" like in C language.

I agree.  Wasted verbosity, not any better than "{ }".

> books out there is that the books don't clearly define which element
> of the language is synthesizable by the synthesis tool and which is
> not.

I've thought about that too.  VHDL allows you to document a huge array of
things that I am sure today have no way to be realized.

> visiting Insight Electronics' Xilinx prototype board website
> (http://www.insight-electronics.com/solutions/kits/xilinx/index.shtml).

Yes, I've seen'em  I plan to get one.

Thanks for your input.

-Martin




Article: 35869
Subject: Re: Verilog vs. VHDL
From: Ray Andraka <ray@andraka.com>
Date: Mon, 22 Oct 2001 03:24:51 GMT
Links: << >>  << T >>  << A >>
Personally, I found VHDL to be more useful for a full range of design capability.  The big
thing at this point is that Verilog does not have an equivalent to the VHDL generate
statement.  This is extremely useful for building macros or anywhere else you have
replicated logic.  In my case, I have built up a library of macros built by instantiation
of primitives so that I get exactly what I want every time.  Even for those not inclined
to build macros, a generate facility is often a welcome tool for such mundane things as
building memory banks from block RAMs. As I understand it, the next generation Verilog
will have a generate statement.  VHDL also knows about attributes, so you can modify
attributes as a function of iteration in a generate statement (step and repeat placement
for example).  Verilog's attributes are comments which are quite inflexible, and appear to
be an afterthought.  They are not natural to the language.  These two items make verilog
very awkward to use in designs where you are doing some low level design to attain
performance or density.

By what measure are you determining gate count?  I typically see "equivalent gates"
reported by PAR to be 1.5 to 3 times the "system gates" size of the device.  For example,
on a recent XC2S100, I got an "equivalent gate count" reported by PAR as 184,328 gates, or
1.8x.   That has 57% of the LUTs, 68% of the slice flip-flops and 90% of the block RAM is
used.  In another recent example, an XCV2000e design reports 4,722,511 "equivalent gates",
or almost 2.4x the nominal device size.  In that case, 57% of the luts, 68% of the
flip-flops, and 100% of the block ram is used.  If you are not converting to ASICs
however, those "gates" don't have much bearing on the device capacity.  A much better
measure is a count of the number of LUTs and flip-flops you have available.

Kevin Brace wrote:

> Although I have less than a year experience using Verilog, I will like
> to chip in my two cents.
> A little less than a year ago, I also had to decide whether or not I
> wanted to use Verilog or VHDL.
> I picked Verilog because the language seemed somewhat simpler than
> VHDL, and seemed like there is less unnecessary writing than VHDL to
> do the same thing.
> Although I do have three things I don't like about Verilog.
> The first thing will be that keywords "begin" and "end."
> I think they should instead be "{" and "}" like in C language.
> The second thing will be that Verilog has weak conditional compilation
> support.
> For example, compiler directive "`ifdef" can only check to if a text
> macro is defined, and can't check a value (in other words, "`if"
> doesn't exist in Verilog).
> The third thing will be type checking.
> Yes, VHDL has stricter type checking, and Verilog's is less
> restrictive.
> I personally think type checking should be strict.
>         Regardless of what Aldec says about Verilog from what I read
> (like EE Times), most ASIC designs done in the US uses Verilog, not
> VHDL.
> Aldec claims that Verilog "lacks the constructs needed for system
> level specification," but if so, is VHDL any better? (I don't know. I
> don't use VHDL.)
>         There seems to be more VHDL books out there compared to
> Verilog (for example, in Borders or Barns & Noble).
> One thing I think is a problem of almost all HDL (Verilog and VHDL)
> books out there is that the books don't clearly define which element
> of the language is synthesizable by the synthesis tool and which is
> not.
> Instead, almost all books mixes up the stuff that no one uses, the
> stuff that can't be synthesized, and the stuff that can be
> synthesized.
> A beginner has no idea of the concept of what is synthesizable, so
> that person will waste time learning stuff no one uses, and less of
> the stuff that is important now (the synthesizable part of the
> language).
>         Although I don't know if you have the hardware (prototype
> board with an FPGA) already, but if you don't have any, I recommend
> visiting Insight Electronics' Xilinx prototype board website
> (http://www.insight-electronics.com/solutions/kits/xilinx/index.shtml).
> Especially the ones that use Spartan-II are pretty affordable (I own
> Insight Electronics Spartan-II PCI board which costs only $145).
>         One thing you should have in mind that PLD vendors lie about
> the gate count the chip has.
> For example, Xilinx calls its Spartan-II XC2S150 part as 150,000
> "system gates", but if you drop the "system" part of it, the
> realistically achievable gate count will drop to about 25,000 gates
> from my experience using that part.
> The Xilinx's "system gates" inflates the realistically achievable gate
> count by 6 times, so before selecting a device for your application,
> you should know the gate count that the device can achieve
> realistically.
>
> Regards,
>
> Kevin Brace (don't respond to me directly, respond within the
> newsgroup)
>
> "

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 35870
Subject: Re: Linux tools
From: AsherM@AsherM.com (Asher C. Martin)
Date: 21 Oct 2001 21:05:24 -0700
Links: << >>  << T >>  << A >>
timjeno@visto.com (Tim O'Connell) wrote in message news:<6612af42.0110171024.7552dac2@posting.google.com>...
> Will this include Max and Quartus or just Quartus?  Any info at all
> about how the licensing will work?  Any idea when an official
> announcement might be made?

As far as UNIX OS's go - Altera has already released Quartus II 1.1
for Solaris and HP-UX.  The Solaris port from Windows NT to Solaris
seems to be solid because the development for Unix OS's is running
parallel with the WinNT development.

However, I have no idea or comment about the official release...

>Asher<

Article: 35871
Subject: Re: FPGA based IPv6 router -- hi
From: "Srinivasan Venkataramanan" <srinivasan@siliconsystems.co.in>
Date: Mon, 22 Oct 2001 10:42:04 +0530
Links: << >>  << T >>  << A >>
Hi Ramnath,

"Ramnath" <ramnathgoenka@yahoo.com> wrote in message
news:62cc2cff.0110210136.59bd4dbf@posting.google.com...
> hai Everybody,
>
>    I am a postgraduate student from Indian Institiute of technology
> India. My project topic is
>

    Interesting, when did IITG start PGs? I was told they had only
Bachelors, anyway good to know that. All The Best.

>    "  Desgin and implementation of FPGA based Ipv6 router "
>
>    As the topic more complex i plan to make a packet forwader with
the
> routing table being maintained by some other process.
>

    I would suggest few things:

1.> If possible get hold of the book "The Switch Book"

http://www.wiley.com/Corporate/Website/Objects/Products/0,9049,37244,0
0.html

I started reading this book few months ago as I was new to the
Networking area and am finding it to be the perfect guide indeed. It
is expesnive and I am not sure if it is available easily in the Indian
market. But try and procure it via your library.

2.> My suggestion would be to first implement a small portion of the
router (as you proposed) than shooting for the whole thing. I guess
you will need to learn a HDL (VHDL/Verilog), simulation, synthesis,
FPGA mapping etc. So plan it accordingly.

Good Luck,
Srinivasan


>    I expect some guidelines and other comments from the experienced
> guru's
>
>    Expecting a positive reply and advance thanks
>
>    Ramnath
>    M.Tech CSE
>    IIT Guwahati
>    ramnathgoenka@yahoo.com


--
Srinivasan Venkataramanan
ASIC Design Engineer
Software & Silicon Systems India Pvt. Ltd. (An Intel company)
Bangalore, India, Visit: http://www.simputer.org)




Article: 35872
Subject: Re: Verilog vs. VHDL
From: "AME" <AME3141592@yahoo.com>
Date: Sun, 21 Oct 2001 22:13:46 -0700
Links: << >>  << T >>  << A >>
"Brian Drummond" <brian@shapes.demon.co.uk> wrote in message
news:isc5ttcc4gtm1t2vko4jtcej5e0v2845o7@4ax.com...


> Not Pascal, not Modula-[2|3], not ADA, no pure OO languages like
> Smalltalk or Eiffel?

Sorry, at one point I had to set some time aside to spend it with the
family....   :-)
I've never had a need to learn any of the languages you mention.

> >VHDL:  Designed as a documentation language

> Not designed as a documentation language but derived from a type-safe
> language from a high-reliability environment, based on its own tried and
> true convention. The designers apparently thought such things might be
> important in hardware design.

Well, hardware design has been done very succesfully for a long time with
schematic tools that don't have the "type-safe", "high-reliability"
environment you refer to.  Look, documentation is great.  In the software
world it comes in the form of well-commented code.  It should be the same in
the HDL world.  It seems to me that VHDL attempted to make the code
self-documenting ... and in doing that it looks real cumbersome.

Having said that, so far I am leaning towards getting started with VHDL.
There seem to be a lot more resources available for language and, while I
don't yet understand all the underlying subtleties, my gut feeling is that
working through the initial difficulties of getting in the VHDL "mindset"
might pay off in the long run.  I really don't like the verbosity and a lot
of the constructs, it seems neanderthal to me ... but I am in no position to
pass conclusive judgement, I just don't know enough about either one yet.

> >example:  (7 downto 0) instead of [7:0], indexing with paranthesis
instead
> >of brackets, etc.

Reading some of this code (VHDL or Verilog) makes me think about the idea of
creating AutoCAD drawings by hand-typing DXF files and then "compiling them"
by importing into AutoCAD.  Or the concept of writing and communicating
musical compositions with a complex set of ascii words and structures,
instead of clean and intuitive musical notation.  I'm not implying that
schematic entry is the absolute solution for FPGA design, but, in the age of
gigahertz-processors-on-every-desktop there has to be a better way to go
from problem-space to solution-space than having to type things like
"begin", "end", "process", "register", (7 downto 0), etc.

I also understand that the more abstract the description the more difficult
it is to generate efficient hardware.

OK, back to reality.


So far I'm leaning towards VHDL, even though, on first inspection, I don't
really like it.

-Martin






Article: 35873
Subject: What is a difference?
From: "Tomasz Brychcy" <T.Brychcy@ime.pz.zgora.pl>
Date: Mon, 22 Oct 2001 07:24:07 +0200
Links: << >>  << T >>  << A >>
Hello,

What is a difference between digital circuit design and digital IC design?

With sincerely,

Tomek



Article: 35874
Subject: Re: About BLIF
From: Utku Ozcan <ozcan@netas.com.tr>
Date: Mon, 22 Oct 2001 08:54:16 +0300
Links: << >>  << T >>  << A >>
"A. Chemeris" wrote:

> Hello,
>
> I ask to tell me about BLIF to smth. convertors working in Windows 9x/2000.
> I'd prefer BLIF to Bool equations or VHDL convertors.
> What about free simulators for BLIF?
>
> Thanks,
> Alexander Chemeris
> chemeris@svitonline.com

Alexander,

there is converter at http://tech-www.informatik.uni-hamburg.de/vhdl/.
The tool blif2vhdl is what you need.

Utku





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