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Messages from 35900

Article: 35900
Subject: Re: Problems with writing into text file
From: Martin Thompson <martin.j.thompson@trw.com>
Date: 23 Oct 2001 09:51:56 +0100
Links: << >>  << T >>  << A >>
"Allan Aasma" <Allan.Aasma@liewenthal.ee> writes:

<snip>
> At line 21 was: write(TextLine, "HELLO WORLD"); and that generated
> error message: "Expression is ambiguous" Is it possible to write into
> text file with Foundation 3.1i (and how to do it?) and when it isn't
> can you recommend some tool that I could use?
<snip>

The compiler sees anything in double quotes as being either a string
or a std_logic_vector constant, or anything else that is specifiable
like that.  It can't infer from the context whether that is a badly
written std_logic_vector or a string.  Therefore you have to do

write(TextLine, string'"Hello World");

Of course, I don't know whether you can do text I/O in Foundation...

HTH,
Martin

-- 
martin.j.thompson@trw.com
TRW Automotive Technical Centre, Solihull, UK

Article: 35901
Subject: ModelSim SE vs. PE in terms of speed?
From: golov@sony<REMOVEXTHIS>.de (Gil Golov)
Date: 23 Oct 2001 09:07:17 GMT
Links: << >>  << T >>  << A >>


ModelSiM dealer in Germany says that the SE in much faster but I could not 
find any justification for that in the datasheet of Model or their website.

Does anyone have a speed comparison between the two?


Many thanks

Gil Golov


Article: 35902
Subject: Are there any Coolrunner P5Z22V10 (PLCC) devices left anywhere?
From: z80@ds2.com (Peter)
Date: Tue, 23 Oct 2001 10:43:25 +0100
Links: << >>  << T >>  << A >>

Hi,

Xilinx bought this line from Philips, then discontinued it!

Are there any stocks left anywhere? I need a few hundred pieces.

Any speed is OK.


Peter.
--
Return address is invalid to help stop junk mail.
E-mail replies to zX80@digiYserve.com but remove the X and the Y.
Please do NOT copy usenet posts to email - it is NOT necessary.

Article: 35903
Subject: Re: ModelSim SE vs. PE in terms of speed?
From: allan_herriman.hates.spam@agilent.com (Allan Herriman)
Date: Tue, 23 Oct 2001 09:50:56 GMT
Links: << >>  << T >>  << A >>
On 23 Oct 2001 09:07:17 GMT, golov@sony<REMOVEXTHIS>.de (Gil Golov)
wrote:

>ModelSiM dealer in Germany says that the SE in much faster but I could not 
>find any justification for that in the datasheet of Model or their website.
>
>Does anyone have a speed comparison between the two?

Hi Gil,

The speedup you get varies with the type of code you have.  I have
measured increases of 1x (i.e. no increase at all) to 4x.  Most of the
time on larger designs it's about 1.5x to 2x though.

If you are doing a large simulation that takes hours, then it will
probably be worthwhile getting SE.  If you sim only takes a few
minutes, then PE may be more cost effective.

(Tests done with 5.4a.  I haven't done the comparison for 5.5d.)

Bye,
Allan.

Article: 35904
Subject: Re: Verilog vs. VHDL
From: "Andrew Brown" <andrewbr@nortelnetworks.com>
Date: Tue, 23 Oct 2001 11:22:37 +0100
Links: << >>  << T >>  << A >>
"Kevin Brace" <kevinbraceusenet@hotmail.com> wrote in message
news:cc7b0b5f.0110221942.6dc286c5@posting.google.com...
> Yes, I do agree with you that the element of HDL that doesn't
> synthesize becomes important when someone has to do verification on
> the design.
> But from a beginner's point (I knew practically nothing about HDL
> about a year ago now) who knows nothing about HDL, and wants to design
> digital circuits using HDL, the first thing they will like to know
> will be the stuff that synthesizes, not the stuff that is used in
> verification.

I would disagree with this.
The first thing beginners should learn is how to behaviourally model their
work.  They requires the entire language.  Verification and behavioural
modelling are the key skills all designers require and they should be taught
from the start.  The idea of letting people play with hardware before they
know how to model and test it properly starts a bad habit which is damn hard
to break.  If you gave a software engineer a subset of the C language to
perform a task they could do it.  They many complain about this nice feature
they aren't allowed to use, but they could still do it.  It's easier to
learn synthesis when you know the entire language than the other way around.

> After the beginner gets the design up to the point of it can be
> synthesized, I do think that the part of HDL that is used in
> verification becomes more important.

The way i read this you are saying that the synthesisable part of the
language is the most important part (could just be reading it wrong) and the
other elements are only 'more' important than they were beause you can use
them for testbenches.  You can write C as a subset of C++ (don't know why
you'd want to, but anyway).  The best C guru in the world will have trouble
fully understanding and implementing C++ objects because of the complete
mind-shift required.  But a C++ programmer could realtively easily write C
programs just by restricting himself - they won't be the best C programs in
the world, but they will work.

>         About two years ago, I tried to learn HDL in a way what you
> described as "The traditional approach" of learning the whole
> language, but it just didn't work.
> Learning the whole language is just too much because that I had no
> idea how to apply it in a actual design.
> Eventually I got discouraged, and quit.

Thats probably the teachers fault.  Learning a language isn't about learning
the syntax and writing a few example programs someone though up (the vending
machine???).  You should have been walked through the language construct by
construct, learning how and when the ideas are appropriate, then you should
have been taught how to use the language, for behavioural modelling,
testbenches and synthesisable blocks.  Too often a good subject is lost
because of a bad teacher.

> I tried to learn HDL again about a year ago, but this time, my main
> objective was not to learn HDL, but to design something, and learn HDL
> through the design process.

Learning on the job is always a good way to learn - but you tend to learn
what you need to do the job instead of learning what is available for you to
do the job.  If you just decide to start cleaning windows you would go and
get a sponge and water and do a good job.  If you ask people who have been
doing this for a long time, and know the tricks of the trade you may find
yourself putting vinager inthe water and using newspaper to dry the windows
(try it !!!).  Learning on the job should enhance skills you already have -
not give you them.

> It worked pretty well, and now I reached to a point where I have to do
> verification on the design.
> During that process, I only worried about the stuff that synthesized,
> and didn't pay much attention to the stuff that is used in
> verification.

This sentence is worrying.  How could you have properly architected the
design without considering how to test it?  You may find that there are some
parts of your design which can't be fully tested now because you didn't
consider how it would be done before you began coding.

> Now I am realizing that the importance of non-synthesizable part of
> HDL, but again, a beginner who knows nothing shouldn't worry too much
> about the non-synthesizable stuff initially.

Before you being any design, you need to consider how each feature will be
tested.  That involves coming up with the verification strategy for the
design.  If you don't understand the language fully you can't do this.  More
importantly, you need to understand more than the language.  You need to
know about other languages (C,E,vhdl,verilog,Perl,Tcl/Tk) in order to work
out the most suitable way to test the design.  Beginners should work on
behavioural models of code and learn how to test them.  Creating actual
hardware using synthesisable HDL is a very small fraction of the design
process significantly outweighed by the verification effort and the back end
flow.

> In retrospect, the reason I wasn't able to learn HDL two years ago was
> not only because the books I read weren't that interesting (used a
> Verilog book called Verilog Digital System Design by Navabi (ISBN
> 0-07-047164-9), and a VHDL book called VHDL for Programmable Logic (I
> don't remember the exact name) by a guy who works at Cypress
> Semiconductor), but also because I didn't have a clear goal of what I
> wanted to design, and therefore, I tried to learn the whole language.

To be frank - there are very few good books for people learning VHDL from
scratch.  There are some good books on synthesisable coding, modelling,
testbench and verification and some good general books.  But none (that i've
read - anyone know any?) that can be used to gain a deep understanding of
the complete language.

Just my opinion !

Andrew.

>
>
>
> Regards,
>
>
>
> Kevin Brace (don't respond to me directly, respond within the
> newsgroup)
>
>
>
>
> Andy Peters <andy@exponentmedia.deletethis.com> wrote in message
news:<3BD47664.BDDA6CA3@exponentmedia.deletethis.com>...
> > Kevin Brace wrote:
> >
> > > One thing I think is a problem of almost all HDL (Verilog and VHDL)
> > > books out there is that the books don't clearly define which element
> > > of the language is synthesizable by the synthesis tool and which is
> > > not.
> > > Instead, almost all books mixes up the stuff that no one uses, the
> > > stuff that can't be synthesized, and the stuff that can be
> > > synthesized.
> > > A beginner has no idea of the concept of what is synthesizable, so
> > > that person will waste time learning stuff no one uses, and less of
> > > the stuff that is important now (the synthesizable part of the
> > > language).
> >
> > I disagree.  I have found that all of that so-called "useless" stuff
> > becomes very useful indeed when you're trying to simulate and verify a
design.
> >
> > The traditional approach to learning an HDL has been to learn the
> > "whole" language, and at some point, learn the "synthesizable subset."
> > The problem is that this subset varies among tools.  Some tools do RAM
> > and ROM inference, some don't.  Some need "hints" and pragmas and
> > non-language stuff to cajole the tool into doing what you want.
> >
> > --a



Article: 35905
Subject: WISHBONE / SoC Interconnect / IP Core
From: "Wade D. Peterson" <wadep@silicore.net>
Date: Tue, 23 Oct 2001 11:43:44 GMT
Links: << >>  << T >>  << A >>
The latest "WISHBONE System-on-Chip Interconnection Architecture for Portable IP
Cores" is now available.  Revision B.2 has just been released, and can be
downloaded from: http://www.silicore.net/wishbone.htm

*** New items in Revision B.2 include:

- Capabilities for stopping the clock and varying clock frequency.

- New timing diagrams explaining the reset operation.

- Substantial revisions to the tutorial in Appendix A.

- Numerous other changes (as recommended by users) have been made to the
specification.  For a complete list, please see the 'change tracking' documents
in the WISHBONE Service Center.


*** Other newsworthy events include:

- The first WISHBONE public domain library for VHDL has been completed.  It can
be downloaded from the WISHBONE service center.

- Drawings of shared bus and crossbar switch interconnects are now available on
the WISHBONE FAQ page.

- Additional SoC patents have been researched and added to the 'Cited Patent
References' web page.

- Benchmarks for the 32-bit point-to-point and shared bus interconnections have
been published. These were done on Xilinx Spartan 2 and Virtex 2 FPGAs. All of
the benchmarking code and instructions can be found in the new WISHBONE tutorial
in the appendix of the spec. This means that you can run the benchmarks on your
own FPGA or ASIC device, and compare your results with those devices.

- We were able to get 800 Mbyte/sec on a Xilinx Virtex 2 FPGA. This was on a
64-bit, shared bus interconnection with 4 DMA MASTERs and 4 memory SLAVEs.

Wade Peterson
www.silicore.net




Article: 35906
Subject: Re: Verilog vs. VHDL
From: "Tim" <tim@rockylogic.com.nospam.com>
Date: Tue, 23 Oct 2001 13:17:29 +0100
Links: << >>  << T >>  << A >>

"Andrew Brown" <andrewbr@nortelnetworks.com> wrote

> The first thing beginners should learn is how to behaviourally model their
> work.  They requires the entire language.  Verification and behavioural
> modelling are the key skills all designers require and they should be taught
> from the start.

Probably correct, but not how people's heads work.  Sure is nice to
write a few lines, compile them, and examine the output as FFs, etc.

Then verify the few lines, then write some more, then...

Of course, you do not work this way when you are up to speed.





Article: 35907
Subject: Newbie: Need Help With Xilinx State Machine Using ABEL.....
From: "John Branthoover" <jbranthoover@yahoo.com.NOSPAM>
Date: Tue, 23 Oct 2001 13:24:06 GMT
Links: << >>  << T >>  << A >>
Hello All,
    I am a student at Point Park College in Pittsburgh,  PA.  I am trying to
learn the ins and outs of Xilinx's Foundation 2.1i software for my Digital
Electronics II class.

    I have tried create a JK flip-flop using Xilinx's Foundation 2.1i State
Machine editor.  I decided to use ABEL due to licensing issues.  I basically
copied the design from the State Machine's help menus.

    When I try to synthesize the macro,  I get the following error: Error:
The executable "ahdl2blf" exited with error code 1.  Does anyone know what
this means?

    Any information that you can give me will be greatly appreciated.  Thank
you for your time and have a nice day.

Below are the error files and the HDL code generated.


#Created by S95_SYN 3.01.1.3
JK_FLIPFLOP.ABL: abl2edif.exe  -a XC9500 -o JK_FlipFlop.EDN -s mod
JK_FlipFlop.ABL
abl2edif:  version C.16 -- Xilinx ABEL Software
Copyright (c) 1996 Xilinx Inc. All Right Reserved.

 Input   : D:\FNDTN\ACTIVE\PROJECTS\JRB\LAB1\JK_FlipFlop.abl
 Design  : JK_FlipFlop
 Family  : XC9500
 Strategy: mod
 Optimize: balance
 Output  : D:\FNDTN\ACTIVE\PROJECTS\JRB\LAB1\JK_FlipFlop.edn


Xabel Executing...
ahdl2blf JK_FlipFlop.abl -mod JK_FlipFlop -ojhd compile -err JK_FlipFlop.err

abl2edif has failed. Please see the abl2edif.log for detailed information.
JK_FLIPFLOP.ABL: Errors


The abl2edif.log file looks like this:


abl2edif:  version C.16 -- Xilinx ABEL Software
Copyright (c) 1996 Xilinx Inc. All Right Reserved.

 Input   : D:\FNDTN\ACTIVE\PROJECTS\JRB\LAB1\JK_FlipFlop.abl
 Design  : JK_FlipFlop
 Family  : XC9500
 Strategy: mod
 Optimize: balance
 Output  : D:\FNDTN\ACTIVE\PROJECTS\JRB\LAB1\JK_FlipFlop.edn


Xabel Executing...
ahdl2blf JK_FlipFlop.abl -mod JK_FlipFlop -ojhd compile -err JK_FlipFlop.err

Error: The executable "ahdl2blf" exited with error code 1.

abl2edif has failed.

And my HDL code Looks like:



"
"  File: D:\FNDTN\ACTIVE\PROJECTS\JRB\LAB1\JK_FlipFlop.abl
"  created: 10/23/01 08:49:46
"  from: 'D:\FNDTN\ACTIVE\PROJECTS\JRB\LAB1\JK_FlipFlop.asf'
"  by:  fsm2hdl - version: 2.0.1.53
"
module jk_flipflop
Title 'jk_flipflop'

Declarations

"clocks
Clk PIN;

"input ports
J PIN;
K PIN;

"output ports
NQ PIN;
Q PIN;

"******** SYMBOLIC state machine: Sreg0 ******
Sreg0 STATE_REGISTER;
S1, S2 STATE;


"diagram ACTIONS

"************* state machine: Sreg0 *************

Equations
" clock signals definitions
 Sreg0.clk = Clk;

State_diagram Sreg0


State S1:

    Q:=0;
    NQ:=1;
     IF (J==1) THEN
    S2
     ELSE  IF (J==0) THEN
        S1;


State S2:

    Q:=1;
    NQ:=0;
     IF (K==1) THEN
    S1
     ELSE  IF (K==0) THEN
        S2;

" end of state machine - Sreg0


end jk_flipflop






Article: 35908
Subject: comp.arch.fpg : Reconfiguring of a virtex via JTAG
From: "Anton Zechner" <xyz007@sbox.tu-graz.ac.at>
Date: Tue, 23 Oct 2001 07:11:45 -0700
Links: << >>  << T >>  << A >>
Reconfiguring of a virtex via JTAG

I will change the bits of a LUT in a virtex XCV300.
At first i read 16 frames with the LUT bits form the chip.
and than i write the chaned bits back to the chip.

The reading of the frame works all right.
But wenn I write the frame there is an error.
I think the error is in the startup sequence,
or in the crc-checksum. 
I don't know where i must begin with the calculation
of the checksum.

If anyone has an example with the reconfiguring via JTAG, or 
anyone knows the error in the sequence,
please send it me.

xyz007@sbox.tu-graz.ac.at

thanks.

This is my writing sequenze:

Switch JTAG to CFG_IN mode

0xFFFFFFFF Sync word

0xAA995566

0x30012001 Write to COR

0x00A0BF2D

0x30008001 Start command

0x00000005

0x30008001 Reset CRC 

0x00000007

0x00000000 Flush pipe

Switch JTAG to JSTART mode

Clock TCK 12 ticks

0xAA995566 Synch word  

0x30008001 

0x00000008 AGHIGH command

0x30012001

0x00A03F2D shutdown =0

0x00000000 Flush pipe

0x30008001 Write data

0x00000001

0x30002001 Write frame address

mja mna  addres;

0x30004000 + 357 word count (16 dataframes + pad frame )

... data ... (357 words)

0x30000001 Write checksum

CRC checkum calculated from last sync word

0x30008001 

0x00000003 Writer LFRM

0x30004000 + 21 

... pad frame ... (21 words all zero)

0x30008001 Startcommand

0x00000005

CRC checkum calculated from last crcsum

0x30000001 Write checksum

crc       

0x00000000 Flush pipe

0x00000000

0x00000000

0x00000000

 
Switch JTAG to JSTART mode

Clock TCK 12 ticks

Article: 35909
Subject: Re: Newbie: Need Help With Xilinx State Machine Using ABEL.....
From: "John Branthoover" <jbranthoover@yahoo.com.NOSPAM>
Date: Tue, 23 Oct 2001 14:32:26 GMT
Links: << >>  << T >>  << A >>
OOP's
    I found the problem.  Foundation 2.1i's ABEL compiler does not like
module names longer the 8 characters.

"John Branthoover" <jbranthoover@yahoo.com.NOSPAM> wrote in message
news:WbeB7.5603$W87.224616@bin4.nnrp.aus1.giganews.com...
> Hello All,
>     I am a student at Point Park College in Pittsburgh,  PA.  I am trying
to
> learn the ins and outs of Xilinx's Foundation 2.1i software for my Digital
> Electronics II class.
>
>     I have tried create a JK flip-flop using Xilinx's Foundation 2.1i
State
> Machine editor.  I decided to use ABEL due to licensing issues.  I
basically
> copied the design from the State Machine's help menus.
>
>     When I try to synthesize the macro,  I get the following error: Error:
> The executable "ahdl2blf" exited with error code 1.  Does anyone know what
> this means?
>
>     Any information that you can give me will be greatly appreciated.
Thank
> you for your time and have a nice day.
>
> Below are the error files and the HDL code generated.
>
>
> #Created by S95_SYN 3.01.1.3
> JK_FLIPFLOP.ABL: abl2edif.exe  -a XC9500 -o JK_FlipFlop.EDN -s mod
> JK_FlipFlop.ABL
> abl2edif:  version C.16 -- Xilinx ABEL Software
> Copyright (c) 1996 Xilinx Inc. All Right Reserved.
>
>  Input   : D:\FNDTN\ACTIVE\PROJECTS\JRB\LAB1\JK_FlipFlop.abl
>  Design  : JK_FlipFlop
>  Family  : XC9500
>  Strategy: mod
>  Optimize: balance
>  Output  : D:\FNDTN\ACTIVE\PROJECTS\JRB\LAB1\JK_FlipFlop.edn
>
>
> Xabel Executing...
> ahdl2blf JK_FlipFlop.abl -mod JK_FlipFlop -ojhd compile -err
JK_FlipFlop.err
>
> abl2edif has failed. Please see the abl2edif.log for detailed information.
> JK_FLIPFLOP.ABL: Errors
>
>
> The abl2edif.log file looks like this:
>
>
> abl2edif:  version C.16 -- Xilinx ABEL Software
> Copyright (c) 1996 Xilinx Inc. All Right Reserved.
>
>  Input   : D:\FNDTN\ACTIVE\PROJECTS\JRB\LAB1\JK_FlipFlop.abl
>  Design  : JK_FlipFlop
>  Family  : XC9500
>  Strategy: mod
>  Optimize: balance
>  Output  : D:\FNDTN\ACTIVE\PROJECTS\JRB\LAB1\JK_FlipFlop.edn
>
>
> Xabel Executing...
> ahdl2blf JK_FlipFlop.abl -mod JK_FlipFlop -ojhd compile -err
JK_FlipFlop.err
>
> Error: The executable "ahdl2blf" exited with error code 1.
>
> abl2edif has failed.
>
> And my HDL code Looks like:
>
>
>
> "
> "  File: D:\FNDTN\ACTIVE\PROJECTS\JRB\LAB1\JK_FlipFlop.abl
> "  created: 10/23/01 08:49:46
> "  from: 'D:\FNDTN\ACTIVE\PROJECTS\JRB\LAB1\JK_FlipFlop.asf'
> "  by:  fsm2hdl - version: 2.0.1.53
> "
> module jk_flipflop
> Title 'jk_flipflop'
>
> Declarations
>
> "clocks
> Clk PIN;
>
> "input ports
> J PIN;
> K PIN;
>
> "output ports
> NQ PIN;
> Q PIN;
>
> "******** SYMBOLIC state machine: Sreg0 ******
> Sreg0 STATE_REGISTER;
> S1, S2 STATE;
>
>
> "diagram ACTIONS
>
> "************* state machine: Sreg0 *************
>
> Equations
> " clock signals definitions
>  Sreg0.clk = Clk;
>
> State_diagram Sreg0
>
>
> State S1:
>
>     Q:=0;
>     NQ:=1;
>      IF (J==1) THEN
>     S2
>      ELSE  IF (J==0) THEN
>         S1;
>
>
> State S2:
>
>     Q:=1;
>     NQ:=0;
>      IF (K==1) THEN
>     S1
>      ELSE  IF (K==0) THEN
>         S2;
>
> " end of state machine - Sreg0
>
>
> end jk_flipflop
>
>
>
>
>
>



Article: 35910
Subject: New Spartan-II Evaluation Board
From: "Jan Pech" <j.pech@sh.cvut.cz>
Date: Tue, 23 Oct 2001 17:11:39 +0200
Links: << >>  << T >>  << A >>
Look at: http://fpga.f2g.net/

It's a low-cost "open design" (What is analogy of "open source" for
hardware?) Xilinx Spartan-II FPGA evaluation board.

I know it's not state-of-the-art technology but it's cheap and fully
sufficient for learnig programmable logic design.

Jan Pech
___________________________
     j.pech@sh.cvut.cz
     +420 (723) 760802
     ICQ: 56431283




Article: 35911
Subject: Re: Verilog vs. VHDL
From: Ray Andraka <ray@andraka.com>
Date: Tue, 23 Oct 2001 16:57:08 GMT
Links: << >>  << T >>  << A >>
I'm in the learn the synthesis subset first camp, with the very important caveat
that the pupil already has a good set of digital design skills.  You can write
testbenches using the synthesizable subset quite effectively.  As you gain
experience, it is easy to extend your knowledge of the language to handle stuff
in the testbenches more gracefully.  IMHO it is much harder to learn an entire
language without being able to apply it to practical problems, then finding out
the hard way what doesn't work for the more limited case.

Andrew Brown wrote:

> "Kevin Brace" <kevinbraceusenet@hotmail.com> wrote in message
> news:cc7b0b5f.0110221942.6dc286c5@posting.google.com...
> > Yes, I do agree with you that the element of HDL that doesn't
> > synthesize becomes important when someone has to do verification on
> > the design.
> > But from a beginner's point (I knew practically nothing about HDL
> > about a year ago now) who knows nothing about HDL, and wants to design
> > digital circuits using HDL, the first thing they will like to know
> > will be the stuff that synthesizes, not the stuff that is used in
> > verification.
>
> I would disagree with this.
> The first thing beginners should learn is how to behaviourally model their
> work.  They requires the entire language.  Verification and behavioural
> modelling are the key skills all designers require and they should be taught
> from the start.  The idea of letting people play with hardware before they
> know how to model and test it properly starts a bad habit which is damn hard
> to break.  If you gave a software engineer a subset of the C language to
> perform a task they could do it.  They many complain about this nice feature
> they aren't allowed to use, but they could still do it.  It's easier to
> learn synthesis when you know the entire language than the other way around.
>
> > After the beginner gets the design up to the point of it can be
> > synthesized, I do think that the part of HDL that is used in
> > verification becomes more important.
>
> The way i read this you are saying that the synthesisable part of the
> language is the most important part (could just be reading it wrong) and the
> other elements are only 'more' important than they were beause you can use
> them for testbenches.  You can write C as a subset of C++ (don't know why
> you'd want to, but anyway).  The best C guru in the world will have trouble
> fully understanding and implementing C++ objects because of the complete
> mind-shift required.  But a C++ programmer could realtively easily write C
> programs just by restricting himself - they won't be the best C programs in
> the world, but they will work.
>
> >         About two years ago, I tried to learn HDL in a way what you
> > described as "The traditional approach" of learning the whole
> > language, but it just didn't work.
> > Learning the whole language is just too much because that I had no
> > idea how to apply it in a actual design.
> > Eventually I got discouraged, and quit.
>
> Thats probably the teachers fault.  Learning a language isn't about learning
> the syntax and writing a few example programs someone though up (the vending
> machine???).  You should have been walked through the language construct by
> construct, learning how and when the ideas are appropriate, then you should
> have been taught how to use the language, for behavioural modelling,
> testbenches and synthesisable blocks.  Too often a good subject is lost
> because of a bad teacher.
>
> > I tried to learn HDL again about a year ago, but this time, my main
> > objective was not to learn HDL, but to design something, and learn HDL
> > through the design process.
>
> Learning on the job is always a good way to learn - but you tend to learn
> what you need to do the job instead of learning what is available for you to
> do the job.  If you just decide to start cleaning windows you would go and
> get a sponge and water and do a good job.  If you ask people who have been
> doing this for a long time, and know the tricks of the trade you may find
> yourself putting vinager inthe water and using newspaper to dry the windows
> (try it !!!).  Learning on the job should enhance skills you already have -
> not give you them.
>
> > It worked pretty well, and now I reached to a point where I have to do
> > verification on the design.
> > During that process, I only worried about the stuff that synthesized,
> > and didn't pay much attention to the stuff that is used in
> > verification.
>
> This sentence is worrying.  How could you have properly architected the
> design without considering how to test it?  You may find that there are some
> parts of your design which can't be fully tested now because you didn't
> consider how it would be done before you began coding.
>
> > Now I am realizing that the importance of non-synthesizable part of
> > HDL, but again, a beginner who knows nothing shouldn't worry too much
> > about the non-synthesizable stuff initially.
>
> Before you being any design, you need to consider how each feature will be
> tested.  That involves coming up with the verification strategy for the
> design.  If you don't understand the language fully you can't do this.  More
> importantly, you need to understand more than the language.  You need to
> know about other languages (C,E,vhdl,verilog,Perl,Tcl/Tk) in order to work
> out the most suitable way to test the design.  Beginners should work on
> behavioural models of code and learn how to test them.  Creating actual
> hardware using synthesisable HDL is a very small fraction of the design
> process significantly outweighed by the verification effort and the back end
> flow.
>
> > In retrospect, the reason I wasn't able to learn HDL two years ago was
> > not only because the books I read weren't that interesting (used a
> > Verilog book called Verilog Digital System Design by Navabi (ISBN
> > 0-07-047164-9), and a VHDL book called VHDL for Programmable Logic (I
> > don't remember the exact name) by a guy who works at Cypress
> > Semiconductor), but also because I didn't have a clear goal of what I
> > wanted to design, and therefore, I tried to learn the whole language.
>
> To be frank - there are very few good books for people learning VHDL from
> scratch.  There are some good books on synthesisable coding, modelling,
> testbench and verification and some good general books.  But none (that i've
> read - anyone know any?) that can be used to gain a deep understanding of
> the complete language.
>
> Just my opinion !
>
> Andrew.
>
> >
> >
> >
> > Regards,
> >
> >
> >
> > Kevin Brace (don't respond to me directly, respond within the
> > newsgroup)
> >
> >
> >
> >
> > Andy Peters <andy@exponentmedia.deletethis.com> wrote in message
> news:<3BD47664.BDDA6CA3@exponentmedia.deletethis.com>...
> > > Kevin Brace wrote:
> > >
> > > > One thing I think is a problem of almost all HDL (Verilog and VHDL)
> > > > books out there is that the books don't clearly define which element
> > > > of the language is synthesizable by the synthesis tool and which is
> > > > not.
> > > > Instead, almost all books mixes up the stuff that no one uses, the
> > > > stuff that can't be synthesized, and the stuff that can be
> > > > synthesized.
> > > > A beginner has no idea of the concept of what is synthesizable, so
> > > > that person will waste time learning stuff no one uses, and less of
> > > > the stuff that is important now (the synthesizable part of the
> > > > language).
> > >
> > > I disagree.  I have found that all of that so-called "useless" stuff
> > > becomes very useful indeed when you're trying to simulate and verify a
> design.
> > >
> > > The traditional approach to learning an HDL has been to learn the
> > > "whole" language, and at some point, learn the "synthesizable subset."
> > > The problem is that this subset varies among tools.  Some tools do RAM
> > > and ROM inference, some don't.  Some need "hints" and pragmas and
> > > non-language stuff to cajole the tool into doing what you want.
> > >
> > > --a

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 35912
Subject: Re: Verilog vs. VHDL
From: Ray Andraka <ray@andraka.com>
Date: Tue, 23 Oct 2001 17:06:52 GMT
Links: << >>  << T >>  << A >>


Kevin Brace wrote:

> I don't have anything to say about VHDL comments you made (I don't
> know much about VHDL, so I cannot compare the two languages).
> But besides the lack of `if (not `ifdef), I am happy with Verilog
> right now.
>         Regarding the gate count, I used only LUTs and FFs in my
> design, and didn't used any of the stuff that may be proprietary
> (BlockRAM, DLL, etc.) because in my design, design portability (i.e.,
> porting my design from a Xilinx device to an Altera device without
> modifying the HDL code) is important.

There in lies your problem.  Don't complain about the gate counts if you are not willing to use
the features of the device.  The synthesizers still do not do a stellar job at pulling out
inferences of device features.  Even if they did, one could argue that even at the hgh level
design description, you should be cognizant of the device architecture.  You should proceed
differently in your system level design to take advantage of the features that are there (eg.
don't use a memory intensive design if you don't have the memory in the chip to support it, or
if you do have memories, perhaps look-up tables make more sense than computation for certain
algorithms).   One can still keep a design more or less portable by designing hierarchically and
simply replacing the lowest level elements to match a specific architecture.

By all means, you have a right to do an "architecture blind" design, but please, don't complain
about the costs.

>
> Also, I didn't see the need to use the Xilinx proprietary stuff to
> complete the design.
> The synthesis tool I used was XST Verilog that came with ISE WebPack
> 4.1, and the design with a small user module consumed about 35% of the
> Slices of XC2S150.
> P&R (Place & Route) tool told me that the equivalent gate count was
> about 10,000 gates.
> Okay, I suppose that will equate to a little less than 30,000 gates,
> but certainly, far less than the 150,000 "system" gates Xilinx always
> claims about.
> Yes, I do realize that the term "system gates" really means nothing,
> and counts BlockRAM as gates, but should RAM really be called gates?
> I personally think storage elements like RAM or ROM shouldn't be
> counted as gates.
>

So, if you have an FPGA without storage but need it you end up building it out of flip-flops.
Guess that doesn't count for gates either?  As it happens, the BRAM is useful for functions not
normally needing RAM (suppose you have BRAMs left over, you can use them for function
generators, delay queues, counters, etc), giving you "free" logic.  Still, even if you take the
BRAMs out of the equation, it is not unusual to get "equivalent gate" counts close to the
nominal device capacity, provided you design to the architecture.


--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 35913
Subject: Bidirectional port is converted to input during synthesis
From: "Dave Brown" <dbrown@novatel.ca>
Date: Tue, 23 Oct 2001 13:05:52 -0600
Links: << >>  << T >>  << A >>
Hi,
    I'm using Xilinx ISE 4.1 for a SpartanXL design. I have a bidirectional
port that works great during simulation. When I sysnthesize it however, at
the top level where the bidi is formed from an input, an output, and an
enable signal, the tool removes the output signal at the top level and says
this signal is unused, and I end up with only an input. I'm scratching my
head here, what have I missed?
Thanks,
Dave




Article: 35914
Subject: Re: Are there any Coolrunner P5Z22V10 (PLCC) devices left anywhere?
From: Jim Granville <jim.granville@designtools.co.nz>
Date: Wed, 24 Oct 2001 08:48:31 +1300
Links: << >>  << T >>  << A >>
Peter wrote:
> 
> Hi,
> 
> Xilinx bought this line from Philips, then discontinued it!
> 
> Are there any stocks left anywhere? I need a few hundred pieces.
> 
> Any speed is OK.
> 
 Peter,

 I would think they are 'long gone' - web searches turn up some
'dusty numbers', but no stocks.

 There is no perfect match, but closest are the ATF22V10CQZ, and
PEEL22V10Z.
 Both are available as 'web samples', so you could qualify them.

 Longer term, look at the ATF1502ASL - this has an ITD option
( not well explained in the data), that allows a clock that
is NOT in the prod terms ( ie -> Reg CLK only), to not activate the
ITD, and this can greatly reduce Icc.
 Best results are from paused state engines, worst, but still 50%
saving, is from a simple counter.
 In QFP44, it's appx the same/smaller than PLCC28



-jg

Article: 35915
Subject: Re: Bidirectional port is converted to input during synthesis
From: "Dave Brown" <dbrown@novatel.ca>
Date: Tue, 23 Oct 2001 14:05:12 -0600
Links: << >>  << T >>  << A >>
The design is using VHDL and below is the architecture of my bidi ports, in
case this helps. As a side note, other ports in the design that are
bidirectional synthesize correctly I'm stumped.
entity bidi is
   port
   (
         EN    : in std_ulogic;   -- output enable
         DIN   : out std_ulogic;  -- input data from bus
         DOUT  : in std_ulogic;   -- output data to bus
         DIO   : inout std_ulogic -- I/O bus
   );
end bidi;
architecture behavioural of bidi is
   component OBUFT
   port(
      O                              : out   STD_ULOGIC;
      I                              : in    STD_ULOGIC;
      T                              : in    STD_ULOGIC);
   end component;
 component IBUF
   port(
      O                              : out   STD_ULOGIC;
      I                              : in    STD_ULOGIC);
   end component;
   signal noten : std_ulogic;
begin
   noten <= not EN;
    U1 : OBUFT port map
   (
      O  => DIO,
      I  => DOUT,
      T  => noten
   );
 U2 : IBUF port map
   (
      O  => DIN,
      I  => DIO
   );
end behavioural;

"Dave Brown" <dbrown@novatel.ca> wrote in message
news:9r4f1t$qom$1@pallas.novatel.ca...
> Hi,
>     I'm using Xilinx ISE 4.1 for a SpartanXL design. I have a
bidirectional
> port that works great during simulation. When I sysnthesize it however, at
> the top level where the bidi is formed from an input, an output, and an
> enable signal, the tool removes the output signal at the top level and
says
> this signal is unused, and I end up with only an input. I'm scratching my
> head here, what have I missed?
> Thanks,
> Dave
>
>
>



Article: 35916
Subject: P5Z22V10 - any left anywhere?
From: z80@ds2.com (Peter)
Date: Tue, 23 Oct 2001 21:13:56 +0100
Links: << >>  << T >>  << A >>

Hello,

Xilinx took over this line from Philips and promptly discontinued it.
I am after a few hundred, PLCC, any speed.

Or maybe pin for pin replacements. It does not have to be "zero
power".


Peter.
--
Return address is invalid to help stop junk mail.
E-mail replies to zX80@digiYserve.com but remove the X and the Y.
Please do NOT copy usenet posts to email - it is NOT necessary.

Article: 35917
Subject: Re: Verilog vs. VHDL
From: Magnus Homann <d0asta@mis.dtek.chalmers.se>
Date: 23 Oct 2001 22:18:34 +0200
Links: << >>  << T >>  << A >>
"Andrew Brown" <andrewbr@nortelnetworks.com> writes:

> To be frank - there are very few good books for people learning VHDL from
> scratch.  There are some good books on synthesisable coding, modelling,
> testbench and verification and some good general books.  But none (that i've
> read - anyone know any?) that can be used to gain a deep understanding of
> the complete language.

I happened to know ADA before learnt VHDL. That was a great help. You
get used to some of the constructs, the ability to work with types,
the modularity etc.

Homann
-- 
Magnus Homann, M.Sc. CS & E
d0asta@dtek.chalmers.se

Article: 35918
Subject: High-speed Logic, Military/Space Grade
From: rk <stellare@nospamplease.erols.com>
Date: Tue, 23 Oct 2001 16:53:29 -0400
Links: << >>  << T >>  << A >>
Hi,

Perhaps a bit off-topic for an FPGA group but I think the right audience
is here.

I haven't used ECL in a number of years (silly FPGAs taking up too much
time) but would like to know what the current families (and
manufacturers) are for very high-speed logic, US military/space
qualified, with "reasonable" power levels and worst-case clock
frequencies of 600 MHz, min.  I'm looking at some operations such as
synchronous counters, Johnson twisted ring counters, etc.  The output of
the logic will be fed into an FPGA (there, that should make this
on-topic :-).

Thanks in advance.

-- 
rk

Article: 35919
Subject: Re: Verilog vs. VHDL
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Wed, 24 Oct 2001 00:20:56 +0100
Links: << >>  << T >>  << A >>


Tim wrote:

> "Andrew Brown" <andrewbr@nortelnetworks.com> wrote
>
> >
>
> Of course, you do not work this way when you are up to speed.

By then you should have a good feel when to copy & bend someone else's design and
when you'll just have to grit your teeth and do it yourself.

Seriously - looking at existing, working, designs and testbenches and trying to
understand ``why on earth did he/she/it do that ?!'' is one of the best ways of
learning. When you're confident you can even try and improve it (with probability
1-delta you'll break it the first time).


Article: 35920
Subject: Re: Verilog vs. VHDL
From: Andy Peters <andy@exponentmedia.deletethis.com>
Date: Wed, 24 Oct 2001 00:35:52 GMT
Links: << >>  << T >>  << A >>
Kevin Brace wrote:

I agree with what Andrew Brown says...

> In retrospect, the reason I wasn't able to learn HDL two years ago was
> not only because the books I read weren't that interesting (used a
> Verilog book called Verilog Digital System Design by Navabi (ISBN
> 0-07-047164-9), 

There's problem #1.  That book is AWFUL.  You should've gotten the
Bhaskar book, or the Palnitkar book.

> and a VHDL book called VHDL for Programmable Logic (I
> don't remember the exact name) by a guy who works at Cypress
> Semiconductor), but also because I didn't have a clear goal of what I
> wanted to design, and therefore, I tried to learn the whole language.

There's problem #2.  That book was written to deal with Cypress' broken
VHDL.  You should've gotten the Ashenden book.

--a

Article: 35921
Subject: RLOC under VHDL
From: <khtsoi@pc90026.cse.cuhk.edu.hk>
Date: 24 Oct 2001 02:12:27 GMT
Links: << >>  << T >>  << A >>
Hi,

In a project, I must design a cell such that the relative
location of components inside the cell is fixed. I know
that I can give the RLOC attribute under schematic design.
But I must use VHDL only this time. The environment is
synopsys design_compiler (DC) under SunOS. Could somebody
tell me how to set it in VHDL? (uning Xilinx XV1000E FPGA)

sample code:

reg1: FDC port map (...);
reg2: SRL16E port map (...);

The location or reg1 must beside reg2

Thanks in advance!

---- Brittle

P.S. If VHDL cannot do it, I may want to change the edif file,
but how?

Article: 35922
Subject: Re: LUT Glitches
From: gah@ugcs.caltech.edu (glen herrmannsfeldt)
Date: 24 Oct 2001 02:18:47 GMT
Links: << >>  << T >>  << A >>
Bob Perlman <bob@cambriandesign.com> writes:

>You can build glitch filters with tapped delay lines and majority
>detection logic, but with an important caveat.  These filters will
>eliminate pulses shorter than X ns and pass pulses longer than Y ns,
>but X and Y aren't the same number.  In between X and Y, the circuit
>can misbehave; there's a range of pulse durations that can produce
>glitches at the output of the filter.  

>If there were such a thing as a perfect glitch filter, we could build
>a metastable-proof flip-flop by filtering out runt pulses.  Were it
>that it were.

The original question asked about asynchronous logic, which doesn't
have a metastability problem.  Asynchronous logic, also called self
timed logic, runs as fast as gates can change.  Look up self-timed
logic somewhere.

-- glen

Article: 35923
Subject: JTAG question
From: Dean Armstrong <daa1@cs.waikato.ac.nz>
Date: Wed, 24 Oct 2001 15:36:14 +1300
Links: << >>  << T >>  << A >>
Hi All,

I am designing a system which contains three Xilinx CPLDs, and a Xilinx
Spartan II FPGA. I wish to provide for a JTAG access to the Spartan, and
to the CPLDs. I also wish to allow the Spartan to access the CPLDs via
their TAPs.

My initial thought was to implement this as two chains. One contains
only the Spartan. The other contains the CPLDs. This allows me to access
all devices through a JTAG cable, and by placing jumpers on a header I
can connect the CPLD chain to Spartan user I/Os giving it control.

I think I can go one better than this though. I would like to include
all devices on the same chain, and also connect the user I/Os on the
spartan to this chain. Hopefully this would mean that when the Spartan
is not configured, or not wanting to program the CPLDs then it could
leave these I/Os high impedence, and a cable could be plugged onto them
and used. When a cable is not being used then the Spartan could take
control of the chain, bypass itself, and access the other devices. This
means I only have to provide one pin header, and don't have to worry
about fiddling around with jumpers.

Can anyone see any problems with this approach? Has anyone done anything
like this? Any comments?

Kind Regards,
Dean Armstrong


Article: 35924
Subject: Re: RLOC under VHDL
From: Ray Andraka <ray@andraka.com>
Date: Wed, 24 Oct 2001 04:47:44 GMT
Links: << >>  << T >>  << A >>
As long as your synthesis tool (you didn't mention which you use)
supports user attributes you can put RLOCs on primitives.  Here is how:

attribute RLOC:string;
attribute RLOC of U1:label is "R1C3.S0";

begin

--other stuff

--primitive instantiation:
U1:FD port map(
    C=>clk,
    D=>din,
    Q=> Q);

You can also use this within a generate statement, in which case the
string needs to have new row, column and/or slice numbers.  To do that
you have to write a function to convert an integer to string ('image
does that, but isn't recognized in the synthesis tools).

The above is generic, so it will work in any tool that passes user
attributes.  Synplicity has a set of synplicity specific attributes to
do RLOCs to, but frankly, I think the portable one is a better choice.


khtsoi@pc90026.cse.cuhk.edu.hk wrote:

> Hi,
>
> In a project, I must design a cell such that the relative
> location of components inside the cell is fixed. I know
> that I can give the RLOC attribute under schematic design.
> But I must use VHDL only this time. The environment is
> synopsys design_compiler (DC) under SunOS. Could somebody
> tell me how to set it in VHDL? (uning Xilinx XV1000E FPGA)
>
> sample code:
>
> reg1: FDC port map (...);
> reg2: SRL16E port map (...);
>
> The location or reg1 must beside reg2
>
> Thanks in advance!
>
> ---- Brittle
>
> P.S. If VHDL cannot do it, I may want to change the edif file,
> but how?

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759





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