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Messages from 36150

Article: 36150
Subject: Re: Second Scenario: BRAM usage reduction in FIFO design
From: Falk Brunner <Falk.Brunner@gmx.de>
Date: Wed, 31 Oct 2001 10:54:59 +0100
Links: << >>  << T >>  << A >>
Chua Kah Hean schrieb:
> 
> Hi all experts out there,
> 
> I would like to seek help in ways to reduce BRAM usage under two
> scenarios.  This post contains only the second scenario.  I have
> posted the first scenario in an earlier post.
> 
> (2)
> I need a 1024 by 9 FIFO (independent read/write clocks).  If I
> implement a 1024 by 16, I will be needing four 4Kbit BRAMs and
> actually wasting 7/16 of the capacity.  Suppose I can afford only two
> block RAMs.  Can I implement a 1024 by 8 (two blocks) BRAM-based FIFO
> and then parallel it with a 1024 by 1 FIFO implemented with
> distributed SRAM?

Possible, but also here I think rearangeing of BRAMS can save a lot of
trouble.
Just remember. The BRAMs on Virtex-E/Spartan-II can be configured as

4096x1
2048x2
1024x4
512x8
256x16

So for your 1024x9 FIFO just use 3 1024x4 BRAms in parallel, wasting
only 25%.
 
> I am personally not uncomfortable with this approach, because the
> full/empty flags of the two FIFOs may not be in-sync (especially now

??? No, all you have to do is to create a DP-RAM (consisting of BRAMs
and Dis. RAMs), which is part of the FIFO. DONT create two FIFOS, ist
senseless.

> Supposing I can solve the above problem, how do I code a 1024 by 1
> FIFO for Xilinx Virtex-E FPGA?  I noticed that Coregen only allows

There are two ways. Coregen or direct instanciating of Virtex
primitives. When using Foundation, simply have a look at the virtex
library.

-- 
MFG
Falk



Article: 36151
Subject: Re: Clock attribute problem
From: Falk Brunner <Falk.Brunner@gmx.de>
Date: Wed, 31 Oct 2001 10:58:09 +0100
Links: << >>  << T >>  << A >>
Banana schrieb:
> 
> 
>                 if reset = '1' then
>                         count_3_interno := "000";
>                 else
>                         if clk'event then
>                                 if falling_edge(clk) then

Here is your problem. you have two "If then" constructs to check for the
clock, where just one is allowed (and nesseccary)
Just write

If falling_edge(clk) then

-- 
MFG
Falk


Article: 36152
Subject: Re: pci-card with Virtex2?
From: Andreas Kugel <kugel@ti.uni-mannheim.de>
Date: Wed, 31 Oct 2001 13:48:04 +0100
Links: << >>  << T >>  << A >>
.... you might look at http://www-li5.ti.uni-mannheim.de/fpga/?race/

Cheers,
Andreas

Seb wrote:

> Hi group
> 
> i'm looking for a pci-card with a large Virtex2 FPGA and memory on it, to
> implement a signal processing design. The application has to receive its
> data through an external connector and deliver its data to the host pc
> system (using the pci bus).
> 
> Which cards/vendors should i look at? Do any of you have experience with
> such cards?
> 
> thanx in advance
> cheers,
>     Seb
> 
> 
> 


Article: 36153
Subject: Re: Can anyone guide me in selecting an FPGA?
From: Erik Lins <e.lins@hightronix.de>
Date: Wed, 31 Oct 2001 14:23:27 +0100
Links: << >>  << T >>  << A >>
David wrote:

> I'm looking for a FPGA that will b e used with a SERDES
> device. Originally I was looking at an XCV2000 or APEX1000
> along with a SERDES device (most likely TI or Conexant

Look at http://www.quicklogic.com/devices/quicksd/default.htm
It's an integrated device with 8 LVDS SERDES channels, two clock channels 
and programmable logic cells included.

Cheers,
ER!K


Article: 36154
Subject: Re: Can anyone guide me in selecting an FPGA?
From: "Peter Ormsby" <faepete.deletethis@mediaone.net>
Date: Wed, 31 Oct 2001 14:06:36 GMT
Links: << >>  << T >>  << A >>
David <dvdprsns36@hotmail.com> wrote in message
news:b254a41e.0110301425.79669d81@posting.google.com...
> I'm looking for a FPGA that will b e used with a SERDES
> device. Originally I was looking at an XCV2000 or APEX1000
> along with a SERDES device (most likely TI or Conexant
> 3.125Gbps) but I've heard that Xilinx is coming out with a
> FPGA that will have high-speed SERDES functionality built in.
> Does anyone know what the story is with that? Would you
> recommend that as a better/cheaper (how much?) alternative?
>
>
> Dave

I have a couple of comments on this topic.  I'll start with replying to this
one:

Mike Treseler <mike.treseler@flukenetworks.com> wrote in message
news:3BDF2ED2.A6405CCF@flukenetworks.com...
>If you are in a hurry, just buy an off the shelf SERDES.
>
>Both brand A and X have new parts out designed for this,
>but you know how version 1.0 of anything can go . . .
>
>  --Mike Treseler

Altera is actually on about Rev 3.0.  Apex 20KE devices have had 16 channels
of 840 Mbps LVDS (with dedicated SerDes circuitry)  for a couple of years
now.  Altera Mercury devices have had up to 18 channels of 1.25 Gbps LVDS
and those devices have been shipping since the first half of this year.
Apex II devices have 36 channels of 1.0 Gbps LVDS and 54 channels of 640
Mbps LVDS on currently shipping devices (up to 88 of those 640 Mbps channels
on larger memebers of the APEX II family).  I realize this isn't 3.125 Gbps
(yet), but it definitely is a long way past "Rev 1.0".

As far as the Xilinx plans go...

Philip Freidin <philip@fliptronics.com> wrote in message
news:o2juttcq2pc8nbfkf6722a4qcjahb6bgv2@4ax.com...
> The Xilinx Virtex-2 is the underlying FPGA for their upcomming
> Virtex-2 Pro parts that they say will have the 3.125GBaud SerDes
> blocks on it. Xilinx press releases and presentations say that the
> underlying SerDes technology is the Conexant SerDes that
> they have licensed. I believe that Conexant SerDes technology
> has been spun out into a separate company named MindSpeed.
>
> Given this, I would recommend doing your design with Xilinx Virtex-2
> and the MindSpeed/Conexant SerDes, and use the integrated
> product when it becomes available.
>
> You can probably get more info on this by contacting your local
> Xilinx sales office.
>
> Philip Freidin

Before I go into this, let me clarify that I have the utmost respect for the
engineering capabilities of the folks at Xilinx.  These guys are good.
However, just because they licensed the Mindspeed/Conexant SerDes design,
doesn't mean that this 3.125 Gbps design is a slam dunk  Integrating these
designs into your chips on new processes is difficult and claiming that this
is easy because you bought someone else's IP smells a bit of an over-active
marketing department.

The truth be told, neither Xilinx nor Altera have a 3.125 Gbps SerDes
available today.  Xilinx has purchased technology and is well on the way to
having a product available.  Altera has several 640 Mbps to 1.25 Gbps
solutions available today and are also well on their way to taking their
experience in high speed SerDes to 3.125 Gbps.

If you need 3.125 Gbps today, buy an off-the-shelf dedicated SerDes part.
If you can go a bit slower and wider (3 x 1.25Gbps), then Altera's Mercury
is available today (or 4 x 1.0 Gbps in Apex II - also available today).  If
you have a few months to wait, then probably both Altera and Xilinx will
have a 3.125 Gbps solution available.  Only time will tell how successful
those products turn out to be.

I hope this helps.

-Pete-



Article: 36155
Subject: Re: Field Programmable Logic in energy poor environments
From: "Tim" <tim@rockylogic.com.nospam.com>
Date: Wed, 31 Oct 2001 14:36:50 -0000
Links: << >>  << T >>  << A >>
"Peter Alfke" <palfke@earthlink.net> wrote
> Irwin Kennedy wrote:
> > * Use less "leaky" transistors! (?)
>
> Until recently, there was extremely little junction leakage or
> sub-threshold leakage current. XC3000L could run on 50 microamps.
> Unfortunately, as we approach 100 nm technology, subthreshold leakage
> current becomes significant ( for every IC manufacturer. Ask Intel! )

I should not have to ask, but what is sub-threshold leakage?







Article: 36156
Subject: Hard macro in xilinx
From: mbonnici@r-and-d.de (mbonnici)
Date: 31 Oct 2001 06:50:55 -0800
Links: << >>  << T >>  << A >>
I would like to know how to make a hard macro in Xilinx (after place
and route)
I open the design_file.ncd in FPGA editor and saves the design as a
macro. The real problem is to
change an IOB into a macro external pin. 
Anybody have a solution
Thanks
mbonnici

Article: 36157
Subject: Re: Firewire chipset
From: "Eric Braeden" <braeden@erinet.com>
Date: Wed, 31 Oct 2001 09:56:38 -0500
Links: << >>  << T >>  << A >>
"electron-man" <going@speed-of-light.com> wrote in message >

<clipped out stuff>

> And BTW, not everyone is embracing USB 2.0:
> http://www.agere.com/NEWS/PRESS2001/071601a.html
>

Agere's decision to exit the USB 2.0 market is not based on
the superiority of 1394 over USB 2.0. The question is how
to make a profit. USB 2.0 will be ubiquitous. It will be built
into motherboards and available on $12 PCI addin cards which
will probably cast less than $2 to produce. Everyone will
be selling USB 2.0 chips/cards. Therefore the profit margins
will be very slim. So I believe electron-man's comment
above may be exactly 180 degrees out of phase.

A better GUESS of Agere's motivation: Because everyone is
embracing the USB 2.0 standard the profit margins will be
so small so we are focusing on Firewire where we can still
make some money.






Article: 36158
Subject: Implementing Filter
From: emi.fre@caramail.com (fre)
Date: 31 Oct 2001 07:32:08 -0800
Links: << >>  << T >>  << A >>
Holla
Wich different techniques do you know about Implementing FIR/IIR
Filters
in Spartan-FPGA (195 CLB). Is there any program to use or VHDL-Code.
Any Informations specially on Spartan (XILINX-FPGA) will be very
neccessary.
thanks for help!

Article: 36159
Subject: Re: Can anyone guide me in selecting an FPGA?
From: Wenyi_Feng <wenyi@agere.com>
Date: Wed, 31 Oct 2001 11:51:56 -0500
Links: << >>  << T >>  << A >>

Guess this is what you want :

http://www.agere.com/NEWS/PRESS2000/112000a.html

The company formerly known as Lucent ME, now Agere systems;
and a couple of customers are using the chips right now.


Erik Lins wrote:

> David wrote:
>
> > I'm looking for a FPGA that will b e used with a SERDES
> > device. Originally I was looking at an XCV2000 or APEX1000
> > along with a SERDES device (most likely TI or Conexant
>
> Look at http://www.quicklogic.com/devices/quicksd/default.htm
> It's an integrated device with 8 LVDS SERDES channels, two clock channels
> and programmable logic cells included.
>
> Cheers,
> ER!K


Article: 36160
Subject: Re: Leonardo bugs
From: husby_d@yahoo.com (Don Husby)
Date: 31 Oct 2001 09:02:55 -0800
Links: << >>  << T >>  << A >>
Mike Treseler <mike.treseler@flukenetworks.com> wrote in message news:<3BDF4799.A379AA16@flukenetworks.com>...
> Russell Shaw wrote:
> > ...
> > most of the
> > device settings you do in the flow tabs don't get
> > saved with the project. 
> 
> Haven't seen anything like that.

Leonardo is full of things like that:  project settings
flip around like a bad politician.  Constraints evaporate.
Constraints are added.  Flags appear to be set, but really
aren't.  File names are changed.  My favorite is when
each source file is added twice to the compile list.
The most consistently annoying is when the output file
name is silently changed - sometimes you don't discover
it until you've done a complete place and route, and find
that nothing changed.

At some point, you just have to delete all of the Leonardo
project files (*.lsp *.scr *.xdb ...) and start over.

It's amazing to me that the Leonardo user interface has
been so crappy for so many years.  At some point, you
just have to delete Leonardo and start over.

Article: 36161
Subject: Re: Second Scenario: BRAM usage reduction in FIFO design
From: Ray Andraka <ray@andraka.com>
Date: Wed, 31 Oct 2001 17:07:26 GMT
Links: << >>  << T >>  << A >>
Doing it with two FIFOs does make sense if you are tight on the timing.
The block RAMs are often the slowest part of a well executed design.
Automatic placement does an abyssmal job placing block RAMs, and even in a
well placed design, the fanout to more than one or two block RAMs kills
performance.  It will cost you some area, but there are many times when it
makes sense to use parallel FIFOs instead of one bigger one.

Falk Brunner wrote:
...(stuff snipped)...

> > I am personally not uncomfortable with this approach, because the
> > full/empty flags of the two FIFOs may not be in-sync (especially now
>
> ??? No, all you have to do is to create a DP-RAM (consisting of BRAMs
> and Dis. RAMs), which is part of the FIFO. DONT create two FIFOS, ist
> senseless.
>
>
> --
> MFG
> Falk

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 36162
Subject: Re: one SPROM for 2 XCS30XLs?
From: Ray Andraka <ray@andraka.com>
Date: Wed, 31 Oct 2001 17:10:33 GMT
Links: << >>  << T >>  << A >>
It may be cheaper to use a parallel eprom plus a small CPLD.

Utku Ozcan wrote:

> In ds030.pdf, v1.8, I haven't found any PROM that can hold config data
> of 2 separate XCS30XLs. Is there any such big PROM? Or shall I use 2
> separate XC17S30XLs?
>
> Utku

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 36163
Subject: Re: Field Programmable Logic in energy poor environments
From: Peter Alfke <peter.alfke@xilinx.com>
Date: Wed, 31 Oct 2001 10:03:02 -0800
Links: << >>  << T >>  << A >>


Kolja Sulimma wrote:

> <snip>. You do not need fast transistors in your configuration memory.

True, except in the LUT-RAM, where speed matters

>
> As you are using an SOI technology for Virtex-II

Xilinx does *NOT* use SOI in any of its products

> you could easily use a
> higher
> threshold voltage for your configuration SRAM transistors as for your CLB
> logic transistors. (Hmmm. You probably do allready.)

If we (and our customers) were willing to accept higher cost, or lower
performance, or a more restricted applications area ( market niche), or all
three together, we could do various things to reduce power. But that is not a
realistic assumption.

Fundamentally, there are two aspects to low power:

1.) Long battery life for handheld equipment. This means single-digit milliamps,
and the larger FPGAs cannot achieve this. Use CoolRunner instead.

2.) Less heat, lower junction temperature. This means amps, and is a concern for
all large chips running at high clock rates.  A few milliamps to store the
configuration are irrelevant in those applications. It's mainly a dynamic power
issue. Capacitance times frequency times square of the voltage.

For some of our customers,  "100 picoseconds are as important as 100 mA."

We are working hard to reduce power consumption, but FPGAs cannot reach the
ultra-low power levels.
That's CoolRunner territory.

Peter Alfke



Article: 36164
Subject: Re: one SPROM for 2 XCS30XLs?
From: Peter Alfke <peter.alfke@xilinx.com>
Date: Wed, 31 Oct 2001 10:59:36 -0800
Links: << >>  << T >>  << A >>
Each XCS30XL needs almost 250,000 configuration bits.
For two different bitstreams, you need almost 500,000 bits.

The XC17S50XL stores 559,232 bits, one-time programmable
The XC18V512 stores 521,880 bits and is in-system (re)programmable.

Peter Alfke, Xilinx Applications
==========================================
Utku Ozcan wrote:

> In ds030.pdf, v1.8, I haven't found any PROM that can hold config data
> of 2 separate XCS30XLs. Is there any such big PROM? Or shall I use 2
> separate XC17S30XLs?
>
> Utku


Article: 36165
Subject: Synthesis of picoJava II for FSOC
From: "Dany XP" <danyxp@hotmail.com>
Date: Wed, 31 Oct 2001 20:16:01 +0100
Links: << >>  << T >>  << A >>
Can anyone help me about synthesis of picoJava-II core with another tool
than Synopsys DC?
Also, I would like to know about experiences with this core, scripts and
performance.
Thanks.



Article: 36166
Subject: Re: Cloning someone else's IP core
From: Eric Crabill <eric.crabill@xilinx.com>
Date: Wed, 31 Oct 2001 11:36:47 -0800
Links: << >>  << T >>  << A >>

Hi,

Again, as I stated, I am not a lawyer, but I don't quite
understand the reasoning behind your comments.  The rest
of this post are my comments and opinions, not those of
my employer.

> A contract to transfer a good for an unlimited amount
> of time without paying a recurrent fee is a purchase,
> no matter what it is called in the contract.  I am pretty
> sure that after purchasing the core package I own the
> documentation, constraints files and the core generator
> software.

I don't believe the license for the Xilinx PCI core,
be it an evaluation or not, transfers ownership of the
IP to the person buying the license.  This appears to
be the case in:

http://www.xilinx.com/ipcenter/doc/xilinx_click_core_project_license.pdf
http://www.xilinx.com/products/logicore/pci/docs/stanusag.htm
http://www.xilinx.com/ipcenter/ipevaluation/ipevaluation_license.htm

Those who license the IP do not own it, although Xilinx
grants the right to distribute FPGA configuration bitstreams
generated with the licensed IP.  You cannot, however, distribute
the IP itself, because you do not own it and are not authorized
to distribute it.  And you do have to pay a recurring fee,
called "maintenance" to keep your license valid for all
versions except the evaluation version.

> To be able to sell copies of the core to customers I need of
> course a license as this can not be covered by the purchase
> alone. In a b2b context this license can be more or less
> contain arbitrary agreements between me and the vendor.

Purchasing a license entitles you to distribute FPGA configuration
bitstreams which are generated from the IP.  You cannot distribute
the IP itself, or the netlist.  If that were allowed, a licensee
could re-sell the netlist and compete against Xilinx with Xilinx's
own IP product, selling it very cheaply because the licensee did not
have to pay the research and development costs.

> However, a license that states that Xilinx remains the owner of
> the IP is worthless, as this would mean that Xilinx would own
> part of any product that contains the core.  At least the end
> customer of my product must become owner of the netlist in
> the FPGA.  And this of course allows me to become owner of the
> netlist myself.

I believe the distinction that needs to be made is the difference
between a bitstream and a netlist.  It is very difficult, indeed,
to reverse engineer a piece of IP from a bitstream.  I believe
Xilinx is not concerned about distribution (and ownership?) of
device bitstreams because the IP which was used to create the
bitstream cannot be "distilled" from the bitstream.

> (Would you buy a network adapter that comes with a license
> agreement that states that part of the adapter is owned by Xilinx?)

Would I buy a shirt with a picture of Mickey Mouse?  Sure.  It probably
says on the tag that it is officially licensed from the Disney
Corporation.
I would not pretend to own Mickey Mouse because I bought a shirt with
his
image stamped on it.

Would I buy a design with a licensed image of the Xilinx PCI core
in it?  Yes.

> If I use part of the netlist or source code in my own PCI core I
> of course violate theire copyright. I can however not violate any
> Xilinx patents because I licensed them from SIGPCI.

I don't think this is correct.  Where did you get this information?
Did you read:

http://www.pcisig.com/membership/about_us/bylaws

This suggests to me, in Section 15.3, that if Xilinx contributes
anything to a specification, that Xilinx grants the PCI SIG the
unrestricted license to use it.  This grant is reciprocal, meaning
that other PCI companies are allowed to use it as well.

Then, if you keep reading down to Section 15.6, this flat says:

"The Members agree no patent license, immunity or other right is
granted under these Bylaws by any Member or its Affiliates to any
other Members or their Affiliates or to the Corporation, either
directly or by implication, estoppel or otherwise, other than the
agreements to grant licenses expressly set forth in this ARTICLE 15."

That doesn't sound like you have licensed any Xilinx patents via
the PCI by being a PCI member.

Thanks for reading,
Eric

Article: 36167
Subject: Re: timing difference
From: "Norman Yang" <norman@zh.t2-design.com>
Date: Wed, 31 Oct 2001 12:20:51 -0800
Links: << >>  << T >>  << A >>
The delay information calculated by synthesis tool is based on
WIRE_LOAD_MODEL of the synthesis library and the drive/load information. The
wire_load_model that XILINX provided indicated the delay will increase
significantly when loading increasing. So the delay will be large in
synthesis report.

--
Best regards!

Norman Yang
norman@zh.t2-design.com
Nandini <pnandini@hotmail.com> wrote in message
news:36c97582.0110300815.432f0187@posting.google.com...
> hi,
>
> Is the timing analysis after synthesis and after mapping very
> different?
> I used synopsys design compiler for synthesis and I got a max_time
> delay as 140 ns for a 56 bit adder, whereas after mapping using xilinx
> alliance tool on xcv1000 virtex, i get  a minimum period as 35ns [but
> here I had instantiated this 56 bit adder as partof another entity]
> still why is there such a big difference between the timing? and as
> such while reporting what is the timing I shud consider? kindly help.
>
> nandini



Article: 36168
Subject: Xilinx CLB Pack Factor Percentage setting?
From: "Dave Brown" <super.dave@home.com>
Date: Wed, 31 Oct 2001 13:27:12 -0700
Links: << >>  << T >>  << A >>
Hi,
    I wanted to get an estimate of how much space my SpartanXL design is currently taking up on the device, not all the desired funcionality is there yet, so I want a good estimate of how much space I have left. I'm using
Xilinx Foundation 4.1. I have set the Synthesize and Implement design
settings to optimize for area, yet I get a fairly high number of CLBs
utilized, about 97%. However, if I go and put in a lower CLB pack factor percentage, I get a smaller design, about 83%. I looked at the Floor Plan when it was using 97% area and things weren't that dense, there were CLBs using only one LUT all over the place. Am I correct in assuming that by setting the CLB Pack Factor percentage lower, I'm getting a better estimate of how much room I actually have left?
Thanks,
Dave

Article: 36169
Subject: Re: Leonardo bugs
From: david.meigs@timedomain.com (David Meigs)
Date: 31 Oct 2001 13:56:53 -0800
Links: << >>  << T >>  << A >>
Russell Shaw <rjshaw@iprimus.com.au> wrote in message news:<3BDF3934.7F19DC45@iprimus.com.au>...
> Mike Treseler wrote:
> > Perhaps you forgot to save your project settings.
> 
> I've tried that plenty of times, but leonardo has
> lots of bugs, and one of them is that most of the
> device settings you do in the flow tabs don't get
> saved with the project. Are you using a similar
> version?

I'm also running version: v2001_1d.45 and find it will not save
information from the flow tabs, particularly the device type
designator.  I've also seen the system go belly up when attempting to
print to a non-default printer.

Article: 36170
Subject: Hardware Software Partitioning help required.
From: weareallbastardsRE@MOVEinsurer.com (Christofire)
Date: Wed, 31 Oct 2001 23:35:44 GMT
Links: << >>  << T >>  << A >>
Hi everyone,

I'm a student in the UK and I'm part of a project group investigating
using FPGAs to increase application performance.  Our project is
investigating two different routes for moving part of a program to an
FPGA.

One route requires the use of a hardware/software partitioner.  Can
anyone on the newsgroup point me in the direction of any work done in
this area?  I have read various papers on the net (mainly on
http://citeseer.nj.nec.com/cs) but I was hoping for something more
practical based.

Initially we were hoping there would be an automated process we could
use or follow but after newsgroup searches I've found this is highly
unlikely.  As the person responsible for this section of the project
will I have to sit down and partition the test programs by hand?

If anyone could spare a little time to briefly explain about this area
or answer questions then please drop me a mail at
chris[at]ukrm[dot]org, or reply here.

Thanks in advance.

-- 
Christofire
"If at first you don't succeed, parachuting is not for you."

Article: 36171
Subject: Re: Leonardo bugs
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Thu, 01 Nov 2001 00:40:24 +0000
Links: << >>  << T >>  << A >>


David Meigs wrote:

> Russell Shaw <rjshaw@iprimus.com.au> wrote in message news:<3BDF3934.7F19DC45@iprimus.com.au>...
> > Mike Treseler wrote:
> > > Perhaps you forgot to save your project settings.
> >
> > I've tried that plenty of times, but leonardo has
> > lots of bugs, and one of them is that most of the
> > device settings you do in the flow tabs don't get
> > saved with the project. Are you using a similar
> > version?
>
> I'm also running version: v2001_1d.45 and find it will not save
> information from the flow tabs, particularly the device type
> designator.  I've also seen the system go belly up when attempting to
> print to a non-default printer.

When the GUI bites it takes out most of your ass.

Try command line+make to re-gain sanity and control over what you want to happen.



Article: 36172
Subject: Re: BRAM usage reduction in FIFO design: First Scenario
From: kahhean@hotmail.com (Chua Kah Hean)
Date: 31 Oct 2001 17:08:12 -0800
Links: << >>  << T >>  << A >>
Hi Falk,

Thanks for the post.

> > <about possible pitfalls of cascading FIFOs to make a deeper FIFO>
> 
> - this will increase latency
> - using two FIFO from Xapp131 will take 3 clock nets (write clock,
> in-between clock, read clock)

OK, I can take these in my design.  (Actually, I will use the read
clock for the in-between clock as well)

> > <about alternative ways to reduce BRAM usage>
> 
> Why dont you rearange the RAMS? Just use 12 256x16 BRAMs and create a
> chip select from the address counter[11:8]. Since this is just a 4 bit
> decoder it take only 1 LUT, so only 1 level of locic -> very fast

Yes, this is possible.  But my read/write clocks are independent, and
the source codes I have seen use gray-coding to reliably sample the
read/write addresses across the read/write clock domains for status
signal generation .  Correctly me if I am wrong: but I think gray
codes must come in blocks of power 2.  Anyway, I thought if there are
no other pitfalls other than increased latency, cascading may be
cleaner and faster than adding in decoding logic + sorting through the
status signal generation code.

Thanks.  TA TA.  :-)

Regards,
kahhean

Article: 36173
Subject: Re: Second Scenario: BRAM usage reduction in FIFO design
From: kahhean@hotmail.com (Chua Kah Hean)
Date: 31 Oct 2001 17:22:31 -0800
Links: << >>  << T >>  << A >>
Hi Falk,

Thanks again for your post.

> > block RAMs.  Can I implement a 1024 by 8 (two blocks) BRAM-based FIFO
> > and then parallel it with a 1024 by 1 FIFO implemented with
> > distributed SRAM?
> 
> Possible, but also here I think rearangeing of BRAMS can save a lot of
> trouble.
> Just remember. The BRAMs on Virtex-E/Spartan-II can be configured as
> 
> 4096x1
> 2048x2
> 1024x4
> 512x8
> 256x16
> 
> So for your 1024x9 FIFO just use 3 1024x4 BRAms in parallel, wasting
> only 25%.

Hmm, I did mis-calculate the number of BRams I needed.  Still,
unfortunately for me, I cannot afford 3 BRAMs.  Actually, my situation
is this: I have used up all the BRAMs in the XCV400E, then news came
along that I have to increase the (3 sets of)512x9 FIFO(currently
implemented using two 512x8 BRAMs) to about 620x9.  So I am trying to
keep the BRAM usage to 2 (I was thinking of using the distributed SRAM
to complement the BRAMs, but this looks like a very dirty fix to me),
or in my Scenario 1 post, salvage some BRAMs from other FIFOs in my
design.  :-P

Thanks.  TA TA.

Regards,
kahhean

Article: 36174
Subject: Re: Leonardo bugs
From: Russell Shaw <rjshaw@iprimus.com.au>
Date: Thu, 01 Nov 2001 12:43:50 +1100
Links: << >>  << T >>  << A >>


Rick Filipkiewicz wrote:
> 
> David Meigs wrote:
> 
> > Russell Shaw <rjshaw@iprimus.com.au> wrote in message news:<3BDF3934.7F19DC45@iprimus.com.au>...
> > > Mike Treseler wrote:
> > > > Perhaps you forgot to save your project settings.
> > >
> > > I've tried that plenty of times, but leonardo has
> > > lots of bugs, and one of them is that most of the
> > > device settings you do in the flow tabs don't get
> > > saved with the project. Are you using a similar
> > > version?
> >
> > I'm also running version: v2001_1d.45 and find it will not save
> > information from the flow tabs, particularly the device type
> > designator.  I've also seen the system go belly up when attempting to
> > print to a non-default printer.
> 
> When the GUI bites it takes out most of your ass.
> 
> Try command line+make to re-gain sanity and control over what you want to happen.

I hope most users complain to the vendor about these bugs. I am...



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