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Messages from 36175

Article: 36175
Subject: Re: Leonardo bugs
From: Ray Andraka <ray@andraka.com>
Date: Thu, 01 Nov 2001 01:50:49 GMT
Links: << >>  << T >>  << A >>
The Leonardo UI bugs make me appreciate Synplicity all that much more.

Russell Shaw wrote:

> Rick Filipkiewicz wrote:
> >
> > David Meigs wrote:
> >
> > > Russell Shaw <rjshaw@iprimus.com.au> wrote in message news:<3BDF3934.7F19DC45@iprimus.com.au>...
> > > > Mike Treseler wrote:
> > > > > Perhaps you forgot to save your project settings.
> > > >
> > > > I've tried that plenty of times, but leonardo has
> > > > lots of bugs, and one of them is that most of the
> > > > device settings you do in the flow tabs don't get
> > > > saved with the project. Are you using a similar
> > > > version?
> > >
> > > I'm also running version: v2001_1d.45 and find it will not save
> > > information from the flow tabs, particularly the device type
> > > designator.  I've also seen the system go belly up when attempting to
> > > print to a non-default printer.
> >
> > When the GUI bites it takes out most of your ass.
> >
> > Try command line+make to re-gain sanity and control over what you want to happen.
>
> I hope most users complain to the vendor about these bugs. I am...

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 36176
Subject: Re: Cloning someone else's IP core
From: kevinbraceusenet@hotmail.com (Kevin Brace)
Date: 31 Oct 2001 19:03:35 -0800
Links: << >>  << T >>  << A >>
Kolja Sulimma <kolja@sulimma.de> wrote in message news:<3BDC4A97.9505F214@sulimma.de>...
> Kevin Brace wrote:
> 
> > Thanks to everyone who replied to the posting I made.
> > Here are more details I will like to throw in.
> > Looking at Xilinx IP Evaluation license, does this evaluation license
> > stop someone from cloning Xilinx's IP cores?
> >
> > http://www.xilinx.com/ipcenter/ipevaluation/ipevaluation_license.htm
> >
> > ************************* (C) Xilinx *******************************
> > Xilinx IP Evaluation License Agreement
> >
> > Xilinx Evaluation IP is owned and controlled by Xilinx and
> > must be used solely for design, simulation, implementation and
> > creation of design files limited to Xilinx devices or technologies.
> > Use with non-Xilinx devices or technologies is expressly prohibited
> > and immediately terminates your license.
> 
> This violates the "principle of first sale" in the US and the "Erschöpfungsgrundsatz" in germany.
> When I buy a product the vendor looses all control over how I use the product.
> 
> 

        I understand what you are saying, but recently, Altera seems
to have won a key rulings against Clear Logic (an Altera cloner).

http://www.altera.com/corporate/press_box/releases/corporate/pr-wins_clear_logic.html


Basically the judge said that the bitstream file generated after P&R
cannot be sent to another company (Clear Logic) and used to program
non-Altera devices.
So, what the judge is saying here sounds like Altera has the right to
control what the customer can do with the bitstream file.
Almost sounds like Microsoft telling software developers that software
compiled with Microsoft's compiler contains Microsoft's libraries
inside the binary, so Microsoft has the right to control how the
compiled binary can be distributed.
I know that Microsoft does give a license for their libraries in the
binary, so what I described doesn't happen in practice.


> > Xilinx products are not intended for use in life support appliances,
> > devices, or systems.
> > Use in such applications are expressly prohibited
> > ********************************************************************
> >
> > Let's say that someone sign up for their IP evaluation, and use
> > Xilinx's technical documents like user's guide, design guide, and
> > reference design contained inside the evaluation zip file from Xilinx
> > to derive that person's original, but compatible implementation.
> > After someone is done cloning the IP core, release it to the public
> > (of course, without the files that came with the IP evaluation,
> > because I don't have the right to redistribute it) as a synthesizable
> > vendor neutral HDL implementation with constraint files for multiple
> > vendors' devices.
> > Since that work was derived from the original evaluation version of
> > the IP core, will that person have the right to implement it with any
> > vendor's device?
> 
> It is derived from the documentation, not from the IP core. Usually IP cores are not shipped with  source code and as
> long as you do not do any reverse engineering on the netlist you can hardly violate any copyright on the IP core
> implementation.

        It looks like the consensus of the replies I got seems to
suggest that as long as my design is based on reading the
documentation that describes how the IP core works, it is okay.



> 
> On the other hand the new (not cloned!) IP core does usually not contain anything from the documentation so you also do
> not violate any copyright on the documentation.
> 
> You might however violate patents. Even if your core is not compatible and not derived from the original one. This does
> not apply to PCI and many other open standards.


        I am totally aware that even if I come up with the design
independently, I can still violate patents.
From the patent title search I did at Delphion
(http://www.delphion.com) and USPTO (http://www.uspto.gov), it seems
to me that most Xilinx and Altera patents have to do with the internal
structure of an FPGA (like circuit techniques), and they seem to have
very few patents that can protect their IP cores from cloning.


> 
> Complication comes with open source software. If essentially the whole community knows the original source code then the
> original vendor will allways claim that you derive your core from theire work. Even if you didn't.
> 
> > Again, the method used here design that person's original
> > implementation compatible with the original will be:
> >
> > 1) Studying the bus protocol listed in the user guide, design guide,
> > or reference design
> >
> > 2) Entering waveform stimulus into the evaluation IP core, and analyze
> > how it behaves
> >
> > 3) Attach a user module that tests the evaluation IP core, and analyze
> > how it behaves
> >
> > 4) Study third party literature (IEEE, trade groups, or books related
> > that can be purchased at a book store)
> >
> > 5) Will not reverse engineer the netlist or any encrypted design
> > information (i.e., convert the netlist to gate-level symbols. Sort of
> > like disassembler software VCommunications used to have (maybe they
> > still have) that spit out .ASM file from .EXE file which can be
> > assembled again).
> >
> > The thing I guess I am trying to describe here is that is it possible
> > to clone Xilinx's IP core or any other IP core in a way Cyrix cloned
> > Intel's x86 implementation?
> >
> 
> I guess the main point is, that building something that does the same as someone elses product is not cloning.
> 
> You have a patent violation if you implement it the same way as it is stated in the patent, idependently of whether you
> did reverse engineering or whatever.
> 
> You have a copyright violation if you use part of the original source code, netlist or bitstream in you own
> implementation.

        I will never include any files distributed by the original
vendor, so I should clear that problem.


> 
> The license agreements are legaly worthless to a large extend. Especially if all information you need can be obtained
> without licensing the original core.
> (E.g. I do not need any Xilinx documentation to build a PCI to CoreConnect interface.)
> 
> IANAL,
> 
> Kolja Sulimma

        I don't know if the licensing agreement is totally worthless,
but from I read, and hear from people in the newsgroups, Xilinx's
licensing agreement doesn't explicitly prohibit someone else from
cloning their IP core.
Perhaps Xilinx didn't bother to state that because they knew they
won't be able to stop it.
        Anyhow, thanks for the advise, Kolja.



Regards,



Kevin Brace (don't respond to me directly, respond within the
newsgroup)

Article: 36177
Subject: Re: searchin for High density non bga packages something like PGA.
From: "Kevin Neilson" <kevin_neilson@removethis-yahoo.com>
Date: Thu, 01 Nov 2001 03:14:39 GMT
Links: << >>  << T >>  << A >>
There are no PGAs.  You're limited to variations of the QFP and BGAs
(including CSP, which is pretty much a small BGA).  I think QFPs are a bit
cheaper, but I'd rather use a BGA.  In my prototyping experience, QFP pins
always bend and get soldered together.

"Richard Meester" <rme@quest-innovations.com> wrote in message
news:3BDFC791.CA95D40D@quest-innovations.com...
> Hello all,
>
> I am searching for a high density non bga package FPGA. I don't want to
> use BGA since the high prototyping costs involved. My estimation is that
> PGA packages are cheaper to produce. Are there any SPartanII Virtex/II/E
> devices in this package?
>
> Hope you can help.
>
> Richard
>
> --
>
>
> Quest Innovations
> tel: +31 (0) 227 604046
> fax: +31 (0) 227 604053
> http://www.quest-innovations.com
>
>



Article: 36178
Subject: Re: Cloning someone else's IP core
From: kevinbraceusenet@hotmail.com (Kevin Brace)
Date: 31 Oct 2001 19:32:48 -0800
Links: << >>  << T >>  << A >>
Kolja Sulimma <kolja@sulimma.de> wrote in message news:<3BDFC4FA.121D269B@sulimma.de>...
> > I am sure that it depends on the skill of the designer, but from my
> > experience trying to meeting timings with my own PCI IP core, I think
> > meeting 33MHz PCI timings with a synthesizable (HDL based) PCI IP core
> > with only automatic P&R is very challenging to say the least.
> 
> I found that most constraints violations were false paths.
> For a PCI slave only TRDY and the output enable generation is a real problem.

        Yes, in my design too, TRDY# is a problem, but the worst TRDY#
path isn't any slower than the worst AD[31:0] path right now.
The best method I found so far to improve timings is to use a faster
part (i.e., use Spartan-II speed grade -6 instead of speed grade -5),
but my Insight Electronics Spartan-II PCI development board already
has speed grade -5, so using speed grade -6 really isn't an option.
I get about 20% improvements in timings, but that is still about 10%
to 15% short of meeting 33MHz PCI timings.



> In Virtex architectures there is a special logic block for this. The functionality was documented earlier
> in this newsgroup.
> 
> Kolja Sulimma


        I am aware that Virtex family including Spartan-II has the
mysterious special IRDY and TRDY pin (for 208-pin PQFP package
Spartan-II, special IRDY pin is at pin 24 and special TRDY pin is at
pin 27), which looks like (from reading old comp.arch.fpga postings)
it used to be a secret or an unofficial feature, but recent Spartan-II
pinout diagram and P&R PAD report tells you about it, so I guess it is
no longer a big secret.
From reading old comp.arch.fpga posting it looks like a user can
enable that feature from the HDL code, or from FPGA Editor.
I personally don't like to make my PCI IP a proprietary design that
targets only Xilinx devices (I want it to run on Altera FPGAs too,
although I am not an Altera fan.), so I personally don't like to use
this feature.
Plus, ISE WebPack doesn't come with FPGA Editor, so I cannot use this
method either.
I personally don't mind using this feature as long as I don't have to
make any modification to the HDL code though.
If the Floorplanner can activate it, that will be great, but it
doesn't look like it can.



Regards,



Kevin Brace (don't respond to me directly, respond within the
newsgroup)

Article: 36179
Subject: Re: Cloning someone else's IP core
From: kevinbraceusenet@hotmail.com (Kevin Brace)
Date: 31 Oct 2001 19:48:05 -0800
Links: << >>  << T >>  << A >>
Will Xilinx have a problem if someone designs a clone of Xilinx's IP
core (PCI IP core in particular) with a methodology I have mentioned
in
the second posting I made?
This is the methodology I am talking about (it is from the second
posting I made).


**********************************************************************
1) Studying the bus protocol listed in the user guide, design guide,
or reference design

2) Entering waveform stimulus into the evaluation IP core, and analyze
how it behaves

3) Attach a user module that tests the evaluation IP core, and analyze
how it behaves

4) Study third party literature (IEEE, trade groups, or books related
that can be purchased at a book store)

5) Will not reverse engineer the netlist or any encrypted design
information (i.e., convert the netlist to gate-level symbols. Sort of
like disassembler software VCommunications used to have (maybe they
still have) that spit out .ASM file from .EXE file which can be
assembled again).
**********************************************************************


       Also, any opinion (personal or official) about AMI
Semiconductor's Xilinx LogiCore PCI IP core clone?

http://www.eetimes.com/story/OEG20010907S0103

http://www.amis.com/trans/xilinx-pci.cfm



Why hasn't Xilinx taken any legal action against AMI Semiconductor?
Is it because Xilinx really can't? (doesn't have any legal grounds to
do so)



Regards,



Kevin Brace (don't respond to me directly, respond within the
newsgroup)




Eric Crabill <eric.crabill@xilinx.com> wrote in message news:<3BE052CF.51BB1510@xilinx.com>...
> Hi,
> 
> Again, as I stated, I am not a lawyer, but I don't quite
> understand the reasoning behind your comments.  The rest
> of this post are my comments and opinions, not those of
> my employer.
> 
> > A contract to transfer a good for an unlimited amount
> > of time without paying a recurrent fee is a purchase,
> > no matter what it is called in the contract.  I am pretty
> > sure that after purchasing the core package I own the
> > documentation, constraints files and the core generator
> > software.
> 
> I don't believe the license for the Xilinx PCI core,
> be it an evaluation or not, transfers ownership of the
> IP to the person buying the license.  This appears to
> be the case in:
> 
> http://www.xilinx.com/ipcenter/doc/xilinx_click_core_project_license.pdf
> http://www.xilinx.com/products/logicore/pci/docs/stanusag.htm
> http://www.xilinx.com/ipcenter/ipevaluation/ipevaluation_license.htm
> 
> Those who license the IP do not own it, although Xilinx
> grants the right to distribute FPGA configuration bitstreams
> generated with the licensed IP.  You cannot, however, distribute
> the IP itself, because you do not own it and are not authorized
> to distribute it.  And you do have to pay a recurring fee,
> called "maintenance" to keep your license valid for all
> versions except the evaluation version.
> 
> > To be able to sell copies of the core to customers I need of
> > course a license as this can not be covered by the purchase
> > alone. In a b2b context this license can be more or less
> > contain arbitrary agreements between me and the vendor.
> 
> Purchasing a license entitles you to distribute FPGA configuration
> bitstreams which are generated from the IP.  You cannot distribute
> the IP itself, or the netlist.  If that were allowed, a licensee
> could re-sell the netlist and compete against Xilinx with Xilinx's
> own IP product, selling it very cheaply because the licensee did not
> have to pay the research and development costs.
> 
> > However, a license that states that Xilinx remains the owner of
> > the IP is worthless, as this would mean that Xilinx would own
> > part of any product that contains the core.  At least the end
> > customer of my product must become owner of the netlist in
> > the FPGA.  And this of course allows me to become owner of the
> > netlist myself.
> 
> I believe the distinction that needs to be made is the difference
> between a bitstream and a netlist.  It is very difficult, indeed,
> to reverse engineer a piece of IP from a bitstream.  I believe
> Xilinx is not concerned about distribution (and ownership?) of
> device bitstreams because the IP which was used to create the
> bitstream cannot be "distilled" from the bitstream.
> 
> > (Would you buy a network adapter that comes with a license
> > agreement that states that part of the adapter is owned by Xilinx?)
> 
> Would I buy a shirt with a picture of Mickey Mouse?  Sure.  It probably
> says on the tag that it is officially licensed from the Disney
> Corporation.
> I would not pretend to own Mickey Mouse because I bought a shirt with
> his
> image stamped on it.
> 
> Would I buy a design with a licensed image of the Xilinx PCI core
> in it?  Yes.
> 
> > If I use part of the netlist or source code in my own PCI core I
> > of course violate theire copyright. I can however not violate any
> > Xilinx patents because I licensed them from SIGPCI.
> 
> I don't think this is correct.  Where did you get this information?
> Did you read:
> 
> http://www.pcisig.com/membership/about_us/bylaws
> 
> This suggests to me, in Section 15.3, that if Xilinx contributes
> anything to a specification, that Xilinx grants the PCI SIG the
> unrestricted license to use it.  This grant is reciprocal, meaning
> that other PCI companies are allowed to use it as well.
> 
> Then, if you keep reading down to Section 15.6, this flat says:
> 
> "The Members agree no patent license, immunity or other right is
> granted under these Bylaws by any Member or its Affiliates to any
> other Members or their Affiliates or to the Corporation, either
> directly or by implication, estoppel or otherwise, other than the
> agreements to grant licenses expressly set forth in this ARTICLE 15."
> 
> That doesn't sound like you have licensed any Xilinx patents via
> the PCI by being a PCI member.
> 
> Thanks for reading,
> Eric

Article: 36180
Subject: LeonardoSpectrum-Altera stability
From: kevinbraceusenet@hotmail.com (Kevin Brace)
Date: 31 Oct 2001 20:49:42 -0800
Links: << >>  << T >>  << A >>
I am wondering if someone else had the same experiences like I did.
I recently installed LeonardoSpectrum-Altera (Level 1, a freebie from
Altera) to my computer.
I synthesized a Verilog design with LeonardoSpectrum-Altera that
synthesized absolutely fine with Xilinx ISE WebPack's synthesis tool
XST (actually XST Verilog) and compiled absolutely fine with ModelSim
5.5b XE-Starter (the simulation went fine).
But when I synthesized it with LeonardoSpectrum-Altera, it crashed 
(LEONARDO caused an invalid page fault in module MSVCRT.DLL at
016f:780120b1.) 100% of the time at when it is at "Boundary
Optimization."
What I noticed was that if I synthesized a Verilog design that
contains defparam in two modules (in module_a.v and module_b.v), the
problem occurs, but if I removed defparam from module_a.v,
LeonardoSpectrum-Altera no longer crashed.
I know I can use defparam to directly define the runtime parameter of
module_c.v from module_a.v (by writing defparam
Module_B_Inst.Module_C_Inst.NUMBER = 8;), but because of various
requirements I have, I don't want to do that.
Isn't this LeonardoSpectrum-Altera's bug, or am I violating Verilog's
syntax?
        Besides the defparam issue when I press "stop" button of
LeonardoSpectrum-Altera during synthesis, it often crashes (causes a
general protection fault or an invalid page fault ).
I have used XST for several months, but it never crashed like the way
I described.
I know that the version I used is a freebie Altera OEM version, but do
people really pay several thousand dollars for the full
LeonardoSpectrum which at least the freebie one crashes very
frequently?
The version I used was v2001_1a.28_OEM_Altera, and I am aware that it
is not the latest, but I cannot download the latest through 56K modem
because Altera stores the LeonardoSpectrum-Altera on its FTP server
(various download utilities cannot resume download if the file is on
an FTP server).




Regards,



Kevin Brace (don't respond to me directly, respond within the
newsgroup)





************************* module_a.v 
*********************************

module Module_A(



               );



Module_B Module_B_Inst(
                       
                       
                       
                       
				);



defparam	Module_B_Inst.NUMBER	= 8;




endmodule

***********************************************************************


************************* module_b.v 
*********************************

module Module_B(



               );



Module_C Module_C_Inst(
                       
                       
                       
                       
				);


parameter      NUMBER = 16;


defparam	Module_C_Inst.NUMBER	= 8;




endmodule

***********************************************************************


************************* module_c.v 
*********************************

module Module_C(



               );



parameter      NUMBER = 4;




endmodule

***********************************************************************

Article: 36181
Subject: XC18V04 serial EEPROM problem - 5V tolerance ?
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Thu, 01 Nov 2001 08:03:56 +0000
Links: << >>  << T >>  << A >>

We seem are having some strange problems programming these devices. The
situation is this:

o We have copied the Xilinx Parallel-III download cable logic onto our
boards with the exception that the HC125 parts have been replaced by
ordinary LS125As.

o The power supply for this logic is 5V (inheirited from a previous
board which used the original 5V XC95K parts). We have even kept the
Schottky diode (~0.3V drop) between VCC and the LS125As power pin.

o Short JTAG chain with an XC18V04 followed by an XC95144XL.

What we have found is this: The XC18V04 does not respond to the
initialise chain command if:

1. I short out the Schottky.

2. I happen to use an ATX power supply whose nominal 5V is actually
~5.25. Most of the ones we have are 5.1-5.2V.

#2 can be worse in that sometimes the device is partially programmed but
gets verify errors.

The XC18V04 is claimed to be tolerant to 5.5V. This may be a red herring
with the real problem being down to edge rates.

Anybody seen anything similar ?

What I'm going to try is to either reverse the chain order (we know from
another board that the XL parts are o.k. with this download design) or
try replacing the LS parts with HCs powered from 3.3V.



Article: 36182
Subject: Re: Leonardo bugs
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Thu, 01 Nov 2001 08:14:06 +0000
Links: << >>  << T >>  << A >>


Ray Andraka wrote:

> The Leonardo UI bugs make me appreciate Synplicity all that much more.
>
>

Seconded with one caveat. From what I remember of our evaluation of the two products the Leonardo command
documentation was much better than Synplify's (this came close to tipping the balance the other way).
Synplify's docs have come on a long way since then but they are still basically ``Help'' file based
instead of the (IMO better) Unix man-page style of Leo's.



Article: 36183
Subject: Altera Local Routing
From: digari@dacafe.com (digari)
Date: 1 Nov 2001 00:34:32 -0800
Links: << >>  << T >>  << A >>
Why there is interleaved routing from an LE to adjecent LLIs in
Mercury and ApexII architectures.

"APEX II devices use an interleaved LAB structure, so that each LAB
can
drive two local interconnect areas. Every other LE drives to either
the left
or right local interconnect area, alternating by LE."

Can anyone shed some light on the alternate routing structure of LEs
within a LAB.

Article: 36184
Subject: Registered as well as unregistered outputs?
From: ndeshmukh@yahoo.com (nitin)
Date: 1 Nov 2001 01:32:43 -0800
Links: << >>  << T >>  << A >>
Hi...

Can anyone tell me how frequently and where both registered and
unregistered outputs from an LE are required...?

Ciao,
nitin.

Article: 36185
Subject: Re: Virtex 2 or E Evaluation Board
From: "John Adair" <newsanswer@removethisenterpoint.co.uk>
Date: Thu, 1 Nov 2001 11:06:19 -0000
Links: << >>  << T >>  << A >>
We have a product under development that meets your requirement.

John Adair
Enterpoint Ltd.
Unit 4
Malvern Hills Science Park
Geraldine Road
Malvern
Worcestershire
United Kingdom
www.enterpoint.co.uk

The views expressed in this message are those of the writer and not
necessarily those of Enterpoint Ltd.. The use of information in this message
is without warranty and persons using the information are advised to make
their own checks as to it's validity. No responsibility will be accepted for
any incorrect, inaccurate or missleading information supplied.


Matt Bielstein <mbielstein@qwest.net> wrote in message
news:UoNC7.892$Ju6.349701@news.uswest.net...
> Try http://www.nallatech.com/products/dime.htm
>
> They might have something in line with what you are seeking. There are
> others. They just come to mind.
>
> Good luck!
> Matt
>
>
> "#BASUKI ENDAH PRIYANTO#" <PH892987@ntu.edu.sg> wrote in message
> news:8D5C8824989A21458FFF1C3CE9902036058AF144@mail12.main.ntu.edu.sg...
> > Hi,
> >
> > Currently, I am looking for Xilinx Virtex 2 or Virtex E evaluation
> > board. Basically, ,my requirement is the FPGA which has at least 3
> > Million System gate.
> >
> > Anybody can help me ?
> >
> > Thanks !
> >
> > Basuki
> >
>
>



Article: 36186
Subject: Re: LeonardoSpectrum-Altera stability
From: Andrzej Ekiert <treike@zeus.polsl.gliwice.pl>
Date: Thu, 1 Nov 2001 11:22:22 -0500
Links: << >>  << T >>  << A >>
Dnia 31 Oct 2001 20:49:42 -0800
kevinbraceusenet@hotmail.com (Kevin Brace) napisa³:


> But when I synthesized it with LeonardoSpectrum-Altera, it crashed 
> (LEONARDO caused an invalid page fault in module MSVCRT.DLL at
> 016f:780120b1.) 100% of the time at when it is at "Boundary
> Optimization."

On average, it happens once every 3 compilations, no matter how small 
and simple the design is.

>         Besides the defparam issue when I press "stop" button of
> LeonardoSpectrum-Altera during synthesis, it often crashes (causes a
> general protection fault or an invalid page fault ).

Yup, it does. 

> The version I used was v2001_1a.28_OEM_Altera, and I am aware that it
> is not the latest, but I cannot download the latest through 56K modem
> because Altera stores the LeonardoSpectrum-Altera on its FTP server
> (various download utilities cannot resume download if the file is on
> an FTP server).
> 

I'm using the very latest OEM_Altera version and experience the same. 
BTW: have you tried ncftp or gFTP (available for *BSD, Linux and most other 
Unices) ?

Article: 36187
Subject: Xilinx multiplier core - problem
From: "George Constantinides" <g.constantinides@ic.ac.uk>
Date: Thu, 1 Nov 2001 16:28:37 -0000
Links: << >>  << T >>  << A >>
Has anyone noticed that for the xilinx multiplier core (v. 3.1), a constant
coefficient multiplier with a negative coefficient appears to require one
more coefficient bit (port B width) than it should?

    Thus coef = 5 requires 3 bits, coef = -5 requires 5 bits (NOT 4 bits).

This contradicts the (correct) statement in the core datasheet which states
that the coef value must be between -2^(port_b_width-1) and
2^(port_b_width-1) - 1 for signed coefficients. What's going on here??

        George




Article: 36188
Subject: Re: BRAM usage reduction in FIFO design: First Scenario
From: "Falk Brunner" <Falk.Brunner@gmx.de>
Date: Thu, 1 Nov 2001 18:01:10 +0100
Links: << >>  << T >>  << A >>

"Chua Kah Hean" <kahhean@hotmail.com> schrieb im Newsbeitrag
news:e2270493.0110311708.1f112372@posting.google.com...

> Yes, this is possible.  But my read/write clocks are independent, and
> the source codes I have seen use gray-coding to reliably sample the
> read/write addresses across the read/write clock domains for status
> signal generation .  Correctly me if I am wrong: but I think gray

Right, the use gray code to transfer the write/read pointers across the
clock boundary. But the use normal binary couters for addressinf the two
port of the RAM , arnt they?

--
MfG
Falk




Article: 36189
Subject: Xilinx Foundation: Generation of EDIF from VHDL in Batch Mode
From: "George Constantinides" <g.constantinides@ic.ac.uk>
Date: Thu, 1 Nov 2001 17:03:38 -0000
Links: << >>  << T >>  << A >>
Hello,
    I'm trying to synthesise VHDL using Foundation 3.1i. For the first time,
I need to do this in batch mode and I'm having problems. Although I can do
all the steps from EDIF onwards, I can't figure out how to generate the
initial EDIF from the VHDL except by going through the project manager GUI
and clicking on "Synthesis". Surely there must be a way??

        Thanks,
            George




Article: 36190
Subject: Synplicity, Xilinx, & unwanted BUFGs
From: "Jason T. Wright" <Jason.T.Wright@Boeing.com>
Date: Thu, 1 Nov 2001 17:18:30 GMT
Links: << >>  << T >>  << A >>
How does one prohibit Synplify from inferring a global buffer?  I read
the on-line help, and it mentions using an attribute in the VHDL (or
verilog) code to FORCE a global buffer, but negating that attribute did
not stop its insertion.  LeonardoSpectrum and FPGAExpress each has a
command to stop such an undesired action (or, correspondingly, to force
such an insertion.)   Left to their own devices, the tools can create
wonderfully efficient, or wonderfully bloated, results from a user's
code.  I've seen a little bit of each.

-- 
Jason T. Wright

The opinions I express are my own ...
    unless otherwise indicated!

Article: 36191
Subject: Re: Verilog vs. VHDL
From: Richard Iachetta <iachetta@us.ibm.com>
Date: Thu, 1 Nov 2001 11:26:55 -0600
Links: << >>  << T >>  << A >>
In article <3BDE2C28.5CC709DE@yahoo.com>, spamgoeshere4@yahoo.com says...
> But to be conversent in both languages is not so hard. I learned VHDL
> first and found it workable but always had trouble with type changes. I
> then learned Verilog and found few "trouble spots" that were unique.

Right, both are adequate but both have faults.  I learned Verilog first 
and while I did my first VHDL design, I was convinced that Verilog was 
better.  Then after switching back to Verilog (after a second VHDL 
design) I was convinced that VHDL was better.  The grass is always 
greener on the other side.  :-)

-- 
Rich Iachetta
iachetta@us.ibm.com
I do not speak for IBM.

Article: 36192
Subject: Re: Second Scenario: BRAM usage reduction in FIFO design
From: Peter Alfke <peter.alfke@xilinx.com>
Date: Thu, 01 Nov 2001 09:27:23 -0800
Links: << >>  << T >>  << A >>
If you have plenty of time ( low frequency ), you can store the 9 bits in five
sequential accesses to two concatenated  2Kx2 BlockRAMs. That gives you 4K/5 =
819 depth and effectively 10 bit width, but the throughput is very slow, in the
max 30 M words per second area. May be worthless, but packs well.

Peter Alfke


Chua Kah Hean wrote:

> Hi Falk,
>
> Thanks again for your post.
>
> > > block RAMs.  Can I implement a 1024 by 8 (two blocks) BRAM-based FIFO
> > > and then parallel it with a 1024 by 1 FIFO implemented with
> > > distributed SRAM?
> >
> > Possible, but also here I think rearangeing of BRAMS can save a lot of
> > trouble.
> > Just remember. The BRAMs on Virtex-E/Spartan-II can be configured as
> >
> > 4096x1
> > 2048x2
> > 1024x4
> > 512x8
> > 256x16
> >
> > So for your 1024x9 FIFO just use 3 1024x4 BRAms in parallel, wasting
> > only 25%.
>
> Hmm, I did mis-calculate the number of BRams I needed.  Still,
> unfortunately for me, I cannot afford 3 BRAMs.  Actually, my situation
> is this: I have used up all the BRAMs in the XCV400E, then news came
> along that I have to increase the (3 sets of)512x9 FIFO(currently
> implemented using two 512x8 BRAMs) to about 620x9.  So I am trying to
> keep the BRAM usage to 2 (I was thinking of using the distributed SRAM
> to complement the BRAMs, but this looks like a very dirty fix to me),
> or in my Scenario 1 post, salvage some BRAMs from other FIFOs in my
> design.  :-P
>
> Thanks.  TA TA.
>
> Regards,
> kahhean


Article: 36193
Subject: Re: Second Scenario: BRAM usage reduction in FIFO design
From: Peter Alfke <peter.alfke@xilinx.com>
Date: Thu, 01 Nov 2001 10:22:14 -0800
Links: << >>  << T >>  << A >>
You can also store 4 bits each in 3 consecutive accesses to two concatenated 1K x
4 BlockRAMs, which effectively gives you a 682-deep, 12 bit wide FIFO, slightly
faster. It all depends to your (unknown) speed requirements.

Peter Alfke
==============================
Peter Alfke wrote:

> If you have plenty of time ( low frequency ), you can store the 9 bits in five
> sequential accesses to two concatenated  2Kx2 BlockRAMs. That gives you 4K/5 =
> 819 depth and effectively 10 bit width, but the throughput is very slow, in the
> max 30 M words per second area. May be worthless, but packs well.
>
> Peter Alfke
>


Article: 36194
Subject: Help with a 1996 XC3064 design!!
From: z80@ds2.com (Peter)
Date: Thu, 01 Nov 2001 19:04:44 +0000
Links: << >>  << T >>  << A >>
Hello,

In 1996 I designed a complicated pulse generator which used 32
identical XC3064 modules. There are 32 TQFP packages of these, plus
one XC3030 for address decoding etc (this is an ISA card).

The 3k series device is now obsolete. I would also not like to risk
rebuilding this board with some newer XC3064s because I know the more
recent devices are much faster and some structures don't work anymore,
e.g. shift registers which use local interconnects for the clock line.

Now the customer wants three more of these very expensive boards!

If I have timing problems, I may have to re-do the design. The design
was done in Viewlogic 4 (under MS-DOS, a very solid package but I
cannot run it anymore). I do have printouts of the circuits inside the
FPGAs.

I would appreciate any suggestions.


Peter.
--
Return address is invalid to help stop junk mail.
E-mail replies to zX80@digiYserve.com but remove the X and the Y.
Please do NOT copy usenet posts to email - it is NOT necessary.

Article: 36195
Subject: Re: High level synthesis will never work well :)
From: Ken McElvain <ken@synplicity.com>
Date: Thu, 01 Nov 2001 11:08:31 -0800
Links: << >>  << T >>  << A >>


Rick Filipkiewicz wrote:

> 
> In other words what would help is a publicly accessible database of
> problems/inefficiencies and their workarounds/solutions like the Xilinx answers
> DB. It sometimes seems that when I (maybe others as well) send in a bug report
> it seems to vanish into a vacuum. I get an acknowlegement that there's a
> problem and that's it. It gets worse when, as in a recent test case of mine, I
> send in what appears to be a Xilinx MAP problem only to get told by Xilinx that
> its really a synthesis problem and its been passed over to Synplicity.


The concept is good and the economic reasons to go this route increase
with the size of the customer base.  It costs a lot to put out a
sanitized bug data base that deletes any reference to customer
information that might be sensitive, plus merging duplicate problem
reports, plus editing the info so you can understand it (Notations in
our internal bug system can become somewhat cryptic).   For now we
are relying on direct contact with our customer support engineers via
phone or email.


> 
> This needs to be combined with a lisiting in the release notes for each version
> of all issues (bugs + imporovements) that have been fixed. ModelSIM is the
> paragon here.
> 
> I do appreciate that HDL synthesis  is complex and there's always the
> possibility that fixing one thing will break something else or that my ``bug''
> may be unique to me; stemming perhaps from pushing the boundaries of
> synthesisability. That information is, in itself, very valuable.
> 
> IMO Synplify is the best of the bunch - at least for Xilinx parts - but with
> some attention to the issues above you could win the engineer's ultimate
> accolade `Synplify ? Great tool, low hassle'.
> 
> As a test case that's relevant to this thread since the problem relates to the
> reset type - async/sync:
> 
> What's the status of bug report #33437 (register replication) ?
> 
My understanding is that this was about a failure to replicate 

registers with sync resets to improve timing.  The fix has been

made and will be included our next major release (after 7.0).







Article: 36196
Subject: Re: Synplicity, Xilinx, & unwanted BUFGs
From: Alan Nishioka <alann@accom.com>
Date: Thu, 01 Nov 2001 11:16:22 -0800
Links: << >>  << T >>  << A >>
"Jason T. Wright" wrote:

> How does one prohibit Synplify from inferring a global buffer?

In synplify, using verilog, the directive to not use a global buffer is:
/* synthesis syn_noclockbuf=1 */

Alan Nishioka
alann@accom.com



Article: 36197
Subject: Re: Synplicity, Xilinx, & unwanted BUFGs
From: "Kevin Neilson" <kevin_neilson@removethis-yahoo.com>
Date: Thu, 01 Nov 2001 19:28:12 GMT
Links: << >>  << T >>  << A >>
I've used the "synthesis syn_noclockbuf" directive in source code and it has
worked for me.
-Kevin

"Jason T. Wright" <Jason.T.Wright@Boeing.com> wrote in message
news:3BE183E6.204EA0C9@Boeing.com...
> How does one prohibit Synplify from inferring a global buffer?  I read
> the on-line help, and it mentions using an attribute in the VHDL (or
> verilog) code to FORCE a global buffer, but negating that attribute did
> not stop its insertion.  LeonardoSpectrum and FPGAExpress each has a
> command to stop such an undesired action (or, correspondingly, to force
> such an insertion.)   Left to their own devices, the tools can create
> wonderfully efficient, or wonderfully bloated, results from a user's
> code.  I've seen a little bit of each.
>
> --
> Jason T. Wright
>
> The opinions I express are my own ...
>     unless otherwise indicated!



Article: 36198
Subject: Re: Xilinx Foundation: Generation of EDIF from VHDL in Batch Mode
From: Dave Vanden Bout <devb@xess.com>
Date: Thu, 01 Nov 2001 14:28:24 -0500
Links: << >>  << T >>  << A >>
George Constantinides wrote:

> Hello,
>     I'm trying to synthesise VHDL using Foundation 3.1i. For the first time,
> I need to do this in batch mode and I'm having problems. Although I can do
> all the steps from EDIF onwards, I can't figure out how to generate the
> initial EDIF from the VHDL except by going through the project manager GUI
> and clicking on "Synthesis". Surely there must be a way??
>
>         Thanks,
>             George

We have an application note on running Xilinx Foundation tools from a makefile.
Part of that involves running the FPGA Express VHDL synthesizer so it may
pertain to your problem.  You can find it at
http://www.xess.com/appnotes/fndmake.pdf.


--
|| Dr. Dave Van den Bout   XESS Corp.               (919) 387-0076 ||
|| devb@xess.com           2608 Sweetgum Dr.        (800) 549-9377 ||
|| http://www.xess.com     Apex, NC 27502 USA   FAX:(919) 387-1302 ||



Article: 36199
Subject: Re: Can anyone guide me in selecting an FPGA?
From: Peter Alfke <peter.alfke@xilinx.com>
Date: Thu, 01 Nov 2001 11:35:08 -0800
Links: << >>  << T >>  << A >>

--------------CB9EFA7AFD951A9974B26431
Content-Type: text/plain; charset=us-ascii; x-mac-type="54455854"; x-mac-creator="4D4F5353"
Content-Transfer-Encoding: 7bit

Xilinx is officially quite guarded about mentioning and explaining the next
generation Virtex-II devices ( although we are obviously quite far along ).
But here is a brand-new magazine article that puts the Xilinx and Altera efforts
in perspective.
Read at you own peril, and please don't accuse me of "Marketing"...

http://www.eet.com/story/OEG20011031S0025

Peter Alfke
=========================================
David wrote:

> I'm looking for a FPGA that will b e used with a SERDES
> device. Originally I was looking at an XCV2000 or APEX1000
> along with a SERDES device (most likely TI or Conexant
> 3.125Gbps) but I've heard that Xilinx is coming out with a
> FPGA that will have high-speed SERDES functionality built in.
> Does anyone know what the story is with that? Would you
> recommend that as a better/cheaper (how much?) alternative?
>
> Dave

--------------CB9EFA7AFD951A9974B26431
Content-Type: text/html; charset=us-ascii
Content-Transfer-Encoding: 7bit

<!doctype html public "-//w3c//dtd html 4.0 transitional//en">
<html>
Xilinx is officially quite guarded about mentioning and explaining the
next generation Virtex-II devices ( although we are obviously quite far
along ).
<br>But here is a brand-new magazine article that puts the Xilinx and Altera
efforts in perspective.
<br>Read at you own peril, and please don't accuse me of "Marketing"...
<p><u><A HREF="http://www.eet.com/story/OEG20011031S0025">http://www.eet.com/story/OEG20011031S0025</A></u>
<p>Peter Alfke
<br>=========================================
<br>David wrote:
<blockquote TYPE=CITE>I'm looking for a FPGA that will b e used with a
SERDES
<br>device. Originally I was looking at an XCV2000 or APEX1000
<br>along with a SERDES device (most likely TI or Conexant
<br>3.125Gbps) but I've heard that Xilinx is coming out with a
<br>FPGA that will have high-speed SERDES functionality built in.
<br>Does anyone know what the story is with that? Would you
<br>recommend that as a better/cheaper (how much?) alternative?
<p>Dave</blockquote>
</html>

--------------CB9EFA7AFD951A9974B26431--




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