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Threads Starting Jan 2002
38029: 02/01/01: satya: Virtex-II FPGA Chips Availability
38031: 02/01/01: Colin Cook: Re: Virtex-II FPGA Chips Availability
38032: 02/01/02: Orlls: Verilog code
38042: 02/01/02: Brad Eckert: Re: Verilog code
38033: 02/01/02: divya: FPGA
38039: 02/01/02: Andy Peters: Re: FPGA
38034: 02/01/02: divya: FLOORPLANNING IN XILINX
38118: 02/01/06: Kevin Brace: Re: FLOORPLANNING IN XILINX
38035: 02/01/02: renjini: floorplanning
38119: 02/01/06: Kevin Brace: Re: floorplanning
38036: 02/01/02: Matthias Weber: asic vs. fpga
38044: 02/01/02: Rene Tschaggelar: Re: asic vs. fpga
38064: 02/01/03: Noel Klonsky: Re: asic vs. fpga
38072: 02/01/04: Peter Alfke: Re: asic vs. fpga
38077: 02/01/04: Thomas Stanka: Re: asic vs. fpga
38095: 02/01/04: Richard Iachetta: Re: asic vs. fpga
38099: 02/01/04: S. Ramirez: Re: asic vs. fpga
38100: 02/01/04: Peter Alfke: Re: asic vs. fpga
38104: 02/01/05: <hamish@cloud.net.au>: Re: asic vs. fpga
38108: 02/01/05: Rick Filipkiewicz: Re: asic vs. fpga
38124: 02/01/06: Kim Enkovaara: Re: asic vs. fpga
38266: 02/01/10: Martin Darwin: Re: asic vs. fpga
38276: 02/01/10: Rick Filipkiewicz: Re: asic vs. fpga
38302: 02/01/11: Thomas Stanka: Re: asic vs. fpga
38304: 02/01/11: Ray Andraka: Re: asic vs. fpga
38310: 02/01/11: Martin Darwin: Re: asic vs. fpga
38336: 02/01/11: jay mitchell: Re: asic vs. fpga
38362: 02/01/12: Petter Gustad: Re: asic vs. fpga
42188: 02/04/18: Sujatha Sriram: fpga limitation
42191: 02/04/18: Russell: Re: fpga limitation
42230: 02/04/18: Manfred Kraus: Re: fpga limitation
42236: 02/04/18: Jay: Re: fpga limitation
42240: 02/04/18: Austin Lesea: Re: fpga limitation
42251: 02/04/18: Tim: Re: fpga limitation
42254: 02/04/18: John_H: Re: fpga limitation
42257: 02/04/18: Austin Lesea: Re: fpga limitation
42321: 02/04/20: Hal Murray: Re: fpga limitation
42377: 02/04/22: Austin Lesea: Re: fpga limitation
42644: 02/04/30: Hal Murray: Re: fpga limitation
42648: 02/04/30: Tim: Re: fpga limitation
43042: 02/05/10: Rick Filipkiewicz: Re: fpga limitation
42386: 02/04/22: John_H: Re: fpga limitation
42295: 02/04/19: Jay: Re: fpga limitation
42310: 02/04/20: Tim: Re: fpga limitation
42268: 02/04/19: Marco Serafini: Re: fpga limitation
38045: 02/01/02: Jason Berringer: A Fast counter in VHDL?
38047: 02/01/03: S. Ramirez: Re: A Fast counter in VHDL?
38067: 02/01/03: Jason Berringer: Re: A Fast counter in VHDL?
38070: 02/01/04: Peter Alfke: Re: A Fast counter in VHDL?
38083: 02/01/04: Falk Brunner: Re: A Fast counter in VHDL?
38113: 02/01/06: Ray Andraka: Re: A Fast counter in VHDL?
38132: 02/01/06: Jason Berringer: Re: A Fast counter in VHDL?
38048: 02/01/03: Andreas Schweizer: Re: A Fast counter in VHDL?
38085: 02/01/04: Brad Eckert: Re: A Fast counter in VHDL?
38046: 02/01/03: Kenneth: Problem/Question about the timing report on Xilinx ISE 4.1
38056: 02/01/03: <hamish@cloud.net.au>: Re: Problem/Question about the timing report on Xilinx ISE 4.1
38075: 02/01/04: Kenneth: Re: Problem/Question about the timing report on Xilinx ISE 4.1
38079: 02/01/04: <hamish@cloud.net.au>: Re: Problem/Question about the timing report on Xilinx ISE 4.1
38049: 02/01/03: Alex Sherstuk: Q: Cable for multiple LVDS signals - ?
38058: 02/01/03: Austin Lesea: Re: Q: Cable for multiple LVDS signals - ?
38059: 02/01/03: Patrick McGuirk: Re: Cable for multiple LVDS signals - ?
38060: 02/01/03: Petter Gustad: Re: Q: Cable for multiple LVDS signals - ?
38050: 02/01/02: Antonio: Large ROM question
38052: 02/01/03: Daniel Yap: Help on RAM-based Shift Registers
38053: 02/01/03: Peter van Beek: PCI Solution: LogiCore?
38065: 02/01/03: clevin1234: Re: PCI Solution: LogiCore?
38066: 02/01/03: Colin Cook: Re: PCI Solution: LogiCore?
38068: 02/01/03: Austin Franklin: Re: PCI Solution: LogiCore?
38078: 02/01/04: Peter van Beek: Re: PCI Solution: LogiCore?
38084: 02/01/04: Austin Franklin: Re: PCI Solution: LogiCore?
38148: 02/01/07: John Jakson: Re: PCI Solution: LogiCore?
38548: 02/01/17: Stefan Klein: Re: PCI Solution: LogiCore?
38554: 02/01/17: Iwo Mergler: Re: PCI Solution: LogiCore?
39091: 02/01/31: Peter van Beek: Re: PCI Solution: LogiCore?
38076: 02/01/04: Kevin Brace: Re: PCI Solution: LogiCore?
38097: 02/01/04: Eric Smith: Re: PCI Solution: LogiCore?
38054: 02/01/03: Ashley: Automatically pipeline combinatorial EDIF
38055: 02/01/03: Steven Derrien: Re: Automatically pipeline combinatorial EDIF
38057: 02/01/03: Andreas Wassatsch: Re: Automatically pipeline combinatorial EDIF
38069: 02/01/03: Doug: Spartan-IIE interfacing issues
38080: 02/01/04: Kevin Brace: Re: Spartan-IIE interfacing issues
38081: 02/01/04: Rick Filipkiewicz: Re: Spartan-IIE interfacing issues
38088: 02/01/04: Austin Lesea: Re: Spartan-IIE interfacing issues
38298: 02/01/11: rickman: Re: Spartan-IIE interfacing issues
38316: 02/01/11: Austin Lesea: Re: Spartan-IIE interfacing issues
38073: 02/01/03: Markus Meng: ACTEL SX-A serie and ROM implementation ...
38082: 02/01/04: Falk Brunner: Re: ACTEL SX-A serie and ROM implementation ...
38074: 02/01/03: Antonio: conv_integer problem ???
39385: 02/02/07: Madhu: Re: conv_integer problem ???
38086: 02/01/04: Chuck Woodring: multiplexing a clock
38090: 02/01/04: Falk Brunner: Re: multiplexing a clock
38092: 02/01/04: Steve Rencontre: Re: multiplexing a clock
38093: 02/01/04: Bob Perlman: Re: multiplexing a clock
38087: 02/01/04: Claus Ritter: Configuration Times of FPGAs
38089: 02/01/04: Falk Brunner: Re: Configuration Times of FPGAs
38091: 02/01/04: Ulf Samuelsson: Re: Configuration Times of FPGAs
38096: 02/01/04: Chris Stinson: Re: Configuration Times of FPGAs
38094: 02/01/04: dev: help with older xilinx fpga's
38098: 02/01/04: Peter Alfke: Re: help with older xilinx fpga's
38101: 02/01/04: Yu Jun: ASIC faster than VirtexII FPGA?
38102: 02/01/05: Nicholas Weaver: Re: ASIC faster than VirtexII FPGA?
38106: 02/01/05: Muzaffer Kal: Re: ASIC faster than VirtexII FPGA?
38103: 02/01/04: Peter Alfke: Re: ASIC faster than VirtexII FPGA?
38105: 02/01/05: Muzaffer Kal: Re: ASIC faster than VirtexII FPGA?
38291: 02/01/10: Jay: Re: ASIC faster than VirtexII FPGA?
38314: 02/01/11: Austin Lesea: Re: ASIC faster than VirtexII FPGA?
38107: 02/01/05: jacky Renaux: RNS
38112: 02/01/06: Ray Andraka: Re: RNS
38109: 02/01/05: Matthias Weber: full custom design
38110: 02/01/05: Phil Hays: Re: full custom design
38111: 02/01/05: Muzaffer Kal: Re: full custom design
38114: 02/01/05: ssy: Q:where can I find an indepth manual about P&R in Quartus II ?
38116: 02/01/06: Kevin Brace: Re: Q:where can I find an indepth manual about P&R in Quartus II ?
38122: 02/01/06: ssy: Re: Q:where can I find an indepth manual about P&R in Quartus II ?
38115: 02/01/05: Orlls: simprims_ver/xilinxcorelib_ver /unisims_ver
38133: 02/01/06: Mike Treseler: Re: simprims_ver/xilinxcorelib_ver /unisims_ver
38137: 02/01/06: Orlls: Re: simprims_ver/xilinxcorelib_ver /unisims_ver
38141: 02/01/07: Utku Ozcan: Re: simprims_ver/xilinxcorelib_ver /unisims_ver
38154: 02/01/07: Brian Philofsky: Re: simprims_ver/xilinxcorelib_ver /unisims_ver
38682: 02/01/21: Paulo Dutra: Re: simprims_ver/xilinxcorelib_ver /unisims_ver
38117: 02/01/05: Nachiket Kapre: how do i program a Spartan FPGA
38123: 02/01/06: Falk Brunner: Re: how do i program a Spartan FPGA
38211: 02/01/08: swan: Re: how do i program a Spartan FPGA
38236: 02/01/09: Falk Brunner: Re: how do i program a Spartan FPGA
38125: 02/01/06: S. Ramirez: Re: how do i program a Spartan FPGA
38273: 02/01/10: Jon Elson: Re: how do i program a Spartan FPGA
38120: 02/01/05: Stout: Suitability of Atmel for project?
38121: 02/01/06: Jim Granville: Re: Suitability of Atmel for project?
38130: 02/01/06: Stout: Re: Suitability of Atmel for project?
38131: 02/01/07: Jim Granville: Re: Suitability of Atmel for project?
38155: 02/01/07: Stout: Re: Suitability of Atmel for project?
38162: 02/01/08: Jim Granville: Re: Suitability of Atmel for project?
38349: 02/01/11: Stout: Re: Suitability of Atmel for project?
38182: 02/01/08: Ulf Samuelsson: Re: Suitability of Atmel for project?
38187: 02/01/08: Falk Brunner: Re: Suitability of Atmel for project?
38166: 02/01/08: Marc: Re: Suitability of Atmel for project?
38126: 02/01/06: Ashok Mahadevan: Re: Suitability of Atmel for project?
38129: 02/01/06: Stout: Re: Suitability of Atmel for project?
38146: 02/01/07: Ulf Samuelsson: Re: Suitability of Atmel for project?
38127: 02/01/07: Daniel Yap: scalling ammulator problem
38128: 02/01/06: Nahum Abramovitch: 4 fpga configuration using 1 EPROM
38134: 02/01/06: Peter Alfke: Re: 4 fpga configuration using 1 EPROM
38135: 02/01/07: Przemyslaw Wegrzyn: Xilinx - Spartan, Spartan II, Virtex, Virtex II differences
38138: 02/01/07: Peter Alfke: Re: Xilinx - Spartan, Spartan II, Virtex, Virtex II differences
38147: 02/01/07: Przemyslaw Wegrzyn: Re: Xilinx - Spartan, Spartan II, Virtex, Virtex II differences
38274: 02/01/10: Jon Elson: Re: Xilinx - Spartan, Spartan II, Virtex, Virtex II differences
38275: 02/01/10: rickman: Re: Xilinx - Spartan, Spartan II, Virtex, Virtex II differences
38277: 02/01/10: Rick Filipkiewicz: Re: Xilinx - Spartan, Spartan II, Virtex, Virtex II differences
38287: 02/01/10: Peter Alfke: Re: Xilinx - Spartan, Spartan II, Virtex, Virtex II differences
38286: 02/01/10: Peter Alfke: Re: Xilinx - Spartan, Spartan II, Virtex, Virtex II differences
38136: 02/01/06: <johnt246@yahoo.com>: Celoxica DK1 and Handel C
38139: 02/01/06: llossak: WARNING
38143: 02/01/07: Utku Ozcan: Re: WARNING
38157: 02/01/07: Andy Peters: Re: WARNING
38160: 02/01/07: Brian Philofsky: Re: WARNING
38173: 02/01/07: llossak: Re: WARNING
38184: 02/01/08: Brian Philofsky: Re: WARNING
38140: 02/01/06: cortyus: WARNING
38142: 02/01/07: Utku Ozcan: Re: WARNING
38144: 02/01/06: ssy: Re: WARNING
38150: 02/01/07: newman: Re: WARNING
38145: 02/01/07: Antonio: Synplify and Xilinx clock discovery
38156: 02/01/07: Brian Philofsky: Re: Synplify and Xilinx clock discovery
38149: 02/01/07: satya: Regarding frequency achieving in fpga design
38158: 02/01/07: Falk Brunner: Re: Regarding frequency achieving in fpga design
38159: 02/01/07: Brian Philofsky: Re: Regarding frequency achieving in fpga design
38164: 02/01/08: Rick Filipkiewicz: Re: Regarding frequency achieving in fpga design
38151: 02/01/07: Michael Boehnel: Article FPGA + Reliable Systems
38152: 02/01/07: Austin Lesea: Re: Article FPGA + Reliable Systems
38165: 02/01/07: ikauranen: Re: Article FPGA + Reliable Systems
38153: 02/01/07: <dainis@safequipment.com>: PDH MUX (E2,E3) VHLD cores
38431: 02/01/14: Juan-Luis Lopez: RE: PDH MUX (E2,E3) VHLD cores
38161: 02/01/07: Kevin Neilson: FIR Linear Interpolation
38175: 02/01/08: Jonathan Bromley: Re: FIR Linear Interpolation
38163: 02/01/07: ac-ic: I2C/SPI implementation on FPGA
38167: 02/01/07: newman: Re: I2C/SPI implementation on FPGA
38168: 02/01/07: Yu Jun: 128 bit compare delay kill me!
38169: 02/01/07: Eric Smith: Re: 128 bit compare delay kill me!
38172: 02/01/08: Nicholas Weaver: Re: 128 bit compare delay kill me!
38194: 02/01/08: Ray Andraka: Re: 128 bit compare delay kill me!
38171: 02/01/08: Nicholas Weaver: Re: 128 bit compare delay kill me!
38174: 02/01/08: Aki M Suihkonen: Re: 128 bit compare delay kill me!
38186: 02/01/08: John_H: Re: 128 bit compare delay kill me!
38170: 02/01/07: dotty1319: please tell me how to solve xilinx error xml
38237: 02/01/09: Dennis McCrohan: Re: please tell me how to solve xilinx error xml
38240: 02/01/09: Rick Filipkiewicz: Re: please tell me how to solve xilinx error xml
38176: 02/01/08: Kenily: multiply (*) 11000000000
38177: 02/01/08: Nicolas Matringe: Re: multiply (*) 11000000000
38180: 02/01/08: Keith R. Williams: Re: multiply (*) 11000000000
38280: 02/01/10: Jay: Re: multiply (*) 11000000000
38300: 02/01/11: Ray Andraka: Re: multiply (*) 11000000000
38303: 02/01/11: Allan Herriman: Re: multiply (*) 11000000000
38345: 02/01/11: Ken McElvain: Re: multiply (*) 11000000000
38354: 02/01/12: Ray Andraka: Re: multiply (*) 11000000000
38178: 02/01/08: Matthias Weber: latch vs. register
38185: 02/01/08: Peter Alfke: Re: latch vs. register
38192: 02/01/08: Eric Smith: Re: latch vs. register
38196: 02/01/08: John_H: Re: latch vs. register
38204: 02/01/08: Peter Alfke: Re: latch vs. register
38206: 02/01/09: Rick Filipkiewicz: Re: latch vs. register
38209: 02/01/08: Peter Alfke: Re: latch vs. register
38215: 02/01/09: Jonathan Bromley: Re: latch vs. register
38337: 02/01/11: Martin Rice: Re: latch vs. register
38342: 02/01/11: Peter Alfke: Re: latch vs. register
38179: 02/01/08: Matthias Weber: Xilinx XC2000, XC3000, XC4000 families
38181: 02/01/08: Keith R. Williams: Re: Xilinx XC2000, XC3000, XC4000 families
38183: 02/01/08: Ian Dedic: Virtex-II parallel LVDS demo board (FAO Austin Lesea?)
38189: 02/01/08: Austin Lesea: Re: Virtex-II parallel LVDS demo board (FAO Austin Lesea?)
38188: 02/01/08: David G.: S-video -> VGA
38193: 02/01/08: Eric Smith: Re: S-video -> VGA
38210: 02/01/09: David G.: Re: S-video -> VGA
38190: 02/01/08: Brad Eckert: ROM synthesis question
38195: 02/01/08: Dr. Jeff Jackson: Re: ROM synthesis question
38201: 02/01/08: Falk Brunner: Re: ROM synthesis question
38203: 02/01/08: Ray Andraka: Re: ROM synthesis question
38214: 02/01/09: Antonio: Re: ROM synthesis question
38254: 02/01/10: Ray Andraka: Re: ROM synthesis question
38191: 02/01/08: Kevin Brace: Repost: Should clock skew be included for setup time analysis?
38199: 02/01/08: Bob Perlman: Re: Repost: Should clock skew be included for setup time analysis?
38205: 02/01/08: Peter Alfke: Re: Repost: Should clock skew be included for setup time analysis?
38230: 02/01/09: Kevin Brace: Re: Repost: Should clock skew be included for setup time analysis?
38252: 02/01/10: Bob Perlman: Re: Repost: Should clock skew be included for setup time analysis?
38253: 02/01/10: Peter Alfke: Re: Repost: Should clock skew be included for setup time analysis?
38200: 02/01/08: Falk Brunner: Re: Repost: Should clock skew be included for setup time analysis?
38202: 02/01/08: Mike Treseler: Re: Repost: Should clock skew be included for setup time analysis?
38208: 02/01/09: Allan Herriman: Re: Repost: Should clock skew be included for setup time analysis?
38207: 02/01/08: Marc Klingelhofer: Re: Repost: Should clock skew be included for setup time analysis?
38365: 02/01/12: <hamish@cloud.net.au>: Re: Repost: Should clock skew be included for setup time analysis?
38369: 02/01/12: Magnus Homann: Re: Repost: Should clock skew be included for setup time analysis?
38376: 02/01/13: <hamish@cloud.net.au>: Re: Repost: Should clock skew be included for setup time analysis?
38440: 02/01/14: Magnus Homann: Re: Repost: Should clock skew be included for setup time analysis?
38441: 02/01/14: Magnus Homann: Re: Repost: Should clock skew be included for setup time analysis?
38465: 02/01/15: <hamish@cloud.net.au>: Re: Repost: Should clock skew be included for setup time analysis?
38490: 02/01/15: Magnus Homann: Re: Repost: Should clock skew be included for setup time analysis?
38516: 02/01/16: <hamish@cloud.net.au>: Re: Repost: Should clock skew be included for setup time analysis?
38371: 02/01/12: Hal Murray: Re: Repost: Should clock skew be included for setup time analysis?
38377: 02/01/13: <hamish@cloud.net.au>: Re: Repost: Should clock skew be included for setup time analysis?
38389: 02/01/13: Rick Filipkiewicz: Re: Repost: Should clock skew be included for setup time analysis?
38394: 02/01/13: Hal Murray: Re: Repost: Should clock skew be included for setup time analysis?
38466: 02/01/15: <hamish@cloud.net.au>: Re: Repost: Should clock skew be included for setup time analysis?
38475: 02/01/15: Ray Andraka: Re: Repost: Should clock skew be included for setup time analysis?
38488: 02/01/15: Peter Alfke: Re: Repost: Should clock skew be included for setup time analysis?
38514: 02/01/16: Allan Herriman: Re: Repost: Should clock skew be included for setup time analysis?
38517: 02/01/16: <hamish@cloud.net.au>: Re: Repost: Should clock skew be included for setup time analysis?
38527: 02/01/16: Peter Alfke: Re: Repost: Should clock skew be included for setup time analysis?
38537: 02/01/16: Ray Andraka: Re: Repost: Should clock skew be included for setup time analysis?
38542: 02/01/17: Allan Herriman: Re: Repost: Should clock skew be included for setup time analysis?
38543: 02/01/17: Ray Andraka: Re: Repost: Should clock skew be included for setup time analysis?
38615: 02/01/19: Philip Freidin: Re: Should clock skew be included for setup time analysis?
38629: 02/01/19: Ray Andraka: Re: Should clock skew be included for setup time analysis?
38633: 02/01/20: <hamish@cloud.net.au>: Re: Repost: Should clock skew be included for setup time analysis?
38637: 02/01/20: Hal Murray: Re: Repost: Should clock skew be included for setup time analysis?
38758: 02/01/24: <hamish@cloud.net.au>: Re: Repost: Should clock skew be included for setup time analysis?
38510: 02/01/16: Jonathan Bromley: Re: Repost: Should clock skew be included for setup time analysis?
38515: 02/01/16: Jonathan Bromley: Re: Repost: Should clock skew be included for setup time analysis?
38197: 02/01/08: a_darabiha: Core Generator
38283: 02/01/11: Angel Pino: Re: Core Generator
38530: 02/01/16: a_darabiha: Re: Core Generator
38558: 02/01/17: #BASUKI ENDAH PRIYANTO#: Re: Core Generator
38198: 02/01/08: john: Actel Simulations
38212: 02/01/09: Anthony Ellis: ADPCM?
38224: 02/01/09: Utku Ozcan: Re: ADPCM?
38229: 02/01/09: Austin Lesea: Re: ADPCM?
38564: 02/01/17: Greg Schmid: Re: ADPCM?
38213: 02/01/09: axilon: How can I relate Virtex2 pin names and Slice XY loc?
38235: 02/01/09: Falk Brunner: Re: How can I relate Virtex2 pin names and Slice XY loc?
38239: 02/01/09: Kevin Neilson: Re: How can I relate Virtex2 pin names and Slice XY loc?
38248: 02/01/09: Bret Wade: Re: How can I relate Virtex2 pin names and Slice XY loc?
38379: 02/01/13: Kevin Neilson: Re: How can I relate Virtex2 pin names and Slice XY loc?
38422: 02/01/14: Bret Wade: Re: How can I relate Virtex2 pin names and Slice XY loc?
38401: 02/01/13: Assaf Sarfati: Re: How can I relate Virtex2 pin names and Slice XY loc?
38216: 02/01/09: Matthias Weber: distributed ram bits in XCVxxxx series
38228: 02/01/09: Peter Alfke: Re: distributed ram bits in XCVxxxx series
38255: 02/01/10: Ray Andraka: Re: distributed ram bits in XCVxxxx series
38217: 02/01/09: Matthias Weber: function generators of Xilinx XCVxxxxE series
38238: 02/01/09: John_H: Re: function generators of Xilinx XCVxxxxE series
38218: 02/01/09: k.: bufg instantiation in ISE 4.1
38220: 02/01/09: Allan Herriman: Re: bufg instantiation in ISE 4.1
38260: 02/01/10: k.: Re: bufg instantiation in ISE 4.1
38233: 02/01/09: Andy Peters: Re: bufg instantiation in ISE 4.1
38256: 02/01/10: Ray Andraka: Re: bufg instantiation in ISE 4.1
38257: 02/01/10: Ray Andraka: Re: bufg instantiation in ISE 4.1
38259: 02/01/10: k.: Re: bufg instantiation in ISE 4.1
38361: 02/01/12: <hamish@cloud.net.au>: Re: bufg instantiation in ISE 4.1
38219: 02/01/09: satya: Xilinx XC2000, XC3000, XC4000 families
38223: 02/01/09: Keith R. Williams: Re: Xilinx XC2000, XC3000, XC4000 families
38221: 02/01/09: Richard Padovan: Interpreting Xilinx Timing Analyser report files
38232: 02/01/09: Brian Philofsky: Re: Interpreting Xilinx Timing Analyser report files
38279: 02/01/10: Jay: Re: Interpreting Xilinx Timing Analyser report files
38222: 02/01/09: Hua Wang: comp.arch.fpga : Problem with modelsim and ISE4.1
38234: 02/01/09: Brian Philofsky: Re: comp.arch.fpga : Problem with modelsim and ISE4.1
38242: 02/01/09: Rick Filipkiewicz: Re: comp.arch.fpga : Problem with modelsim and ISE4.1
38258: 02/01/10: Ray Andraka: Re: comp.arch.fpga : Problem with modelsim and ISE4.1
38225: 02/01/09: Markus Meng: Triscend ARM+FPGA chips Experience
38226: 02/01/09: Victor Levandovsky: Where can I download Maxlock`s PCI core (It`s freecore, but I can`t download this from their WWW). Can anyone sent me this by email ?
38249: 02/01/10: Philip Cummins: Re: Where can I download Maxlock`s PCI core (It`s freecore, but I can`t download this from their WWW). Can anyone sent me this by email ?
38227: 02/01/09: Gacquer William: FPGA and CCD : any experience?
38231: 02/01/09: Jonathan Bromley: Re: FPGA and CCD : any experience?
38245: 02/01/09: Gacquer William: Re: FPGA and CCD : any experience?
38261: 02/01/10: Jonathan Bromley: Re: FPGA and CCD : any experience?
38250: 02/01/09: ikauranen: Re: FPGA and CCD : any experience?
38278: 02/01/10: Jay: Re: FPGA and CCD : any experience?
38309: 02/01/11: M.B.: Re: FPGA and CCD : any experience?
38495: 02/01/15: Jay: Re: FPGA and CCD : any experience?
38241: 02/01/09: rickman: Spartan IIE pinout compatibililty with Virtex E
38243: 02/01/09: Rick Filipkiewicz: Re: Spartan IIE pinout compatibililty with Virtex E
38244: 02/01/09: rickman: Re: Spartan IIE pinout compatibililty with Virtex E
38246: 02/01/09: Han, MT: Where to buy Altera APEX20K with reasonable price?
38247: 02/01/09: Alex Rast: Error -10010 during Digital Buffer Control
38251: 02/01/09: dotty1319: xilinx service pack error
38262: 02/01/10: Santiago de Pablo: [WebPACK or ISE] Mixing Verilog and EDIF?
38358: 02/01/12: <hamish@cloud.net.au>: Re: [WebPACK or ISE] Mixing Verilog and EDIF?
38263: 02/01/10: ssy: Q:Hand placed fast 32 bit barrel shifter for APEX?
38301: 02/01/11: Ray Andraka: Re: Q:Hand placed fast 32 bit barrel shifter for APEX?
38306: 02/01/11: ssy: Re: Q:Hand placed fast 32 bit barrel shifter for APEX?
38328: 02/01/11: Ray Andraka: Re: Q:Hand placed fast 32 bit barrel shifter for APEX?
38351: 02/01/11: ssy: Re: Q:Hand placed fast 32 bit barrel shifter for APEX?
38355: 02/01/12: Ray Andraka: Re: Q:Hand placed fast 32 bit barrel shifter for APEX?
38264: 02/01/10: Matthias Scheerer: XST in ISE Alliance 4.1 for Solaris
38267: 02/01/10: Matthias Scheerer: Re: XST in ISE Alliance 4.1 for Solaris
38265: 02/01/10: Herrera, Alfredo [CAR:5T12:EXCH]: coregen in Alliance ISE v4.1i
38268: 02/01/10: Stephan Flock: Re: FPGA Synthesis and implementation
38269: 02/01/10: Ray Andraka: Re: FPGA Synthesis and implementation
38271: 02/01/10: Ray Andraka: Re: FPGA Synthesis and implementation
38329: 02/01/11: H.L: Re: FPGA Synthesis and implementation
38297: 02/01/10: H.L: Re: FPGA Synthesis and implementation
38270: 02/01/10: Matthias Dyer: Avoid routing through a certain area (Xilinx)
38272: 02/01/10: rickman: Re: Avoid routing through a certain area (Xilinx)
38315: 02/01/11: Phil James-Roxby: Re: Avoid routing through a certain area (Xilinx)
38321: 02/01/11: rickman: Re: Avoid routing through a certain area (Xilinx)
38359: 02/01/12: <hamish@cloud.net.au>: Re: Avoid routing through a certain area (Xilinx)
38413: 02/01/14: Christian Plessl: Re: Avoid routing through a certain area (Xilinx)
38430: 02/01/14: Phil James-Roxby: Re: Avoid routing through a certain area (Xilinx)
38281: 02/01/10: Bret Wade: Re: Avoid routing through a certain area (Xilinx)
38307: 02/01/11: Christian Plessl: Re: Avoid routing through a certain area (Xilinx)
38308: 02/01/11: Tim: Re: Avoid routing through a certain area (Xilinx)
38320: 02/01/11: Bret Wade: Re: Avoid routing through a certain area (Xilinx)
38322: 02/01/11: rickman: Re: Avoid routing through a certain area (Xilinx)
38327: 02/01/11: Bret Wade: Re: Avoid routing through a certain area (Xilinx)
38338: 02/01/11: Bret Wade: Re: Avoid routing through a certain area (Xilinx)
38282: 02/01/11: Angel Pino: EXPAL language ?
38296: 02/01/11: Jim Granville: Re: EXPAL language ?
38318: 02/01/11: Angel Pino: Re: EXPAL language ?
38284: 02/01/10: BM: Xilinx High speed I/O
38312: 02/01/11: Austin Lesea: Re: Xilinx High speed I/O
38319: 02/01/11: Falk Brunner: Re: Xilinx High speed I/O
38285: 02/01/10: H.L: FPGA Synthesis and implementation
38305: 02/01/11: Michael Boehnel: Runtime reconfiguration internals
38323: 02/01/11: Philip Freidin: Re: Runtime reconfiguration internals
38410: 02/01/14: Alex Carreira: Re: Runtime reconfiguration internals
38414: 02/01/14: Michael Boehnel: Re: Runtime reconfiguration internals
38311: 02/01/11: Dan Benson: Help with Older Programmer
38313: 02/01/11: Eric Lukac-Kuruc: Actel Libero for ProAsic in big trouble?
38317: 02/01/11: Timothy R. Sloper: Re: Actel Libero for ProAsic in big trouble?
38324: 02/01/11: rickman: Picking an FPGA
38330: 02/01/11: Austin Lesea: Re: Picking an FPGA
38341: 02/01/11: rickman: Re: Picking an FPGA
38331: 02/01/11: Ray Andraka: Re: Picking an FPGA
38339: 02/01/11: rickman: Re: Picking an FPGA
38352: 02/01/12: Ray Andraka: Re: Picking an FPGA
38380: 02/01/13: rickman: Re: Picking an FPGA
38340: 02/01/11: guy: Re: Picking an FPGA
38353: 02/01/12: Ray Andraka: Re: Picking an FPGA
38364: 02/01/12: rickman: Re: Picking an FPGA
38325: 02/01/11: Steve Holroyd: APEX-II vs VIRTEX-II
38332: 02/01/11: Ray Andraka: Re: APEX-II vs VIRTEX-II
38587: 02/01/18: Steve Holroyd: Re: APEX-II vs VIRTEX-II
38656: 02/01/20: rickman: Re: APEX-II vs VIRTEX-II
39132: 02/02/01: Magnus Homann: Re: APEX-II vs VIRTEX-II
38593: 02/01/18: Mike Treseler: Re: APEX-II vs VIRTEX-II
38740: 02/01/23: Jay: Re: APEX-II vs VIRTEX-II
39181: 02/02/03: Guy Schlacter: Re: APEX-II vs VIRTEX-II
39190: 02/02/04: Russell Shaw: Re: APEX-II vs VIRTEX-II
39720: 02/02/17: rickman: Re: APEX-II vs VIRTEX-II
40084: 02/02/26: Steve Holroyd: Re: APEX-II vs VIRTEX-II
40115: 02/02/27: Austin Lesea: Re: APEX-II vs VIRTEX-II
40165: 02/02/28: Girl: Re: APEX-II vs VIRTEX-II
40167: 02/03/01: Russell Shaw: QuartusII (was Re: APEX-II vs VIRTEX-II)
38326: 02/01/11: Kevin Brace: How to constrain the inputs of a multi-level parity generator and
38335: 02/01/11: Ray Andraka: Re: How to constrain the inputs of a multi-level parity generator and
38444: 02/01/14: Kevin Brace: Re: How to constrain the inputs of a multi-level parity generator and
38333: 02/01/11: Bryan: Xilinx PAR and Editor speed up
38334: 02/01/11: Bryan: Re: Xilinx PAR and Editor speed up
38344: 02/01/11: Duane Clark: Re: Xilinx PAR and Editor speed up
38421: 02/01/14: Bryan: Re: Xilinx PAR and Editor speed up
38426: 02/01/14: Duane Clark: Re: Xilinx PAR and Editor speed up
38363: 02/01/12: Petter Gustad: Re: Xilinx PAR and Editor speed up
38418: 02/01/14: Chandrakiran: Re: Xilinx PAR and Editor speed up
38423: 02/01/14: Bret Wade: Re: Xilinx PAR and Editor speed up
38343: 02/01/11: chris: speech recognition - active noise cancellation
38346: 02/01/12: Kevin Neilson: Re: speech recognition - active noise cancellation
38347: 02/01/11: Jerry Avins: Re: speech recognition - active noise cancellation
38357: 02/01/12: Leon Heller: Re: speech recognition - active noise cancellation
38367: 02/01/12: Jerry Avins: Re: speech recognition - active noise cancellation
38372: 02/01/12: Ray Andraka: Re: speech recognition - active noise cancellation
38373: 02/01/13: Leon Heller: Re: speech recognition - active noise cancellation
38378: 02/01/13: Kevin Neilson: Re: speech recognition - active noise cancellation
38392: 02/01/13: Ray Andraka: Re: speech recognition - active noise cancellation
38434: 02/01/14: Chip Wood: Re: speech recognition - active noise cancellation
38433: 02/01/14: Chip Wood: Re: speech recognition - active noise cancellation
38350: 02/01/12: Ray Andraka: Re: speech recognition - active noise cancellation
38368: 02/01/12: david garnett: Re: speech recognition - active noise cancellation
38405: 02/01/14: Raman Arora: Re: speech recognition - active noise cancellation
38356: 02/01/11: Balakrishnan: FPGA : Configurtion
38366: 02/01/12: C.Schlehaus: Re: FPGA : Configurtion
38360: 02/01/11: balakrishnan: FPGA configuration
38381: 02/01/13: rickman: Re: FPGA configuration
38388: 02/01/13: z.karim: Re: FPGA configuration
38398: 02/01/13: rickman: Re: FPGA configuration
38370: 02/01/12: Adam Elbirt: Quick question regarding IEEE-TVLSI and IEEE-Computer
38374: 02/01/12: llossak: modelsim
38390: 02/01/13: Rick Filipkiewicz: Re: modelsim
38375: 02/01/12: ssy: the timng of the lpm_fifo
38382: 02/01/13: rickman: Re: MSP430 + Xilinx via JTAG
38400: 02/01/13: DG_1: Re: MSP430 + Xilinx via JTAG
38403: 02/01/14: rickman: Re: MSP430 + Xilinx via JTAG
38451: 02/01/15: DG_1: Re: MSP430 + Xilinx via JTAG
38852: 02/01/26: DG_1: Re: MSP430 + Xilinx via JTAG
38874: 02/01/27: rickman: Re: MSP430 + Xilinx via JTAG
39046: 02/01/30: Elizabeth D. Rather: Re: MSP430 + Xilinx via JTAG
39130: 02/02/01: rickman: Re: MSP430 + Xilinx via JTAG
39182: 02/02/03: rickman: Re: MSP430 + Xilinx via JTAG
39282: 02/02/05: Elizabeth D. Rather: Re: MSP430 + Xilinx via JTAG
38847: 02/01/26: rickman: Re: MSP430 + Xilinx via JTAG
38420: 02/01/14: Damir Danijel Zagar: Re: MSP430 + Xilinx via JTAG
38449: 02/01/15: DG_1: Re: MSP430 + Xilinx via JTAG
38477: 02/01/15: Geir Atle Ward: Re: MSP430 + Xilinx via JTAG
38552: 02/01/17: Damir Danijel Zagar: Re: MSP430 + Xilinx via JTAG
38856: 02/01/26: Matti Ruusunen: Re: MSP430 + Xilinx via JTAG
38872: 02/01/27: rickman: Re: MSP430 + Xilinx via JTAG
38881: 02/01/27: Matti Ruusunen: Re: MSP430 + Xilinx via JTAG
38383: 02/01/13: TonyS2: FS xilinx 963//Data I/O 2900 Programmers
38384: 02/01/13: David Findlay: Homebrew computers using FPGA?
38385: 02/01/13: Falk Brunner: Re: Homebrew computers using FPGA?
38396: 02/01/13: Jan Gray: Re: Homebrew computers using FPGA?
38386: 02/01/13: cn99: Re: Homebrew computers using FPGA?
38391: 02/01/13: Ray Andraka: Re: Homebrew computers using FPGA?
38399: 02/01/13: David Findlay: Re: Homebrew computers using FPGA?
38402: 02/01/14: Peter Ormsby: Re: Homebrew computers using FPGA?
38416: 02/01/14: David Findlay: Re: Homebrew computers using FPGA?
38854: 02/01/26: Franck Pissotte: Re: Homebrew computers using FPGA?
38954: 02/01/28: Eric Smith: Re: Homebrew computers using FPGA?
38393: 02/01/13: Duane Clark: Re: Homebrew computers using FPGA?
38461: 02/01/15: Herbert Kleebauer: Re: Homebrew computers using FPGA?
38395: 02/01/13: Peter Ormsby: Re: Homebrew computers using FPGA?
38437: 02/01/14: Andy Ray: Re: Homebrew computers using FPGA?
38397: 02/01/14: Jim Granville: Re: Homebrew computers using FPGA?
38855: 02/01/26: Franck Pissotte: Re: Homebrew computers using FPGA?
38900: 02/01/28: Rob Finch: Re: Homebrew computers using FPGA?
38404: 02/01/14: Antonio: CLKDLL cascade questions
38428: 02/01/14: Falk Brunner: Re: CLKDLL cascade questions
38463: 02/01/15: <hamish@cloud.net.au>: Re: CLKDLL cascade questions
38472: 02/01/15: Austin Lesea: Re: CLKDLL cascade questions
38446: 02/01/15: Peter Alfke: Re: CLKDLL cascade questions
38406: 02/01/14: Antonio: .sdf question
38409: 02/01/14: Ansgar Bambynek: Re: .sdf question
38455: 02/01/15: Rick Filipkiewicz: Re: .sdf question
38407: 02/01/14: balakrishnan: SPARTAN-XL CONFIGURTAION
38573: 02/01/17: Yury: Re: SPARTAN-XL CONFIGURTAION
38408: 02/01/14: grohss: variable declare
38439: 02/01/14: Andy Ray: Re: variable declare
38500: 02/01/15: Jay: Re: variable declare
38411: 02/01/14: Martin Fischer: Falling edge in PLD
38427: 02/01/14: Falk Brunner: Re: Falling edge in PLD
38450: 02/01/15: David Miller: Re: Falling edge in PLD
38456: 02/01/15: Rick Filipkiewicz: Re: Falling edge in PLD
38464: 02/01/15: <hamish@cloud.net.au>: Re: Falling edge in PLD
38452: 02/01/15: Thomas Stanka: Re: Falling edge in PLD
38459: 02/01/15: Martin Fischer: Re: Falling edge in PLD
38479: 02/01/15: Falk Brunner: Re: Falling edge in PLD
38412: 02/01/14: Philippe Robert: Hard macro for Xilinx FPGA
38481: 02/01/15: Bret Wade: Re: Hard macro for Xilinx FPGA
38417: 02/01/14: Antonio: Some Aldec Questions
38419: 02/01/14: Philippe Robert: test
38424: 02/01/14: Steven Menk: Synthesis: Protel 99SE to XC2S200
38505: 02/01/16: z.karim: Re: Synthesis: Protel 99SE to XC2S200
38519: 02/01/16: <hamish@cloud.net.au>: Re: Synthesis: Protel 99SE to XC2S200
38425: 02/01/14: Rodolfo Jardim de Azevedo: Leonardo + Xilinx tools help
38436: 02/01/14: Mike Treseler: Re: Leonardo + Xilinx tools help
38489: 02/01/15: Rodolfo Jardim de Azevedo: Re: Leonardo + Xilinx tools help
38492: 02/01/15: Mike Treseler: Re: Leonardo + Xilinx tools help
38520: 02/01/16: Rodolfo Jardim de Azevedo: Re: Leonardo + Xilinx tools help
38524: 02/01/16: Mike Treseler: Re: Leonardo + Xilinx tools help
38525: 02/01/16: Mike Treseler: Re: Leonardo + Xilinx tools help
38538: 02/01/16: Ray Andraka: Re: Leonardo + Xilinx tools help
38553: 02/01/17: Rodolfo Jardim de Azevedo: Re: Leonardo + Xilinx tools help
38566: 02/01/17: Mike Treseler: Re: Leonardo + Xilinx tools help
38560: 02/01/17: newman: Re: Leonardo + Xilinx tools help
38442: 02/01/14: Tom Dillon: Re: Leonardo + Xilinx tools help
38491: 02/01/15: Rodolfo Jardim de Azevedo: Re: Leonardo + Xilinx tools help
38509: 02/01/16: Nicolas Matringe: Re: Leonardo + Xilinx tools help
38518: 02/01/16: Rodolfo Jardim de Azevedo: Re: Leonardo + Xilinx tools help
38521: 02/01/16: Nicolas Matringe: Re: Leonardo + Xilinx tools help
38429: 02/01/14: Falk Brunner: Radiation Resistance
38432: 02/01/14: Austin Lesea: Re: Radiation Resistance
38484: 02/01/15: Falk Brunner: Re: Radiation Resistance
38435: 02/01/14: H.L: Synthesis in FPGA Express
38504: 02/01/16: z.karim: Re: Synthesis in FPGA Express
38511: 02/01/16: H.L: Re: Synthesis in FPGA Express
38523: 02/01/16: Jay: Re: Synthesis in FPGA Express
38438: 02/01/14: Seb: Insight eval board: i/o problem
38443: 02/01/14: Angel Pino: PAL Express Language
38445: 02/01/14: kossyma: how do i implement it?
38457: 02/01/15: Rick Filipkiewicz: Re: how do i implement it?
38447: 02/01/15: ÀÌÃá¿ë: SDH Pointer generator and Pointer interpreter
38480: 02/01/15: Falk Brunner: Re: SDH Pointer generator and Pointer interpreter
38448: 02/01/14: strut911: SYN_HIER attribute in synplify v7.0
38499: 02/01/15: Jay: Re: SYN_HIER attribute in synplify v7.0
38453: 02/01/15: kossyma: remainder
38471: 02/01/15: luigi funes: Re: remainder
38503: 02/01/16: z.karim: Re: remainder
38498: 02/01/15: Jay: Re: remainder
38454: 02/01/15: Madhura Bokil: FPGA : VHDL netlist for simulation
38502: 02/01/16: z.karim: Re: FPGA : VHDL netlist for simulation
38458: 02/01/15: Rick Filipkiewicz: Synplify and CoolRunner - Help
38460: 02/01/15: Rick Filipkiewicz: Re: Synplify and CoolRunner - Help
38462: 02/01/15: Andreas Kugel: Virtex-2 Frequency Synhtesis
38473: 02/01/15: Austin Lesea: Re: Virtex-2 Frequency Synhtesis
38482: 02/01/15: Rick Filipkiewicz: Re: Virtex-2 Frequency Synhtesis
38486: 02/01/15: Austin Lesea: Re: Virtex-2 Frequency Synhtesis
38540: 02/01/17: Rick Filipkiewicz: Re: Virtex-2 Frequency Synhtesis
38541: 02/01/16: Austin Lesea: Re: Virtex-2 Frequency Synhtesis
38467: 02/01/15: Bernd Scheuermann: RS232 on Atmel ATSTK40 board
38470: 02/01/15: Jan Pech: Re: RS232 on Atmel ATSTK40 board
38476: 02/01/15: Bernd Scheuermann: Re: RS232 on Atmel ATSTK40 board
38483: 02/01/15: Dave Vanden Bout: Re: RS232 on Atmel ATSTK40 board
38468: 02/01/15: Petter Gustad: Xilinx XC4003A-6, docs and tools?
38469: 02/01/15: Russell Tessier: FPGA'2002: Early Registration Deadline
38474: 02/01/15: Richard Auletta: ASIC 2002 Call For Papers
38550: 02/01/17: Paulo Valentim: Re: ASIC 2002 Call For Papers
38478: 02/01/16: Daniel Yap: Altera Compiling Error..WHY?????
38487: 02/01/15: Alan Nishioka: Re: Altera Compiling Error..WHY?????
38493: 02/01/15: Mike Treseler: Re: Altera Compiling Error..WHY?????
38496: 02/01/15: Jay: Re: Altera Compiling Error..WHY?????
38497: 02/01/15: Guy Schlacter: Re: Altera Compiling Error..WHY?????
38485: 02/01/15: Annette Van Benthum: Flexbus and Altera
38494: 02/01/15: David Rogoff: path for Vital component in assert?
38934: 02/01/28: Brian Philofsky: Re: path for Vital component in assert?
38506: 02/01/15: Antonio: A strange Xilinx 4.1 parser error
38507: 02/01/15: Antonio: Xilinx 4.1 Implementation report questions
38590: 02/01/18: Brian Philofsky: Re: Xilinx 4.1 Implementation report questions
38508: 02/01/15: Antonio: Xilinx Timing report question
38743: 02/01/23: Jay: Re: Xilinx Timing report question
38512: 02/01/16: Christian Lehmann: info about NIOS softcore processor
38513: 02/01/16: Wolfgang Loewer: Re: info about NIOS softcore processor
38522: 02/01/16: Simon Fisher: Audio time delay circuit
38526: 02/01/16: Peter Alfke: Re: Audio time delay circuit
38528: 02/01/16: Falk Brunner: Re: Audio time delay circuit
38531: 02/01/16: Leon Heller: Re: Audio time delay circuit
38563: 02/01/17: Kevin Neilson: Re: Audio time delay circuit
38565: 02/01/17: Leon Heller: Re: Audio time delay circuit
38568: 02/01/17: Eric Smith: Re: Audio time delay circuit
38569: 02/01/17: Peter Alfke: Re: Audio time delay circuit
38571: 02/01/17: Eric Smith: Re: Audio time delay circuit
38574: 02/01/18: Peter Alfke: Re: Audio time delay circuit
38578: 02/01/18: Simon Fisher: Re: Audio time delay circuit
38592: 02/01/18: Kevin Neilson: Re: Audio time delay circuit
38595: 02/01/18: Falk Brunner: Re: Audio time delay circuit
38634: 02/01/19: tony: Re: Audio time delay circuit
38598: 02/01/18: Ray Andraka: Re: Audio time delay circuit
38600: 02/01/18: Georg Acher: Re: Audio time delay circuit
38603: 02/01/19: Jim Granville: Re: Audio time delay circuit
38627: 02/01/19: Ray Andraka: Re: Audio time delay circuit
38625: 02/01/19: Ray Andraka: Re: Audio time delay circuit
38779: 02/01/25: Andy Peters: Re: Audio time delay circuit
38781: 02/01/25: Ray Andraka: Re: Audio time delay circuit
38782: 02/01/24: Peter Alfke: Re: Audio time delay circuit
38529: 02/01/16: Andrew Ha: I2C multiplexer
38606: 02/01/18: Randy Bolling: Re: I2C multiplexer
38613: 02/01/19: AH: Re: I2C multiplexer
38739: 02/01/23: Carl Brannen: Re: I2C multiplexer
38532: 02/01/16: a_darabiha: Image Processing on FPGAs. Dose System Generator help??
38567: 02/01/17: Ray Andraka: Re: Image Processing on FPGAs. Dose System Generator help??
38707: 02/01/22: Niall Battson: Re: Image Processing on FPGAs. Dose System Generator help??
38533: 02/01/16: a_darabiha: SysGen on PC / Unix ?
38534: 02/01/16: Amit Thakar: Signal processing using FPGAs
38535: 02/01/16: Austin Lesea: Re: Signal processing using FPGAs
38536: 02/01/16: Ray Andraka: Re: Signal processing using FPGAs
38561: 02/01/17: Falk Brunner: Re: Signal processing using FPGAs
38661: 02/01/21: Ron Huizen: Re: Signal processing using FPGAs
38669: 02/01/21: Ray Andraka: Re: Signal processing using FPGAs
38539: 02/01/16: Amit Thakar: Re: Signal processing using FPGAs
38556: 02/01/17: Austin Lesea: Re: Signal processing using FPGAs
38544: 02/01/17: Steve Underwood: Re: Signal processing using FPGAs
38546: 02/01/17: Bert Cuzeau: Re: Signal processing using FPGAs
38570: 02/01/18: #BASUKI ENDAH PRIYANTO#: RE: Signal processing using FPGAs
38668: 02/01/21: glen herrmannsfeldt: Re: Signal processing using FPGAs
38675: 02/01/21: Peter Alfke: Re: Signal processing using FPGAs
38680: 02/01/21: Eric Smith: Re: Signal processing using FPGAs
38681: 02/01/21: Peter Alfke: Re: Signal processing using FPGAs
38700: 02/01/22: John_H: Re: Signal processing using FPGAs
38683: 02/01/22: Ray Andraka: Re: Signal processing using FPGAs
38545: 02/01/17: David A Hand: How to set PROM package in ISE 4.1 ?
38547: 02/01/17: Christian Plessl: Virtex2 ICAP
38557: 02/01/17: Austin Lesea: Re: Virtex2 ICAP
38559: 02/01/17: Christian Plessl: Re: Virtex2 ICAP
38549: 02/01/17: hoothsb: how should i change it?
38551: 02/01/17: adrian: Too many errors
38555: 02/01/17: Brad Eckert: CoreGen question
38562: 02/01/17: Speedy Zero Two: Re: CoreGen question
38591: 02/01/18: Brad Eckert: Re: CoreGen question
38596: 02/01/18: Falk Brunner: Re: CoreGen question
38572: 02/01/17: Yury: Coregen Half-Band FIR filter implemenation does not work
38582: 02/01/18: newman: Re: Coregen Half-Band FIR filter implemenation does not work
38597: 02/01/18: Yury: Re: Coregen Half-Band FIR filter implemenation does not work
39757: 02/02/19: Chris Dick: Re: Coregen Half-Band FIR filter implemenation does not work
39791: 02/02/19: newman: Re: Coregen Half-Band FIR filter implemenation does not work
39796: 02/02/19: Clark Pope: Re: Coregen Half-Band FIR filter implemenation does not work
38780: 02/01/25: Andy Peters: Re: Coregen Half-Band FIR filter implemenation does not work
38815: 02/01/25: Clark Pope: Re: Coregen Half-Band FIR filter implemenation does not work
38850: 02/01/26: Yury: Re: Coregen Half-Band FIR filter implemenation does not work
38818: 02/01/25: Yury: Re: Coregen Half-Band FIR filter implemenation does not work
38870: 02/01/26: newman: Re: Coregen Half-Band FIR filter implemenation does not work
38876: 02/01/27: Rick Filipkiewicz: Re: Coregen Half-Band FIR filter implemenation does not work
39085: 02/01/31: <news@rtrussell.co.uk>: Re: Coregen Half-Band FIR filter implemenation does not work
38575: 02/01/17: chandrakiran Verma: Floorplanning :Problem in floorplanning
38576: 02/01/17: dotty1319: service pack8 can't use
38577: 02/01/18: H.L: Re: service pack8 can't use
38602: 02/01/18: rs: Re: service pack8 can't use
38579: 02/01/18: Benn: verilog/vhdl codeing style
38583: 02/01/18: Pallek, Andrew [CAR:CN34:EXCH]: Re: verilog/vhdl codeing style
38621: 02/01/19: VhdlCohen: Re: verilog/vhdl codeing style
38580: 02/01/18: Juergen Buehler: DDR-Interface
38581: 02/01/18: Paul Baxter: Re: DDR-Interface
38588: 02/01/18: Juergen Buehler: Re: DDR-Interface
38584: 02/01/18: Roberta Crescentini: Re: DDR-Interface
38586: 02/01/18: Austin Lesea: Re: DDR-Interface
38663: 02/01/21: Edward Moore: Re: DDR-Interface
40460: 02/03/07: Manfred Kraus: Re: DDR-Interface
38585: 02/01/18: Paul: Quartus 2 and bus ripping
38658: 02/01/21: Paul: Re: Quartus 2 and bus ripping
38666: 02/01/21: Mike Treseler: Re: Quartus 2 and bus ripping
38671: 02/01/21: Paul: Re: Quartus 2 and bus ripping
38678: 02/01/21: Steen Larsen: Re: Quartus 2 and bus ripping
38688: 02/01/22: Paul: Re: Quartus 2 and bus ripping
38733: 02/01/23: Paul: Re: Quartus 2 and bus ripping
38962: 02/01/28: Steen Larsen: Re: Quartus 2 and bus ripping
38972: 02/01/29: Paul: Re: Quartus 2 and bus ripping
38589: 02/01/18: Steve Holroyd: Fast LVDS Backplanes
38594: 02/01/19: Daniel Yap: why Altera LPM_ROM can't drive out value?
38601: 02/01/18: rs: VirtexII ES configuration
38604: 02/01/18: Austin Lesea: Re: VirtexII ES configuration
38619: 02/01/19: rs: Re: VirtexII ES configuration
38605: 02/01/18: Randy Bolling: Re: VirtexII ES configuration
38607: 02/01/18: Kevin Goodsell: Simple shift register not working
38610: 02/01/18: Brian Philofsky: Re: Simple shift register not working
38639: 02/01/20: Kevin Goodsell: Re: Simple shift register not working
38628: 02/01/19: Ray Andraka: Re: Simple shift register not working
38638: 02/01/20: Kevin Goodsell: Re: Simple shift register not working
38742: 02/01/23: Jay: Re: Simple shift register not working
38748: 02/01/23: spyng: Re: Simple shift register not working
38849: 02/01/26: Kevin Goodsell: Re: Simple shift register not working (update)
38889: 02/01/27: newman: Re: Simple shift register not working (update)
38931: 02/01/28: Kevin Goodsell: Re: Simple shift register not working (update)
38932: 02/01/28: Peter Alfke: Re: Simple shift register not working (update)
38935: 02/01/28: Ray Andraka: Re: Simple shift register not working (update)
38936: 02/01/28: Bob Perlman: Re: Simple shift register not working (update)
38940: 02/01/28: Kevin Goodsell: Re: Simple shift register not working (update)
38965: 02/01/28: newman: Re: Simple shift register not working (update)