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Messages from 39250

Article: 39250
Subject: Re: solutions manuals, and no they are not for school
From: Bob Cain <arcane@znet.com>
Date: Mon, 04 Feb 2002 22:20:06 -0800
Links: << >>  << T >>  << A >>


Steve wrote:
> 
> If he's legit then fair enough but you have to be a bit suspect about
> people asking for solutions manuals on a NG. After what I saw on a
> course last year nothing would surprise me about what students will do
> to get out of work. He may sound legit but you'd expect him to attempt
> to sound honest.

I just wish there was some bonded credential I could get that stated
"Bob Cain is not a student nor is he assisting one."  :-)


Bob
-- 

"Things should be described as simply as possible, but no simpler."

                                             A. Einstein


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 To contribute your unused processor cycles to the fight against cancer:

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Article: 39251
Subject: Re: MUX seelction question
From: dottavio@ised.it (Antonio)
Date: 4 Feb 2002 23:35:59 -0800
Links: << >>  << T >>  << A >>
newman5382@aol.com (newman) wrote in message news:<e6038423.0202040515.78a04fa4@posting.google.com>...
> >> architecture demux_3x10_arch of demux_3x10 is
> >> begin				  
> >> 	process (sel, in_mux, clk)
> >> 	begin
> >> 		if falling_edge(clk) then		 
>  
> > in_mux and sel should not be in the sensitivity list, as your
> > process is not sensitive to them (only to the clock).
> >
>  ...
> >
> > Hamish
> 
> In a previous thread, someone posted the previous information. 
> Apparently you have decided to ignore the comment.
> 
> Newman


No Newman, it is that this information is delivered from any
synthesizer, so I don't look at it like the real problem in any case
what I've understood from this post is :
1) clk or not clk is the same
2) registered input or output are project dependant
3) do not put unused signal on process sensitivity list

Article: 39252
Subject: Re: Xilinx synthesis tools
From: thomas.stanka@tesat.de (Thomas Stanka)
Date: 5 Feb 2002 08:49:52 GMT
Links: << >>  << T >>  << A >>
Hi all,

Arvin Patel <apatel@chello.no> wrote:

> Does anyone have any experience with the latest version of
> Xilinx XST? I would be interested in any comments on stability
> of the tool and of the quality of results.

Interessting point. We do the same test (as all abround the world I guess) 
since  FE-lizence is no longer included in Xilinx. I will post, wehn we 
have results.
 
> Does anyone have any comparisons of XST and Synopsys FPGA Express?
> I have made some tests and it seems that XST gives slightly
> better timing results than FPGA Express.

Do you mean after PAR your bitfile is faster, or is it just, that you get 
better timing values after synthesis which results in equivalent results 
after PAR?

bye Thomas

-- 
Thomas Stanka TE/EMD4
Space Communications Systems
Tesat Spacecom GmbH & Co KG
thomas.stanka@tesat.de

Article: 39253
Subject: Core generator Asynchronous FIFO
From: jaiphen_interqos@yahoo.com.hk (starpanda)
Date: 5 Feb 2002 01:17:44 -0800
Links: << >>  << T >>  << A >>
I use core generator to generate a Asynchronous FIFO. I wrote a
testbench and used project navigator to do some simulation.  The
behavioral simulation went through without any problem. After that
simulation with post-translate model doesn't give me any output. The
post-mapping model gave me an error when modelsim is loading the
model. The error is as follow:
# ** Fatal: asyn_fifo_tb.tf(20): Too many port connections.
#    Time: 0 ps  Iteration: 0  Region: /testbench/test_fifo
# FATAL ERROR while loading design
# Error loading design
# Error: Error loading design 
#        Pausing macro execution 
# MACRO ./asyn_fifo_tb.mdo PAUSED at line 9
 
Is there anyone know what is going wrong?

Thanks!

Starpanda

Article: 39254
Subject: Re: Coregen & PAR
From: hamish@cloud.net.au
Date: 05 Feb 2002 10:18:59 GMT
Links: << >>  << T >>  << A >>
niv <niv@ntlworld.com> wrote:
> "B" model revisions to "A" model design.
> RTL sims OK.
> PAR and post PAR FAILS.

In what way does it fail?

Is it a timing failure? The block RAM clock-to-out time changed
significantly around that version (eg from 1.1 to 2.4 ns in the -8 part).

> Is 3.3i a load of rubbish?, the BLKRAM coregen GUI in 3.3 is very different: I can't select either pos. or neg. clk edge as per 3.1, (clka is -ve edge in my design).  Is this the cause of the prob.

I don't use it so I can't comment. I always instantiate things
like BRAMs directly.


Hamish
-- 
Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>

Article: 39255
Subject: Re: RAM question
From: hamish@cloud.net.au
Date: 05 Feb 2002 10:34:44 GMT
Links: << >>  << T >>  << A >>
Peter Alfke <peter.alfke@xilinx.com> wrote:
> Sorry, Ray, but I just looked at the data sheet on the web:
> Virtex-E BlockRAM set-up times for address and data are 1.1 ns for -6, the slowest
> speed grade, ( yes, Enable and WE are longer, 2.5 and 2.0 ns respectively)
> For the fastest speed grade the numbers are 0.9 ns, 2.0 ns and 1.7 ns respectively.

Actually the latest speed files for V2000E-8 say Tbeck is 1.928 ns
and Tbwck is 1.697 ns. Tell me about it, I'm rerouting some old
designs now and the longer delays (compared to older speed files)
is hurting.

That's v1.65 on 4.1i SP3.

cheers,
Hamish
-- 
Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>

Article: 39256
Subject: Re: Destroying a CPLD by JTAG
From: k_mc_a@yahoo.co.uk (k.)
Date: 5 Feb 2002 02:47:59 -0800
Links: << >>  << T >>  << A >>
assaf_sarfati@yahoo.com (Assaf Sarfati) wrote in message news:<44b0ca4e.0202040850.10dfe4db@posting.google.com>...
> One day, we've tried synthesizing the CPLD with XST.
> When we've downloaded it (no errors during synthesis or fitting), the CPLD
> didn't work.
> 
> Since that download, we can't access the V-2 OR the CPLD with iMpact. When
> connecting, it recognizes (correctly) only the CPLD; if we try any operation
> on the CPLD (erasing, programming or whatever), we get a message "invalid
> device ID".

Are you using the Parallel port download cable? I have had this same
problem with impact and the parallel cable. The problem disappeared
when I changed to a different parallel port (I have three on my PC). I
don't know the cause of the problem as the original port still works
with other devices, just not with impact.

Article: 39257
Subject: Re: Xilinx synthesis tools
From: "Sanket Bandyopadhyay" <sanket@insight.memec.co.in>
Date: Tue, 5 Feb 2002 02:50:32 -0800
Links: << >>  << T >>  << A >>
Well, XST is more stable and has the better QoR than FPGA Express.
You can make a small design of a PWM and see for yourself.
You will see that,after synthesising with FPGA express,you may get slightly different P&R results every time, but with XST you get repeatedly same P&R results after synthesis.XST is better.Moreover you can actually feel the difference in a more than million gate design.That is actually the trial by fire.

Article: 39258
Subject: When is Xilinx going to have multi-gigabit serial PHY?
From: "Gamma Globulin" <nexsan@aol.com>
Date: Tue, 5 Feb 2002 10:53:22 -0000
Links: << >>  << T >>  << A >>
Xilinx bought RocketChips a while back so that they could develop Virtex II
chips with multi-gigabit PHY's in them (for Fibre Channel, Gigabit Ethernet,
etc).  Do any of you know when we are likely to see any product or any data
sheets?
Gary

--




Article: 39259
Subject: Re: chipscope "disable JTAG clock BUFG insertion"
From: "Sanket Bandyopadhyay" <sanket@insight.memec.co.in>
Date: Tue, 5 Feb 2002 03:07:39 -0800
Links: << >>  << T >>  << A >>
HI,
   ILA cores are robust enough and won't pose a timing problem if local resources are used.Moreover if at all you think ILA is causing such a problem---go to Constraints Editor---use LOWSKEWLINES control for the clock net.
regds.
Sanket.
Xilinx FAE from Insight.

Article: 39260
Subject: Re: solutions manuals, and no they are not for school
From: ricklyon@remove.onemain.com (Rick Lyons)
Date: Tue, 05 Feb 2002 11:30:04 GMT
Links: << >>  << T >>  << A >>
On Mon, 04 Feb 2002 22:20:06 -0800, Bob Cain <arcane@znet.com> wrote:
>
>Steve wrote:
>> 
>> If he's legit then fair enough but you have to be a bit suspect about
>> people asking for solutions manuals on a NG. After what I saw on a
>> course last year nothing would surprise me about what students will do
>> to get out of work. He may sound legit but you'd expect him to attempt
>> to sound honest.

That original post just sounded fishy.
Can you imagine someone saying, "I want 
solution manuals to textbooks.  I don't 
care which books, just help me get  
solutions manuals."  Just doesn't sound 
kosher.  The solutions manuals I've seen 
contain answers, but not the questions.
Now tell me, just exactly how the heck are ya' 
gonna tell if a book is useful by looking at 
the algebraic answers to homework problems.

>I just wish there was some bonded credential I could get that stated
>"Bob Cain is not a student nor is he assisting one."  :-)
>Bob

Ah ha!  That credential would be handy for a student 
to have!  Are you sure you're not a student Bob?  ;-)
[Maybe a student of the 'School of Hard Knocks'.]

Yea, it happens.  I once posted a question about 
solving equations containing complex exponentials 
whose real parts are non-zero.  [e^(a +jb)]
Someone teased me that my question looked like 
a homework problem, and that surprised/shocked 
me.  No matter though, 'cause then the fellow 
proceeded to help me out for which I really was 
grateful.  The guy's answer forced me to stick my 
toes in the chilly waters of hyperbolic functions.
Brrrrr!

[-Rick-]


Article: 39261
Subject: Re: When is Xilinx going to have multi-gigabit serial PHY?
From: sanketinsight.memec.co.in <>
Date: Tue, 5 Feb 2002 03:40:12 -0800
Links: << >>  << T >>  << A >>
HI,
  10Gb Ethernet MAC w/XGMII core is available for Virtex-II.Go to
http://www.xilinx.com/apps/virtexapp.htm#appnotes.

Sanket.
Xilinx FAE from Insight.

Article: 39262
Subject: I want pla2tdf.exe
From: "Jeff Stout" <jeffstout@mylinuxisp.com>
Date: Tue, 5 Feb 2002 08:08:03 -0600
Links: << >>  << T >>  << A >>
Does anyone have, or know where to find a program called
"PLA2TDF.EXE"?  My information says it was once included
with the MAX PLUS software package, but I did not find it there.

"PLA2TDF.EXE" is a program once provided by Altera to
convert "pla" files to Altera format.

Thanks,
Jeff Stout




Article: 39263
Subject: Adding internal JTAG chains on FPGA
From: guiducci@cern.ch (Luigi)
Date: 5 Feb 2002 06:39:27 -0800
Links: << >>  << T >>  << A >>
I'm a student and I'm developing a design on an APEX20k. This device
is not really a choice now, I just started to try Quartus. I'll have
the need to add a jtag chain, not attached to the boundary scan one,
but parallel, to be used for some configuration registers I'll have in
the chip. It seems that the apex has a built in port, the tap
controller, a boundary scan registers chain (in silicon?). No way to
add what I need using basically the same jtag port? I could rewrite by
hand all the jtag circuitry, but would this mean I could not use
anymore the pin-dedicated fast input/output registers?
Sorry if i wasn't clear or if it's a stupid question

Luigi

Article: 39264
Subject: Re: F3.3 SP8
From: "Alex Jumper" <jalexv@hotmail.com>
Date: Tue, 5 Feb 2002 15:26:35 +0000 (UTC)
Links: << >>  << T >>  << A >>
"Hristo Stevic" <hristostev@yahoo.com> wrote in message
news:2ff310a6a56b3542961d75ddf9a7b8a2.52609@mygate.mailgate.org...

> Hello,
> want to install service pack8 for the F3.3i
> the file did unpack successfully, but nothing happen later 
> according to
> 
> 
> http://www.xilinx.com/support/techsup/sw_updates/31i/33i_sp8/33if_sp8_readme_pc.htm
> 
> i should be prompt to input the location of the foundation, but no such
> thing happens, moreover, the version of my tool has not been upgarded to
> 08i version
> 
> has someone exprience a similair situation
> 
> thanks


    Looks like something went wrong inside Windows registry etc. Try to
reinstall Foundation
and then apply SP8. I had the same problem installing SP6 and it helped.
    Best wishes.
        Alex.





-- 
Posted via Mailgate.ORG Server - http://www.Mailgate.ORG

Article: 39265
Subject: Re: Destroying a CPLD by JTAG
From: Austin Lesea <austin.lesea@xilinx.com>
Date: Tue, 05 Feb 2002 07:32:56 -0800
Links: << >>  << T >>  << A >>
Tim,

Really?  I am surprised that other folks would have such intolerant output buffers.
I supose the last time I used a CPLD it was called a PAL (22V10), so I have not kept
up with them.

Not to be able to tolerate a short to Vcc or ground is pretty bad.  I'll ask our
CPLD folks about it.

Too bad, really.  Just another reason to try to put everything into the FPGA....

Austin


Tim wrote:

> Austin
>
> "Austin Lesea" wrote
>
> > Tim,
> >
> > I doubt that shorting two outputs kills anything at all.  We have left outputs
> > shorted to Vcc and Ground for months with no ill effects.
> >
> > Maybe ESD is to blame?  Who knows.
>
> My poor syntax.  What I meant was that I have seen FPGA outputs
> effortless kill other devices when pins intended to be inputs
> are programmed as outputs.
>
> In my limited experience, the FPGA buffers can source enough
> current to fry other chips.  I have done this a couple of times,
> most recently to a clock generator part.


Article: 39266
Subject: Re: When is Xilinx going to have multi-gigabit serial PHY?
From: Austin Lesea <austin.lesea@xilinx.com>
Date: Tue, 05 Feb 2002 07:45:25 -0800
Links: << >>  << T >>  << A >>
And you expect me to answer this?

New product introduction, and introduction of new features is a closely held
secret (at most well run companies).

If you are willing to sign an NDA, please contact your FAE.  They will be more
than happy to let you in on future products and features.

The Rocket Chips IC Designers are very busy right now, so don't worry about
them.

Be patient, or sign the NDA, your choice.

Austin


Gamma Globulin wrote:

> Xilinx bought RocketChips a while back so that they could develop Virtex II
> chips with multi-gigabit PHY's in them (for Fibre Channel, Gigabit Ethernet,
> etc).  Do any of you know when we are likely to see any product or any data
> sheets?
> Gary
>
> --


Article: 39267
Subject: Re: Core generator Asynchronous FIFO
From: Brian Philofsky <brian.philofsky@xilinx.com>
Date: Tue, 05 Feb 2002 08:45:53 -0700
Links: << >>  << T >>  << A >>


It sounds like from the error message that some of your design's ports
were removed during implementation.  Take a look at the port
declarations in the <design>_timesim.v file and see if all the
originally declared ports are in that file.  If not, look at the Map
report to see if you can determine why it was removed.  If the port was
removed on purpose (you are not actually using it in your design) then
you may either modify the testbench file, removing those unused ports or
you could try enabling the "Correlate Simulation Data to Input Design"
in the options for generating the simulation netlist file.  That
sometimes replaces optimized ports from the design in the simulation
netlist.


--  Brian



starpanda wrote:

> I use core generator to generate a Asynchronous FIFO. I wrote a
> testbench and used project navigator to do some simulation.  The
> behavioral simulation went through without any problem. After that
> simulation with post-translate model doesn't give me any output. The
> post-mapping model gave me an error when modelsim is loading the
> model. The error is as follow:
> # ** Fatal: asyn_fifo_tb.tf(20): Too many port connections.
> #    Time: 0 ps  Iteration: 0  Region: /testbench/test_fifo
> # FATAL ERROR while loading design
> # Error loading design
> # Error: Error loading design
> #        Pausing macro execution
> # MACRO ./asyn_fifo_tb.mdo PAUSED at line 9
>
> Is there anyone know what is going wrong?
>
> Thanks!
>
> Starpanda


Article: 39268
Subject: Re: When is Xilinx going to have multi-gigabit serial PHY?
From: "Gamma Globulin" <nexsan@aol.com>
Date: Tue, 5 Feb 2002 15:48:00 -0000
Links: << >>  << T >>  << A >>
<sanketinsight.memec.co.in> wrote in message news:ee74aae.0@WebX.sUN8CHnE...
> HI,
>   10Gb Ethernet MAC w/XGMII core is available for Virtex-II.Go to
> http://www.xilinx.com/apps/virtexapp.htm#appnotes.
>
> Sanket.
> Xilinx FAE from Insight.


Thanks, but I'm looking for a 1 to 2 gigabit serial PHY built into the chip,
not an external PHY.  The interface described in the app note is only
running at a few hundred MHz.

Gary



Article: 39269
Subject: Re: When is Xilinx going to have multi-gigabit serial PHY?
From: Austin Lesea <austin.lesea@xilinx.com>
Date: Tue, 05 Feb 2002 08:11:18 -0800
Links: << >>  << T >>  << A >>
Gary,

Not interested in signing an NDA?

Austin

Gamma Globulin wrote:

> <sanketinsight.memec.co.in> wrote in message news:ee74aae.0@WebX.sUN8CHnE...
> > HI,
> >   10Gb Ethernet MAC w/XGMII core is available for Virtex-II.Go to
> > http://www.xilinx.com/apps/virtexapp.htm#appnotes.
> >
> > Sanket.
> > Xilinx FAE from Insight.
>
> Thanks, but I'm looking for a 1 to 2 gigabit serial PHY built into the chip,
> not an external PHY.  The interface described in the app note is only
> running at a few hundred MHz.
>
> Gary


Article: 39270
Subject: Re: Leonardo=>MaxPlus/Quartus Vs Synopsys=>MaxPlus/Quartus
From: Mike Treseler <mike.treseler@flukenetworks.com>
Date: Tue, 05 Feb 2002 08:39:51 -0800
Links: << >>  << T >>  << A >>
sbf wrote:
> 
> Igor -
> 
> I have seen this a couple of times.  FPGA Express tends to pass arithmetic
> operators on to Altera through LPM's while Leonardo generally tries to
> synthesize and optimize those structures. 

The full mentor version of leonardo infers LPMs extensively.
I have not tried the Altera oem version.

> Look for arithmetic operators (especially multiplies & divides) and see what
> block sizes Synopsys & Leonardo generate - if you want to stay with leo then
> you can always generate LPM black boxes for those type functions.

Yes. Even < and = can waste LEs if you don't really need a full comparison.

> Secondarily, if the design is hieararchical do a synthesis / place & route
> on the lower level modules to see where the differences exist  - it's a good
> way to gain insight on coding style & synthesis issues.

Yes. Also the full version of leo lets you click on code and jump to
the netlist schematic to see what it generated.

 -- Mike Treseler

Article: 39271
Subject: Re: Destroying a CPLD by JTAG
From: Austin Lesea <austin.lesea@xilinx.com>
Date: Tue, 05 Feb 2002 09:01:55 -0800
Links: << >>  << T >>  << A >>
Well,

>From the CPLD apps folks:

"I have never destroyed one as such, but people frequently
don't tell you everything.  Key little facts are often omitted.
For instance, recently, we have had people doing ESD testing
on parts while they are powered up and driving 200 MHz
I/Os with all I/Os switching.  When we tell them ESD testing
is basically static and unpowered (I guess they think ESD means
ElectroDynamic Discharge), they act surprised.

If the guy is pulling an output to -10 volts (down) or + 10 volts (up),
there may be a problem.  Would need to know more."

So there is the word from those who know about our CPLDs.

Austin

Austin Lesea wrote:

> Tim,
>
> Really?  I am surprised that other folks would have such intolerant output buffers.
> I supose the last time I used a CPLD it was called a PAL (22V10), so I have not kept
> up with them.
>
> Not to be able to tolerate a short to Vcc or ground is pretty bad.  I'll ask our
> CPLD folks about it.
>
> Too bad, really.  Just another reason to try to put everything into the FPGA....
>
> Austin
>
> Tim wrote:
>
> > Austin
> >
> > "Austin Lesea" wrote
> >
> > > Tim,
> > >
> > > I doubt that shorting two outputs kills anything at all.  We have left outputs
> > > shorted to Vcc and Ground for months with no ill effects.
> > >
> > > Maybe ESD is to blame?  Who knows.
> >
> > My poor syntax.  What I meant was that I have seen FPGA outputs
> > effortless kill other devices when pins intended to be inputs
> > are programmed as outputs.
> >
> > In my limited experience, the FPGA buffers can source enough
> > current to fry other chips.  I have done this a couple of times,
> > most recently to a clock generator part.


Article: 39272
Subject: Re: DCM relationship question
From: newman5382@aol.com (newman)
Date: 5 Feb 2002 09:13:35 -0800
Links: << >>  << T >>  << A >>
> > > The DCM will have feed back from the middle on the PCB trace,
> > > for delay compensation.
> > >

Do you think the creation of a trace stub from the feedback from the
middle of the PCB trace will mess up the clock signal integrity?

Newman

Article: 39273
(removed)


Article: 39274
Subject: Re: I want pla2tdf.exe
From: heyho <heyho@hohey.ho>
Date: Tue, 5 Feb 2002 09:23:33 -0800
Links: << >>  << T >>  << A >>
if I remember that right (sometimes I feel Alzheimer has taken so´me of my memory contents away) there was a so called "First Step" utility provided by Altera which included that pla2tdf. In reality, First Step was a very basic Max+2 which supported only the EPM7032 and AHDL. You should check if that utility is still available on Altera´s ftp site. otherwise, ask one of the altera veterans,. They will know.



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