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Messages from 38900

Article: 38900
Subject: Re: Homebrew computers using FPGA?
From: "Rob Finch" <robfinch@sympatico.ca>
Date: Mon, 28 Jan 2002 02:29:51 -0500
Links: << >>  << T >>  << A >>
You can build a pretty decent homebrew computer in an FPGA much faster and
more powerful than an older microprocessor like the 6502 or 8088. Simple
RISC architectures seem to match the FPGA architecture better than CISC.
Have a look at www.fpgacpu.org  Keep in mind that if you homebrew a cpu it's
a lot of work ! You have to come up with development tools (assembler,
compiler, etc) If you'd like to see a work in progress, I'm currently
working on a 32 bit cpu that's "almost" working at 25 MHz. Compared to say a
25 MHz 486 it's probably much faster.  www.birdcomputer.ca

You can reach a pretty decent clock rate in an FPGA, 50 MHz+ is certainly
obtainable and more than adequate for many applications.

Rob

"Franck Pissotte" <franck.pissotte@free.fr> wrote in message
news:3C531C98.821F5591@free.fr...
> David Findlay a écrit :
>
> > Is it possible to build a homebrew computer of some description using
FPGA's? I know it won't be
> > as powerful as a PC, but I'm more interested in designing and building
my own. Also does anyone
> > know of an FPGA simulator for Linux? Thanks,
>
> i have the same interest.
> if you find some ressource please post here.
> evaluation board seem expensive.
> for 100$ digilent seem good
> but with shipping, curstoms tax and money order
> (i am in france) it will cost 50$ more.
> and even in Paris fpga are not sold in shops.
>
> i am looking for a free design DIY FPGA board.
> should use a PLCC84, use standard part i have
> in my box or buy at low price,
> and have free software running on win98.
> any url? thanks
> --
> http://www.pascaland.org/ compilateurs, sources et liens langage pascal,
delphi
> http://franck.pissotte.free.fr/ mon vide grenier: vieux materiels,
logiciels, livres et revues
>
>



Article: 38901
Subject: String manipulation in VHDL question
From: dottavio@ised.it (Antonio)
Date: 27 Jan 2002 23:31:23 -0800
Links: << >>  << T >>  << A >>
I would want in VHDL to produce a file with a different name depending
on the value of a signal
named rate_sel , it is a std_logic_vector(2 downto 0) , I know in
Matlab I could do this
with the following instructions , but how it's possible (if it is ..)
to obtain the same result
in VHDL ??

rate_sel = 4 ;
fid      = fopen( strcat('SRRCx', num2str( rate_sel),
'_FreqSampl_scaled.dat') , 'r');

Article: 38902
Subject: Problem with type definition
From: dottavio@ised.it (Antonio)
Date: 27 Jan 2002 23:32:25 -0800
Links: << >>  << T >>  << A >>
Here's a programmable counter that also produce the pulse for a clock
enable structure,
about it I've a simple (I think ..) problem, the data rate can assume
only three values
and so to reduce logic I would want to tell this to the synthesizer
with the instruction

type rate is ("010" , "011" , "101");	

this produce the error "identifier or character literal expected" how
I can solve the question ??


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

package types is
	type rate is rate("010" , "011" , "101");
end types;



library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use work.types.all;

entity counter is
	port (
		clk 	       : in  std_logic;
		reset 	 : in  std_logic;					 
--		rate_sel     : in  std_logic_vector(2 downto 0);
		rate_sel     : in  rate;
		count 	 : out std_logic_vector(2 downto 0);
		clk_en 	 : out std_logic
	);
end entity;

architecture counter_arch of counter is
	signal TEMP_count 	: std_logic_vector(2 downto 0);
	signal TEMP_clk_en 	: std_logic;
begin

	process(clk, reset)
	begin
		if reset = '1' then
			TEMP_count  <= "000";   
			TEMP_clk_en <= '1'  ;
		elsif rising_edge(clk) then
			if (TEMP_count   =  rate_sel) then
				TEMP_count  <= "000";
				TEMP_clk_en <= '1'  ;
			else
				TEMP_count <= TEMP_count + 1;
				TEMP_clk_en <= '0'  ;				
			end if;
		end if;
	end process;

	count 	<= TEMP_count;
	clk_en  <= TEMP_clk_en;	

end counter_arch;

Article: 38903
Subject: Re: Pin assignment on ACEX1K
From: heyho <nospam@heyho.com>
Date: Mon, 28 Jan 2002 00:39:22 -0800
Links: << >>  << T >>  << A >>
Hi,

both, Max+plus 2 as well as Quartus 2 provide you with a lot of information which is not shown in any datasheet. If you´re using Max+2 just go to the "Online Help" and the search for the string "pins". Then you will find all the relevant information on which pins are conneceted to which row or which column. If your´re going for spped it is importnat that you will do the pin assignments based on that information. For example, the 32bit bus or the 16bit bus should be assigned to the pins which are connected to the SAME row or SAME column. 

BTW, Kevin, why should he use Spartan II´s? ACEX devices are great! This should be a newsgroup which discusses technical questions and not stupid stuff what device is a few cents cheaper than another one. This kind of information hich cannot be proven anyway!!

Article: 38904
Subject: Is this a Xilinx XST synthesis problem ?
From: "Rob Finch" <robfinch@sympatico.ca>
Date: Mon, 28 Jan 2002 03:40:58 -0500
Links: << >>  << T >>  << A >>
What am I doing wrong in the following code ? XST synthesis synthesizes only
a four bit subtractor here, but a thirty-three bit adder.

module addsub(op, ci, a, b, o, co, v);
 parameter DBW = 32;
 input op;   // 0 = add, 1 = sub
 input ci;   // carry in
 input [DBW-1:0] a, b; // operands input
 output [DBW-1:0] o; // result
 reg [DBW-1:0] o;
 output co;   // carry out
 reg co;
 output v;   // overflow

 reg ign;

 always @(op or ci or a or b) begin
  if (op)
   {co,o,ign} <= {a,ci} - {b,1'b1};
  else
   {co,o,ign} <= {a,ci} + {b,1'b1};
 end

 // compute overflow
 assign v = (op ^ o[DBW-1] ^ b[DBW-1]) & (~op ^ a[DBW-1] ^ b[DBW-1]);

endmodule


If I code the adder/subtractor like the following it seems to work.

module addsub(op, ci, a, b, o, co, v);
 parameter DBW = 32;
 input op;   // 0 = add, 1 = sub
 input ci;   // carry in
 input [DBW-1:0] a;
 input [DBW-1:0] b; // operands input
 output [DBW-1:0] o; // result
 output co;   // carry out
 output v;   // overflow

 reg ign;
 reg [33:0] sum;

 always @(op or ci or a or b) begin
  if (op)
   sum <= {a,ci} - {b,1'b1};
  else
   sum <= {a,ci} + {b,1'b1};
 end
 assign o = sum[32:1];
 assign co = sum[33];

 // compute overflow
 assign v = (op ^ o[DBW-1] ^ b[DBW-1]) & (~op ^ a[DBW-1] ^ b[DBW-1]);

endmodule





Article: 38905
Subject: Books on DSP
From: Przemyslaw Wegrzyn <czajnik@czajsoft.pl>
Date: Mon, 28 Jan 2002 10:47:51 +0100
Links: << >>  << T >>  << A >>

Hello !

I'm looking for some books about implementing DSP algorithms in FPGA. Can 
someone advise any title ?

-=Czaj-nick=-


Article: 38906
Subject: Re: Peaks in smaller PLDs
From: "Martin Fischer" <Martin.Fischer@fzi.de>
Date: Mon, 28 Jan 2002 11:43:29 +0100
Links: << >>  << T >>  << A >>
> What do you mean with peaks?? small pulses (glitches) on data signals.
This
> is just normal an ca be ignored in 99% of all cases. But your clock
signals
> must be absolutely glitch free.

Yes, I mean glitches.
Do you mean also the clock for the processes ?

For example  I have a signal Zustandsfehler with glitches and an process
Ladenabbrechen
can I than ignore the glitches in my output signal Laden_abbrechen ?

Ladenabbrechen : process (Abbruch, Zustandsfehler)
Begin
  if Abbruch='1' or Zustandsfehler='1'
  then
     Laden_abbrechen<='1';
  else Laden_abbrechen<='0';
  end if;
end process Ladenabbrechen;

Thanks

Martin




Article: 38907
Subject: Re: negative offset warning message
From: remi.seglie@nettest.com (RS)
Date: 28 Jan 2002 03:22:02 -0800
Links: << >>  << T >>  << A >>
Hi,

It's a problem of clock delay, ie the clock comes 6.4ns after the
data, that is no good for a design. Probably you don't use global
clock buffer.


dottavio@ised.it (Antonio) wrote in message news:<fb35ea96.0201272329.27c1f16f@posting.google.com>...
> I've the following message from Xilinx ISE, what to do about the warning
> " Offset is  -6.400ns.
>  Negative offset in this situation may cause a hold violation."
> 
> 
> 
> --------------------------------------------------------------------------------
> Release 4.1.03i - Trace E.30
> Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.
> 
> trce -e 3 -l 3 -xml ROM_polyphase ROM_polyphase.ncd -o ROM_polyphase.twr
> ROM_polyphase.pcf
> 
> Design file:              rom_polyphase.ncd
> Physical constraint file: rom_polyphase.pcf
> Device,speed:             xcv1000,-4 (FINAL 1.115 2001-06-20)
> Report level:             error report
> --------------------------------------------------------------------------------
> 
> 
> ================================================================================
> Timing constraint: NET "clk_ibuf/IBUFG" PERIOD =  20 nS   HIGH 50.000000 % ;
> 
>  52 items analyzed, 0 timing errors detected.
>  Minimum period is  13.908ns.
> --------------------------------------------------------------------------------
> 
> ================================================================================
> Timing constraint: TS_clk = PERIOD TIMEGRP "clk"  20 nS   HIGH 50.000000 % ;
> 
>  0 items analyzed, 0 timing errors detected.
> --------------------------------------------------------------------------------
> 
> ================================================================================
> Timing constraint: OFFSET = IN 20 nS  BEFORE COMP "clk" ;
> 
>  1 item analyzed, 0 timing errors detected.
>  Offset is  -6.400ns.
>  Negative offset in this situation may cause a hold violation.
> --------------------------------------------------------------------------------
> 
> 
> All constraints were met.
> 
> 
> Data Sheet report:
> -----------------
> All values displayed in nanoseconds (ns)
> 
> Setup/Hold to clock clk
> ---------------+------------+------------+
>                |  Setup to  |  Hold to   |
> Source Pad     | clk (edge) | clk (edge) |
> ---------------+------------+------------+
> to_SRRC_I      |    3.600(F)|    0.000(F)|
> ---------------+------------+------------+
> 
> Clock to Setup on destination clock clk
> ---------------+---------+---------+---------+---------+
>                | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
> Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
> ---------------+---------+---------+---------+---------+
> clk            |         |    6.954|         |    7.340|
> ---------------+---------+---------+---------+---------+
> 
> 
> Timing summary:
> ---------------
> 
> Timing errors: 0  Score: 0
> 
> Constraints cover 53 paths, 0 nets, and 55 connections (74.3% coverage)
> 
> Design statistics:
>    Minimum period:  13.908ns (Maximum frequency:  71.901MHz)
> 
> 
> Analysis completed Sat Jan 26 16:31:26 2002
> --------------------------------------------------------------------------------

Article: 38908
Subject: FPGA or Micro-controller in Lowpower designs?
From: "Arash Salarian" <arash.salarian@epfl.ch>
Date: Mon, 28 Jan 2002 12:24:32 +0100
Links: << >>  << T >>  << A >>
Hi,

I'm starting a new design in which I'm using a multi-channel A/D with a low
sampling-rate and Flash memory for the storage and the system is going to be
powered by battery. In this stage, I'm not yet sure if using a FPGA would be
wise, as I'm very concerned with the power consumption. The gate count of
the circuit will be 3k~4k in my opinion so basically any medium Spartan
family or even maybe XPLA would do. I've seen a device from ATmel (T87C5111)
that consumes only 5mA and I guess is a good candidate too. This makes me
hesitate to choose any FPGA over these types of micro-controller in designs
were every bit of current matters..

Does anyone has experience in using FPGAs in low power applications and is
there any suggestion in selection FPGAs over micros in these types of
designs?

Regards
Arash



Article: 38909
Subject: Re: Xilinx webpack
From: Russell Shaw <rjshaw@iprimus.com.au>
Date: Mon, 28 Jan 2002 11:57:28 GMT
Links: << >>  << T >>  << A >>


Peter Alfke wrote:
> 
> Russell, the circuit has 4 inputs, and its functionality is
> therefore described by how it reacts to the 16 different
> patterns that might ever appear on its four inputs. Anything
> less is insufficient, anything more is redundant.
> Just think about it, and it will become obvious...

yes, but no matter how the 4 inputs are wired, the
synthesizer will adjust the LUT contents to give the
same result. So, 4 inputs gives 16 outputs, and
permutations don't matter.

Article: 38910
Subject: Re: Xilinx webpack
From: "Paul" <nospam@nospamplease.com>
Date: Mon, 28 Jan 2002 12:31:48 -0000
Links: << >>  << T >>  << A >>

"Russell Shaw" <rjshaw@iprimus.com.au> wrote in message
news:3C553CD6.30C0EFE@iprimus.com.au...
>
>
> Peter Alfke wrote:
> >
> > Russell, the circuit has 4 inputs, and its functionality is
> > therefore described by how it reacts to the 16 different
> > patterns that might ever appear on its four inputs. Anything
> > less is insufficient, anything more is redundant.
> > Just think about it, and it will become obvious...
>
> yes, but no matter how the 4 inputs are wired, the
> synthesizer will adjust the LUT contents to give the
> same result. So, 4 inputs gives 16 outputs, and
> permutations don't matter.

Think of it as all 16 input combinations are needed to define the Karnaugh
map of the output 1's and 0's which then determine a LUT function.

Two functions can have 15 of the 16 outputs the same, but the 16th is
different. Therefore they are different functions.

There are 16 possible outputs, so 2^16 possible functions....

I'm not sure that it is fair to suggest that two identical functions but one
operating on say A,B,C and D inputs whilst another has the same transfer
function but mapped to A, B, D and C should be classed as different however.
I believe this would be a function of the routing and not the LUT.

Hence the number of functions should be reduced (in which case Peter should
fire himself :) )

I did try to work out what that would mean, but my head hurt so I'll leave
it to clever people....

Over to you Peter





Article: 38911
Subject: configuring an FPGA from an Hard-drive with a 80c51 (Stupid idea ?)
From: Steven Derrien <sderrien@irisa.fr>
Date: Mon, 28 Jan 2002 14:06:25 +0100
Links: << >>  << T >>  << A >>
Hello,

This post is just for submitting an idea to those who are familiar with
embedded system design, in order to get some feed-back (with respect to
feasibility, cost, usefulness and so on…).

The basic idea is the following :

We want to design a reconfigurable SoC, which will be connected to an
IDE hard-drive,  used by the application running on the SoC. One of the
key point, is that we need to perform dynamic reconfiguration of the
FPGA.

Our idea is to use the Hard-drive memory to store the various FPGA
configurations, and to use a small 32 I/O MCU (8051) to perform the FPGA
reconfiguration from the HDD. (the 8051 would share the IDE bus with the
FPGA, but they would have a mutual  exclusive use of the HDD, since the
MCU would only be used during reconfiguration)

Since the FPGA should be a relatively big Virtex/Spartan-II, and since a
large density configuration EEPROMs (several Mbits) are quite expensive
compared to a small MCU, we feel that this could be a nice way to reduce
the total system cost.

Now we are wondering whether this idea is good or not :), we are
specifically concerned with :

- PCB layout and signal integrity problems due to the fact that the IDE
connection is shared between the MCU and the FPGA. For ex. would it be
possible to use high-speed IDE (50Mhz clock) protocols from the FPGA ?

- Reliability   : since the hard-drive will be used for both read and
write operation during the application, we must ensure that some part of
the HDD storage is locked (to guarantee that the configurations are not
overwritten by mistake)

- Feasibility  : How difficult would it be to design and debug such a
system ?

Any advice, comments, critics, ideas are welcome,

Thank you in advance.
Steven









Article: 38912
Subject: Re: configuring an FPGA from an Hard-drive with a 80c51 (Stupid idea ?)
From: "Paul" <nospam@nospamplease.com>
Date: Mon, 28 Jan 2002 13:41:51 -0000
Links: << >>  << T >>  << A >>
You could try looking at the IDE core at http://www.opencores.org and even a
simple CPU core there or at www.free-ip.com

It might get you started.

Paul




Article: 38913
Subject: Re: Problem with Altera programmer
From: Iwo Mergler <Iwo.mergler@soton.sc.philips.com>
Date: Mon, 28 Jan 2002 13:43:36 +0000
Links: << >>  << T >>  << A >>
Tim wrote:
> 
> Sometimes these problems are helped by using an add-on
> printer port card rather than the port on the motherboard.
> 
> "Marcin E. Hamerla" <mehamerla@.........pl> wrote
> 
> > According to Altera datasheet I made my own ByteBlaster programmer
> > board for programming FLEXes and MAXes. Up to now everything worked
> > with minor problems. There was only a limitation of the programmer
> > cable lenght. Two weeks ago I have purchused a new fast computer
> > (Athlon 1600+). Then I have  realized that I can not program any
> > chips. Cutting the cable down to 20cm helped but it is rather
> > difficult to work with such a short cable. Changing BIOS parallel port
> > properties did not help - I tried this. And there is a question: are
> > there any problems with the original ByteBlaster (LPT) board used with
> > these new fast computers or I should rather go for USB programmer
> > cable? Does it work with +5V chips? Is it expensive?

Your new chipset probably uses 3.3V or less on the parport pins. That
is borderline for driving 5V logic and with a long cable you push it
over the edge. 

The suggestion to use a add-on port is a good one. Another thing you
can try is to pull the lines up to 5V (with resistors). This should 
give a high-level of about 4V and may allow a longer cable.

Iwo

Article: 38914
Subject: Re: configuring an FPGA from an Hard-drive with a 80c51 (Stupid idea ?)
From: Steven Derrien <sderrien@irisa.fr>
Date: Mon, 28 Jan 2002 14:49:43 +0100
Links: << >>  << T >>  << A >>


Paul wrote:

> You could try looking at the IDE core at http://www.opencores.org and even a
> simple CPU core there or at www.free-ip.com

Weel, I might have not been very clear. Right now we want to use a dicrete
external 8051
since the FPGA cannot recofnigure itself. Besides we already have some 8051
assembly
code to access a IDE drive and to configure a Xilinx FPGA.

The operating mode is the following :

1) At boot-up, the FPGA is not configured (all IO in three state), the 8051
fetches configuartion data from the Hard-drive and use this data to configure
the FGPA. Once the configuration is done, all the 8051 pind connected to the IDE
pins go three state, and the FPGA now has access to the Hard-drive.

2) When the FPGA decides to recofnigure itself, it ask the 8051 by aserting some
signal, the 8051 the puts the FPGA in recofniguration mode (all io ion therr
state), resets its pins in normal (in or out) mode, anf fetches another
configuration data from the hard drive. Once the configuration is done, all the
8051 pind connected to the IDE pins go three state, and the FPGA now has again
access to the Hard-drive.

Steven

>
>
> It might get you started.
>
> Paul


Article: 38915
Subject: Re: tri-state vs. Mux
From: Ray Andraka <ray@andraka.com>
Date: Mon, 28 Jan 2002 13:53:21 GMT
Links: << >>  << T >>  << A >>
The pseudo-tristates in Virtex require you to space the bus drivers every 4th
column (you can actually put stuff in 2 adjacent columns then skip two and then
two adjacent) because of the architecture.  You should floorplan these drivers
because the automatic place and route is lousy at figuring out where the
tristates should go.  If you let PAR do it, your tristae enable ends up going all
over the chip and you get exceptionally poor performance.  That said, a design
with only 3 drivers is usually better off using a mux in Virtex.

David Miller wrote:

> Josh Pfrimmer wrote:
>
> >     I'm trying to implement a stacked-register entity; each register will
> > have an input, an output, and 4 levels of stacking, which will be used when
> > an interrupt is received.  That is: on an interrupt, the contents of the
> > register will be pushed, to be restred when the ISR has completed.
>
> Naturally, Peter's advice is probably the best you can get.  The only
> thing I can add is my own experience with this question.
>
> I found that in a particular Virtex design, tristates were actually
> slower than multiplexors.  It's not clear to me why this was.  There
> were only 3 inputs to choose from, (one of which was a compile-time
> constant), so I guess it had to do with LUT delay versus BUFT switching
> time.
>
> I guess you have to suck it and see.  If you are designing in an HDL,
> then switching between multiplexors and tristate buffers is trivial.  It
> has to be a very design sensitive matter, so experimentation will yield
> the best results!
>
> --
> David Miller, BCMS (Hons)  | When something disturbs you, it isn't the
> Endace Measurement Systems | thing that disturbs you; rather, it is
> Mobile: +64-21-704-djm     | your judgement of it, and you have the
> Fax:    +64-21-304-djm     | power to change that.  -- Marcus Aurelius

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 38916
Subject: Re: configuring an FPGA from an Hard-drive with a 80c51 (Stupid idea ?)
From: "Bill Blyth" <bb@alphadata.co.uk>
Date: Mon, 28 Jan 2002 14:24:57 -0000
Links: << >>  << T >>  << A >>
Have you considered SystemACE from Xilinx. One of the options is to boot
from compact flash with relatively large storage.

Bill
"Steven Derrien" <sderrien@irisa.fr> wrote in message
news:3C5556F7.6BEAF057@irisa.fr...
>
>
> Paul wrote:
>
> > You could try looking at the IDE core at http://www.opencores.org and
even a
> > simple CPU core there or at www.free-ip.com
>
> Weel, I might have not been very clear. Right now we want to use a dicrete
> external 8051
> since the FPGA cannot recofnigure itself. Besides we already have some
8051
> assembly
> code to access a IDE drive and to configure a Xilinx FPGA.
>
> The operating mode is the following :
>
> 1) At boot-up, the FPGA is not configured (all IO in three state), the
8051
> fetches configuartion data from the Hard-drive and use this data to
configure
> the FGPA. Once the configuration is done, all the 8051 pind connected to
the IDE
> pins go three state, and the FPGA now has access to the Hard-drive.
>
> 2) When the FPGA decides to recofnigure itself, it ask the 8051 by
aserting some
> signal, the 8051 the puts the FPGA in recofniguration mode (all io ion
therr
> state), resets its pins in normal (in or out) mode, anf fetches another
> configuration data from the hard drive. Once the configuration is done,
all the
> 8051 pind connected to the IDE pins go three state, and the FPGA now has
again
> access to the Hard-drive.
>
> Steven
>
> >
> >
> > It might get you started.
> >
> > Paul
>



Article: 38917
Subject: ARe: configuring an FPGA from an Hard-drive with a 80c51 (Stupid idea ?)
From: Steven Derrien <sderrien@irisa.fr>
Date: Mon, 28 Jan 2002 15:28:36 +0100
Links: << >>  << T >>  << A >>


Bill Blyth wrote:

> Have you considered SystemACE from Xilinx. One of the options is to boot
> from compact flash with relatively large storage.

Yes, I've seen what they were offering (actually they even allow to use IBM
micro-drive hard-disks to store up to 340 GB configuration data on the board).

The pb is that in our system, once the FPGA is configured, its design (Soft-cpu
+ co-processor) actually uses the Hard-drive as a standard system would do. This
is not possible with SystemAce.

Aditionnaly it is probably very expensive (we want to use COTS like a cheap MCU
plus a <100$ standard hard-drive).

Steven


>
>
> Bill
> "Steven Derrien" <sderrien@irisa.fr> wrote in message
> news:3C5556F7.6BEAF057@irisa.fr...
> >
> >
> > Paul wrote:
> >
> > > You could try looking at the IDE core at http://www.opencores.org and
> even a
> > > simple CPU core there or at www.free-ip.com
> >
> > Weel, I might have not been very clear. Right now we want to use a dicrete
> > external 8051
> > since the FPGA cannot recofnigure itself. Besides we already have some
> 8051
> > assembly
> > code to access a IDE drive and to configure a Xilinx FPGA.
> >
> > The operating mode is the following :
> >
> > 1) At boot-up, the FPGA is not configured (all IO in three state), the
> 8051
> > fetches configuartion data from the Hard-drive and use this data to
> configure
> > the FGPA. Once the configuration is done, all the 8051 pind connected to
> the IDE
> > pins go three state, and the FPGA now has access to the Hard-drive.
> >
> > 2) When the FPGA decides to recofnigure itself, it ask the 8051 by
> aserting some
> > signal, the 8051 the puts the FPGA in recofniguration mode (all io ion
> therr
> > state), resets its pins in normal (in or out) mode, anf fetches another
> > configuration data from the hard drive. Once the configuration is done,
> all the
> > 8051 pind connected to the IDE pins go three state, and the FPGA now has
> again
> > access to the Hard-drive.
> >
> > Steven
> >
> > >
> > >
> > > It might get you started.
> > >
> > > Paul
> >


Article: 38918
Subject: Re: Pin assignment on ACEX1K
From: Ray Andraka <ray@andraka.com>
Date: Mon, 28 Jan 2002 14:31:16 GMT
Links: << >>  << T >>  << A >>
Depends on the application.  In a heavily arithmetic or DSP design, the SpartanII is a hands down winner.  Acex does best in "random logic" designs that have little or no data path.

heyho wrote:

>
> BTW, Kevin, why should he use Spartan II´s? ACEX devices are great! This should be a newsgroup which discusses technical questions and not stupid stuff what device is a few cents cheaper than another one. This kind of information hich cannot be proven anyway!!

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 38919
Subject: Re: Xilinx webpack
From: Ray Andraka <ray@andraka.com>
Date: Mon, 28 Jan 2002 14:33:43 GMT
Links: << >>  << T >>  << A >>
The PAR tools will permute the LUT inputs in an attempt to improve routing.
When it does that, it also permutes the LUT contents so that you wind up
with the same function.

Kevin Brace wrote:

> Was the original question was about FPGA Editor, and whether or not the
> user can see logic gates and FFs?
> Or, was the original question about the input order of a LUT?
> If the original question is whether or not the input order of a LUT will
> change the result, and my answer to that question is yes.
> Let's say there is a 4-input function X= ACD# + A#BC#D + AB# + ABD#.
> If you swap B and C (That is, an input going into B will now go into C,
> and an input going into C will now go into B.), the result will be
> totally different.
> The same rule will still apply to a LUT.
>

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 38920
Subject: Architectural question regarding ROM and RAM
From: dottavio@ised.it (Antonio)
Date: 28 Jan 2002 06:39:30 -0800
Links: << >>  << T >>  << A >>
I would want to arrange the following in VHDL, can you tell me what's
the best architectural solution to obtain this :

The problem is that I've 84 coefficients for each of three filters, I
would want to know if it's better to declare three constant with these
coefficients and then choose between them with a case instruction.
Does this produce an enourmously big multiplexer ???
It's better to use a RAM ??

   Bye
            Antonio

Article: 38921
(removed)


Article: 38922
Subject: Re: negative offset warning message
From: dottavio@ised.it (Antonio)
Date: 28 Jan 2002 07:56:04 -0800
Links: << >>  << T >>  << A >>
May be that this depend on the fact I'm using a clock enable structure
for my project ?? In the gated clock version I've not this message
(..but many other) .
The clock came from outside the FPGA so I think any synthesizer will
put a buffer on it. Do I need a buffer also for the enable signal that
is applied to many points in the project ??

Antonio

Article: 38923
Subject: Re: Books on DSP
From: Tom <tomcip@concentric.net>
Date: 28 Jan 2002 16:00:11 GMT
Links: << >>  << T >>  << A >>
Hi,

I am sorry to disappoint you but there really are no books that I am aware of
which focus on DSP in FPGAs. The reason, in my opinion, is as follows..

DSP is a tough enough topic to engage in when we are in the floating point
world and FPGAs do not have floating point multipliers. (Please, everybody,
don't email me that there is a floating point core available somewhere  ;-)
). Even the Virtex 2 devices  with multipliers can only implement "Fixed
Point" aritithmetic. Since, for digital filters, one of the inputs to the
multiplier is always known (the coefficients) a particularly efficient
(area-wise) method of doing fixed point math is called "Bit Serial
Arithmetic". There are some good articles on Bit Serial stuff. One was
written by Peter Alfke, who now writes Xilinx application notes. It has a
title something like "The role of distributed arithmetic in FPGA design".
There are also articles by the late Les Mintzer, which are quite good (I
would have to dig out in the garage for the title and I am sure that a quick
internet search would find it quicker). Mintzer also wrote the last chapter
in the "DSP Applications Handbook" (I hope that the title is close to being
right), which is a really good book to have except for the fact that it
usually goes for more that $100 (I am way too cheap, times being what they
are). Ray Andraka has a web site dedicated to FPGA stuff which has examples
of arithmetic forms other than Bit Serial.

One other thing that I should mention is that doing IIR filters or any
filters of a recursive nature, in Distributed Arithmetic, while very
possible, is really difficult. The fiixed point scaling issue and especially
the feedback to the first order recursive output (say, Y(n-1) ) can be
tricky.

I hope that this helps.

Tom Cipollone




Przemyslaw Wegrzyn wrote:

> Hello !
>
> I'm looking for some books about implementing DSP algorithms in FPGA. Can
> someone advise any title ?
>
> -=Czaj-nick=-


Article: 38924
Subject: Re: Xilinx webpack
From: Peter Alfke <palfke@earthlink.net>
Date: Mon, 28 Jan 2002 16:03:25 GMT
Links: << >>  << T >>  << A >>
Russell, the question wa: How man diffrent functions can a LUT
implement.
And the answer is 64K.
It only taks a few minutes to describe few hundred completely
different ones, not counting input permutations.

Peter

Russell Shaw wrote:

> Peter Alfke wrote:
> >
> > Russell, the circuit has 4 inputs, and its functionality is
> > therefore described by how it reacts to the 16 different
> > patterns that might ever appear on its four inputs. Anything
> > less is insufficient, anything more is redundant.
> > Just think about it, and it will become obvious...
>
> yes, but no matter how the 4 inputs are wired, the
> synthesizer will adjust the LUT contents to give the
> same result. So, 4 inputs gives 16 outputs, and
> permutations don't matter.




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