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Messages from 41575

Article: 41575
Subject: Re: How to activate 5V PCI I/O pads in FLEX10KE/ACEX1K?
From: Kevin Brace <ihatespam99kevinbraceusenet@ihatespam99hotmail.com>
Date: Tue, 02 Apr 2002 12:03:58 -0800
Links: << >>  << T >>  << A >>
I don't own the Altera FLEX10KE PCI board, so I have no way of verifying
that my PCI IP core will work in FLEX10KE, but thanks for the help
anyway.
If I get a FLEX10KE-based PCI card someday, I will try it out. (Although
$2,000 for the FLEX10KE PCI board is too much. Can't Altera just sell me
the hardware only (without software) with ACEX1K instead for $400?)




Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)




Peter Ormsby wrote:
> 
> Kevin,
> 
> For 5V PCI, just leave the I/Os in the default state.  The 3.3V PCI clamping
> diodes default to off, so the standard LVCMOS/LVTTL I/O setting is what you
> need.  If you want to verify the setting, you can check though the
> assignment organizer or the compiler settings menu to see that 3.3V PCI is
> not selected.
> 
> If you need 5V clamping diodes, you need to implement them externally.
> 
> -Pete-

Article: 41576
Subject: Re: XC9500 low temp. problem
From: hw_designer@yahoo.com
Date: 2 Apr 2002 12:11:27 -0800
Links: << >>  << T >>  << A >>
> Device: XC95144, industrial temp. grade.
> At room temp. it operates OK.
> At -25 deg C and below it sometimes fails to configure.
> This is rather not the problem of supply, since supply is out of temperature
> chamber during tests and the scope shows that supply rises correctly (20 ms
> time, monotonic or almost monotonic).

When building a design in a XC9572XL we encountered the same problem.
This was however a commercial temp. part and the problem of
misconfiguration already showed itself at 0 to +5 deg C.

At first Xilinx came up with an answer to check the start up behavior
of the power. Later on we found out that there were more customers
with the same problem and a new mask for this specific devices was
made.

Article: 41577
Subject: Re: Configuring the Virtex II FPGA
From: remi-seglie@infonie.fr (RS)
Date: 2 Apr 2002 12:18:45 -0800
Links: << >>  << T >>  << A >>
Hi,

I configured 1 and 3 million Virtex II without any problem with Jtag.
In my design, there's no prom but I don't think is the problem (I use
slave select map mode for normal operation). Normaly you need only
.bit file (be sure to use "Jtag clock" for startup in the
configuration option). Correct bsdl file are normally inlude with
Impact, and automatically loaded with the bit file. Any other
information from impact window ? (I don't exactly remember command :
try "reset Jtag cable" "auto initialyse chain" ...) sure you have
correct power supply ?

yaot@hotmail.com (Terry) wrote in message news:<301c8b44.0204011113.494ddad7@posting.google.com>...
> Hi all,
> 
> I am testing my designs using the Insight MicroBlaze development board
> with the Virtex II 1 million gate FPGA.  When configuring the FPGA
> directly (ie. bypassing PROM) using the JTAG port, I first attempt to
> establish communication through reading the idcode.  I received an
> error message from iMPACT that the device idcode doesn't match the
> idcode in the bsdl file.  I'm guessing the problem is related to
> bypassing the ISP PROM, and I should perhaps associate the ISP PROM
> with either a dummy .mcs file or a .bsd file to bypass it.  My
> question is:  can I just use the generic bsdl file available on the
> Xilinx site as the dummy .bsd file?  And if so, where should I save
> this file and how do I specify that it's targeted for the PROM?
> 
> I'd appreciate any help on this matter,
> 
> Terry

Article: 41578
Subject: Re: Marquis of Queensbury Rules
From: Ray Andraka <ray@andraka.com>
Date: Tue, 02 Apr 2002 20:43:16 GMT
Links: << >>  << T >>  << A >>
Funny, I didn't see any of this here.  The folks participating in this forum
have been very professional, courteous and mostly helpful.  Without that,
the newsgroup would be a waste of time.

Anon wrote:

> It seems to me that personal attacks of all kinds are getting to be the
> norm in engineering discussions.  No doubt we live in a mean spirited
> age.  The world of professional sports is where we seem to learn
> protocol and etiquette, and rules for sportsmanship and fair play are
> sadly lacking.  Exhibitionism, tantrums, and trash talk, are the new
> standards.

> <rant snipped>

--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 41579
Subject: Re: Laying out the design
From: kevinbraceusenet@hotmail.com (Kevin Brace)
Date: 2 Apr 2002 12:51:45 -0800
Links: << >>  << T >>  << A >>
Peter, I find the things you mentioned somewhat unfair.
In Quartus II 2.0 Web Edition (the free version like the ISE WebPACK),
LogicLock is disabled. (and bunch of other things like Tcl scripting
are also disabled.)
Since the original poster is talking about ISE WebPACK here, I will
say that you shouldn't mention the features available only for the
paid version.
I already did some manual floorplanning in QII 2.0 WE, and some
features like automatically displaying the routing delay on the screen
is nice, but it has its own problems like it lets me assign multiple
FFs to a single LE which shouldn't happen in the first place because
one LE has only one FF.
The Altera floorplanner doesn't even warn me that I am doing something
wrong until fitting when the fitter won't be able to assign multiple
registers to a single LE, and stop.
At least in Xilinx floorplanner, the floorplanner won't allow me to
put more than two FFs per Slice. (in Spartan-II)
        Looking at your past postings, Peter, are you an Altera
employee?
The comments expressed by you, which tends to be highly biased, to me
seems to indicate that your paycheck comes from Altera.
Although the Xilinx employees' postings at comp.arch.fpga also tends
to be highly biased, at least they indicate their affiliation, so I
can see where their opinions are coming from. (Yeah, if their
paychecks come from Xilinx, they won't make too many negative comments
about their own employer.)
Why don't you want to indicate that you are an Altera employee?
Regardless, since you seem to get your paycheck from Altera, I can see
why you so strongly criticized my comments about QII's fast fit option
several weeks ago. (Whoever interested, do a Google Groups search on
"Quartus II fast fit option".)
However, the opinions I expressed were my own from my experience using
both tools, and I don't work for Xilinx.




Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)



"Peter Ormsby" <faepete.deletethis@attbi.com> wrote in message news:<G8dq8.1341$M.502709@typhoon.mn.ipsvc.net>...
> If you'd left out the "Webpack",  this would all be really easy.  The Altera
> tools can do this with the LogicLock feature, even exporting floorplanned
> modules to be used in other designs and in other devices.  Practically
> unlimited parent-child-grandchild-etc relationships are supported.  If
> you're not committed to Xilinx devices, you might want to take a look at
> Altera's solution.
> 
> -Pete-
>

Article: 41580
Subject: Re: Configuring the Virtex II FPGA
From: "Steve Casselman" <sc.nospam@vcc.com>
Date: Tue, 02 Apr 2002 21:03:47 GMT
Links: << >>  << T >>  << A >>
Yes if the prom is in the chain you'll need to tell your tool about it.

Steve


"Terry" <yaot@hotmail.com> wrote in message
news:301c8b44.0204011113.494ddad7@posting.google.com...
> Hi all,
>
> I am testing my designs using the Insight MicroBlaze development board
> with the Virtex II 1 million gate FPGA.  When configuring the FPGA
> directly (ie. bypassing PROM) using the JTAG port, I first attempt to
> establish communication through reading the idcode.  I received an
> error message from iMPACT that the device idcode doesn't match the
> idcode in the bsdl file.  I'm guessing the problem is related to
> bypassing the ISP PROM, and I should perhaps associate the ISP PROM
> with either a dummy .mcs file or a .bsd file to bypass it.  My
> question is:  can I just use the generic bsdl file available on the
> Xilinx site as the dummy .bsd file?  And if so, where should I save
> this file and how do I specify that it's targeted for the PROM?
>
> I'd appreciate any help on this matter,
>
> Terry



Article: 41581
Subject: Re: A petition for Synplify's new fature (FPGA synthesis tool)
From: "sweir" <weirsp@yahoo.com>
Date: Tue, 02 Apr 2002 21:52:37 GMT
Links: << >>  << T >>  << A >>
Hamish, we agree that it is silly for the synthesis tool to chase a
simulator aberration.

In the case of replicating registers for fan-out control, the tool simply
multiplies the a declared instance number by N.  It does not create a new
logical storage point.  This is quite different than creating a new storage
point which is what the push-through "feature".  When the tool does its
convolution, it extends the enable path with registers where none existed
before.  For what N is N * 0 > 0?

If you want to get a good giggle about the stupidity of this "feature", code
a RAM using an array, but source it with a tri-state bus.  Sure enough, the
"Timothy Leary" mode creates a duplicate array in discrete registers to
store the enable state at write time for each RAM word.  Do this for a block
RAM, and you can suddenly fill your part with registers.  However, if you
encapsulate the RAM part of the code in a component, you just get a RAM
element.

I hope that it becomes clear to Synplicity that protecting people who don't
understand the language from themselves is a no-win situation.  So far, they
have only managed to pollute a previously excellent tool with both silly and
inconsistent behavior.

Regards,

<hamish@cloud.net.au> wrote in message
news:3ca9aa76$0$11452$afc38c87@news.optusnet.com.au...
> In comp.arch.fpga sweir <weirsp@yahoo.com> wrote:
> > like any advocate of the Z push-through to explain how it is that in
either
> > VHDL or Verilog we can have store a result without first declaring a
Verilog
> > reg, or VHDL signal to hold that result?  Nowhere in any of the code
> > examples I have seen is there a declaration of that stored result that
> > Synplify dutifully produces.  Do these advocates recognize that their
> > position dictates a discrete 'Z' state register for every address
location
> > in a memory array where the data input is a tri-state bus?
>
> Synthesis adds and removes registers all over the place though.
> Duplicated registers for fan-out control, removed registers for area
> optimisation, extra registers for state machine encoding, etc.
> The synthesis result should behave as described by the code, but
> it is rarely a direct mapping. (I'm not saying that I think Z
> push-through is correct, only that I think this is a weak argument.)
>
> I find the idea of Z push-through a bit silly. VHDL is a hardware
> description language; you use it to describe hardware. Now Synplify
> is changing the behaviour of the hardware to match the behaviour
> of the language. The roles seem a bit reversed here.
>
> Hamish
> --
> Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>



Article: 41582
Subject: Simulator for xilinx Cores?
From: maxedman3503@yahoo.com (Max Edmand)
Date: 2 Apr 2002 14:36:22 -0800
Links: << >>  << T >>  << A >>
Hi everybody,

I'm wondering which simulation tool can be used 
to do behavioral simulation of a VHDL circuit which 
contains Cores from Xilinx Coregen. Porbably the first 
option is Xilinx ModelSim but we do not have the Unix
version of it (if it exists at all !).

So, could I use Synopsys Simulation tool? I think that's
the most available tool for me right now. does any body 
have experience of linking Xilinx cores with Synopsys 
simulation tool on Unix platform? I would assume i need to
add the xilinx core library path somewhere in synopsys... 

Any kinds of hint are highly appreciated,

Thanks a lot,
Max Edmand

Article: 41583
Subject: Re: powerpc in virtex2pro
From: Austin Lesea <austin.lesea@xilinx.com>
Date: Tue, 02 Apr 2002 15:04:39 -0800
Links: << >>  << T >>  << A >>
Ron,

You can put any soft processor core you want in the Virtex II, or II Pro, as long as
they are small enough to fit in the FPGA.

Of course, there are royalty issues when using the ARM core.

The PowerPC(tm IBM) license allows unlimited use of the PowerPC core in Virtex II
Pro.  And the license is free.  MicroBlaze is also free.

Austin

Ron Huizen wrote:

> Peter,
>
> Are you saying that putting an ARM core into a Virtex II is not doable,
> or just not practical?  Or are you only talking about the V2 Pro?
>
> ---------
> Ron Huizen
> BittWare
>
> Peter Alfke wrote:
> >
> > "Cyrille de Brébisson" wrote:
> >
> > > In our design we are using an ARM CPU. My question is:
> > > Can we put an ARM in the virtex 2 pro?
> > > Were can I find/buy an ARM cpu core source (or precompiled) file to program
> > > in my FPGA?
> > >
> >
> > Cyrille,
> > the answer to both your questions is: No.
> > The PowerPC in Virtex-II Pro is a "hard" implementation, packing the
> > microprocessor with its caches and MMU into the smallest possible silicon
> > area, <4 square millimeters.
> > What you seem to be looking for is a "soft" implementation, using the
> > programmable logic "fabric".
> > That solution is impractical for something as complex as PowerPC or even ARM.
> > It would take up an unreasonable portion of a large chip, and achieve mediocre
> > performance at best.
> > Xilinx offers a soft microprocessor, called MicroBlaze, especially tuned for
> > efficient implementation in the Virtex architecture. It is not as fast and
> > capable as PowerPC, but uses only ~900 slices.
> > "Half the size and twice the speed of NIOS" is the Xilinx slogan. Please, no
> > flames...
> >
> > Peter Alfke, Xilinx Applications


Article: 41584
Subject: Re: pricing and gate count info
From: kayrock66@yahoo.com (Jay)
Date: 2 Apr 2002 15:23:08 -0800
Links: << >>  << T >>  << A >>
Are you expecting to buy in quantity?  FPGA pricing (and pricing in
general) is a wild a wholly thing that many engineers don't
understand.  It often has more to do with competative forces that cost
of materials.  If you can, bid vendor X against vendor A.  After the
design-in, don't any price reduction unless "book price" happens to go
below what you've been paying.

And sound advice about what the other dude said, don't compare
marketing's idea of "gates" look at LUTs.

Regards

jzhang@vwebcorp.com (j zhang) wrote in message news:<faad8c19.0204012137.15f9297@posting.google.com>...
> Hello,
> 
>   I am evaluating FPGAs for my next project. Does anyone have
> a list of FPGAs, preferably from altera or Xilinx, and their pricing
> information and gate count info as well.
> 
> Thank,
> 
> JZ

Article: 41585
Subject: Re: Web pack (how to) ?
From: Kamal <>
Date: Tue, 2 Apr 2002 15:33:01 -0800
Links: << >>  << T >>  << A >>
Hello Loi,

The reason for the errors seems to be that if you are tapping off of a bus named DATA(7:0), 
with a net name of A(7).  This is illegal, as A(7) would need to come from A(7:0).  You could 
however tap off the bus with DATA(7), or send that net through a buffer and name the new net 
A(7).  Basically, A(7) is not a member of the bus DATA(7:0) so it can not be "tapped" off.

I hope this helps.

Regards,
Kamal

Article: 41586
Subject: Re: Web pack (how to)?
From: leotran@_*worldnet.att.net (Loi Tran)
Date: Tue, 02 Apr 2002 23:58:01 GMT
Links: << >>  << T >>  << A >>
I'm sorry.  I meant A(7:0).  And I want to tap off of that bus with A(7).

LT

>Hello Loi,
>
>The reason for the errors seems to be that if you are tapping off of a bus 
>named DATA(7:0), 
>with a net name of A(7).  This is illegal, as A(7) would need to come from 
>A(7:0).  You could 
>however tap off the bus with DATA(7), or send that net through a buffer and 
>name the new net 
>A(7).  Basically, A(7) is not a member of the bus DATA(7:0) so it can not be 
>"tapped" off.
>
>I hope this helps.
>
>Regards,
>Kamal

Article: 41587
Subject: Re: Simulator for xilinx Cores?
From: Ray Andraka <ray@andraka.com>
Date: Wed, 03 Apr 2002 01:00:21 GMT
Links: << >>  << T >>  << A >>
Use any simulator you want.  You just have to compile the
xilinxcorelib before you try using it.  The corelib is VHDL
files, and can be found under the xilinx install directory.
Keep in mind the coregen simulation uses behavioral models,
not the primitives or even the synthesized code.
Nevertheless, as long as you compile the library, it doesn't
matter which sim you use.

Max Edmand wrote:

> Hi everybody,
>
> I'm wondering which simulation tool can be used
> to do behavioral simulation of a VHDL circuit which
> contains Cores from Xilinx Coregen. Porbably the first
> option is Xilinx ModelSim but we do not have the Unix
> version of it (if it exists at all !).
>
> So, could I use Synopsys Simulation tool? I think that's
> the most available tool for me right now. does any body
> have experience of linking Xilinx cores with Synopsys
> simulation tool on Unix platform? I would assume i need to
> add the xilinx core library path somewhere in synopsys...
>
> Any kinds of hint are highly appreciated,
>
> Thanks a lot,
> Max Edmand

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin,
1759



Article: 41588
Subject: Re: ByteblasterMV EPM7064S voltage problem
From: Russell Shaw <rjshaw@iprimus.com.au>
Date: Wed, 03 Apr 2002 01:03:35 GMT
Links: << >>  << T >>  << A >>


Arbitrary wrote:
> 
> I am using a 5 meter long cable from the computer to the Byteblaster perhaps
> this is the cause of my problem. I thought that 5 meters was the longest
> recommendend cable length and since the table I work on is about 5 meters
> away from my computer this is what I used. I tried running a thick wire from
> the chassis of the computer to the circuit power supply but to no avail. To
> bad I was really hoping that I could have the programmer next to my work
> table. Anyone know of a way to resolve this other than using a shorter
> cable? I also checked that the chip I used was a 74HC244 which it should be
> according to the schematic in the ByteblasterMV manual. Anyway thanks for
> all the help you have given me.

Make sure your pcb is isolated from mains earth. Make another byteblaster
cable with every second ribbon-cable conductor a ground wire.

Article: 41589
Subject: Re: A petition for Synplify's new fature (FPGA synthesis tool)
From: allan_herriman.hates.spam@agilent.com (Allan Herriman)
Date: Wed, 03 Apr 2002 01:39:11 GMT
Links: << >>  << T >>  << A >>
On Tue, 02 Apr 2002 21:52:37 GMT, "sweir" <weirsp@yahoo.com> wrote:

>Hamish, we agree that it is silly for the synthesis tool to chase a
>simulator aberration.
>
>In the case of replicating registers for fan-out control, the tool simply
>multiplies the a declared instance number by N.  It does not create a new
>logical storage point.

Sure it can.  Consider the case of a synchroniser, in which the flip
flop is used for metastability resolution.  If this gets replicated,
the different copies don't necessarily get the same value all the
time.
The syn_keep attribute fixes this though (and saves much cursing
later).

Regards,
Allan.

Article: 41590
Subject: Re: Marquis of Queensbury Rules
From: Kevin Brace <ihatespam99kevinbraceusenet@ihatespam99hotmail.com>
Date: Tue, 02 Apr 2002 19:51:56 -0600
Links: << >>  << T >>  << A >>
I have gotten some personal attacks from a few die-hard Altera fans
because I made some negative comments about Altera's products. (About
the free tools available from Altera).
Not everyone is professional in this newsgroup.




Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)




Ray Andraka wrote:
> 
> Funny, I didn't see any of this here.  The folks participating in this forum
> have been very professional, courteous and mostly helpful.  Without that,
> the newsgroup would be a waste of time.
> 
> 
> --Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email ray@andraka.com
> http://www.andraka.com
> 
>  "They that give up essential liberty to obtain a little
>   temporary safety deserve neither liberty nor safety."
>                                           -Benjamin Franklin, 1759

Article: 41591
Subject: Re: [HELP] Can't Install Altera QuartusII 2.0 SP1
From: lyqin@cti.com.cn (Leon Qin)
Date: 2 Apr 2002 19:13:08 -0800
Links: << >>  << T >>  << A >>
Anybody can help me?

btw:
 My Quartus is:
    Version 2.0 build 188 01/22/2002 SJ Full Version

lyqin@cti.com.cn (Leon Qin) wrote in message news:<23c59085.0204012110.53673788@posting.google.com>...
> When I Try to install Service Pack1 on my machine(P3+Win98 OR
> P4+Win2000),I get a error Message:
>   "Quartus II 2.0 Full Version is not install on this machine.The
> Service Pack set will exit now."
> 
>    But I had installed Full Version QuartusII 2.0 on my machine.
>  
>    Why?

Article: 41592
Subject: Re: A petition for Synplify's new fature (FPGA synthesis tool)
From: "sweir" <weirsp@yahoo.com>
Date: Wed, 03 Apr 2002 03:25:51 GMT
Links: << >>  << T >>  << A >>
Allan,

I do not see the distinction that you attempt to draw.  The fact that timing
variations, ( could be async input, could be a crummy clock tree ), could
yield different results in different places still doesn't seem to address
the issue that to replicate, there must first be a signal or reg to copy.

The loopy Synplify behavior doesn't make a copy of an existing element, it
invents in order to mimic a simulator hallucination.  Timothy Leary
apparently didn't die after all.  He is apparently alive and well tending
Synplicity's water cooler.

Regards,
"Allan Herriman" <allan_herriman.hates.spam@agilent.com> wrote in message
news:3caa5c4a.73829501@netnews.agilent.com...
> On Tue, 02 Apr 2002 21:52:37 GMT, "sweir" <weirsp@yahoo.com> wrote:
>
> >Hamish, we agree that it is silly for the synthesis tool to chase a
> >simulator aberration.
> >
> >In the case of replicating registers for fan-out control, the tool simply
> >multiplies the a declared instance number by N.  It does not create a new
> >logical storage point.
>
> Sure it can.  Consider the case of a synchroniser, in which the flip
> flop is used for metastability resolution.  If this gets replicated,
> the different copies don't necessarily get the same value all the
> time.
> The syn_keep attribute fixes this though (and saves much cursing
> later).
>
> Regards,
> Allan.



Article: 41593
Subject: Re: Clock termination affecting JTAG interface
From: "Barry Arneson" <barneson@dtgnet.com>
Date: Tue, 2 Apr 2002 22:38:22 -0600
Links: << >>  << T >>  << A >>
Ther is a much simpler method of solving your over and under shoot problem.

Place a series resistor, 33 or 50 ohms or whatever value tames down the
output drive of the clock.  Place it as close to the clock output pin as you
can.

Thats it, Barry

"Martin Schoeberl" <martin.schoeberl@chello.at> wrote in message
news:jrCm8.96126$4h6.978693@news.chello.at...
> > There is a 19.6608MHz Crystal Oscillator Module running on the 5V rail,
> > which provides a clock to the four Xilinx chips. This clock rings more
> > than I would like, so I wish to terminate it using pads included in the
> > design for this reason.
>
> One 'primitiv' suggestion: use a simple RC low pass in the clock line
(e.g.
> fg=60MHz).
>
> I'm not shure, if this is a good way. Just have seen it on a board and the
> clock looks
> fine (after the LP).
>
> Martin
>
>



Article: 41594
Subject: ACEX maximal clock...
From: "S³awomir Balon" <antyspam.bsl@post.pl>
Date: Wed, 3 Apr 2002 07:55:03 +0200
Links: << >>  << T >>  << A >>
Hi!
I'm planning to use ACEX devices in my designs. Can anyone tell me what is
maximum clock frequency for -2 and -3 devices?
I mean external clock input (without clock-lock option).
thanx
Slawek



Article: 41595
Subject: Re: [HELP] Can't Install Altera QuartusII 2.0 SP1
From: fastgirl70@hotmail.com (Girl)
Date: 2 Apr 2002 22:08:59 -0800
Links: << >>  << T >>  << A >>
Try uninstalling Quartus II v2.0 and re-install it, then install the
service pack and it should work.



lyqin@cti.com.cn (Leon Qin) wrote in message news:<23c59085.0204021913.7c175f07@posting.google.com>...
> Anybody can help me?
> 
> btw:
>  My Quartus is:
>     Version 2.0 build 188 01/22/2002 SJ Full Version
> 
> lyqin@cti.com.cn (Leon Qin) wrote in message news:<23c59085.0204012110.53673788@posting.google.com>...
> > When I Try to install Service Pack1 on my machine(P3+Win98 OR
> > P4+Win2000),I get a error Message:
> >   "Quartus II 2.0 Full Version is not install on this machine.The
> > Service Pack set will exit now."
> > 
> >    But I had installed Full Version QuartusII 2.0 on my machine.
> >  
> >    Why?

Article: 41596
Subject: Re: floorplanning for FPGA
From: fastgirl70@hotmail.com (Girl)
Date: 2 Apr 2002 22:20:33 -0800
Links: << >>  << T >>  << A >>
Try using app note 161 from Altera which shows how to use the
LogicLock feature they have.  It is listed in one of the menus in the
user interface.  It explains the basics of block level floorplanning. 
If you are doing a large SRAM design it's very useful.




"niv" <niv@ntlworld.com> wrote in message news:<0ehq8.717$fy.487866@news11-gui.server.ntli.net>...
> Try the Mentor website under LeoSpec. I know they do some App. notes for
> Xilinx floorplanning in conjunction with LeoSpec.  They'll almost certainly
> do some Altera stuff as well.
> 
> Niv.
> 
> sadik <sadik@controlnet.co.in> wrote in message
> news:b8c17961.0204020350.5f3d1f77@posting.google.com...
> > I'm looking for an introduction to floorplanning for FPGA
> > designs.  Can anyone suggest a good reference?  I'm designing for a
> > ALtera apex 20ke leonardo spectrum and quartus II ver 1.0 for UNIX
> >   Thanks!

Article: 41597
Subject: Design of a complex filter used in Bluetooth receiver.
From: "Kelvin Xu Qijun" <qijun@okigrp.com.sg>
Date: Wed, 3 Apr 2002 14:21:41 +0800
Links: << >>  << T >>  << A >>
Hi:

Anybody have information on how to design a complex filter used in Bluetooth
receiver?
I hope I can find any materials on both the theory and implementation in
digital form.
Thanks.

--
Best Regards,
-----------------------------------------------------------------
Xu Qijun
Engineer
OKI Techno Centre (S) Pte Ltd
Tel: 770-7049 Fax: 779-1621
Email: qijun@okigrp.com.sg



Article: 41598
Subject: Re: Handel-C vs SystemC
From: go_stock_boy@yahoo.com (Jeanan Del)
Date: 2 Apr 2002 22:43:19 -0800
Links: << >>  << T >>  << A >>
> What I don't get is your beef about the Handel-C language.  You can
> get a copy of the Handel-C language reference manual from the Celoxica

The manual is nice but it's what absent that ticks me off is.

You must buy the friggin Handel-C simulator  etc. from Celoxica- if
these guys we serious, they would give the simualtor away open source
similar to SystemC. At the very minimum they should disavow any patent
righte pertaining to Handel-C, which again, they haven't done, so
using the Handel-C language is like playing with a grenade.

>I don't know where your interpretation of
> the 'industry standard' is coming from - not from designers.

Of course it's coming from a design perspective. - When I go to
looking for a safe design solution, I want to see lots of tool / IP
companies supporting, not just a teensy single source.  That's why I
was hoping Celoxica would support SystemC since I truly would like to
use their stuff, but also system desig tools from Cadence, Mentor,
Synopsys..  See :
http://www.systemc.org/docman2/ViewCategory.php?group_id=4&category_id=10

Article: 41599
Subject: Re: Configuring the Virtex II FPGA
From: "jakab tanko" <jtanko@ics-ltd.com>
Date: Wed, 3 Apr 2002 02:02:17 -0500
Links: << >>  << T >>  << A >>
First thing I would initialize the chain from iMpact; after that you should
see both the eprom and the fpga.
iMPACT lets you assign programming files to each, (.mcs for eprom, .bit for
V2),
You should also be able to configure any of these two devices independent of
each other!
One thing that is a bit tricky is that the statup clock has to be set to
CCLK when you
generate the bit file for the eprom (used to convert to .mcs) and it should
be set to JTAG clk
when you generate the .bit file for the V2
hope this helps,
jakab
p.s I guess I didn't answer your question, ...I never had any complaints
from iMPACT
about bsdl files, is your ISE up to date ?

Terry <yaot@hotmail.com> wrote in message
news:301c8b44.0204011113.494ddad7@posting.google.com...
> Hi all,
>
> I am testing my designs using the Insight MicroBlaze development board
> with the Virtex II 1 million gate FPGA.  When configuring the FPGA
> directly (ie. bypassing PROM) using the JTAG port, I first attempt to
> establish communication through reading the idcode.  I received an
> error message from iMPACT that the device idcode doesn't match the
> idcode in the bsdl file.  I'm guessing the problem is related to
> bypassing the ISP PROM, and I should perhaps associate the ISP PROM
> with either a dummy .mcs file or a .bsd file to bypass it.  My
> question is:  can I just use the generic bsdl file available on the
> Xilinx site as the dummy .bsd file?  And if so, where should I save
> this file and how do I specify that it's targeted for the PROM?
>
> I'd appreciate any help on this matter,
>
> Terry





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