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Messages from 40000

Article: 40000
Subject: Re: Coolrunner and ISP
From: rickman <spamgoeshere4@yahoo.com>
Date: Sun, 24 Feb 2002 00:39:28 -0500
Links: << >>  << T >>  << A >>
Hal Murray wrote:
> 
> >>  A JTAG MUX is only likely to change with a major silicon rev, on
> >> one of the big devices, and even then, it's likely to be a superset,
> >> not a subset.
> >
> >Unless we find a mistake or we realize something that we overlooked...
> >I can't remember the last time that there were NO changes throughout a
> >product life.
> 
> I thought the idea was to use a (small) PLD to juggle the JTAG chain.
> That seems simple enough so that the risk of not being able to
> (easily) reprogram that PLD during the life of a board is worth taking.

Yes, but we don't know what our target is.  We would be trying things to
see what works with which tools.  When a tool changes, the SPLD solution
may need to change.  


> >I have been wracking my brain to come up with a way to make this all
> >fit.  A 2mm connector still does not save me enough space to have three
> >scan chains and the extra signals for the second emulator.  Remember,
> >this is only 20% smaller than a .1" connector.  Also this becomes
> >totally incompatible with the DSP emulator cable which my customers will
> >need to use.
> 
> That's what they are paying you for.  :)

I know you are kidding, but not exactly.  We are selling hardware to
companies that have volumes too low to justify building their own
hardware.  But they will do their own software.  


> My reading is that JTAG still has a lot of growing up to do.  Until
> it lives up to the hype, board designers are going to get stuck with
> crap like this.

I understand what you are saying.  But JTAG seems to work fine within
the 1149.1 spec.  But it leaves the door open for vendors to add their
own extensions such as emulators.  Then some vendors don't provide
support for operation of these "special" tools in a scan chain, only
stand alone.  Xilinx seems to be one who makes an effort to support
programming and boundary scan in the same scan chain.  TI provides lots
of documentation on emulation and scan chains and the software seems to
support it.  But when you talk to a support person, they tell you it is
better if you don't try it.  Others, like Atmel with their AVR MCUs,
provide tools that flat out don't support operation in a scan chain. 
Some, like the TI MSP430, have a JTAG port, but only support their own
features and do not support 1149.1 boundary scan!!! 


> I think the best you can do is one JTAG connector and some way
> to select the device you want to talk to and bypass the ones
> that will confuse the development software.  The straw man
> is a connector with all the TDI/TDO signals so you can add
> jumpers as appropriate.
> 
> Be sure to check the fine print on the "standard" JTAG
> conector for each development system you plan to use.  The
> 2 or 3 that I've worked with have been slightly different.
> 
> Don't forget to pay attention to the clocks.
> 
> Does anybody know if JTAG works as expected for boundary scan
> when several different devices are on the chain?  Say a DSP
> and an FPGA?

TI emulators "mostly" seem to work when used in a scan chain, but I hear
that you can expect issues.  Like I said above, the Atmel AVR won't work
any way but dedictated.  I have not been able to find out if it is
emulator hardware or software.  They say their chips fully support
boundary scan.  Just don't try to debug code on your board. 


-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 40001
Subject: about EPLD Rules and FLEX Rules
From: shenyun78@263.net (strong)
Date: 23 Feb 2002 23:49:23 -0800
Links: << >>  << T >>  << A >>
I use MAXPLUS to work.In MAXPLUS,I do not know the difference between 
EDLP Rules and FLEX Rules,so please explain me the difference.
  THANKS

Article: 40002
Subject: EPLD RULES AND FLEX RULES
From: shenyun78@263.net (strong)
Date: 24 Feb 2002 00:05:07 -0800
Links: << >>  << T >>  << A >>
I use MAXPLUS to work,but I do not know the difference between EPLD RULES 
and CPLD RULES in MAXPLUS's design doctor setting,so please explain me the
difference.
 THANKS.

Article: 40003
Subject: Re: Coolrunner and ISP
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Sun, 24 Feb 2002 10:13:15 +0000
Links: << >>  << T >>  << A >>


Hal Murray wrote:

> > The trick is that TDO is High-Z if TMS isn't asserted.
>
> Neat/thanks.
>
> Is that true for all parts using JTAG?  (Or just some/most
> of them?)
>
> I just took a quick scan at a few data sheets.  One said the TDO
> pin could go tri-state but didn't give any hints (or timing diagrams)
> on how to do it.  The other said it was pure output - no suggestion
> of any disable.
>
> --
> These are my opinions, not necessarily my employer's.  I hate spam.

If this isn't universal at least it points the way to a minimum SPLD - a
TMS demux & TDO mux - that should be stable.


Article: 40004
Subject: Re: EPLD RULES AND FLEX RULES
From: Frank Vorstenbosch <frank@kingswood-consulting.co.uk>
Date: Sun, 24 Feb 2002 10:49:12 +0000
Links: << >>  << T >>  << A >>
strong wrote:

> I use MAXPLUS to work,but I do not know the difference between EPLD RULES 
> and CPLD RULES in MAXPLUS's design doctor setting,so please explain me the
> difference.

These just enable predefined sets of warnings, you can see the warnings
that are enabled and disabled change if you open the Advanced Options
thing in the Design Doctor window.

Look in help for "Checking Project Reliability with the Design Doctor"
where each of the rules (or warnings) is explained.

Frank
-- 
------------------------------------------------------------------------
Frank A. Vorstenbosch   <SPAM_ACCEPT="NONE">    Phone:  +44-7976-430 569
Wimbledon, London SW19                  frank@kingswood-consulting.co.uk


Article: 40005
Subject: Re: CPLD PROJECT
From: edick@hotmail.com (Richard Erlacher)
Date: Sun, 24 Feb 2002 17:00:25 GMT
Links: << >>  << T >>  << A >>
If you have a really good ALU design and a solid and thrifty
architecture, you should easily be able to fit a small CPU that uses
limited resources, e.g. the 6502 core, into a CPLD.  I'm not sure that
you'll be able to put much RAM in there, however, so allow enough pin
count for an external RAM interface.  The registers should easily fit
inside, and, though a CPLD will have enough resources to do it, you
won't need to build synchronous counters because you should use the
ALU to do the address arithmetic as well as the data arithmetic/logic.


Think about how to keep the ALU doing all the work, with single
register operands and you'll get it to fit.  

The guys who are steering you toward FPGA's are right, BTW, except in
that you can, indeed make this sort of thing work in a CPLD, though it
may need to be a pretty big one.  

If you start with the instruction set and design it with an eye to
what can be done with a SMALL ALU, one which consists of an
adder/subtractor and a large number of multiplexers to do the
shift/rotate operations, and attach a register set to it, perhaps even
a redundant one, which means lots of macrocells (or you could simply
use an external SRAM), and let your mind explore what you can do with
multiplexing and with fast adder/subtractor design, you'll find you
can do this.  The key lies in that your registers will be latches
rather than clocked elements, and your timing will be determined by
the propagation through the ALU, since that has to happen twice for
each instruction, assuming every instruction cycle uses the ALU twice.

good luck!

Dick


On 22 Feb 2002 05:59:17 -0800, yoram@puc.cl (Yoram Rovner) wrote:

>Hi:
>
>I am a newbie on fpga issues and I need some recomendations. I am
>planning to develop a cpu in a cpld. I have XESS XS95 board v.1.3 and
>the student edition of Xilinx Foundation 1.5. I had some experiences
>in programing with verilog so i will like to do this cpu in that
>language. I have heard that Xilinx foundation student edition do not
>provide a good tool for developing with verilog (i mean error reports,
>etc). Would be better to use Webpack ise?, is there another
>software(maybe free or low cost) that is recommended to use?
>
>
>Thanks,
>
>
>Yoram Rovner


Article: 40006
Subject: Re: Few pins but more gates
From: rickman <spamgoeshere4@yahoo.com>
Date: Sun, 24 Feb 2002 12:48:01 -0500
Links: << >>  << T >>  << A >>
Actually, the trend is to put more logic into parts with smaller IO
counts.  This is from one generation to the next, not within a logic
family.  But they don't seem to support the smallest sockets with
anything but the smallest parts.  I have an application that is crying
for FPGAs in very small 100 pin packages.  But the smallest package I
can find is the TQ or VQ100 which is a quad flat pack and too big.  Some
FPGAs come in CS144 packages, but they tend to be more expensive.  

But the newer families are putting more and more gates in the same
packages with the same IO counts. 


svhb wrote:
> 
> This is a general problem with FPGA's, everyone makes components with
> hundreds of I/O on nice and small ball grids. If you make designs with
> serial interfaces to keep the nulmber of connections low (e.g. on industiral
> machinery, ...), you end up with more logic.
> 
> So I think they use the "number of IO pins" in the opposite way for
> commercial reasons. It must be : the more logic you want, the less IO you
> need.
> 
> "Frank Vorstenbosch" <frank@kingswood-consulting.co.uk> wrote in message
> news:3C72C32B.3000105@kingswood-consulting.co.uk...
> > Hallo!
> >
> > I'm trying to put my small design into a MAX3064ATC44 but would really
> > like more than the 64 registers this device offers me.  I do want to
> > keep the 44 pin TQFP, but maybe 96 or even 128 registers would be nice.
> >
> > Any suggestions?
> >
> > Frank
> > --
> > ------------------------------------------------------------------------
> > Frank A. Vorstenbosch   <SPAM_ACCEPT="NONE">    Phone:  +44-7976-430 569
> > Wimbledon, London SW19                  frank@kingswood-consulting.co.uk
> >

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 40007
Subject: Re: init RAM in VirtexII
From: newman5382@aol.com (newman)
Date: 24 Feb 2002 09:55:03 -0800
Links: << >>  << T >>  << A >>
"Seb" <no@valid.address.com> wrote in message news:<aamd8.12498$Wm3.573680@zwoll1.home.nl>...
> I want to initialise the memory core that i made with CoreGen. This can be
> done by making a .coe file before building the core. So if i want to change
> the initialisation data, i have to rebuild the core...again and again.
> 
> My question: is it possible to construct the core with a pointer to the .coe
> file, so that the content is included in a later stage (by ISE)...this way
> it would be possible to change the .coe file without having to rebuild the
> memory core.
> 
> thanx.
> cheers,
> Seb

Seb,

Rumour was that JBITs can be used to change the coefficients used to
initialize RAM after P&R.  I did a little investigation a year ago.  I
think you can send questions to jbits@xilinx.com.  Below is an excerpt
of a message I got from them a while back.  I never got beyond the
investigation stage.

Newman
-----------------------------------------------------------------------

Below are links to our FTP site for Windows, Solaris and Linux. While
we don't officially support Linux, we have many customers using JBits
on Linux. No problems have been reported, except during some
installations. If you experience a problem installing, use one of the
other installation versions and copy it over to your Linux machine.

********************************************************** 
Attention: You must have a 1.2 JDK installed before you install JBits.
We build and test our release with the JavaSoft 1.2.2 Production
Release. The various JDK's are available free from the JavaSoft
website. The 1.3 JDK will not work!
**********************************************************

Article: 40008
Subject: Re: Virtex-II and SDRAM Controller at 133MHz
From: rickman <spamgoeshere4@yahoo.com>
Date: Sun, 24 Feb 2002 12:56:01 -0500
Links: << >>  << T >>  << A >>
Ray Andraka wrote:
> 
> You should be able to pull it off, especially if pipeline latency is not an issue.  We are
> doing a 133MHz SDRAM interface as part of a video processor in spartanII for a customer next
> month, and are not particularly worried about it.  Make sure your board layout is good, and if
> driving more than one chip make sure the lines are properly terminated.  If it is a single
> SDRAM on a private interface to the FPGA, you can get probably away without terminators if you
> are careful with the board layout and route.


I was not aware that terminators were being used on SDRAM busses.  This
will be a bus with both the DSP and the FPGA driving and three different
memories as slaves (Flash, SBSRAM and SDRAM).  The one thing in my favor
is that the board is very small (PC/104, 4" x 4") and so the runs should
all be very short.  My understanding is that I should be able to get
away with no terminators if the runs are kept shorter than 1/6 the rise
time.  I believe I read that rule-of-thumb in one of Howard Johnson's
magazine articles.  With a 2 nS rise time, I would have about 4" of run
before I had to start worrying about signal integrity.  I will have to
pay close attention to this.  

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 40009
Subject: Re: init RAM in VirtexII
From: "Seb" <no@valid.address.com>
Date: Sun, 24 Feb 2002 19:40:11 +0100
Links: << >>  << T >>  << A >>
> A method to achieve the goal is to use the INIT attribute in the VHDL
> description.
> Or in the UCF.

hmmm...sounds good...i'll check it out. thank you.

cheers,
Seb



Article: 40010
Subject: Re: IIR. convolution
From: "MANDY & DOUGLAS" <mandy_ridge@prodigy.net>
Date: Mon, 25 Feb 2002 03:33:16 GMT
Links: << >>  << T >>  << A >>
Depends on the application. Basically an IIR filter can give a similar
response to an FIR filter. The use of an IIR in place of an FIR makes sense
when any implementation of the FIR would cause it to become too expenseive
to implement - typically high numbers of taps at high data rates. There are
lots of books on the subjects of filtering that I'm sure some other readers
of this site can recommend.

"Alkos Nikos" <alkosd@yahoo.co.uk> wrote in message
news:24b1bde3a9b9f5b214e841e536d8a5a7.57871@mygate.mailgate.org...
> basic question, could we tell that IIR performs a convolution operation
> as FIR does
> thanks
>
>
> --
> Posted via Mailgate.ORG Server - http://www.Mailgate.ORG
>



Article: 40011
Subject: Announce: pdcodes-0.01 Beta Release: CRC code modeling
From: Alan J. Coppola <ajjc@nwlink.com>
Date: Sun, 24 Feb 2002 21:15:59 -0800
Links: << >>  << T >>  << A >>
Announcing the beta release of  pdcodes-0.01 at:

http://www.nwlink.com/~ajjc

The pdcodes program is a public domain system for generating and verifying 
implementation models of mathematical coding systems. It is useful for 
people who want to design, simulate, and synthesize hardware models of the 
coding systems, and gives the ability to cross-verify all of the models 
using a common input file.

The first, and currently only, coding system implemented in pdcodes is the 
CRC (Cyclic Redundancy Check) code. Given a generating polynomial, a 
pipeline size, a set of initialization parameters, and an input data file, 
pdcodes will generate a VHDL model and testbench of the given code 
instance, and perform the cross-verification of that code on any given 
user-defined data set.

It will allow you to take a user-defined data file, run a well known public 
domain software C-language model of the CRC code, followed by running a 
math model of the same code, which generates a VHDL model and testbench, 
and finally simulate the VHDL model and testbench using a VHDL simulator.

Please see the README file on the above website for installation and 
prerequisites information.

Thanks!
Alan Coppola
Mathcadix Software






Article: 40012
Subject: Altera FPGA MISC Pipeline
From: "tyew" <teong.guan.yew@intel.com>
Date: Mon, 25 Feb 2002 13:59:32 +0800
Links: << >>  << T >>  << A >>
Hi,

Anyone has the source code for RISC Pipeline in altera FPGA board.

Thanks.



Article: 40013
Subject: Is it possible to have an output FF in IOB, but a tri-state control FF
From: Kevin Brace <ihatespam99kevinbraceusenet@ihatespam99hotmail.com>
Date: Mon, 25 Feb 2002 01:52:01 -0600
Links: << >>  << T >>  << A >>
I am wondering if it is possible to have an output FF in an IOB, but a
tri-state control FF outside of an IOB in Xilinx Virtex family of FPGAs?
The reason I care about this is because I still need to keep output FF's
Tco (Tval) low (That's why I still want to use the IOB output FF.), but
want to use CLB's FF to handle output tri-state buffer control to
improve the setup time of the tri-state control FF.
I know that both FFs can be in a CLB, or inside an IOB, and I already
know how to do that.



Thanks,



Kevin Brace (Don't respond to me directly, respond within the
newsgroup.)

Article: 40014
Subject: Re: RAM question
From: dottavio@ised.it (Antonio)
Date: 24 Feb 2002 23:59:12 -0800
Links: << >>  << T >>  << A >>
Looking at this post with more attenction It comes to me a doubt, it
is about Ray affermation :
  " The block RAMs have fairly long tsu, th and tco numbers compared
to the CLB flip-flop "

but this means that if instead of block RAMs I use the ROM that XST
infer when I use a vhdl CASE , I can obtain a faster design ??

Article: 40015
Subject: Floorplanner and then ??
From: dottavio@ised.it (Antonio)
Date: 25 Feb 2002 00:00:27 -0800
Links: << >>  << T >>  << A >>
After P&R I made the floorplan of my design, where I simply take the
blockram and put inside
the device then I take the register and put it near the respective
blockram, at the end of the job I save
the result with name ram_registered.fnf .
How I could use this like input to the P&R process accordingly to the
fact that I have not placed everything with the floorplanner ??

Article: 40016
Subject: Synplify warning that I don't understand
From: dottavio@ised.it (Antonio)
Date: 25 Feb 2002 00:01:19 -0800
Links: << >>  << T >>  << A >>
I've realized a circuit with the following behaviour :

	clk  -> out_mca[11:0] =  in_mca[11:0]
	clk  -> out_mca[11:0] =  in_mca[11:0]
	clk  -> out_mca[11:0] = -in_mca[11:0]
	clk  -> out_mca[11:0] = -in_mca[11:0]

	....

	clk  -> out_mca[11:0] =  in_mca[11:0]
	clk  -> out_mca[11:0] =  in_mca[11:0]
	clk  -> out_mca[11:0] = -in_mca[11:0]
	clk  -> out_mca[11:0] = -in_mca[11:0]

from Synplify I've a warning that I don't understand , it is :

  @W: mult_C2_adder.vhd(43): Feedback mux created for signal
out_mca[11:0]. Did you forget the set/reset assignment for this
signal?

Can you help me to understand it, here's the code :


library	ieee;
use ieee.std_logic_1164.all;						
use ieee.std_logic_signed.all;

entity mult_C2_adder is
	port(in_mca :	in std_logic_vector(11 downto 0);	
		reset   :   in  std_logic ;
		clk     :   in  std_logic ;
		out_mca	:	out std_logic_vector(11 downto 0));
end mult_C2_adder;

architecture mult_C2_adder_arch of mult_C2_adder is
	signal TEMP_count 	: std_logic_vector(1 downto 0);
begin				  

	process(clk, reset)
	begin
		if reset = '1' then
			TEMP_count  <= "11";   
		elsif rising_edge(clk) then
			TEMP_count  <= TEMP_count + 1;				
		end if;
	end process;

	
	process(clk, reset, TEMP_count(1), in_mca)
		variable temp  : std_logic_vector(11 downto 0);
	begin
		if reset = '1' then
			out_mca <= "000000000000" ;
		elsif rising_edge(clk) then
			temp(11 downto 0) := in_mca ;
			if TEMP_count(1) = '1' then
				temp := ("111111111111" xor temp)+1 ;
			end if;
		end if;
		out_mca <= temp ;
	end process;
	
end mult_C2_adder_arch ;

Article: 40017
Subject: Re: PCI/FPGA evaluation board
From: Matthias Scheerer <scheerer@uni-mannheim.de>
Date: Mon, 25 Feb 2002 09:41:15 +0100
Links: << >>  << T >>  << A >>
Hi Jesus,

I'm actually working with an older avnet (http://www.avnet.com) PCI
board. It has a Virtex 300, 512kB SRAM, 2 MB Flash, 16 MB SDRAM and some
other peripherals like IEEE1394, VGA RAMDAC, RS232 driver, 50 Pin
extension connector ...
Only disadvantage: It is not sold anymore. But maybe there is a new one
meeting your requirements. I don't know wether PCI core was included or
not. IDE wasn't.
The board was my choice because of the 64bit/66MHz PCI interface when
using the XILINX PCI LogiCore.

Greetings
Matthias

Jesus Molina wrote:
> 
> Hello,
> 
> I am trying to find a PCI / FPGA development  board. I have already seen
> some of then at the Xilinx webpage. I will really appreciate some advice,
> as I am new to the FPGA world.
> 
> In the board I need at least a PCI core, IDE controller core (
> both implemented in an FPGA) Flash and SDRAM memory, and a processor
> or some type of way to expand the board to add a processor.
> 
> Sample boards I have found are the H.O.T II distributed by Virtual
> Computer Corporation or the ones distributed by nallatech.
> Thanks for your help,
> 
> Jesus

-- 
Matthias Scheerer        (mailto:scheerer@uni-mannheim.de)
University of Mannheim - Computer Architecture Group
68161 Mannheim - GERMANY (http://mufasa.informatik.uni-mannheim.de)
Phone: +49 621 181 2721  Fax: +49 621 181 2713

Article: 40018
Subject: Re: Implementing MD5 in hardware (Handel C, VHDL)
From: "Panu H" <panuh@cc.tut.fi>
Date: Mon, 25 Feb 2002 10:41:33 +0200
Links: << >>  << T >>  << A >>
"LM" <moriartl@tcd.ie> wrote in message
news:ca4bf693.0202230035.15de5576@posting.google.com...
> Has anyone tried to implement MD5 or DES in Handel C, or in VHDL?
> What was your approach?

I've done DES in VHDL for a Xilinx FPGA. There are several different
approaches possible: iterative implementation with only one round block (one
round per cycle), different amounts of loop unrolling (i.e. more rounds per
clock cycle) and partial/full pipelining (one or more rounds per stage).
These make trade-offs between area, throughput and latency. Which ones are
applicable depends on your encryption mode. S-boxes can be implemented as
ROM or logic.

-- Panu




Article: 40019
Subject: Re: How can I disable clock buffer (BUFG) insertion in Xilinx Foundation F3.1i?
From: Martin Thompson <martin.j.thompson@trw.com>
Date: 25 Feb 2002 09:04:23 +0000
Links: << >>  << T >>  << A >>
dottavio@ised.it (Antonio) writes:
<snip>
> 
>   @W: mult_C2_adder.vhd(43): Feedback mux created for signal
> out_mca[11:0]. Did you forget the set/reset assignment for this
> signal?
> 
<snip>
> 	
> 	process(clk, reset, TEMP_count(1), in_mca)
> 		variable temp  : std_logic_vector(11 downto 0);
> 	begin
> 		if reset = '1' then
> 			out_mca <= "000000000000" ;
> 		elsif rising_edge(clk) then
> 			temp(11 downto 0) := in_mca ;
> 			if TEMP_count(1) = '1' then
> 				temp := ("111111111111" xor temp)+1 ;
> 			end if;
> 		end if;
> 		out_mca <= temp ;
> 	end process;


You are assigning out_mca the value of temp outside of your "if reset
elsif clock" section.  Therefore it gets assigned the value of temp
every time any of your sensitivity list changes, including reset.
This means that your reset clause for out_mca gets ignored.  Move the
out_mca <= temp line inside the elsif ... end if section.

Also, you don;t need tempcount(1) or in_mca in the sensitivity list,
as you only look at them when the clock changes, you don;t care
whether they change in the meantime.

Hope that helps!

Cheers,
Martin


-- 
martin.j.thompson@trw.com
TRW Conekt, Solihull, UK
http://www.trw.com/conekt

Article: 40020
Subject: Re: Synplify warning that I don't understand
From: Nicolas Matringe <nicolas.matringe@ipricot.com>
Date: Mon, 25 Feb 2002 10:11:24 +0100
Links: << >>  << T >>  << A >>
Antonio a écrit :
> 
[...]
>   @W: mult_C2_adder.vhd(43): Feedback mux created for signal
> out_mca[11:0]. Did you forget the set/reset assignment for this
> signal?
> 
> Can you help me to understand it, here's the code :
[...]
>         process(clk, reset, TEMP_count(1), in_mca)
>                 variable temp  : std_logic_vector(11 downto 0);
>         begin
>                 if reset = '1' then
>                         out_mca <= "000000000000" ;
>                 elsif rising_edge(clk) then
>                         temp(11 downto 0) := in_mca ;
>                         if TEMP_count(1) = '1' then
>                                 temp := ("111111111111" xor temp)+1 ;
>                         end if;
>                 end if;
>                 out_mca <= temp ;
>         end process;
> 
> end mult_C2_adder_arch ;

Hi
Your problem is in the last line of your process: out_mac <= temp should be
inside the if...elsif...endif statement.

Besides, I don't understand why you use a variable. Why don't you just write
if temp_count(1) = '1' then
  out_mca <= (x"FFF" xor in_mca) + 1;
endif;

You should also use numeric_std instead of std_logic_signed.

-- 
Nicolas MATRINGE           IPricot European Headquarters
Conception electronique    10-12 Avenue de Verdun
Tel +33 1 46 52 53 11      F-92250 LA GARENNE-COLOMBES - FRANCE
Fax +33 1 46 52 53 02      http://www.IPricot.com/

Article: 40021
(removed)


Article: 40022
Subject: Re: Is it possible to have an output FF in IOB, but a tri-state control FF outside of IOB?
From: sanket@insight.memec.co.in (Xilinx FAE from Insight SANKET)
Date: 25 Feb 2002 02:08:13 -0800
Links: << >>  << T >>  << A >>
Hi,
In "Xilinx Constraints Editor", go to the "Ports" tab.There in "IOBDelay"
column you can achieve what you want.Also in 4.1i ISE (XST) you can right
click on "Synthesis" in process window---click on " Properties" where there
is "Xilinx  Specific Options".Here use the option "Pack IO regs. in IOBs" .
Regards,
SANKET.



Kevin Brace <ihatespam99kevinbraceusenet@ihatespam99hotmail.com> wrote in message news:<a5cpua$876$1@newsreader.mailgate.org>...
> I am wondering if it is possible to have an output FF in an IOB, but a
> tri-state control FF outside of an IOB in Xilinx Virtex family of FPGAs?
> The reason I care about this is because I still need to keep output FF's
> Tco (Tval) low (That's why I still want to use the IOB output FF.), but
> want to use CLB's FF to handle output tri-state buffer control to
> improve the setup time of the tri-state control FF.
> I know that both FFs can be in a CLB, or inside an IOB, and I already
> know how to do that.
> 
> 
> 
> Thanks,
> 
> 
> 
> Kevin Brace (Don't respond to me directly, respond within the
> newsgroup.)

Article: 40023
Subject: Re: RAM question
From: sanket@insight.memec.co.in (Xilinx FAE from Insight SANKET)
Date: 25 Feb 2002 02:09:57 -0800
Links: << >>  << T >>  << A >>
Hi Antonio,

Distributed RAM is always faster than a Block RAM.
regds.
SANKET.



kayrock66@yahoo.com (Jay) wrote in message news:<d049f91b.0202041508.51c9c7dc@posting.google.com>...
> Your disappointment is not uncommon when engineers hear about the
> great numbers often touted by the marketing types.  The hundreds of
> megahertz numbers are acheived by careful placement and highly
> pipelines designs.  Your numbers on pretty typical.
> 
> Some things you might try for speed up are to use a 4096x 12 deep
> memory structure so that Coregen doesn't just replicate those muxes
> you built manually in the first place hen it tries to build a non
> modula 2 length structure.  It would hopefully use 3 4096x4 bit
> memories.  Register everything you can.
> 
> Regards
> 
> 
> dottavio@ised.it (Antonio) wrote in message news:<fb35ea96.0202032329.565fd310@posting.google.com>...
> 
> 
> 
> > In my project I'm using 3 set of values with different dimension, I
> > mean 384x12 bits , 512x12 bits and 768x12 bits , to choose between
> > them I could use a demux-BLOCKRAM-mux chain or to fit each of these
> > block in a zero padded 1024x12 bits and use the addressing
> > capabilities of a Virtex BLOCKRAM 3072x16. with very disappoint I
> > found that this last solution (implemented with the CORE blockRAM
> > single port) may run at a maximum of 60MHZ on a VIRTEX1000BG560-4 and
> > 90MHz on
> > VirtexE600-6 so my question is :
> > 1) is this normal ??
> > 2) when I read 300 MHz on FPGA are we talking of a flip flop ??
> > 3) this is the most important question :  how can I obtain more to
> > solve the same problem with
> > 	the VIRTEXE600-6  ??
> > 
> > Thanks
> > 
> >    Antonio

Article: 40024
Subject: Re: Floorplanner and then ??
From: sanket@insight.memec.co.in (Xilinx FAE from Insight SANKET)
Date: 25 Feb 2002 02:10:43 -0800
Links: << >>  << T >>  << A >>
Hi,
Go to the  " Xilinx Design Manager".Go to the "Design Menu".There you have
"Set Floorplan Files".There you can specify your *.fnf  and *.mfp.
regds.
SANKET.




dottavio@ised.it (Antonio) wrote in message news:<fb35ea96.0202250000.7bd4603f@posting.google.com>...
> After P&R I made the floorplan of my design, where I simply take the
> blockram and put inside
> the device then I take the register and put it near the respective
> blockram, at the end of the job I save
> the result with name ram_registered.fnf .
> How I could use this like input to the P&R process accordingly to the
> fact that I have not placed everything with the floorplanner ??



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