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Messages from 38175

Article: 38175
Subject: Re: FIR Linear Interpolation
From: Jonathan Bromley <Jonathan.Bromley@doulos.com>
Date: Tue, 8 Jan 2002 08:36:36 +0000
Links: << >>  << T >>  << A >>
In article <4tm_7.22154$Sf2.211946@rwcrnsc52>, Kevin Neilson
<kevin_neilson@removethis-yahoo.com> writes
>I have a FIR that can interpolate by M (64 in this case) and I wish to use
[snip]
>  Does anyone know how I can calculate how much noise
>is introduced by linear interpolation?

Although there are a couple of DSP experts hanging around here,
you are much more likely to get a useful response on one
of the DSP newsgroups.
-- 
Jonathan Bromley
DOULOS Ltd.
Church Hatch, 22 Market Place, Ringwood, Hampshire BH24 1AW, United Kingdom
Tel: +44 1425 471223                     Email: jonathan.bromley@doulos.com
Fax: +44 1425 471573                             Web: http://www.doulos.com

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Article: 38176
Subject: multiply (*) 11000000000
From: Kenily <aiurh@iuehr.erug>
Date: Tue, 8 Jan 2002 01:33:04 -0800
Links: << >>  << T >>  << A >>
i want to implement a multiplier.one  
multiply 0x600(Hex).how do i implement?

Article: 38177
Subject: Re: multiply (*) 11000000000
From: Nicolas Matringe <nicolas.matringe@ipricot.com>
Date: Tue, 08 Jan 2002 12:27:57 +0100
Links: << >>  << T >>  << A >>
Kenily a écrit :
> 
> i want to implement a multiplier.one
> multiply 0x600(Hex).how do i implement?

That's just an adder and a shifter.
-- 
Nicolas MATRINGE           IPricot European Headquarters
Conception electronique    10-12 Avenue de Verdun
Tel +33 1 46 52 53 11      F-92250 LA GARENNE-COLOMBES - FRANCE
Fax +33 1 46 52 53 01      http://www.IPricot.com/

Article: 38178
Subject: latch vs. register
From: Matthias Weber <msweber@onlinehome.de>
Date: Tue, 08 Jan 2002 11:55:29 GMT
Links: << >>  << T >>  << A >>
hi,

do i understand right that latches consists of simple flipflops without beeing clocked so that the circuit storesimmediately every change of signal.
is the difference between latches and registers that latter are clocked (constructed by D-, RS- or  JK-FlipFlops)?

thanks for information,

matthias weber



Article: 38179
Subject: Xilinx XC2000, XC3000, XC4000 families
From: Matthias Weber <msweber@onlinehome.de>
Date: Tue, 08 Jan 2002 12:13:28 GMT
Links: << >>  << T >>  << A >>
hi,


i have read about xilinxs fpga families and have a question about connections. it is shown, that 3 types of connections exists:

* directly connections between CLBs
* short connections via switching matrix
* connections via horizontal and vertical long lines

am i right, that global signals, like the clock are transported via long lines and that each CLB is connected to one/more of them?
are information signals (i mean the results of CLBs) are exchanged via switching matrix respectively via direct inter CLB connections?

thanks for help,

matthias



Article: 38180
Subject: Re: multiply (*) 11000000000
From: Keith R. Williams <krw@btv.ibm.com>
Date: Tue, 8 Jan 2002 10:05:05 -0500
Links: << >>  << T >>  << A >>
In article <ee74130.-1@WebX.sUN8CHnE>, aiurh@iuehr.erug says...
> i want to implement a multiplier.one  
> multiply 0x600(Hex).how do i implement?

How about the normal arithmetic?

Y = (X << 10) + (X << 9)
       ^      ^    ^
       |      |    |
       |      |    +- X Shifted left 9 bits
       |      |
       |      +------ Added to
       |
       +------------- X Shifted left 10 bits
 

Or put perhaps a little more simply: 

Y = (X << 1) + X | 000000000b
       ^     ^   ^
       |     |   |
       |     |   +---- Concatinated with 9 '0's 
       |     |  
       |     +-------- Added to X
       |
       +-------------- X Shifted left 1

----
  Keith  

Article: 38181
Subject: Re: Xilinx XC2000, XC3000, XC4000 families
From: Keith R. Williams <krw@btv.ibm.com>
Date: Tue, 8 Jan 2002 10:19:56 -0500
Links: << >>  << T >>  << A >>
In article <1103_1010492008@news.online.de>, msweber@onlinehome.de 
says...
> hi,
> 
> 
> i have read about xilinxs fpga families and have a question about connections. it is shown, that 3 types of connections exists:
> 
> * directly connections between CLBs
> * short connections via switching matrix
> * connections via horizontal and vertical long lines

4th type:

  * global routing resources.

> am i right, that global signals, like the clock are transported via long lines and that each CLB is connected to one/more of them?
> are information signals (i mean the results of CLBs) are exchanged via switching matrix respectively via direct inter CLB connections?

Clocks are normally routed on the global clock resources, not on long 
lines (though I believe you can do this). Clock skew in minimized by 
routing on global resources.  In the older technologies (XC4000) 
signals could be routed on the global clock nets as well.  I don't 
believe this can be done in the Virtex and newer.

Depending on the family, long-lines can be used for tri-state signals.

----
  Keith

Article: 38182
Subject: Re: Suitability of Atmel for project?
From: "Ulf Samuelsson" <ulf@atmel.REMOVE.com>
Date: Tue, 8 Jan 2002 16:37:07 +0100
Links: << >>  << T >>  << A >>
> It's actually several (up to 5).  Each is a pretty standard SPI-like
> synchronous serial interface running at about 150 kbps.  They are
> other boards that are on separate lines, not a shared bus (long
> story).  Anyway if all could come into UARTs then it would be great
> because there's not that much traffic, maybe 256 bytes / second
> throughput.  But without UARTs we have to bit-bang it and there's just
> not enough time to easily do more than 1 or 2 with the AVR.  I suppose
> that we could go to something with a much faster clock rate and be
> able to manage bit-banging with very fast task switching but to my
> mind it's just easier to hang a UART on each one and be done with it.
> Obviously we can also go to a different microcontroller that has
> multiple UARTs, or use separate UART chips, or an FPGA, lots of
> choices.
>
> One of the tasks of this board will be to multiplex these disparate
> data streams onto 1 HSS interface like it should have been in the
> first place, so the next poor engineer who gets thrown into the middle
> of this mess won't have this to contend with. :)
>

I think that if you run the mega8 SPI and a small PLD to mux, you should be
fine.
Since you say you plan to mux, I assume that you only use one at a time.
The mega8 has 1 kB of SRAM which is nice.


--
Best Regards
Ulf at atmel dot com
These comments are intended to be my own opinion and they
may, or may not be shared by my employer, Atmel Sweden.

> - Stout



Article: 38183
Subject: Virtex-II parallel LVDS demo board (FAO Austin Lesea?)
From: ian.dedic@acg.fujitsu-fme.com (Ian Dedic)
Date: 8 Jan 2002 08:53:56 -0800
Links: << >>  << T >>  << A >>
Hi Austin

I posted this before Xmas in an old thread so I guess nobody spotted
it...

About a year ago we designed an evaluation platform using Virtex-E to
source 624Mb/s 28-bit parallel data (2 DDR LVDS 14-bit buses) to drive
a high-speed dual DAC. This was a lot of grief and effort, and had
problems with skew on the data bus in spite of using a customised
Xilinx-supplied parallel LVDS macro.

One necessary feature to remove I/O and track/cable delays (since the
DAC had to be the clock master for jitter reasons) was that we took
the 312MHz clock out from the DAC as the DLL input clock, then sourced
a 312MHz clock from the Virtex (DDR clock synchronised to the data)
and looped it into the DAC and back out to the Virtex as the DLL
reference clock, so the DLL took out the delays.
 
Will this be possible on the Xilinx LVDS demo board, and when will the
board be available? I'm asking this because I know at least one
customer is using an Altera Mercury board (also not released yet?) to
source data, because there wasn't anything suitable available from
Xilinx.

Does the board use SMA connectors (so we could connect it directly)?

Is there any possiblility of a board with wider LVDS output (eg, 32
bit) being made available in the future?

Am I correct in assuming that Virtex-II could run like this up to
840Mb/s?

Ian Dedic
Chief Engineer
Mixed Signal Division
Advanced Communications Group
Fujitsu Microelectronics

Article: 38184
Subject: Re: WARNING
From: Brian Philofsky <brian.philofsky@xilinx.com>
Date: Tue, 08 Jan 2002 10:01:52 -0700
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
--------------19322DEDB0B9653635D8BC12
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit



Just add the `timescale yourself to the file.  Since there is no timing information in the file itself, the values should not make a difference but
if you want to be consistant with the FIFO model, put a value of 1ns/10ps.

I will see what I can do about getting this corrected in the future.


--  Brian


llossak wrote:

> yes ,i have added `timescale in my all verilog file with "include timescale .v",But this 'MEM_BLK' is generated by ISE4.1 coregen fifo include .
> here:
> /*******************************************************************
> * This file is owned and controlled by Xilinx and must be used     *
> * solely for design, simulation, implementation and creation of    *
> * design files limited to Xilinx devices or technologies. Use      *
> * with non-Xilinx devices or technologies is expressly prohibited  *
> * and immediately terminates your license.                         *
> *                                                                  *
> * Xilinx products are not intended for use in life support         *
> * appliances, devices, or systems. Use in such applications are    *
> * expressly prohibited.                                            *
> *                                                                  *
> * Copyright (C) 2001, Xilinx, Inc.  All Rights Reserved.           *
> *******************************************************************/
>
> // The synopsys directives "translate_off/translate_on" specified
> // below are supported by XST, FPGA Express, Exemplar and Synplicity
> // synthesis tools. Ensure they are correct for your synthesis tool(s).
>
> // You must compile the wrapper file na_fifo16_256.v when simulating
> // the core, na_fifo16_256. When compiling the wrapper file, be sure to
> // reference the XilinxCoreLib Verilog simulation library. For detailed
> // instructions, please refer to the "Coregen Users Guide".
>
> module na_fifo16_256 (
>         clk,
>         sinit,
>         din,
>         wr_en,
>         rd_en,
>         dout,
>         full,
>         empty);    // synthesis black_box
>
> input clk;
> input sinit;
> input [15 : 0] din;
> input wr_en;
> input rd_en;
> output [15 : 0] dout;
> output full;
> output empty;
>
> // synopsys translate_off
>
>         SYNC_FIFO_V3_0 #(
>                 1,      // c_dcount_width
>                 0,      // c_enable_rlocs
>                 0,      // c_has_dcount
>                 0,      // c_has_rd_ack
>                 0,      // c_has_rd_err
>                 0,      // c_has_wr_ack
>                 0,      // c_has_wr_err
>                 1,      // c_memory_type
>                 0,      // c_ports_differ
>                 1,      // c_rd_ack_low
>                 1,      // c_rd_err_low
>                 16,     // c_read_data_width
>                 256,    // c_read_depth
>                 16,     // c_write_data_width
>                 256,    // c_write_depth
>                 1,      // c_wr_ack_low
>                 1)      // c_wr_err_low
>         inst (
>                 .CLK(clk),
>                 .SINIT(sinit),
>                 .DIN(din),
>                 .WR_EN(wr_en),
>                 .RD_EN(rd_en),
>                 .DOUT(dout),
>                 .FULL(full),
>                 .EMPTY(empty),
>                 .RD_ACK(),
>                 .WR_ACK(),
>                 .RD_ERR(),
>                 .WR_ERR(),
>                 .DATA_COUNT());
>
> // synopsys translate_on
>
> // FPGA Express black box declaration
> // synopsys attribute fpga_dont_touch "true"
> // synthesis attribute fpga_dont_touch of na_fifo16_256 is "true"
>
> // XST black box declaration
> // box_type "black_box"
> // synthesis attribute box_type of na_fifo16_256 is "black_box"
>
> endmodule
>
> i find 'MEM_BLK' in $xilinx\verilog\src\xilinxcore_lib\ SYNC_FIFO_V3_0.v
>
> how do i add  `timescale commands  in 'MEM_BLK' ?



Article: 38185
Subject: Re: latch vs. register
From: Peter Alfke <peter.alfke@xilinx.com>
Date: Tue, 08 Jan 2002 09:25:27 -0800
Links: << >>  << T >>  << A >>
Tutorial:
A flip-flop consists of two latches, a master and a slave.

A latch accepts data when the Latch Enable is active, and stores data when LE is not active.
With LE active, the latch is transparent, its output follows the input.

A flip-flop combines two latches with opposite LE polarities, such that the master latch accepts incoming data when the clock is Low, and the slave
latch copies the master when the clock is High ( This is thus a rising-clock-edge edge-triggered flip-flop. The opposite clock polarity is also
possible).

A flip-flop is never transparent, its output can thus be fed back to its input without creating a race condition. That's why we need and love
flip-flops.

In FPGAs, all flip-flops are implemented as D-flip-flops. Any different type ( R,S,T) is constructed by additional logic in front of the D.

Peter Alfke

==========================
Matthias Weber wrote:

> hi,
>
> do i understand right that latches consists of simple flipflops without beeing clocked so that the circuit storesimmediately every change of signal.
> is the difference between latches and registers that latter are clocked (constructed by D-, RS- or  JK-FlipFlops)?
>
> thanks for information,
>
> matthias weber


Article: 38186
Subject: Re: 128 bit compare delay kill me!
From: John_H <johnhandwork@mail.com>
Date: Tue, 08 Jan 2002 18:20:55 GMT
Links: << >>  << T >>  << A >>
I was hoping to leverage the Virtex-II architecture to get some very nice
results with the horizontal cascade but the nature of the compare needs a
cascaded selection (like the MUXCY elements), not a cascaded OR.  The
compare can be broken up into two stages by moving the final result to the
front end of the next clock.

Since A[127:0] > B[127:0] can be broken down into segments such as

  A[127:96] > B[127:96] | A[127:96] == B[127:96] &
 ( A[95:64] > B[95:64] | A[95:64] == B[95:64] &
 ( A[63:32] > B[63:32] | A[63:32] == B[63:32] &
 ( A[31:0] > B[31:0] ) ) )

The structure *could* be implemented by registering the ">" and "=="
results from the segments above then chaining them together to produce the
combinatorial A>B with the MUXCY elements.  The designer needs to find the
right balance of first cycle compares to the next cycle chain length.
There might be a fancy equation to assemble the final stage rather than
hand-implementation but the generation is pretty straight forward.  It's
good, hard coding at its best.

- John


Yu Jun wrote:

> I notice a 128bit comparator is a timing-cost path in a FPGA.
>
> For example,
>
> case1: A[127:0] == B[127:0]
>
> It takes around 5 logic level and 6ns in a VirtexII device. It's OK to
> meet our 125MHZ clock.
>
> case2: A[127:0] > B[127:0]
>
> It takes 64 logic levels and 14ns in the same device since a serie of
> carry chain is involved. It force me to serperate the comparing
> process into 2 64bits cycle and deadly degrade the performance.
>
>   My question is why not (or how )the synthesis tools to do the
> compare with LUT like the case1 instead of carry chain? I believe a
> LUT can function as a comparator since no matter how complex the logic
> is it cares only the number of inputs. Although it will use more
> resources.
>
>   Anybody?


Article: 38187
Subject: Re: Suitability of Atmel for project?
From: "Falk Brunner" <Falk.Brunner@gmx.de>
Date: Tue, 8 Jan 2002 19:37:45 +0100
Links: << >>  << T >>  << A >>
"Stout" <i_never_check_this@hotmail.com> schrieb im Newsbeitrag
news:9fc1b2f5.0201070930.42aff5f8@posting.google.com...

> multiple UARTs, or use separate UART chips, or an FPGA, lots of
> choices.

Why not using chip select lines?

> BTW - about how much $$$ is the smallest FPGA that will run a 6805 or
> 8051 core?  Is it like $10 or $100 or what?

Why do you want to use a 8051 core? Usually there are specialized cores like
the NIOS or Microblaze that are better suited for FPGAs in terms of resource
consuption and power. There are also very nice Programmable State machines
available, which are very compact and fast. But anyway, a 8051 core should
fit into an XC2S100, which is 10$ (quanities of 250k and up) according to
the Xilinx website. Maybe a better solution is to use your classic 8051 and
use a small FPGA as complex glue logic. Building an SoC may by tempting, but
is not always sensefull from the economical point of view ;-)

> Thanks also for the link to your web page.  I spent about 10 years
> working with 6805 and 6811 and finally about 5 years ago I had to
> abandon Motorola and to 8051 because I was tired of never being able
> to buy Motorola parts.  In my opinion they REALLY dropped the ball by

Must have been a hard change, all this weired assembly instructions, the
D**m programming model, the divide by 12 of the oscillator and so on . ..

--
MfG
Falk





Article: 38188
Subject: S-video -> VGA
From: "David G." <dgeerinck@yahoo.com>
Date: Tue, 8 Jan 2002 19:38:47 +0100
Links: << >>  << T >>  << A >>

Network Blitz

Hi,
I would like to connect a s-video (SVHS) output to the VGA input of my
monitor.
A found the SDB00022AEB chip of panasonic who a think allows me to do =
that.

I'm just a beginner so, as you can imagine a have some problems with =
it...
As input I use pin31(Luminance Y)  and pin36 (Chominance C).
As output I use the RGB pins 15-16-17

The problem is that I am not shure about the other needed signals.
- I suppose I can connect pin 37 to the Chomance (C) ground.
- I don't see where to connect the Luminance (Y) ground
- Pin 19 is used on the chip as GND(RGB/I=B2C/DAC). I may be wrong but =
should
those the ground signals be separated instead of connected together into =
one
signal?
- I also don't see what hapens to the vertical and horizontal sync.

( May be the chip isn't the best one to perfome this task or, am I blind =
)

Thanks for answering.

David.



Article: 38189
Subject: Re: Virtex-II parallel LVDS demo board (FAO Austin Lesea?)
From: Austin Lesea <austin.lesea@xilinx.com>
Date: Tue, 08 Jan 2002 11:08:04 -0800
Links: << >>  << T >>  << A >>
Ian,

The LVDS demo pcb has gone out to all of the support offices.  Please
contact your local FAE for more information.

I do not have the details on the features of this board.

Austin


Ian Dedic wrote:

> Hi Austin
>
> I posted this before Xmas in an old thread so I guess nobody spotted
> it...
>
> About a year ago we designed an evaluation platform using Virtex-E to
> source 624Mb/s 28-bit parallel data (2 DDR LVDS 14-bit buses) to drive
> a high-speed dual DAC. This was a lot of grief and effort, and had
> problems with skew on the data bus in spite of using a customised
> Xilinx-supplied parallel LVDS macro.
>
> One necessary feature to remove I/O and track/cable delays (since the
> DAC had to be the clock master for jitter reasons) was that we took
> the 312MHz clock out from the DAC as the DLL input clock, then sourced
> a 312MHz clock from the Virtex (DDR clock synchronised to the data)
> and looped it into the DAC and back out to the Virtex as the DLL
> reference clock, so the DLL took out the delays.
>
> Will this be possible on the Xilinx LVDS demo board, and when will the
> board be available? I'm asking this because I know at least one
> customer is using an Altera Mercury board (also not released yet?) to
> source data, because there wasn't anything suitable available from
> Xilinx.
>
> Does the board use SMA connectors (so we could connect it directly)?
>
> Is there any possiblility of a board with wider LVDS output (eg, 32
> bit) being made available in the future?
>
> Am I correct in assuming that Virtex-II could run like this up to
> 840Mb/s?
>
> Ian Dedic
> Chief Engineer
> Mixed Signal Division
> Advanced Communications Group
> Fujitsu Microelectronics


Article: 38190
Subject: ROM synthesis question
From: brad@tinyboot.com (Brad Eckert)
Date: 8 Jan 2002 11:52:14 -0800
Links: << >>  << T >>  << A >>
I plan to use a ROM generated by an external programming tool whose
source looks something like this:

-- Definition of 128 x 32 ROM

entity MyROM is
port (addr: in  std_logic_vector(6 downto 0);
      data: out std_logic_vector(31 downto 0));
subtype cell is bit_vector(31 downto 0);
type ROMarray is array(0 to 127) of cell;
constant contents: ROMarray :=
      '00101001010010101010010100000010',
      '00101010010100101010100101000010',
      '00101010010101010010100000010000',
      '00110100101001010101001010000001',
      ...
      '00101001010010101010010100000010',
      );
end entity MyROM;

architecture MyArch of ROM is
begin rd: process is
      out <= ROMarray[addr];
      end process rd;
end architecture MyArch;

My question is, is this okay for FPGA synthesis? I would think that
Xilinx Webpack or Altera Baseline should be smart enough to fit this
into a RAM block. But, maybe not. Do I need some special attributes,
or is there a better way to have the programming tool express the ROM?

Article: 38191
Subject: Repost: Should clock skew be included for setup time analysis?
From: Kevin Brace <nospamtomekevinbraceusenet@nospamtomehotmail.com>
Date: Tue, 08 Jan 2002 14:12:06 -0600
Links: << >>  << T >>  << A >>
I made this posting around Chrismas, and that seems to be the reason no
one responded, so I am reposting the same posting again.




_________________________________________________________________________

Hi, I will like to know how the readers of this newsgroup think of
including clock skew for setup time analysis?
I am working on a PCI IP core which with various suggestions from the
readers of this newsgroup, I was able to improve setup timings (Tsu)
through reduction of logic levels (reduction of levels of LUTs).
I am using ISE WebPack 4.1 and targeting Spartan-II 150K system gate
part for my PCI IP core.
In ISE WebPack when I ran TRCE to generate a timing error report, the
timing report for setup time includes clock skew occurring, and this
clock skew time subtracts some time off the data path delay (data path
delay = gate delay + routing delay) which becomes total or final delay,
and the worst time here is shown in the timing summary section.
However, if I think carefully about the timing data shown in the report,
the temperature assumed here is 85 degrees celsius, and since
semiconductor devices have less delays in a lower temperature, at room
temperature (20 degrees Celsius) the clock skew will likely be much less
than what the report suggests, and even lower at a freezing temperature
(0 degrees Celsius, the lowest temperature commercial package version of
Spartan-II is guaranteed to function).
Yes, I do realize that at a temperature lower than 85 degrees Celsius,
the gate delays for LUTs and FFs will also decrease, therefore even if
the clock skew decreases that shouldn't cause a major problem, however,
no one really knows which one will decrease faster.
        Another problem I can think is that in the case of Xilinx
devices, several Xilinx employees have written publicly in this
newsgroup (I know those are their own opinions, and not necessarily the
company's official position on the issues being raised) that whether or
not it is a different speed grade, all the chips come from the same
silicon wafer.
That will mean that in the case of Virtex, speed grade -4, -5, or -6
devices come from the same silicon wafer.
I knew nothing about FPGAs two years ago, but from what I hear, Xilinx
first came out with Virtex speed grade -4 in 1998, and later got speed
grade -5 and -6 out (I don't know the exact release date of those two
speed grades. I will be interested to hear when they started to ship).
Likely most chips manufactured back in 1998 ran only at speed grade -4,
but as Xilinx improved the speed of Virtex through circuit and
manufacturing improvements, it was able to pick chips that will run at
speed grade -5 or -6.
However, there are customers who designed products in the days of Virtex
speed grade -4, so Xilinx still has to supply Virtex speed grade -4 to
the market.
The concern I have here is that even though the chip is marked as a
Virtex speed grade -4, isn't it possible that chip could have been
marked as a speed grade -6 device because it was manufactured recently?
(let's say in 2001)
If so, won't the clock skew assumption made during the setup time
analysis be off for such Virtex speed grade -4 device, perhaps by 1ns to
2ns depending on the device size?
I am not criticizing Xilinx for bin splitting devices, but I think it
seems risky to use maximum clock skew during setup time analysis.
Are there any ways to disable using maximum clock skew from being used
in MAP/PAR/TRCE/TimingAn?



Thanks,



Kevin Brace (don't respond to me directly, respond within the newsgroup)

Article: 38192
Subject: Re: latch vs. register
From: Eric Smith <eric-no-spam-for-me@brouhaha.com>
Date: 08 Jan 2002 12:22:35 -0800
Links: << >>  << T >>  << A >>
Peter Alfke <peter.alfke@xilinx.com> writes:
> Tutorial:
> A flip-flop consists of two latches, a master and a slave.
> 
> A latch accepts data when the Latch Enable is active, and stores data
> when LE is not active.  With LE active, the latch is transparent, its
> output follows the input.
> 
> A flip-flop combines two latches with opposite LE polarities, such
> that the master latch accepts incoming data when the clock is Low, and
> the slave latch copies the master when the clock is High ( This is
> thus a rising-clock-edge edge-triggered flip-flop. The opposite clock
> polarity is also possible).

I think you're probably more of an expert on digital logic than I am,
but aren't there several other edge-triggered flip-flop designs that do
NOT operate in a master-slave fashion?  It seems to me that the plain
old 7474 D flip-flop is edge-triggered but not master-slave.  The output
is valid after a short delay from the active edge, whereas on a
master-slave the output would not be valid until after the opposite
clock edge.

Or perhaps I'm completely clueless.  It wouldn't be the first time.
It's been a LONG time since I studied flip-flops in detail.

Article: 38193
Subject: Re: S-video -> VGA
From: Eric Smith <eric-no-spam-for-me@brouhaha.com>
Date: 08 Jan 2002 12:27:58 -0800
Links: << >>  << T >>  << A >>
"David G." <dgeerinck@yahoo.com> writes:
> I would like to connect a s-video (SVHS) output to the VGA input of my
> monitor.
> A found the SDB00022AEB chip of panasonic who a think allows me to do that.

This isn't really an FPGA or VHDL question; you might have better luck
in a more appropriate newsgroup.

Anyhow, your VGA monitor is unlikely to support the NTSC scan rate.  Most
VGA monitors made in the last ten years have had a minimum horizontal
rate of 31.5 KHz, while NTSC horizontal rate is only about 15.734 KHz.
So unless the panasonic chip includes a frame buffer, you'll be
out of luck.

Your best bet would be to run the signal through a PC by using a video
card that has a video input.

Article: 38194
Subject: Re: 128 bit compare delay kill me!
From: Ray Andraka <ray@andraka.com>
Date: Tue, 08 Jan 2002 20:43:53 GMT
Links: << >>  << T >>  << A >>
That is but one way to do magnitude comparison.  The comparison can be
either left transitive or right transitive.  For left transitive (results of
the operation on a bit affect the output bits to the left of the bit
position), the compare operation is equivalent to subtraction.  It sounds
like the synthesis tool is doing that.  For right transitive, you
essentially compare the msbs.  If they are equal, you proceed to the right
until you find a mismatch.  That is typically done with a merged tree
architecture, although it could also be done with a carry chain running in
the opposite direction to the normal flow (the old 4000 chips were good for
that since their carry chains ran both ways).  THe trouble you are running
into is that a 128 bit carry chain is long, which makes it pretty slow.  You
can maximize the speed if you make sure the flip-flops driving the carry
chain are floorplanned to be immediately adjacent to it, and designed to
have as few loads as possible.  For 128 bits, I think the merged tree does
come out  ahead of the carry chain.

Eric Smith wrote:

> A magnitude comparison is fundamentally a subtraction.  The MSB output
> of the subractor, and the carry output, depend on EVERY input to the
> comparator.  You could try  using a carry-save or carry-select adder
> rather than a simple ripple carry adder, but I doubt that you'll
> improve the speed much since the carry chain is quite optimized.

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 38195
Subject: Re: ROM synthesis question
From: "Dr. Jeff Jackson" <jjackson@eng.ua.edu>
Date: Tue, 08 Jan 2002 14:44:41 -0600
Links: << >>  << T >>  << A >>
Brad,

I have no experience with the Xilinx toolset, but I know that Altera
MAX+PLUSII will not place this into an EAB block. The only luck I have
had in getting constructs like this to be implemented in the EAB blocks
is to use the built-in LPM functions. In your case, you would want the
LPM_ROM function.

Since you are generating the programming file with an external tool, I
would look into using the Altera Megawizard Plug-in Manager to create an
instance of the LPM_ROM function. You can specify the ROM contents in
either an Altera MIF (.mif) format or an Intel HEX (.hex) formatted
file.

Alternately, use the Leonardo-Spectrum tool and it should give you an
EAB implementation that you can then import into MAX+PLUS2 for place and
route.

Jeff Jackson
-----------------------------------------------------------------------
David Jeff Jackson
Associate Professor
Electrical & Computer Engineering
P.O. Box 870286
The University of Alabama
Tuscaloosa, AL 35487-0286
Phone: (205) 348-2919
FAX: (205) 348-6959
email: jjackson@eng.ua.edu
WEB: www.ece.ua.edu
-----------------------------------------------------------------------

Article: 38196
Subject: Re: latch vs. register
From: John_H <johnhandwork@mail.com>
Date: Tue, 08 Jan 2002 20:49:52 GMT
Links: << >>  << T >>  << A >>
Eric Smith wrote:

> It seems to me that the plain
> old 7474 D flip-flop is edge-triggered but not master-slave.  The output
> is valid after a short delay from the active edge, whereas on a
> master-slave the output would not be valid until after the opposite
> clock edge.

This is one of the fun parts of looking into other people's hardware.  I
think it was an old TI databook that I really got to understand how the
master-slave thing works - I think it was the 7474.  Using your terminology
above, before the active edge (when the clock is low) the input latch (the
master?  Thanks, Peter) is transparent allowing the incoming data to show up
at the input of the output latch (the slave) but blocked.  When the clock
polarity changes, the output latch becomes transparent allowing the data
from the input latch to show up on the output;  in the mean time the input
latch no longer tracks the input data because it's no longer transparent.
So after the active edge, the output is looking at the data "in the middle"
through a transparent output latch.

When the opposite edge comes by the transparent output latch turns
non-transparent (opaque?) and the data is held for the second half of the
clock cycle as the input latch begins once again to look at the input data.

Ahhhh, for the days when the data books gave all the gate level description
you needed  :-)

- John


Article: 38197
Subject: Core Generator
From: a_darabiha@yahoo.com (a_darabiha)
Date: 8 Jan 2002 13:17:04 -0800
Links: << >>  << T >>  << A >>
Hi all,
can one Xilinx ISE tools experts help me please!
I have gone through the Core Generator guide but
still confused! :(  here is the story:

As a new user of Xilinx Core Generator I am trying 
generate a very simple core (16bit comparator)  and then 
instantiate it in my vhdl design and finally synthesize and 
implement it on a virtexII platform.

The Core Generator works fine and produces .vho, .edn and
.vhd files. I then cut and paste from the .vho file to instantiate
the component in my own design with the proper port map names...

I synthesize the desing by Synplicity  VHDL compiler v6.2.0 and it seems
there is not any problem but after that in ngdbuid I get this error message:

****************************************************************
.
.
.
WARNING:NgdBuild:329 - Line number 5: Invalid PART record value "4003pc84"
   ignored.  Please consult the Xilinx Programmable Logic Data Book for valid
   part/package/speed conbinations.
   Writing NGO file "my_adder_coregen_ports.ngo" ...
Loading design module
"/jayar/q/q6/ahmadd/tm3/coregen/test_5/tm3a/xilinx/fpga0/my_adder_coregen_ports.
ngo"...

Annotating constraints to design from file "virtex0.ucf" ...

Checking timing specifications ...

Checking expanded design ...
ERROR:NgdBuild:604 - logical block
   'wrapped_my_adder_coregen_inst/my_adder_coregen_inst/your_instance_name' with
   type 'new_comp' is unexpanded. Symbol 'new_comp' is not supported in target
   'virtexe'.
WARNING:NgdBuild:454 - logical net 'GND' has no load
WARNING:NgdBuild:454 - logical net 'VCC' has no load

NGDBUILD Design Results Summary:
  Number of errors:     1
  Number of warnings:   2

.
.
.
****************************************************************

Has any friend had this problem before?

I have some guesses in my mind that might also help you
to figure out the problem:

1- I have not compiled the XilinxCore Lib. Is that the problem ?
      There were several reasons for that:
	- it seems compiling VHDL behavioral library requires
	 MTI ModelSim and in our package ModelSim is only supported
	 for PC and not for Solaris...

	- in fact at this time I do not need to do any simulation 
	and want to synthesize it directly, so I dont feel
        any need for simulation. and It should be possible
	to generate a core and synthesize it without any simulation in
	between...

So, is it really neccessary to compile XilinxCoreLib for synthesis?
if so, could someone help how to do that? (the info in Xilix Core 
Generator guide for compile_hdl.pl is too short not clear :( )

2- in page 4-33 of Core generator guide for Synplicity synthesis tool it says:
  "do not read in a separate .vhd file or EDIF file for Core Generator mudule"
  what dose that mean !?	 



I would really appreciate any help,
and please let me know if the problem is not described clearly, 
thanks,
a_darabiha@yahoo.com

Article: 38198
Subject: Actel Simulations
From: john_42_01915@hotmail.com (john)
Date: Tue, 08 Jan 2002 21:24:21 GMT
Links: << >>  << T >>  << A >>
Hi
I've got the Actel Libero package, and I have completed entry of a
fairly complex logic design using schematic capture. 

I am want simulate the various functional blocks in the chip, in a
piecewise fashion. So far, I have not figured out how to work with
anything smaller than the entire design at the device pins. 

I am used to the Xilinx Foundation toolset that allows me to mark
nodes in the schematic as either Stimulus points or Probe points
and exercise the design in small bite sized pieces.


Did Actel forget to put this capability in their Libero package?

Thanks for any ideas...


Article: 38199
Subject: Re: Repost: Should clock skew be included for setup time analysis?
From: Bob Perlman <no-spam@sonic.net>
Date: Tue, 08 Jan 2002 21:24:44 GMT
Links: << >>  << T >>  << A >>
Hi - 

I assume you're talking about setup time margins within the chip,
i.e., both the source and destination flip-flops are on-chip.

The question boils down to how well the data delay tracks the clock
skew delay over temperature, voltage, and process.  Xilinx used to
claim (and maybe still does) that gate delays track to 70%, i.e., if a
gate is at its maximum delay, no other gate on the die will have a
delay of less than 70% of its maximum.  Someone at Xilinx can correct
me, but I believe that the actual tracking of delays on a die is far
better than that, and that the 70% tracking number was chosen because
there was absolutely no chance of it ever being violated.

I tend to obsess over timing, but have to admit that I don't worry too
much about Xilinx subtracting the clock skew from setup time.  In
essense, they're guaranteeing that the resulting setup time is
correct, and that you can design to it.

If you want something to worry about, wonder whether the speed files
are correct.  The nice thing is, this concern is vendor-independent
and will never go away no matter how much you worry, something that
can be appreciated by those of us seeking constancy in an
ever-changing, chaotic world.

Bob Perlman
Cambrian Design Works

On Tue, 08 Jan 2002 14:12:06 -0600, Kevin Brace
<nospamtomekevinbraceusenet@nospamtomehotmail.com> wrote:

>I made this posting around Chrismas, and that seems to be the reason no
>one responded, so I am reposting the same posting again.
>
>
>
>
>_________________________________________________________________________
>
>Hi, I will like to know how the readers of this newsgroup think of
>including clock skew for setup time analysis?
>I am working on a PCI IP core which with various suggestions from the
>readers of this newsgroup, I was able to improve setup timings (Tsu)
>through reduction of logic levels (reduction of levels of LUTs).
>I am using ISE WebPack 4.1 and targeting Spartan-II 150K system gate
>part for my PCI IP core.
>In ISE WebPack when I ran TRCE to generate a timing error report, the
>timing report for setup time includes clock skew occurring, and this
>clock skew time subtracts some time off the data path delay (data path
>delay = gate delay + routing delay) which becomes total or final delay,
>and the worst time here is shown in the timing summary section.
>However, if I think carefully about the timing data shown in the report,
>the temperature assumed here is 85 degrees celsius, and since
>semiconductor devices have less delays in a lower temperature, at room
>temperature (20 degrees Celsius) the clock skew will likely be much less
>than what the report suggests, and even lower at a freezing temperature
>(0 degrees Celsius, the lowest temperature commercial package version of
>Spartan-II is guaranteed to function).
>Yes, I do realize that at a temperature lower than 85 degrees Celsius,
>the gate delays for LUTs and FFs will also decrease, therefore even if
>the clock skew decreases that shouldn't cause a major problem, however,
>no one really knows which one will decrease faster.
>        Another problem I can think is that in the case of Xilinx
>devices, several Xilinx employees have written publicly in this
>newsgroup (I know those are their own opinions, and not necessarily the
>company's official position on the issues being raised) that whether or
>not it is a different speed grade, all the chips come from the same
>silicon wafer.
>That will mean that in the case of Virtex, speed grade -4, -5, or -6
>devices come from the same silicon wafer.
>I knew nothing about FPGAs two years ago, but from what I hear, Xilinx
>first came out with Virtex speed grade -4 in 1998, and later got speed
>grade -5 and -6 out (I don't know the exact release date of those two
>speed grades. I will be interested to hear when they started to ship).
>Likely most chips manufactured back in 1998 ran only at speed grade -4,
>but as Xilinx improved the speed of Virtex through circuit and
>manufacturing improvements, it was able to pick chips that will run at
>speed grade -5 or -6.
>However, there are customers who designed products in the days of Virtex
>speed grade -4, so Xilinx still has to supply Virtex speed grade -4 to
>the market.
>The concern I have here is that even though the chip is marked as a
>Virtex speed grade -4, isn't it possible that chip could have been
>marked as a speed grade -6 device because it was manufactured recently?
>(let's say in 2001)
>If so, won't the clock skew assumption made during the setup time
>analysis be off for such Virtex speed grade -4 device, perhaps by 1ns to
>2ns depending on the device size?
>I am not criticizing Xilinx for bin splitting devices, but I think it
>seems risky to use maximum clock skew during setup time analysis.
>Are there any ways to disable using maximum clock skew from being used
>in MAP/PAR/TRCE/TimingAn?
>
>
>
>Thanks,
>
>
>
>Kevin Brace (don't respond to me directly, respond within the newsgroup)

--
Cambrian Design Works
digital design, signal integrity
http://www.cambriandesign.com
e-mail: respond to bob at the domain above.



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