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Messages from 38725

Article: 38725
Subject: Re: Internal tri state buffer..
From: vt313@comsys.ntu-kpi.kiev.ua
Date: Wed, 23 Jan 2002 15:53:58 +0200
Links: << >>  << T >>  << A >>


uttam singh wrote:
> 
> what are the advantages and disadvantages of internal tri state buffer which xilinx provided but altera does not?


I felt the advantage when we designed the microprocessor model.
The common bus with tenths of sources and destinations
is mapped into Xilinx FPGA exellently.
And when we synthesized this project into Altera Flex,
then the LC number doubled due to the very heavy multiplexers.

Altera says that due to the absent of tristates,
its FPGAs are cheapest.

Regards,
Anatoli Sergyienko

Article: 38726
Subject: Re: Atmel FPGA configuration memory?!
From: "Andrej Jancura" <andrej.jancura@tu-ilmenau.de>
Date: Wed, 23 Jan 2002 15:19:24 +0100
Links: << >>  << T >>  << A >>

"Ulf Samuelsson" <ulf@atmel.REMOVE.com> schrieb im Newsbeitrag
news:m4v38.6146$O5.15095@nntpserver.swip.net...
> > At first I'd like to say, that the board, I start to design, is not
> > commercial. It is just my hobby and Atmel sends me 3-4 free samples. May
> be
> > Xilinx too, but I didn't found any page for sample request... Now I have
> 2x
> > XC2S200 and would like to use something for configuration. What is the
> best
> > type for this device? Thank you.
> >
> > Andrej
> >
>
> I think that the AT17LV002 may be a suitable device.
>

Thank you.

Andrej



Article: 38727
Subject: Re: input source to feed 20 filters! how to decrease the load
From: "Hristo Stevic" <hristostev@yahoo.com>
Date: Wed, 23 Jan 2002 14:33:13 +0000 (UTC)
Links: << >>  << T >>  << A >>
thanks RAY, nice and simple idea!!i should think about it, (weak!!)
Peter i am targetting virtex-e. fanout will be done internally 
any coment?



-- 
Posted via Mailgate.ORG Server - http://www.Mailgate.ORG

Article: 38728
Subject: Missing IPAD, OPAD, etc. in Xilinx WebPACK Schematic Capture Library
From: "Robert S. Grimes" <rsg@payload.nospam.com>
Date: Wed, 23 Jan 2002 10:43:41 -0500
Links: << >>  << T >>  << A >>
Hi all,

I'm missing the IPAD, OPAD, IOPAD symbols in the unified libraries.  Any
ideas?

Thanks!

-Bob



Article: 38729
Subject: Re: Missing IPAD, OPAD, etc. in Xilinx WebPACK Schematic Capture Library
From: Kamal Patel <kamal.patel@xilinx.com>
Date: Wed, 23 Jan 2002 10:29:03 -0700
Links: << >>  << T >>  << A >>
Hello Bob,

In ECS, the schematic capture tool for ISE, PADs have been replaced by
I/O Markers.  Therefore in place of an IPAD or OPAD you would have
either an input or output I/O Marker.  Additionally, IBUFs and OBUFs
have also become optional parts of the schematic.  The only reason you
may still want to use I/O Buffers is for clocks, tri-states, renaming nets
for
the port listing, and special I/Os.

To use I/O Markers in ECS, go to Add ==> I/O Marker, then make
sure you have selected the correct polarity and click on the end of the
net where you would normally place the buffer or pad.

I hope this helps.

Best regards,
Kamal Patel

"Robert S. Grimes" wrote:

> Hi all,
>
> I'm missing the IPAD, OPAD, IOPAD symbols in the unified libraries.  Any
> ideas?
>
> Thanks!
>
> -Bob


Article: 38730
Subject: Re: Missing IPAD, OPAD, etc. in Xilinx WebPACK Schematic Capture Library
From: "Robert S. Grimes" <rsg@payload.nospam.com>
Date: Wed, 23 Jan 2002 15:25:55 -0500
Links: << >>  << T >>  << A >>
Thanks, Kamal!  It's this sort of beginner's question that is so frustrating
for, well, beginners!

"Kamal Patel" <kamal.patel@xilinx.com> wrote in message
news:3C4EF2DF.E8111FEF@xilinx.com...
> Hello Bob,
>
> In ECS, the schematic capture tool for ISE, PADs have been replaced by
> I/O Markers.  Therefore in place of an IPAD or OPAD you would have
> either an input or output I/O Marker.  Additionally, IBUFs and OBUFs
> have also become optional parts of the schematic.  The only reason you
> may still want to use I/O Buffers is for clocks, tri-states, renaming nets
> for
> the port listing, and special I/Os.
>
> To use I/O Markers in ECS, go to Add ==> I/O Marker, then make
> sure you have selected the correct polarity and click on the end of the
> net where you would normally place the buffer or pad.
>
> I hope this helps.
>
> Best regards,
> Kamal Patel
>
> "Robert S. Grimes" wrote:
>
> > Hi all,
> >
> > I'm missing the IPAD, OPAD, IOPAD symbols in the unified libraries.  Any
> > ideas?
> >
> > Thanks!
> >
> > -Bob
>



Article: 38731
Subject: IDT7204 Using CoreGen
From: "AP" <escorpiontale@hotmail.com>
Date: Wed, 23 Jan 2002 20:42:27 GMT
Links: << >>  << T >>  << A >>
Trying to implement a 4K by 9 Asynchronous FIFO using Xilinx CoreGen 4.1 and
I am running into problems.
The Xilinx Fifo uses a WE_CLK and W_EN signals where the 7204 only uses a
WE_N. I tried pulling up the W_EN and using the not(WE_N) for the clock but
the Xilinx FIFO expects a rising edge after reset in order to start writing
data so I am loosing the first word.
Anyone has any ideas of how to implement this.
Regards
Angel




Article: 38732
Subject: Re: Analog input into Altera FLEX10K using ADC. Can anyone help??
From: "Gunther May" <g.may@tu-bs.de>
Date: Wed, 23 Jan 2002 22:47:46 +0100
Links: << >>  << T >>  << A >>
Hi,

best would be to connect the 8 output bits of the ADC directly to your input
bus and drive the control bits with some additional pins from the FPGA. You
will have to implement a simple state machine on the FPGA for that. The
exact connections, timing etc. are described in the data sheet (you will
find it quickly by typing the part number in www.google.com).
The output on the DAC would be the same: connect your 8 bit output bus to
the input pins and the control pins of the DAC to additional pins of the
FPGA.

Probably the signed values you are talking of are 2-complement values. The
easiest way to convert the 8-bit values to 16 bit is to take the 8 bit as
LSB and add 8 zeros to the MSB. This method is also working if you have a
sign bit in the 16-Bit value which is 1 for negative values (no complement
representation). If the sign bit is inverted, you take 10000000b as higher
byte.
When converting the other way, you just leave the 8 MSBs away. But: be sure
that your design has no overflow! This would be the case when the final
result is bigger than 255 or less than 0. You could add saturation logic for
this case; if the value is less than 0, you set it to zero and if it is
bigger than 255, you set it to 255. If you do not do that and you have
overflows, your results are completely wrong.

Regards,
Gunther

"jcding" <jcding@yahoo.com> schrieb im Newsbeitrag
news:3c4f1e49_1@news.tm.net.my...
> Hi.. Can you give ideas how to interface the ADC0804 with the Altera
FLEX10K
> ? I have planned to interface the output with DAC0808 also.
>
> I have another problem here. I have designed 8-tap FIR filter using bit
> serial approach. How to convert the output 8 bit from ADC to 16 bit signed
> extended input into the FPGA? And how to convert from 16 bit output from
> FPGA into 8 bit to support DAC0808? Or it is impossible at all..
>
> Thanks alot...
>
>



Article: 38733
Subject: Re: Quartus 2 and bus ripping
From: "Paul" <nospam@nospamplease.com>
Date: Wed, 23 Jan 2002 22:19:32 -0000
Links: << >>  << T >>  << A >>
Because I hate threads without an answer, I've posted my solution.

After ripping the single bit from the output bus use a WIRE primitive and
connect the output of WIRE to the desired output signal.

You do not seem to be able to use the block mapper to map say q[23..0] to
one signal bus as well as say q[7] to a single signal. Bring q[23..0] out
and name it to some arbitrary bus name and then also take the single bit
from that bus to the WIRE primitive.

Paul



Article: 38734
Subject: Re: Q: can ROM content affect logic syn result
From: kayrock66@yahoo.com (Jay)
Date: 23 Jan 2002 14:53:46 -0800
Links: << >>  << T >>  << A >>
Provided the ROM is being implimented as an EAB I don't see how it
would change the netlist.  I'm assuming your code changes all the bits
at least once so nothing is hardwired.  I simpethize with your plight
because I had a similar issue when I was simulating a digital imager
(CMOS) output stream and wanted to eaily change the pictures stoed in
the APEX EAB ROMs.  I never figured out a way to get out of waiting
for the whole P&R to run, and I was using all of a 20K1500, so it took
all night to P&R.

Off the top of my head I'd suggest using an external JTAG programmable
non-volitle memory to hold your code.  Have the APEX part pull the
code off the external memory and into EAB ram at reset release, then
run from EAB RAM.  Whenever you want to try new code on your
processor, just program the external ROM and hit reset.

Jay


shengyu_shen@hotmail.com (ssy) wrote in message news:<f4a5f64f.0201212341.40127c59@posting.google.com>...
> Hi everyone
> 
> I am using synplicity6.2.4 to sythesis and then use quartus to P&R
> 
> my design is an CPU(nnarm),I INFER a small rom to hold the small
> program for it.
> so I want to ask a question : if the content of the rom can affect the
> synthesis result of the whole cpu?
> 
> because the syn and then p&r is a very long process(about 40 min), so
> when I only modify the program in the rom, I do not want to run the
> whole process, I want to regenerate the mif file , and then directly
> P&R with back annotated placemenmt information, this reduce the
> process to only 10 min

Article: 38735
Subject: Re: IDT7204 Using CoreGen
From: Peter Alfke <peter.alfke@xilinx.com>
Date: Wed, 23 Jan 2002 15:05:35 -0800
Links: << >>  << T >>  << A >>
Can you explain? Most designers want to use a write clock to write into any
memory ( or FIFO). So why would you miss the first word?

Peter Alfke, Xilinx Applications ( FIFO is my middle name )
==============================================
AP wrote:

> Trying to implement a 4K by 9 Asynchronous FIFO using Xilinx CoreGen 4.1 and
> I am running into problems.
> The Xilinx Fifo uses a WE_CLK and W_EN signals where the 7204 only uses a
> WE_N. I tried pulling up the W_EN and using the not(WE_N) for the clock but
> the Xilinx FIFO expects a rising edge after reset in order to start writing
> data so I am loosing the first word.
> Anyone has any ideas of how to implement this.
> Regards
> Angel


Article: 38736
Subject: Re: CRC-32 48bit(width)
From: Ray Andraka <ray@andraka.com>
Date: Wed, 23 Jan 2002 23:31:13 GMT
Links: << >>  << T >>  << A >>
Right, but if the invalid bytes come in the middle of a stream, as I understood it, then it
will screw up your CRC.  My suggestion was based on the assumption that there were invalid
bytes midstream, not just before it.

Allan Herriman wrote:

> On Tue, 22 Jan 2002 16:38:46 GMT, Ray Andraka <ray@andraka.com> wrote:
>
> >You need to decide how you will deal with these invalid bytes.  I presume they should be
> >ignored (dropped) from the stream.  If that is the case, then you'll have to buffer the
> >incoming data so that you can drop unwanted bytes.  Masking the unwanted bytes at the CRC
> >is not trivial if you are presenting 6 bytes at a time.  It is much easier if you present
> >a byte at a time, but it also means running the CRC at a 6x clock.  If you can't do the 6x
> >clock, I'd opt for a fifo arrangement that stores bytes until you have at least 6 valid
> >ones and drops bad bytes.  The holes left by bad bytes get grouped together so that you
> >skip over 6 bytes at a time at the CRC.
>
> Hi Ray,
>
> There's a magic trick you can do in which the dropped bytes simply get
> masked to all zeros.  The trick is arranging the 2nd parallel CRC
> generator such that leading zero bytes have no effect on the value of
> the CRC.  This happens when the 2nd CRC is initialised to zero.
>
> Regards,
> Allan.
>
> >Muthu wrote:
> >
> >> Yeah,
> >>
> >> You can get the source code for 48bits crc-32 parallel calculation.
> >> Incase, if the all 48bits are not valid, How will you calculate the
> >> crc-32 for that valid bytes only.
> >>
> >> For example:
> >>
> >> Your code will take always 48bits ie., 6Bytes of data. If the incoming
> >> frame is not multiple of 6Bytes, atlast you will have some less bytes
> >> (<6Bytes). For that how will you use the same module.
> >>
> >> Regards,
> >> Muthu.
> >>
> >> Ray Andraka <ray@andraka.com> wrote in message news:<3C308D4E.280F00EA@andraka.com>...
> >> > Sure there is, but it is not obvious.  check the 32 AND the 16 bit
> >> > boxes.  That gives you the 48 bit variant.
> >> >
> >> > Kenily wrote:
> >> >
> >> > > Thanks!
> >> > > But there is not 48bit(width)
> >> >
> >> > --
> >> > --Ray Andraka, P.E.
> >> > President, the Andraka Consulting Group, Inc.
> >> > 401/884-7930     Fax 401/884-7950
> >> > email ray@andraka.com
> >> > http://www.andraka.com
> >> >
> >> >  "They that give up essential liberty to obtain a little
> >> >   temporary safety deserve neither liberty nor safety."
> >> >                                           -Benjamin Franklin, 1759
> >
> >--
> >--Ray Andraka, P.E.
> >President, the Andraka Consulting Group, Inc.
> >401/884-7930     Fax 401/884-7950
> >email ray@andraka.com
> >http://www.andraka.com
> >
> > "They that give up essential liberty to obtain a little
> >  temporary safety deserve neither liberty nor safety."
> >                                          -Benjamin Franklin, 1759
> >
> >

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 38737
Subject: Re: Q: can ROM content affect logic syn result
From: Ray Andraka <ray@andraka.com>
Date: Wed, 23 Jan 2002 23:36:14 GMT
Links: << >>  << T >>  << A >>
It will give you different results if the ROM is an inferred EAB and one of the bits happens to be constant
for all addresses.  If that is the case, that bit gets optimized out.  To keep it, you need to put a keep
buffer on the ROM output bits so that synthesis doesn't dissolve the flip-flop.  I've seen instances in the
past where it (synthesis) still dissolves the ROM, as well as not consistently assigning the data bits to
particular ROM bits.  For these reasons, I prefer to instantiate any ROMs which I may have to update later.

Jay wrote:

> Provided the ROM is being implimented as an EAB I don't see how it
> would change the netlist.  I'm assuming your code changes all the bits
> at least once so nothing is hardwired.  I simpethize with your plight
> because I had a similar issue when I was simulating a digital imager
> (CMOS) output stream and wanted to eaily change the pictures stoed in
> the APEX EAB ROMs.  I never figured out a way to get out of waiting
> for the whole P&R to run, and I was using all of a 20K1500, so it took
> all night to P&R.
>
> Off the top of my head I'd suggest using an external JTAG programmable
> non-volitle memory to hold your code.  Have the APEX part pull the
> code off the external memory and into EAB ram at reset release, then
> run from EAB RAM.  Whenever you want to try new code on your
> processor, just program the external ROM and hit reset.
>
> Jay
>
> shengyu_shen@hotmail.com (ssy) wrote in message news:<f4a5f64f.0201212341.40127c59@posting.google.com>...
> > Hi everyone
> >
> > I am using synplicity6.2.4 to sythesis and then use quartus to P&R
> >
> > my design is an CPU(nnarm),I INFER a small rom to hold the small
> > program for it.
> > so I want to ask a question : if the content of the rom can affect the
> > synthesis result of the whole cpu?
> >
> > because the syn and then p&r is a very long process(about 40 min), so
> > when I only modify the program in the rom, I do not want to run the
> > whole process, I want to regenerate the mif file , and then directly
> > P&R with back annotated placemenmt information, this reduce the
> > process to only 10 min

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 38738
Subject: Re: Analog input into Altera FLEX10K using ADC. Can anyone help??
From: Ray Andraka <ray@andraka.com>
Date: Wed, 23 Jan 2002 23:48:00 GMT
Links: << >>  << T >>  << A >>
Whoa there, that is not real good answer.  You have an 8 bit input you wish to
extend to 16 bits.  Normally, you'd append 0's to the LSBs (not the MSBs) so as
to keep your signal reasonably sized compared to the dynamic range of your
system.  In those cases where you have a need to put guard bits above the input,
and assuming your input is 2's complement, any additional bits added to the MSB
end have to be sign extended.  That means copy the MSB of your input into the
added bits, otherwise your negative inputs will become positive (2^16-input
value) which you do not want.

At the output, take the 8 MSBs and accept the truncation.  You can add X"0010"
(half the taken LSB) before truncating to reduce the bias on the quantization
error.  Also, if you know you'll have repeated sign bits in the output, you can
discard the redundant signs by dropping MSBs before taking the 8 MSBs of what is
left, just watch out for and possibly treat potential overflow.

Gunther May wrote:

> Hi,
>
> best would be to connect the 8 output bits of the ADC directly to your input
> bus and drive the control bits with some additional pins from the FPGA. You
> will have to implement a simple state machine on the FPGA for that. The
> exact connections, timing etc. are described in the data sheet (you will
> find it quickly by typing the part number in www.google.com).
> The output on the DAC would be the same: connect your 8 bit output bus to
> the input pins and the control pins of the DAC to additional pins of the
> FPGA.
>
> Probably the signed values you are talking of are 2-complement values. The
> easiest way to convert the 8-bit values to 16 bit is to take the 8 bit as
> LSB and add 8 zeros to the MSB. This method is also working if you have a
> sign bit in the 16-Bit value which is 1 for negative values (no complement
> representation). If the sign bit is inverted, you take 10000000b as higher
> byte.
> When converting the other way, you just leave the 8 MSBs away. But: be sure
> that your design has no overflow! This would be the case when the final
> result is bigger than 255 or less than 0. You could add saturation logic for
> this case; if the value is less than 0, you set it to zero and if it is
> bigger than 255, you set it to 255. If you do not do that and you have
> overflows, your results are completely wrong.
>
> Regards,
> Gunther
>
> "jcding" <jcding@yahoo.com> schrieb im Newsbeitrag
> news:3c4f1e49_1@news.tm.net.my...
> > Hi.. Can you give ideas how to interface the ADC0804 with the Altera
> FLEX10K
> > ? I have planned to interface the output with DAC0808 also.
> >
> > I have another problem here. I have designed 8-tap FIR filter using bit
> > serial approach. How to convert the output 8 bit from ADC to 16 bit signed
> > extended input into the FPGA? And how to convert from 16 bit output from
> > FPGA into 8 bit to support DAC0808? Or it is impossible at all..
> >
> > Thanks alot...
> >
> >

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 38739
Subject: Re: I2C multiplexer
From: "Carl Brannen" <carl.brannen@terabeam.com>
Date: Wed, 23 Jan 2002 23:49:43 +0000 (UTC)
Links: << >>  << T >>  << A >>
Andrew, the I2C bus is rather slow, compared to FPGA speed, so there
is a way that you can easily multiplex logic to control more than one
I2C bus with the same logic.  When they do it in processors it's
called something like "hyperfine multithreading".  The idea is to
design the control logic for a single I2C bus, and then add enough
pipeline delays between stages of logic so that a given I2C state
is only valid every 4th clock, if you want to get 4 I2C buses from
a single logic design.

For example, if the design included a counter, you would separate
the counter into an increment circuit and a register.  Then, feedback
the register output to the incrementer input through 3 extra stages
of logic.  That way the incrementer will be incrementing four
completely independent values, each every 4th clock.

Then you need a trivial amount of control logic to determine which
of the four phases go to which of the four I2C buses, and to
interface to the processor (or controller).

This trick is particularly cute in Xilinx FPGAs that support single
LUT shift registers.  Of course knowing that you're going to
duplicate a design will influence you to choose different design
techniques.  One that works well with this sort of multithreading
is state machines implemented with ROMs.

Carl


"Andrew Ha" <akha@cisco.com> wrote in message
news:3C45D59A.F7C0B6CE@cisco.com...

> Is there verilog code available in public domain that will multiplex an
> I2C bus among multiple I2C busses?


-- 
Posted via Mailgate.ORG Server - http://www.Mailgate.ORG

Article: 38740
Subject: Re: APEX-II vs VIRTEX-II
From: kayrock66@yahoo.com (Jay)
Date: 23 Jan 2002 15:53:56 -0800
Links: << >>  << T >>  << A >>
I've used both the 20K1500 and XC2V6000.  We had a similar requirement
and went with the Xilinx part.  As far as speed, I think you're in the
same ball park with the latest chips from each guy.  We were under the
impression that the Xilinx offering had more on chip block ram (at the
time the decision was made).  As it turns out it wasn't that big a
deal because we just ended up expanding our rams to fit the size of
the part (parameterized design).  I think the bigger issue is that of
tools.  Tool crashes at 2am can ruin your whole day.  My most recent
experience with Quartus II was not good, and IMHO it seems the Xilinx
stuff, while clunkier looking, gets the job done.

Jay

spholroyd@iee.org (Steve Holroyd) wrote in message news:<b623f4cf.0201111039.2a16155@posting.google.com>...
> I am currently task of recommending the largest, fastest and most
> memory FPGA that's readily available the first half of this year for a
> FPGA Array Card.
> 
> The choices have been narrowed down to two families Altera's APEX-II
> (EP2A70) and XILINX Virtex-II (XC2V6000).
> 
> Which can operate at the highest speed?
> 
> Steve

Article: 38741
Subject: Re: Internal tri state buffer..
From: Ray Andraka <ray@andraka.com>
Date: Wed, 23 Jan 2002 23:54:54 GMT
Links: << >>  << T >>  << A >>
Cheapest in cost per lut, but far less a foregone conclusion when you compare the logic implemented per dollar.  The
tristates are not the only thing that can eat LEs.  Small delay queues need a flip-flop per bit, where all Xilinx since
the early 4K devices can use the LUTs as RAM, or even shift registers so you can get up to 17 bits of delay per
LUT+FF.    Also, another LE eater is the fact that the Altera carry logic separates the 4 input LUT into a pair of
3LUTs, one of which does the carry function.  That pushes arithmetic with more than two inputs (or in the case of 10K a
clock enable) to two or more layers of logic where the same function fits in one level in any Xilinx device.  Examples
here are accumulators with load, adder/subtractors, adders with muxes, etc.

vt313@comsys.ntu-kpi.kiev.ua wrote:

> uttam singh wrote:
> >
> > what are the advantages and disadvantages of internal tri state buffer which xilinx provided but altera does not?
>
> I felt the advantage when we designed the microprocessor model.
> The common bus with tenths of sources and destinations
> is mapped into Xilinx FPGA exellently.
> And when we synthesized this project into Altera Flex,
> then the LC number doubled due to the very heavy multiplexers.
>
> Altera says that due to the absent of tristates,
> its FPGAs are cheapest.
>
> Regards,
> Anatoli Sergyienko

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 38742
Subject: Re: Simple shift register not working
From: kayrock66@yahoo.com (Jay)
Date: 23 Jan 2002 16:08:09 -0800
Links: << >>  << T >>  << A >>
A couple of comments:

1) What does this thing do in your simulation?  If you're learning, do
it on a simulator, its faster to see when you make mistakes
like...(read below)
2) No reset, add this, you might get away with it in the FPGA because
the flops power up with zeros in them.  Your sim will not work because
initial state is not known.
3) Although theoretically it should work, I've never seen anyone do
the reverse order [0:8] thing, its arbitrary so might as well follow
convention.
4) You know that clock pins on FPGA's have to be particular pins?
5) What the guy said about not using #'s in synthsizable code, they
have no place except to mark where someone was having trouble getting
something to work.
6) data <= {data[6:0], in};  Pure genious, I just learned a new trick
on how to code shift registers, just goes to show you can always pick
up new tricks no matter how long you mess around with these things? 
I've been using loops as of late to do that very thing, this is
better.
7) As far as blocking versus non-blocking- Use "<=" in clocked
processes, and use "=" in non clocked processes and functions.  You
did it correctly here!

Jay

goodsell@bridgernet.com (Kevin Goodsell) wrote in message news:<2fa5ba58.0201181414.75af84d5@posting.google.com>...
> Hi. I know very little about FPGAs or using HDLs, so please bare with
> me. I'm trying to get the following module (in Verilog) to work with a
> Spartan 2 FPGA using the Xilinx Webpack software:
> 
> module shift_reg(in, clk, out);
> input in, clk;
> output [0:8] out;
> 
> reg [0:8] data;
> 
> assign out = data;
> 
> always @(posedge clk)
> begin
> 	data <= #1 {data[1:8], in};
> /*	data[0] <= #1 data[1];
> 	data[1] <= #1 data[2];
> 	data[2] <= #1 data[3];
> 	data[3] <= #1 data[4];
> 	data[4] <= #1 data[5];
> 	data[5] <= #1 data[6];
> 	data[6] <= #1 data[7];
> 	data[7] <= #1 data[8];
> 	data[8] <= #1 in; */
> end
> endmodule
> 
> The part that is commented out is another thing that I've tried. I've
> also tried many variations on the assignments (blocking, non-blocking,
> with/without delays inside and outside the assignments, and so on). I
> am nearly convinced that the problem is not the code, but has
> something to do with the way the software is handling the clk signal.
> 
> First, let me explain what I'm seeing when I test it. It seems that on
> the rising edge of clk, the "in" signal is read into every bit of
> data, rather than only data[8]. Occasionally, the lower bits seem to
> fail to register a change, though.
> 
> In my user constraints file, if I try to assign clk to a normal I/O
> pin, I get the following error:
> 
> ERROR:MapLib:93 - Illegal LOC on symbol "clk" (pad signal=clk) or
> BUFGP symbol "clk_BUFGP" (output signal=clk_BUFGP), IPAD-IBUFG should
> only be LOCed to GCLKIOB site.
> 
> I don't know what this means, or whether it has anything to do with
> the module not working. For the record, here's my .ucf file:
> 
> #NET "clk" LOC = "P112"; # this line causes the error
> NET "in" LOC = "P110";
> NET "out<0>" LOC = "P3";
> NET "out<1>" LOC = "P5";
> NET "out<2>" LOC = "P7";
> NET "out<3>" LOC = "P9";
> NET "out<4>" LOC = "P14";
> NET "out<5>" LOC = "P16";
> NET "out<6>" LOC = "P18";
> NET "out<7>" LOC = "P21";
> NET "out<8>" LOC = "P23";
> 
> Thanks ahead of time for any help.
> 
> -Kevin

Article: 38743
Subject: Re: Xilinx Timing report question
From: kayrock66@yahoo.com (Jay)
Date: 23 Jan 2002 16:20:26 -0800
Links: << >>  << T >>  << A >>
I'm going to venture to guess that if you're gating your clock, using
an FPGA and your asking a question on a newsgroup, that you aren't
doing this for power savings but instead because you want to slow down
the operation of the circuit.  The answer assuming this is to not gate
your clock, use a counter to generate an enable at the desired
frequency and use it in your clocked processes to enable operation.

Jay



dottavio@ised.it (Antonio) wrote in message news:<fb35ea96.0201152338.4ee5882e@posting.google.com>...
> In a project using Gated Clock implemented with Synplify I've the
> following Xilinx Timing Report, but I control in Synplify, there's a
> BUFG on clk_div_n line, so my question is what else it needs ??
> 
> WARNING:Timing - Clock nets using non-dedicated resources were found
> in this
>    design. Clock skew on these resources will not be automatically
> addressed
>    during path analysis. To create a timing report that analyzes clock
> skew for
>    these paths, run trce with the '-skew' option.
> 
>    The following clock nets use non-dedicated resources:
>       clk_div_n  
> 
>                     
> 
> 
>                         Antonio

Article: 38744
Subject: Re: Missing IPAD, OPAD, etc. in Xilinx WebPACK Schematic Capture Library
From: Dave Vanden Bout <devb@xess.com>
Date: Wed, 23 Jan 2002 20:09:06 -0500
Links: << >>  << T >>  << A >>
"Robert S. Grimes" wrote:

> Thanks, Kamal!  It's this sort of beginner's question that is so frustrating
> for, well, beginners!

If you really are a beginner, then we have some tutorials on using WebPACK 4.1
for FPGAs

    http://www.xess.com/appnotes/webpack-4_1-fpga.pdf

and for CPLDs

    http://www.xess.com/appnotes/webpack-4_1-cpld.pdf



>
>
> "Kamal Patel" <kamal.patel@xilinx.com> wrote in message
> news:3C4EF2DF.E8111FEF@xilinx.com...
> > Hello Bob,
> >
> > In ECS, the schematic capture tool for ISE, PADs have been replaced by
> > I/O Markers.  Therefore in place of an IPAD or OPAD you would have
> > either an input or output I/O Marker.  Additionally, IBUFs and OBUFs
> > have also become optional parts of the schematic.  The only reason you
> > may still want to use I/O Buffers is for clocks, tri-states, renaming nets
> > for
> > the port listing, and special I/Os.
> >
> > To use I/O Markers in ECS, go to Add ==> I/O Marker, then make
> > sure you have selected the correct polarity and click on the end of the
> > net where you would normally place the buffer or pad.
> >
> > I hope this helps.
> >
> > Best regards,
> > Kamal Patel
> >
> > "Robert S. Grimes" wrote:
> >
> > > Hi all,
> > >
> > > I'm missing the IPAD, OPAD, IOPAD symbols in the unified libraries.  Any
> > > ideas?
> > >
> > > Thanks!
> > >
> > > -Bob
> >




--
|| Dr. Dave Van den Bout   XESS Corp.               (919) 387-0076 ||
|| devb@xess.com           2608 Sweetgum Dr.        (800) 549-9377 ||
|| http://www.xess.com     Apex, NC 27502 USA   FAX:(919) 387-1302 ||



Article: 38745
Subject: boot manager
From: bburnett01@hotmail.com (Burnett)
Date: 23 Jan 2002 19:02:43 -0800
Links: << >>  << T >>  << A >>
I'm designing a test board with a microprocessor and an fpga.  The
microprocessor has several pins that can be jumpered at bootup to
specify the bus width, whether to boot from flash or rom, etc.  Some
of the pins need to be held to certain logic levels in a certain
sequence depending on the desired boot settings.  I've got plenty of
room in the fpga and I'm considering implementing a timer and counter
to control these signals.  I would then use an external jumpered pin
on the fpga that I might jumper to control booting in a production
versus debug mode.

I'm comparing this to the old pc motherboards that used to require
lots of jumpers on board versus newer models that have all software
settings for the boot sequence.  Are fpga's used in this way or am I
looking for a different type of component?

Article: 38746
Subject: NTSC/IEEE1394 input to VGA output in FPGA, with overlay
From: "Speedy" <speedracer67@yahoo.invalid>
Date: Thu, 24 Jan 2002 03:36:05 GMT
Links: << >>  << T >>  << A >>
Hi All,

    I'm looking at designing a system to acquire live video from NTSC or
IEEE1394, overlay an image on it (cross hairs, text, maybe more) and output
that image to a VGA monitor at 30fps.  I see the XSV series from Xess, and
it looks like I'm half way there using that setup.  I would need to add the
IEEE1394 PHY, possibly a LLC, and a microcontroller (for IEEE1394 set-up and
other stuff).  Anyone use this dev board, and have some opinions to share?
What are the limitations of implementing IEEE1394 in a FPGA, with or without
the link layer chip?  All opinions are welcome!

Ryan Press



Article: 38747
Subject: Re: boot manager
From: Mike Treseler <tres@tc.fluke.com>
Date: Wed, 23 Jan 2002 20:41:40 -0800
Links: << >>  << T >>  << A >>
Burnett wrote:
> I'm designing a test board with a microprocessor and an fpga.  The
> microprocessor has several pins that can be jumpered at bootup to
> specify the bus width, whether to boot from flash or rom, etc.  Some
> of the pins need to be held to certain logic levels in a certain
> sequence depending on the desired boot settings.  I've got plenty of
> room in the fpga and I'm considering implementing a timer and counter
> to control these signals.  I would then use an external jumpered pin
> on the fpga that I might jumper to control booting in a production
> versus debug mode.

Might work with an eeprom-based device. 
A ram-based device might not be sane at  boot time.

On the other hand, what's the advantage of a jumper on an fpga pin
vs. a jumper on a processor pin?

> Are fpga's used in this way or am I
> looking for a different type of component?

It could be, but for rarely changed options, consider using resistors,
selectively loaded in a pullup or pulldown position.

           --Mike Treseler

Article: 38748
Subject: Re: Simple shift register not working
From: ospyng@yahoo.com (spyng)
Date: 23 Jan 2002 23:22:28 -0800
Links: << >>  << T >>  << A >>
Hi,
you did not define your clk pad, (it is mask off in your ucf file), so
did you connect your external clk to the corrected clock pad?

spyng



goodsell@bridgernet.com (Kevin Goodsell) wrote in message news:<2fa5ba58.0201181414.75af84d5@posting.google.com>...
> Hi. I know very little about FPGAs or using HDLs, so please bare with
> me. I'm trying to get the following module (in Verilog) to work with a
> Spartan 2 FPGA using the Xilinx Webpack software:
> 
> module shift_reg(in, clk, out);
> input in, clk;
> output [0:8] out;
> 
> reg [0:8] data;
> 
> assign out = data;
> 
> always @(posedge clk)
> begin
> 	data <= #1 {data[1:8], in};
> /*	data[0] <= #1 data[1];
> 	data[1] <= #1 data[2];
> 	data[2] <= #1 data[3];
> 	data[3] <= #1 data[4];
> 	data[4] <= #1 data[5];
> 	data[5] <= #1 data[6];
> 	data[6] <= #1 data[7];
> 	data[7] <= #1 data[8];
> 	data[8] <= #1 in; */
> end
> endmodule
> 
> The part that is commented out is another thing that I've tried. I've
> also tried many variations on the assignments (blocking, non-blocking,
> with/without delays inside and outside the assignments, and so on). I
> am nearly convinced that the problem is not the code, but has
> something to do with the way the software is handling the clk signal.
> 
> First, let me explain what I'm seeing when I test it. It seems that on
> the rising edge of clk, the "in" signal is read into every bit of
> data, rather than only data[8]. Occasionally, the lower bits seem to
> fail to register a change, though.
> 
> In my user constraints file, if I try to assign clk to a normal I/O
> pin, I get the following error:
> 
> ERROR:MapLib:93 - Illegal LOC on symbol "clk" (pad signal=clk) or
> BUFGP symbol "clk_BUFGP" (output signal=clk_BUFGP), IPAD-IBUFG should
> only be LOCed to GCLKIOB site.
> 
> I don't know what this means, or whether it has anything to do with
> the module not working. For the record, here's my .ucf file:
> 
> #NET "clk" LOC = "P112"; # this line causes the error
> NET "in" LOC = "P110";
> NET "out<0>" LOC = "P3";
> NET "out<1>" LOC = "P5";
> NET "out<2>" LOC = "P7";
> NET "out<3>" LOC = "P9";
> NET "out<4>" LOC = "P14";
> NET "out<5>" LOC = "P16";
> NET "out<6>" LOC = "P18";
> NET "out<7>" LOC = "P21";
> NET "out<8>" LOC = "P23";
> 
> Thanks ahead of time for any help.
> 
> -Kevin

Article: 38749
Subject: NIOS ver 1.1.1 type boards for sale: Money making opportunity.
From: "Victor Schutte" <victors@mweb.co.za>
Date: Thu, 24 Jan 2002 09:28:45 +0200
Links: << >>  << T >>  << A >>
Would anybody out there be interested in  buying and/or reselling my Nios
based SBC. I am currently using it in some of my products but the more I
sell the cheaper I can manufacture it for.  I stopped waiting for Nios v2
and will be releasing my current design to the public.

The current board includes 256K SRAM, 512 user FLASH, 67 I/Os, 8 interrupts,
10 LEDs, 512 x 32 bit registers, 4 serial ports and  MSTEP multiply, but
what I propose doing is selling each board with a set of different
configurations e.g. 32bit CPU, hardware multiplier, 1 UART and less I/O,
or more I/O, no interrupts, more UARTs. The idea is that the user buys the
hardware and transforms it into what he/she wants it to be. When I create
newer or faster configurations I will email the files to the registered
clients.  The toolset is GNU so I can just make copies of the set supplied
to me by Altera (I cannot give away the IP core).

The current board runs at 20MHz and will be fast enough for most
applications. The speed can be increased to about  50MHz with faster
devices. You can also opt. to buy a board with a 160 000 or 200 000 gate
device. Although I currently do not have any implementations larger than 100
000 gates I will be creating some that may include fast IDE ports, simple
VGA, Ethernet MAC, SPI, SDRAM (probably requires lots more I/O pins on PCB)
and DSP type functions. So by buying the a bigger chip will pay off later.
When Nios V2 is released I expect  to put more functions in the chip.

Cost: The standard 20MHz board  sells for about $370 USD one off. Everything
is quantity driven and higher quantities will be cheaper. Faster/Larger
FPGAs will obviously  be more expensive. I am still busy working out prices
because our exchange rate is messing up everything (but then our labor and
assembly costs are extremely cheap)


Other uses: The board is based on a FPGA (20K100QFP-240) with RAM and FLASH.
I can, if  requested (with signed NDA), supply pin layouts which an advanced
user (using Quartus) can use as a FPGA development board.

Size: The PCB is a 4 layer PCB measuring 120mm x 90 mm.

Requirements: A PC with Win98 or Win2000,  serial port and Power supply
(2.5V, 3.3V and 5V). You do not need to know how a FPGA works. If you can
program C you will be up and running in about 30 minutes.

Uses of board: Just about any embedded task you can think of, usually where
the fastest PIC or 8051 circuit would never reach and a 486 SBC would cost
too much. Educational, control, logging, ........ Remember that the user
self will be able to load the configuration and that a single hardware
configuration will have several uses, because it will be controlled by many
possible software configurations.


Contact: Victor Schutte at victors@mweb.co.za





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