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Messages from 36275

Article: 36275
Subject: Is There a Xilinx Floorplanner Tutorial?
From: kevinbraceusenet@hotmail.com (Kevin Brace)
Date: 4 Nov 2001 23:55:16 -0800
Links: << >>  << T >>  << A >>
Sort of a follow up question to the posting I made about Xilinx
Floorplanner (see: Xilinx Floorplanner Effectiveness).
Other than the Floorplanner Guide I can download from Xilinx website,
are there any other documentation on how to use Xilinx Floorplanner?
Some kind of tutorial on actually floorplanning a real design will be
nice.



Regards,



Kevin Brace (don't respond to me directly, respond within the
newsgroup)

Article: 36276
Subject: Aldec question
From: cappellainfuocata@yahoo.it (Banana)
Date: 5 Nov 2001 00:02:51 -0800
Links: << >>  << T >>  << A >>
I use Aldec 3.6 to create a simulation of my project in vhdl, in it
there's the opportunity to create schematics, my problem is how I can
to send the output of one block to another block on the same schematic
and at the same time to another block on another schematic, in fact if
I use a port the simulator tell me that there's a problem. Can you
help me in this ???


Banana

Article: 36277
Subject: Re: Aldec question
From: "wojtek" <b_wojtek@aldec.katowice.pl>
Date: Mon, 5 Nov 2001 09:20:59 +0100
Links: << >>  << T >>  << A >>
You should create a named wire connected to your output terminal and other
ports of  schematic blocks.
The name of wire should be differ from a name of output terminal.
Wojtek

"Banana" <cappellainfuocata@yahoo.it> wrote in message
news:d23ae64d.0111050002.ee8f4b8@posting.google.com...
> I use Aldec 3.6 to create a simulation of my project in vhdl, in it
> there's the opportunity to create schematics, my problem is how I can
> to send the output of one block to another block on the same schematic
> and at the same time to another block on another schematic, in fact if
> I use a port the simulator tell me that there's a problem. Can you
> help me in this ???
>
>
> Banana



Article: 36278
Subject: Re: High level synthesis will never work well :)
From: "Andrew Brown" <andrewbr@nortelnetworks.com>
Date: Mon, 5 Nov 2001 08:28:59 -0000
Links: << >>  << T >>  << A >>
"Petter Gustad" <newsmailcomp1@gustad.com> wrote in message
news:m3elnhcg2w.fsf@scimul.dolphinics.no...
> Iwo.mergler@soton.sc.philips.com writes:
>
> > Here we go...
> >
> > #include <stdio.h>
> >
> > int main(void)
> > {
> > printf("Hello World.\n");
> > }
> >
> > gcc -o hello hello.c; strip hello
> >
> > -rwxr-xr-x    1 mergler  users        3016 Nov  2 15:00 hello
> >
> > < 3 KB
>
> You're cheating. If you do a "file hello" you will see that it's
> dynamically linked. Most of the code resides in libraries which are
> linked in at run time. Try to add a -static to your compile command
> line and check the size of the executable then...
>
> Petter
> --
> ________________________________________________________________________
> Petter Gustad   8'h2B | (~8'h2B) - Hamlet in Verilog   http://gustad.com

Okay - so the code on the boot sector of a floppy which uses int 10 (i
think) to write is only 512 bytes, int 10 isn't that big either (a few K).
It writes to the screen and could easily write helloe world.
The code IS small.
If you want to link in several meg of crap that's up to u.




Article: 36279
Subject: Re: High level synthesis will never work well :)
From: Petter Gustad <newsmailcomp1@gustad.com>
Date: 05 Nov 2001 10:20:38 +0100
Links: << >>  << T >>  << A >>
"Andrew Brown" <andrewbr@nortelnetworks.com> writes:

> "Petter Gustad" <newsmailcomp1@gustad.com> wrote in message
> news:m3elnhcg2w.fsf@scimul.dolphinics.no...
> > Iwo.mergler@soton.sc.philips.com writes:
> >
> > > Here we go...
> > >
> > > #include <stdio.h>
> > >
> > > int main(void)
> > > {
> > > printf("Hello World.\n");
> > > }
> > >
> > > gcc -o hello hello.c; strip hello
> > >
> > > -rwxr-xr-x    1 mergler  users        3016 Nov  2 15:00 hello
> > >
> > > < 3 KB
> >
> > You're cheating. If you do a "file hello" you will see that it's
> > dynamically linked. Most of the code resides in libraries which are
> > linked in at run time. Try to add a -static to your compile command
> > line and check the size of the executable then...
> >
> > Petter
> > --
> > ________________________________________________________________________
> > Petter Gustad   8'h2B | (~8'h2B) - Hamlet in Verilog   http://gustad.com
> 
> Okay - so the code on the boot sector of a floppy which uses int 10 (i
> think) to write is only 512 bytes, int 10 isn't that big either (a few K).
> It writes to the screen and could easily write helloe world.
> The code IS small.
> If you want to link in several meg of crap that's up to u.

I didn't want to link in several megs of crap. I just wanted to point
out that the size of a any dynamically linked executable can be made
very small, simply by moving most of the code into the library. 

Petter
-- 
________________________________________________________________________
Petter Gustad   8'h2B | (~8'h2B) - Hamlet in Verilog   http://gustad.com

Article: 36280
Subject: Re : Xilinx multiplier core - problem
From: Nick Mckay <mckay@xilinx.com>
Date: Mon, 05 Nov 2001 11:53:36 +0000
Links: << >>  << T >>  << A >>
Hi,

George brought this point up earlier in the month. I'd like to point out
that this problem has been fixed in version 4.0 of the multiplier.
I hope this helps,

Nick

> > Subject: Xilinx multiplier core - problem
> > Date: Thu, 1 Nov 2001 16:28:37 -0000
> > From: "George Constantinides" <g.constantinides@ic.ac.uk>
> > Organization: Imperial College, London, UK
> > Newsgroups: comp.arch.fpga
> >
> > Has anyone noticed that for the xilinx multiplier core (v. 3.1), a
constant
> > coefficient multiplier with a negative coefficient appears to
require one
> > more coefficient bit (port B width) than it should?
> >
> >     Thus coef = 5 requires 3 bits, coef = -5 requires 5 bits (NOT 4
bits).
> >
> > This contradicts the (correct) statement in the core datasheet which
states
> > that the coef value must be between -2^(port_b_width-1) and
> > 2^(port_b_width-1) - 1 for signed coefficients. What's going on
here??
> >
> >         George


Article: 36281
Subject: Re: JTAG problem
From: Jan Coombs <jcoombs@cwcom.net>
Date: Mon, 05 Nov 2001 13:02:33 +0000
Links: << >>  << T >>  << A >>
"J. Reed Walker" wrote:
> 
> Hi.
> 
> I'm using Xilinx WebPack with a SpartanII board.  I have checked everything
> on my board time and again, but I keep getting the following error message
> when
> trying to use the Xilinx JTAG Programmer software:
> 
> 'counter(Device1): Manufacturer's ID = Unknown Manufacturer ID :
> 01110001000001001000001001110001

After other suggestions Xilinx recommended to change my printer port
when I had similar problems with an XC95108. I fitted an old ISA printer
port card into my Athlon system and all then worked consistantly. Still
don't know why!

Jan Coombs
--
Murray Microft - logical design in & around chips.
+44 23 80 90 95 00

Article: 36282
Subject: Re: spartan synthesis with synopsis
From: newman5382@aol.com (newman)
Date: 5 Nov 2001 05:17:36 -0800
Links: << >>  << T >>  << A >>
I yield to the experts Ray and Peter.  
In my defense, I had done a quick looksy at Figure 2 
Spartan/XL Simplified CLB Logic Diagram (some featuresnot shown) 
on page 4-63 of the Xilinx Programmable Logic Data Book 2000, and it
shows a G-LUT, F-LUT, H-LUT, two registers, and some configuration
controlled muxes.  I had remembered that Ray had said in a previous
post, that the FPGA Editor was a good way to analyze what was truely
in the CLB, and I did mention using the FPGA editor in the reply to
Tim.

But thank-you Peter and Ray for enlightening me on the Spartan I clb
structure.

Newman

Ray Andraka <ray@andraka.com> wrote in message news:<3BE581AE.BE3D18DC@andraka.com>...
> Patently untrue.  The Spartan architecture is basically the xilinx 4000E architecture.  It has a dedicated
> carry chain _in_front_ of the LUTs.  To instantiate it, you use the CY4 primitive plus one of the CY4 mode
> select primitives, which is connected to the CY4 with an 8 bit bus, selecting the right CY4 mode set for the
> function you wish to instantiate.  You'll have to refer to the carry section of the libraries guide for the
> details.  That said, synthesis should instantiate the carry chain.  IIRC (It has been a little while since I
> last used the 4K architecture), synplicity doesn't infer the carry chain for 4K devices when there are less
> than about 6-8 bits in the arithmetic/count function.  You may have to massage your description to make it into
> something the synthesizer can successfully infer.  Try putting the mux and add outside the process as a
> concurrent statement.
> 
> newman wrote:
> 
> > It looked to me that the Spartan CLB does not include any
> > dedicated carry logic.  Each LUT has one output, so
> > at least two LUT's would be required per bit... one to
> > generate the cout bit, and one to generate the pc bit.
> >
> > Have you tried looking at the design after P&R with the
> > FPGA editor?  This may shed more light on the situation.
> >
> > Newman
> >
> > "Tim Boescke" <t.boescke@tu-harburg.de> wrote in message news:<9rvn5u$10hndj$1@ID-107613.news.dfncis.de>...
> > > I am currently trying to synthesize a loadable
> > > accumulator with synopsis. The target architecture
> > > is a spartan. (not 2)
> > >
> > > In my opinion the code below should fit into one 4 LUT
> > > per bit. (inputs to each 4 LUT: pc, cin, load, inp)
> > > However, after synthesis the design requires no less
> > > than 16 4-luts.
> > >
> > > Did I miss something ? Is there any way to infer a
> > > combined add/load structure ? I already tried
> > > lots of combinations without success and unfortunately
> > > it seems that the xilinx libs dont allow direct
> > > access to the LUTs and the carry logic for spartan..
> > > (They do for spartan 2)
> > >
> > > ------------------------------------------------------
> > >
> > > architecture synth of counter is
> > >   signal pc: std_logic_vector(7 downto 0);
> > > begin
> > >      process(clk)
> > >      begin
> > >         if (res ='1') then
> > >           pc <= "00000000";
> > >         elsif rising_edge(clk) then
> > >           if (load = '1') then
> > >             pc <= inp;
> > >           else
> > >             pc <= pc + inp;
> > >           end if;
> > >         end if;
> > >      end process;
> > >
> > >         outp <= pc;
> > > end synth;
> 
> --
> --Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email ray@andraka.com
> http://www.andraka.com
> 
>  "They that give up essential liberty to obtain a little
>   temporary safety deserve neither liberty nor safety."
>                                           -Benjamin Franklin, 1759

Article: 36283
Subject: Re: Synplyfy to Xilinx pipe
From: Michael Boehnel <boehnel@iti.tu-graz.ac.at>
Date: Mon, 05 Nov 2001 15:00:50 +0100
Links: << >>  << T >>  << A >>
a) Start the Xilinx Design Manager (don't confuse with Xilinx project
manager)
from within Synplify IDE (Options-Xilinx-Start Design Manager..). The
Synplify project must use a Xilinx device to have this option enabled.

b) Use Xilinx Foundation ISE 4.1

Michael

Banana wrote:

> Good Morning,
> I use Synplify 6 to synthesize my project, it also perform the mapping
> and produce an edif file, I want to send this for Place and Route to
> Xilinx 3.3 , how I could perform this ??
> There's an opprtunity to use synplify directly from Xilinx but this
> seems not work in my computer. Thanks for your help.
>
> Banana




Article: 36284
Subject: Help with Synplify Warning
From: Adam Elbirt <aelbirt@ece.wpi.edu>
Date: Mon, 5 Nov 2001 09:13:30 -0500
Links: << >>  << T >>  << A >>
I'm getting a warning from Synplify that doesn't make a lot of sense:

@W:"/home/aelbirt/tmp/ntru/roundfunction.vhd":5:7:5:19|Resource limit for
cost not achieved. Available = 0, used = 756.

Can anyone provide some clues as to what this may mean?  I get two of
these warnings in the file roundfunction.vhd and when I double click on
the warning it brings me to the following line of my code:

TYPE statetype IS (WAITING, OP1, OP2);

Any help would be much appreciated.

Adam

-------------------------------------------------------------------------------------
Instructor Adam Elbirt
Cryptography and Information Security Laboratory
Electrical and Computer Engineering Department
Worcester Polytechnic Institute
Worcester, Massachusetts
508-831-5840 Phone
508-831-5491 Fax

"A mathematician is a blind man in a dark room looking for a black cat
that isn't there."
          -- Charles Darwin


Article: 36285
Subject: Re: Implementing Filter
From: Ray Andraka <ray@andraka.com>
Date: Mon, 05 Nov 2001 14:43:47 GMT
Links: << >>  << T >>  << A >>
The Aldec (Alatek) generator does not put any placement info in its core
as far as I can see.  The xilinx cores will probably get you better
performance, if for no other reason than that they are floorplanned.


vt313@comsys.ntu-kpi.kiev.ua wrote:

> The Aldec Active HDL 4.2. has a core generator which
> generates VHDL file for any FIR filter for XILINX FPGA.
>
> fre wrote:
> >
> > Holla
> > Wich different techniques do you know about Implementing FIR/IIR
> > Filters
> > in Spartan-FPGA (195 CLB). Is there any program to use or VHDL-Code.
> > Any Informations specially on Spartan (XILINX-FPGA) will be very
> > neccessary.
> > thanks for help!

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 36286
Subject: count and divide Idea needed
From: cappellainfuocata@yahoo.it (Banana)
Date: 5 Nov 2001 07:00:33 -0800
Links: << >>  << T >>  << A >>
Good Morning, 
I'm trying to produce a counter that count 0 , 1 , 2 at a rate of
99MHz and at the same time to use it to produce a clock of 33MHz, the
clock I need must be symmetrical so I can't use a simple loop counter.
Have you any idea on how I could arrange it in vhdl, following there
is my code but it seems to be not synthesizable, thanks for your help
...

             Banana






library IEEE;
use IEEE.std_logic_1164.all;	  
use IEEE.std_logic_unsigned.all;

entity counter_divider_3 is
	port (
		clk			: in  STD_LOGIC;
		reset		   : in  STD_LOGIC;
		count_3		: out STD_LOGIC_VECTOR (2 downto 0);
		clk_div_3 	: out STD_LOGIC 
		);
end counter_divider_3;


architecture counter_divider_3_arch of counter_divider_3 is
begin
	process (clk, reset)
		variable count_3_internal   : STD_LOGIC_VECTOR (2 downto 0);
		variable clk_div_3_internal : std_logic;
	begin
		if reset = '1' 
		then  
			count_3_internal := "000"; 
		elsif falling_edge(clk)
			then
				if (count_3_internal = "010") 
				then  -- si deve riazzerare il contatore
					count_3_internal     := "000";
					clk_div_3_internal	:= '0' ;
				else  
					count_3_internal := count_3_internal + 1;
				end if;
			elsif count_3_internal = "001"
				then
					clk_div_3_internal := '1' ;
		end if ;
		count_3 	<= count_3_internal   ;
		clk_div_3 	<= clk_div_3_internal ;
	end process;
	
end counter_divider_3_arch;

Article: 36287
Subject: Re: Registered as well as unregistered outputs?
From: Ray Andraka <ray@andraka.com>
Date: Mon, 05 Nov 2001 15:14:57 GMT
Links: << >>  << T >>  << A >>
It simply gives synthesis and mapping more options.  Often, synthesis will share the
combinatorial logic in front of a flip-flop, necessitating an unregistered connection.
With the 10K architecture, any shared logic prevents the use of the flip-flop.

nitin wrote:

> Hi...
>
>     Well i was very much asking from the veiw point of FLEX10K and
> APEX20K architectures. U see in 10K they had one output of the LE
> going to the feedback matrix of the LLI and one output to RFTs and
> CFTs. So that meant only either registered or unregistered output
> going to the LLI feedback matrix and also to the RFT's and CFTs.
>
>     But that changed with APEX20K devices where both outputs could got
> to all routing resources. Now is that becuse they wanted both
> registered and unregisterd outputs at the same time...?  What was the
> need that made them to do this change in the architecture...? I
> presumed there might be circuits where one might need that.
>
>     Well some more discussion on this will help a lot.
>
> Nitin.
>
> Ray Andraka <ray@andraka.com> wrote in message news:<3BE298CA.B67829D6@andraka.com>...
> > Depends entirely on your design style.  For highest performance, you'll
> > generally want to avoid using the unregistered output, but that also
> > limits your design options.
> >
> > nitin wrote:
> >
> > > Hi...
> > >
> > > Can anyone tell me how frequently and where both registered and
> > > unregistered outputs from an LE are required...?
> > >
> > > Ciao,
> > > nitin.
> >
> > --
> > --Ray Andraka, P.E.
> > President, the Andraka Consulting Group, Inc.
> > 401/884-7930     Fax 401/884-7950
> > email ray@andraka.com
> > http://www.andraka.com
> >
> >  "They that give up essential liberty to obtain a little
> >   temporary safety deserve neither liberty nor safety."
> >                                           -Benjamin Franklin, 1759

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 36288
Subject: Virtex II introduction schedule
From: rickman <spamgoeshere4@yahoo.com>
Date: Mon, 05 Nov 2001 10:49:41 -0500
Links: << >>  << T >>  << A >>
I am taking a serious look at using the Virtex II chips in a design that
will be going to prototype in Feb, '02. The size I will need is less
than the XC2V1000, but more than the XC2V40. That leaves the '80, '250
and '500 sized parts. But I can find no information on when they will be
available or target pricing. The '40 lists (web pricing) at about
$35-$40 and the '1000 shows up at $250-$300. 

I am not sure if the XC2V80 will be big enough and it looks like the
XC2V250 might be too expensive (>$100) for this application. Anyone have
the skinny on when Xilinx will be introducing these parts? Is Xilinx
planning to bring down the cost of the XC2V devices any time soon?
Certainly at the small end they are very pricey compared to Spartan II
or other brands of FPGAs. I can get an XC2S150 with 3500 LCs for the
price of an XC2V40 with only 512! Certainly the cost of the extra
features in the XC2V family is not THAT high?!


-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 36289
(removed)


Article: 36290
Subject: Xilinx ISE false timing errors?
From: "Dave Brown" <dbrown@novatel.ca>
Date: Mon, 5 Nov 2001 10:19:29 -0700
Links: << >>  << T >>  << A >>
Hi,
    When I run place and route using foundation ISE 4.1 (using FPGA Express
as synthesis tool), I get the report that the submitted design did not meet
timing requirements, those requirements with an asterix were not met. Then,
in the list of timing requirements, none have an asterix, and at the
completeion of place and route, it says all timing requirements met, 0
errors. Same thing if I look at the static timing report, it says all
constaints met. What gives? Is there a timing error in there? Seems like
there isn't, anyone else noticed this?
Thanks,
Dave




Article: 36291
Subject: Re: spartan synthesis with synopsis
From: Brian Philofsky <brian.philofsky@xilinx.com>
Date: Mon, 05 Nov 2001 10:31:29 -0700
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
--------------F1086CCDAC9C5FE4A48E1FE6
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit



You do have low-level access to the Spartan/XL resources via instantiation as you do with all Xilinx devices
however it is a bit different than with the Spartan-II and newer families.  In order to specify the logic in a
LUT, you must first describe the logic contents in the LUT, typically by specifying logic gate(s) with up to four
inputs and one output.  You then "entomb" this logic by instantiating an FMAP component around the logic.  This
tells the mapper that you want this logic in a LUT.  Look at FMAP in the Libraries guide for more details about
this.

In order to specify the carry chain, you must instantiate the proper CY4_xx component that tells the tools what
function you want to program into the carry structure.  There is an entire chapter devoted to this in the
Libraries Guide.  Check out chapter 12 for more details on how this works.

You can access the fore mentioned manuals on-line if you wish at http://support.xilinx.com/support/library.htm

Good luck,


--  Brian


Peter Alfke wrote:

> Spartan is based on XC4000, and SpartanXL is based on XC4000XL, and all of them have the same carry structure.
> Take a look at the XC4000 and XC4000XL documentation, it may be clearer. But it describes the identical
> architecture.
>
> Peter Alfke
> ====================================
> newman wrote:
>
> > It looked to me that the Spartan CLB does not include any
> > dedicated carry logic.  Each LUT has one output, so
> > at least two LUT's would be required per bit... one to
> > generate the cout bit, and one to generate the pc bit.
> >
> > Have you tried looking at the design after P&R with the
> > FPGA editor?  This may shed more light on the situation.
> >
> > Newman
> >
> > "Tim Boescke" <t.boescke@tu-harburg.de> wrote in message news:<9rvn5u$10hndj$1@ID-107613.news.dfncis.de>...
> > > I am currently trying to synthesize a loadable
> > > accumulator with synopsis. The target architecture
> > > is a spartan. (not 2)
> > >
> > > In my opinion the code below should fit into one 4 LUT
> > > per bit. (inputs to each 4 LUT: pc, cin, load, inp)
> > > However, after synthesis the design requires no less
> > > than 16 4-luts.
> > >
> > > Did I miss something ? Is there any way to infer a
> > > combined add/load structure ? I already tried
> > > lots of combinations without success and unfortunately
> > > it seems that the xilinx libs dont allow direct
> > > access to the LUTs and the carry logic for spartan..
> > > (They do for spartan 2)
> > >
> > > ------------------------------------------------------
> > >
> > > architecture synth of counter is
> > >   signal pc: std_logic_vector(7 downto 0);
> > > begin
> > >      process(clk)
> > >      begin
> > >         if (res ='1') then
> > >           pc <= "00000000";
> > >         elsif rising_edge(clk) then
> > >           if (load = '1') then
> > >             pc <= inp;
> > >           else
> > >             pc <= pc + inp;
> > >           end if;
> > >         end if;
> > >      end process;
> > >
> > >         outp <= pc;
> > > end synth;

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Article: 36292
Subject: Re: Help with Synplify Warning
From: Andy Peters <andy@exponentmedia.deletethis.com>
Date: Mon, 05 Nov 2001 18:29:01 GMT
Links: << >>  << T >>  << A >>
Adam Elbirt wrote:
> 
> I'm getting a warning from Synplify that doesn't make a lot of sense:
> 
> @W:"/home/aelbirt/tmp/ntru/roundfunction.vhd":5:7:5:19|Resource limit for
> cost not achieved. Available = 0, used = 756.
> 
> Can anyone provide some clues as to what this may mean?  I get two of
> these warnings in the file roundfunction.vhd and when I double click on
> the warning it brings me to the following line of my code:
> 
> TYPE statetype IS (WAITING, OP1, OP2);
> 
> Any help would be much appreciated.

Wow!  Inscrutable error messages are fun.

you may want to post the code -- it might be something we can deduce.

perhaps you're synthesizing a function and it's getting tooooooo big? 
Trying to unroll a loop?

--a

Article: 36293
(removed)


Article: 36294
Subject: Re: Help with Synplify Warning
From: Adam Elbirt <aelbirt@ece.wpi.edu>
Date: Mon, 5 Nov 2001 13:44:58 -0500
Links: << >>  << T >>  << A >>
I actually just got off the phone with Synplify.  Since there wasn't even
a code associated with it I figured it best to call.  Turns out it's a
Synplify bug - the message is Altera specific but I'm doing a Xilinx
design so it's spurious.

Adam

-------------------------------------------------------------------------------------
Instructor Adam Elbirt
Cryptography and Information Security Laboratory
Electrical and Computer Engineering Department
Worcester Polytechnic Institute
Worcester, Massachusetts
508-831-5840 Phone
508-831-5491 Fax

"A mathematician is a blind man in a dark room looking for a black cat
that isn't there."
          -- Charles Darwin

On Mon, 5 Nov 2001, Andy Peters wrote:

> Adam Elbirt wrote:
> >
> > I'm getting a warning from Synplify that doesn't make a lot of sense:
> >
> > @W:"/home/aelbirt/tmp/ntru/roundfunction.vhd":5:7:5:19|Resource limit for
> > cost not achieved. Available = 0, used = 756.
> >
> > Can anyone provide some clues as to what this may mean?  I get two of
> > these warnings in the file roundfunction.vhd and when I double click on
> > the warning it brings me to the following line of my code:
> >
> > TYPE statetype IS (WAITING, OP1, OP2);
> >
> > Any help would be much appreciated.
>
> Wow!  Inscrutable error messages are fun.
>
> you may want to post the code -- it might be something we can deduce.
>
> perhaps you're synthesizing a function and it's getting tooooooo big?
> Trying to unroll a loop?
>
> --a
>


Article: 36295
Subject: Re: Xilinx ISE false timing errors?
From: Bob Perlman <bob@cambriandesign.com>
Date: Mon, 05 Nov 2001 19:30:14 GMT
Links: << >>  << T >>  << A >>
Hi - 

On Mon, 5 Nov 2001 10:19:29 -0700, "Dave Brown" <dbrown@novatel.ca>
wrote:

>Hi,
>    When I run place and route using foundation ISE 4.1 (using FPGA Express
>as synthesis tool), I get the report that the submitted design did not meet
>timing requirements, those requirements with an asterix were not met. Then,
>in the list of timing requirements, none have an asterix, and at the
>completeion of place and route, it says all timing requirements met, 0
>errors. Same thing if I look at the static timing report, it says all
>constaints met. What gives? Is there a timing error in there? Seems like
>there isn't, anyone else noticed this?
>Thanks,
>Dave
>
>


Yes, I've seen this, too.  I've just installed SP2, and have not yet
determined whether this bug has gone away.

Bob Perlman

Article: 36296
Subject: Re: Virtex II introduction schedule
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Mon, 05 Nov 2001 20:04:19 +0000
Links: << >>  << T >>  << A >>


rickman wrote:

> I am taking a serious look at using the Virtex II chips in a design that
> will be going to prototype in Feb, '02. The size I will need is less
> than the XC2V1000, but more than the XC2V40. That leaves the '80, '250
> and '500 sized parts. But I can find no information on when they will be
> available or target pricing. The '40 lists (web pricing) at about
> $35-$40 and the '1000 shows up at $250-$300.
>
> I am not sure if the XC2V80 will be big enough and it looks like the
> XC2V250 might be too expensive (>$100) for this application. Anyone have
> the skinny on when Xilinx will be introducing these parts? Is Xilinx
> planning to bring down the cost of the XC2V devices any time soon?
> Certainly at the small end they are very pricey compared to Spartan II
> or other brands of FPGAs. I can get an XC2S150 with 3500 LCs for the
> price of an XC2V40 with only 512! Certainly the cost of the extra
> features in the XC2V family is not THAT high?!
>
> --
>

I asked this question a couple of months ago re the XC2V1500 & was told
"spring '02". Whether this means March or May I don't know.

You have to be a little careful with the comparison with the XC2S150's
"slice" count = 1720 vs the XC2V80's 512. Still a ratio of 3:1. What you get
with the V2 is, I think, this - none of which you might need:

o Speed.
o 4x bigger BlockRAMs.
o H/w multipliers.
o Very sophisticated phase adjustable DLLs.
o Lots more IO standards + some kind of output impedance control.
o (supposedly) much more predictable routing.
o `DDR' capable IO cells.

What we've also got it seems is a marketing driven renumbering of the
devices wrt the old V-E range.
e.g. if none of the above features is any use then in logic terms an
XC2V1000 =~ XCV400E.





Article: 36297
Subject: Re: How dense are FPGA/CPLD's
From: Neil Franklin <neil@franklin.ch.remove>
Date: 05 Nov 2001 21:31:41 +0100
Links: << >>  << T >>  << A >>
kevinbraceusenet@hotmail.com (Kevin Brace) writes:

> bazaillion@yahoo.com wrote in message news:<3be44c04.109339469@news.charter.net>...
> >
> > (1) How dense can you get these (How many gates)?
>
>         Most FPGAs are much larger than CPLDs.
> However, manufacturers of FPGAs really have a bad habit of inflating
> the gate count the chip can realistically fit.
> For example, an FPGA I use called Xilinx Spartan-II 150,000 "system
> gate" part (XC2S150), although Xilinx (http://www.xilinx.com) claims
> that part can fit 150,000 "system gates", the realistical gate count
> (not using vendor proprietary features) is
> about 30,000 to 35,000 gates.
> Yes, Xilinx's "system gate" inflates the realistically achievable gate
> count by about 5 times.
> Xilinx's rival Altera (http://www.altera.com) also inflates the gate
> count, but in my opinion, the gate count inflation seems to be about 2
> to 3 times.

Perhaps a small hint at how these numbers got so inflated:

In the days on FPGAs without BRAMs the numbers were fairly realistic.
Since BRAMs the vendors "cheat" by counting them as an obscene amount
of gates. Bad if you have no use for BRAMs.

The difference you observe in Xilinx "times 5" and Altera "times 3" is
due to Altera having less BRAMs.


Example: The Xilinx data sheet for Virtex XCV200 (= Spartan-II XC2S200
sizewise) lists 236'000 system gates without further comment.

But the XCV200E explicitely lists 306'000 system gates _and_ as 63'500
logic gates. As both of these have identical amounts of logic this gives
you for XC2S200 1/3 logic part!


> Spartan-IIs are low-end FPGAs, but a high-end FPGA like Xilinx
> Virtex-II 6M system gate part (XC2V6000) should be able to fit more
> than 1M realistical gates, if my assumption is correct.

The factor is most likely larger, as they have even more BRAMs, not
to forget them multipliers which also distort the "true" (= logic)
numbers even more.


> > (3)  Are they dense enough to build a CPU or a 3d VGA display chip
> > with these? or maybe multiple chips.
>
>         However, my guess is that you are thinking of whether or not
> an x86 processor might fit inside an FPGA.
> Probably a 4 to 5 years old x86 processor might fit inside one Xilinx
> Virtex-II 6M system gate part, and if one is not enough, you can use
> multiple of them.

My own calculations on this:

Define XCV200 or XC2S200 to be 63'500 logic gates (= 254'000 transistors)
plus 14 BRAMs a 4kbit (= 6kByte). That assuming all BRAMs as cache and
none as logic.

For an XCV1000 take 5 times logic (1'250'000 transitors) and 2 times cache.

For an XCV3200E take 3 times logic (3'750'000 transistors) and annother
4 times cache.

For an XC2V10000 (largest) take double logic (7'500'000 transistors).

All the above factors taken from LUT count growth.


This compares with Intel CPUs as follows:

80386 ca 250'000 transistors, no cache, all logic
80486 ca 1'000'000 transistors, >6*8*8k = ~300'000 of them for 8kByte
cache, 700'000 lest for logic
Pentium ca 3'500'000 transistors, >6*8*16k = ~600'000 for cache
PentiumII 5'500'000 transistors, cache most likely irrelevant


So a XC2S200 is basically a 386 with an 486es cache. XCV1000 is about
an dual 486. XCV3200E is a bit better than Pentium. XC2V10000 should
even have reserves on an PII. All that is assuming that you do not
want to downgrade the logic gate numbers by about 1.5.

Speed seems to be also about same ballpark of 30..100MHz for 368/486
in the XC2S200, but lagging when comparing XCV3200E with the fastest
Pentiums of 266MHz or XC2V10000 with 4/500MHz PIIs. I suppose it is
the routing PIPs in the FPGAs that are losing us the speed race.


P.S. I am presently implementing[1] an DEC PDP-10 1970s mainframe,
aiming for an XC2S200 or XCV300, and seem to be at the right size. That
is for processor and all peripherals. But I am using JBits tool, which
is very space efficient, but a lot of work to use.

[1] http://neil.franklin.ch/Projects/PDP-10/


> to put an external RAMDAC outside of the chip because an FPGA doesn't
> contain one (TI and IBM used to make high-end RAMDACs about 4 to 5
> years ago).

Try Brooktree. They seem to be the large RAMDAC people these days.


--
Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/
Hacker, Unix Guru, El Eng HTL/BSc, Sysadmin, Archer, Roleplayer
- Intellectual Property is Intellectual Robbery

Article: 36298
Subject: Re: A problem configuring APEX device
From: ikauranen@netscape.net (ikauranen)
Date: 5 Nov 2001 13:16:38 -0800
Links: << >>  << T >>  << A >>
Dear Colleagues,
I am on the way to resolve the problem. I have found that two clocks
driving APEX chip are 5V signals (though, series resistors are
present). And APEX cannot tolerate 5V levels. Initially, the card was
not 'mine'. I can control almost everything on it via computer
interface,  paying little attention to physical environment. IMHO,
this is a very new problem.

Igor Kauranen
Engineer

Article: 36299
Subject: Heatsink for Xilinx FF896 package?
From: "Pete Fraser" <pete@rgb.com>
Date: 05 Nov 2001 21:45:22 GMT
Links: << >>  << T >>  << A >>
I am involved in a design using a 2V1000 in the FF896 package.

We are allowing for a passive heatsink. Any recommendations?

This is for a shipboard application, so there will be vibration
and a hostile environment, so I'd like to use something
with positive retention (rather than two-sided sticky).

Thanks.





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