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Messages from 35925

Article: 35925
Subject: Re: Verilog vs. VHDL
From: "AME" <AME3141592@yahoo.com>
Date: Tue, 23 Oct 2001 22:37:01 -0700
Links: << >>  << T >>  << A >>
> In retrospect, the reason I wasn't able to learn HDL two years ago was
> not only because the books I read weren't that interesting

A list of good (practical, real-world) books that might be recommended for a
HDL newbie with extensive "real" digital circuit design?

-Martin




Article: 35926
Subject: Re: Verilog vs. VHDL
From: "AME" <AME3141592@yahoo.com>
Date: Tue, 23 Oct 2001 22:47:22 -0700
Links: << >>  << T >>  << A >>
"Ray Andraka" <ray@andraka.com> wrote in message
news:3BD5A1AF.EE18E655@andraka.com...
> I'm in the learn the synthesis subset first camp

Is there a resource (book/website?) with a list of the synthesizeable
elements?


> with the very important caveat
> that the pupil already has a good set of digital design skills.

Having the good digital design skills, it is frustrating to hit the HDL wall
and have to play with FF's, you feel kinda stupid.  But it's part of
learning.  You either deal with it or contract the work out.

As an interesting note, I'm attending a government research conference and
I've run into a number of people voicing frustration with the fact that we
are still using arcane ASCII-based technologies in many areas of computing.
Most of these individuals had nothing to do with FPGA design and work in
such diverse areas as medical databases and manufacturing.  The overall
feeling is that these tools seriously damage productivity because they don't
permit the user to elevate to levels of abstraction that can enhance
throughput and permit far and wide exploration.

-Martin






Article: 35927
Subject: Re: Verilog vs. VHDL
From: "Andrew Brown" <andrewbr@nortelnetworks.com>
Date: Wed, 24 Oct 2001 08:43:29 +0100
Links: << >>  << T >>  << A >>
"AME" <AME3141592@yahoo.com> wrote in message
news:9r5k4f020nr@enews1.newsguy.com...
> "Ray Andraka" <ray@andraka.com> wrote in message
> news:3BD5A1AF.EE18E655@andraka.com...
> > I'm in the learn the synthesis subset first camp
>
> Is there a resource (book/website?) with a list of the synthesizeable
> elements?

The synthesisable subset standard for VHDL is a good start (.6 i think ?)

I can understand people learning synthesisable VHDL first (thats the way i
did it), but if you wanted to use a tool like microsoft word (would you want
to?) you wouldn't be happy with an instructor teaching you only a small set
of it's features - especially when you know that somewhere along the line
you are going to need the features you haven't been taught.  Okay, so i know
that you could work with what you know until you need the extra features and
then go on another course, but think of all the bad habits you could have
formed.  Lists should be done with bullet points not by hitting
"TAB-HYPHEN-TAB", but if you've been doing that for a long time, it's a hard
habit to break.
Testbenches can be written with an RTL subset - but have you ever tried to
do directed random testing this way - i have - it hurts !!  I'd say it's at
least 100 times easier with behavioral code.  Almost all of my testbenches
were in RTL when i started and i wonder how any of my code worked.
I have to agree with your comment on digital design skills though.  In fact
it's probably even more important if you learn the full language.  How many
times have people asked when "my_sig mod 17" won't synthesise !!!  I think
that - in general - you need to understand what hardware your code will
produce.  There are circumstances where it is necessary to code in order to
produce a specific implementation of the hardware, but generally, as long as
you have an understanding of what the synthesiser will produce you should be
okay.
And lets face it ... no matter how good your design or testbench, your
always going to end up in the lab with an analyser trying to figure out why
comething isn't workinng.

> > with the very important caveat
> > that the pupil already has a good set of digital design skills.
>
> Having the good digital design skills, it is frustrating to hit the HDL
wall
> and have to play with FF's, you feel kinda stupid.  But it's part of
> learning.  You either deal with it or contract the work out.

If you have good digital design skills and a good knowledge of the entire
language (for those of us in the learn first camp) you should be able to put
the two together and understand how to use thelanguage to describe hardware.
The problem is learning the full language.

> As an interesting note, I'm attending a government research conference and
> I've run into a number of people voicing frustration with the fact that we
> are still using arcane ASCII-based technologies in many areas of
computing.
> Most of these individuals had nothing to do with FPGA design and work in
> such diverse areas as medical databases and manufacturing.  The overall
> feeling is that these tools seriously damage productivity because they
don't
> permit the user to elevate to levels of abstraction that can enhance
> throughput and permit far and wide exploration.
>
> -Martin

Software construction is years ahead of us and they still rely on ASCII
technologiues for the main implementation phases. (They have object modelers
and UML etc etc but they still write code).



Article: 35928
Subject: S/PDIF interface for FPGA
From: Robert Staven <robertst.stopthespam@tihlde.org>
Date: Wed, 24 Oct 2001 09:52:59 +0200
Links: << >>  << T >>  << A >>
Anyone have (free) code for a S/PDIF receiver?

(target is a Altera (ACEX) for now on, but it may change)

    )RST(


Article: 35929
Subject: Re: Bidirectional port is converted to input during synthesis
From: Nicolas Matringe <nicolas.matringe@ipricot.com>
Date: Wed, 24 Oct 2001 10:12:48 +0200
Links: << >>  << T >>  << A >>
Dave Brown a écrit :
> 
> The design is using VHDL and below is the architecture of my
> bidi ports, in case this helps. As a side note, other ports in
> the design that are bidirectional synthesize correctly I'm
> stumped.

Hi
That code looks fine so I think the problme is somewhere else. Are you sure 'en'
or 'dout' are not optimized and removed?

-- 
Nicolas MATRINGE           IPricot European Headquarters
Conception electronique    10-12 Avenue de Verdun
Tel +33 1 46 52 53 11      F-92250 LA GARENNE-COLOMBES - FRANCE
Fax +33 1 46 52 53 01      http://www.IPricot.com/

Article: 35930
Subject: Re: map,place &route
From: Nicolas Matringe <nicolas.matringe@ipricot.com>
Date: Wed, 24 Oct 2001 10:15:56 +0200
Links: << >>  << T >>  << A >>
Nandini a écrit :
> 
> hi,
[...]
> the ERRORS are: temp_mant and mant_out are 56 bit slv and this
> error occurs for every pad net
> 
> ERROR:basnu:142 - output pad net "mant_out36<56>" has an illegal
> connection
> ERROR:basnu:114 - logical net "temp_mant2<55>" has multiple
> drivers
> ERROR:basnu:114 - logical net "add_carry_in" has multiple
> drivers
> ERROR:basnu:142 - input pad net "add_carry_in" has an illegal
> connection
> ERROR:basnu:114 - logical net "to_start_adder" has multiple
> drivers
> ERROR:basnu:142 - input pad net "to_start_adder" has an illegal
> connection

Hi
I think you should post your code

-- 
Nicolas MATRINGE           IPricot European Headquarters
Conception electronique    10-12 Avenue de Verdun
Tel +33 1 46 52 53 11      F-92250 LA GARENNE-COLOMBES - FRANCE
Fax +33 1 46 52 53 01      http://www.IPricot.com/

Article: 35931
Subject: Re: Verilog vs. VHDL
From: hamish@cloud.net.au
Date: 24 Oct 2001 11:16:31 GMT
Links: << >>  << T >>  << A >>
AME <AME3141592@yahoo.com> wrote:
> Sure.   "<=" used for "assignment" as well as "less than or equal to".

> Of course, you might say that the context differntiates which is meant.
> Well, take, for example:

> a <= b <= c;

> 1-  Does this mean "evaluate b less-than-or-equal-to c and assign this to
> a"?
> 2-  Or, does it mean, "c to both b and an"?

It is never (2).

To assign to signals, use <= ; to assign to variables, use := .
You can write:

a <= b <= c;

(a would be a signal of type boolean), or

a := b <= c;

(a is a variable of type boolean), but not

a <= b := c;
a := b := c;
a <= b <= c; (if a is a variable)



Hamish
-- 
Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>

Article: 35932
Subject: Re: Verilog vs. VHDL
From: hamish@cloud.net.au
Date: 24 Oct 2001 11:33:55 GMT
Links: << >>  << T >>  << A >>
AME <AME3141592@yahoo.com> wrote:
> I've thought about that too.  VHDL allows you to document a huge array of
> things that I am sure today have no way to be realized.

That's because it's a simulation language as well. Some simulation
constructs can never be realized in hardware (like dynamic memory
allocation!).


Hamish
-- 
Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>

Article: 35933
Subject: Re: Bidirectional port is converted to input during synthesis
From: Jens Hildebrandt <jens.hildebrandt@etechnik.uni-rostock.de>
Date: Wed, 24 Oct 2001 13:43:30 +0200
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
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Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

Dave Brown wrote:
> 
> The design is using VHDL and below is the architecture of my bidi ports, in
> case this helps. As a side note, other ports in the design that are
> bidirectional synthesize correctly I'm stumped.
> entity bidi is
>    port
>    (
>          EN    : in std_ulogic;   -- output enable
>          DIN   : out std_ulogic;  -- input data from bus
>          DOUT  : in std_ulogic;   -- output data to bus
>          DIO   : inout std_ulogic -- I/O bus
>    );
> end bidi;
> architecture behavioural of bidi is
>    component OBUFT
>    port(
>       O                              : out   STD_ULOGIC;
>       I                              : in    STD_ULOGIC;
>       T                              : in    STD_ULOGIC);
>    end component;
>  component IBUF
>    port(
>       O                              : out   STD_ULOGIC;
>       I                              : in    STD_ULOGIC);
>    end component;
>    signal noten : std_ulogic;
> begin
>    noten <= not EN;
>     U1 : OBUFT port map
>    (
>       O  => DIO,
>       I  => DOUT,
>       T  => noten
>    );
>  U2 : IBUF port map
>    (
>       O  => DIN,
>       I  => DIO
>    );
> end behavioural;
> 
> "Dave Brown" <dbrown@novatel.ca> wrote in message
> news:9r4f1t$qom$1@pallas.novatel.ca...
> > Hi,
> >     I'm using Xilinx ISE 4.1 for a SpartanXL design. I have a
> bidirectional
> > port that works great during simulation. When I sysnthesize it however, at
> > the top level where the bidi is formed from an input, an output, and an
> > enable signal, the tool removes the output signal at the top level and
> says
> > this signal is unused, and I end up with only an input. I'm scratching my
> > head here, what have I missed?
> > Thanks,
> > Dave
> >
> >
> >

Hi Dave,

although your code is logically correct, I doubt it could be synthesized
correctly. IBUF, OBUF, OBUFT etc. components are mapped to IOBLOCKS in the FPGA
and these blocks are connected to a pin (if not unbound).  An IOBLOCK , AFAIK,
can be configured to be either an input (IBUF), output (OBUF),
three-state-output (OBUFT) or bidirectional port (IOBUF) etc. but not IBUF and
OBUFT at the same time. This is what your code says and hence the compiler has
to decide what to do with port DIO. Obviously, it decides for DIO to be an
input, may be because this is the safe variant in case you have some device
outside the FPGA driving the DIO pin.
A solution would be to instantiate an IO-buffer component (IOBUF , IIRC) or to
write something like

DIO <= DOUT when noten = '0'
		else (others => 'Z');
DIN <= DIO;

I used both veriants in the past and they worked fine. 
Good luck,
 Jens
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adr:;;Richard-Wagner-Str. 31;Rostock-Warnemuende;;18119;Germany
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--------------0A3987229804666F969AEA76--


Article: 35934
Subject: Re: Fpga Synthesis Process
From: "Johan Van Dyck" <Johan.Van.Dyck@philips.com>
Date: Wed, 24 Oct 2001 13:43:51 +0200
Links: << >>  << T >>  << A >>
Hi

* The synth process reads your code and transforms it to known blocks like
mux, adder,... It also unrolls the loops.
* The mapper (implementation) maps the generic blocks from the synth to the
real lay-out from your FPGA. As a generic block could be  a '200 to 5 mux',
in the FPGA only '4 to 2 mux' (this is an expample) could exist. Lot's of
4t02 mux must be cascaded to form the original block.
* After mapping you can simulate a kind of gatelist generated out of the
tool. (We never use that).
*Of course, you need to verify the FPGA after the mapping is programmed
insite.

Hope this helps you a littel bit

Johan.

"Ramnath" <ramnathgoenka@yahoo.com> wrote in message
news:62cc2cff.0110201050.7d89b335@posting.google.com...
> hi,
>
>     I am a newbie to this area and slowly picking up things. I am
> using Xilinx foundation series v 1.5 and Model sim.
>
>     Alothough i have all these and even using these things, i do not
> fully understand the concept of all.
>
>    Could any one tell me what are the various stages in the synthesis
> of FPGA.
>
> To be exact what is done in the synthesis process, implementation
> process, simulation and verification.
>
>    What is the difference between simulation done in ModelSim and the
> simulation done in Xilinx itself.
>
>   Some one told me Modelsim is for simulation the testbeches ( still
> not clear, please through some light)
>
>        Thanks a lot in advance and expecting the reply.
>
> Ramnath



Article: 35935
Subject: Re: Verilog vs. VHDL
From: tgingold@pc204.ipricot.fr
Date: 24 Oct 2001 12:38:46 GMT
Links: << >>  << T >>  << A >>
In article <3BD469F8.4BEAB515@algor.co.uk>, Rick Filipkiewicz wrote:
> 
> 
> Edwin Naroska wrote:
> 
>> Hi,
>>
>> AME wrote:
>>
>> > <hamish@cloud.net.au> wrote in message
>> > news:3bd27bb1$0$26089$afc38c87@news.optusnet.com.au...
>> >
>>
>> > Well, take, for example:
>> >
>> > a <= b <= c;
>> >
> 
> Even to reduce VHDL RSI I would not write something like this. Even if it is well
> defined from the  synthesis and simulation aspects IMHO it's still a bad coding
> style.
> 
> if (b <= c) then a <= '1'; else  a <= '0';
[...]
Non, since the type of (b <= c) is boolean, the corresponding statement is:
if (b <= c) then a <= true; else a <= false;

Of course, it is better written like this:
a <= (b <= c);  -- which I found clearer.

BTW, what's about:
  when '1' => a <= '1';
bad coding style...

Tristan.

Article: 35936
Subject: handel-C
From: phil <p.beylik@libertysurf.fr>
Date: 24 Oct 2001 14:02:52 GMT
Links: << >>  << T >>  << A >>

Hi,

Somebody has already  work with the card rc1000-pp of celoxica 


-- 
User of http://www.foorum.com/. The best tools for usenet searching.

Article: 35937
Subject: Re: Bidirectional port is converted to input during synthesis
From: "Dave Brown" <dbrown@novatel.ca>
Date: Wed, 24 Oct 2001 10:18:20 -0600
Links: << >>  << T >>  << A >>
Thanks, you were right, I checked and the enable signal was the culprit, it
wasn't even in the port mappping for the top level component that
instatiated the padring! Odd that I didn't get a more noticable warning
about that, it only showed up in the MAP report as one line that said the
output portion of the signal was unused and had been removed. It works fine
now, thanks for the reply.
Dave

"Nicolas Matringe" <nicolas.matringe@ipricot.com> wrote in message
news:3BD67800.14F6F230@ipricot.com...
> Dave Brown a écrit :
> >
> > The design is using VHDL and below is the architecture of my
> > bidi ports, in case this helps. As a side note, other ports in
> > the design that are bidirectional synthesize correctly I'm
> > stumped.
>
> Hi
> That code looks fine so I think the problme is somewhere else. Are you
sure 'en'
> or 'dout' are not optimized and removed?
>
> --
> Nicolas MATRINGE           IPricot European Headquarters
> Conception electronique    10-12 Avenue de Verdun
> Tel +33 1 46 52 53 11      F-92250 LA GARENNE-COLOMBES - FRANCE
> Fax +33 1 46 52 53 01      http://www.IPricot.com/



Article: 35938
Subject: Re: Bidirectional port is converted to input during synthesis
From: "Dave Brown" <dbrown@novatel.ca>
Date: Wed, 24 Oct 2001 10:20:49 -0600
Links: << >>  << T >>  << A >>
Hi,
    Thanks for the reply. I've got it working now, it was a problem with the
enable signal. As for using an IOBUF, I can't, that's not supported in a
SpartanXL, so what I posted is correct, you have to make your own IOBUF
using an OBUFT and an IBUF. If you look at the Libraries Guide in the Xilinx
PDF documentation, the little schematic for the IOBUF is basically an IBUF
and an OBUFT anwyay.
Thanks,
Dave

"Jens Hildebrandt" <jens.hildebrandt@etechnik.uni-rostock.de> wrote in
message news:3BD6A962.229FD0A7@etechnik.uni-rostock.de...
> Dave Brown wrote:
> >
> > The design is using VHDL and below is the architecture of my bidi ports,
in
> > case this helps. As a side note, other ports in the design that are
> > bidirectional synthesize correctly I'm stumped.
> > entity bidi is
> >    port
> >    (
> >          EN    : in std_ulogic;   -- output enable
> >          DIN   : out std_ulogic;  -- input data from bus
> >          DOUT  : in std_ulogic;   -- output data to bus
> >          DIO   : inout std_ulogic -- I/O bus
> >    );
> > end bidi;
> > architecture behavioural of bidi is
> >    component OBUFT
> >    port(
> >       O                              : out   STD_ULOGIC;
> >       I                              : in    STD_ULOGIC;
> >       T                              : in    STD_ULOGIC);
> >    end component;
> >  component IBUF
> >    port(
> >       O                              : out   STD_ULOGIC;
> >       I                              : in    STD_ULOGIC);
> >    end component;
> >    signal noten : std_ulogic;
> > begin
> >    noten <= not EN;
> >     U1 : OBUFT port map
> >    (
> >       O  => DIO,
> >       I  => DOUT,
> >       T  => noten
> >    );
> >  U2 : IBUF port map
> >    (
> >       O  => DIN,
> >       I  => DIO
> >    );
> > end behavioural;
> >
> > "Dave Brown" <dbrown@novatel.ca> wrote in message
> > news:9r4f1t$qom$1@pallas.novatel.ca...
> > > Hi,
> > >     I'm using Xilinx ISE 4.1 for a SpartanXL design. I have a
> > bidirectional
> > > port that works great during simulation. When I sysnthesize it
however, at
> > > the top level where the bidi is formed from an input, an output, and
an
> > > enable signal, the tool removes the output signal at the top level and
> > says
> > > this signal is unused, and I end up with only an input. I'm scratching
my
> > > head here, what have I missed?
> > > Thanks,
> > > Dave
> > >
> > >
> > >
>
> Hi Dave,
>
> although your code is logically correct, I doubt it could be synthesized
> correctly. IBUF, OBUF, OBUFT etc. components are mapped to IOBLOCKS in the
FPGA
> and these blocks are connected to a pin (if not unbound).  An IOBLOCK ,
AFAIK,
> can be configured to be either an input (IBUF), output (OBUF),
> three-state-output (OBUFT) or bidirectional port (IOBUF) etc. but not IBUF
and
> OBUFT at the same time. This is what your code says and hence the compiler
has
> to decide what to do with port DIO. Obviously, it decides for DIO to be an
> input, may be because this is the safe variant in case you have some
device
> outside the FPGA driving the DIO pin.
> A solution would be to instantiate an IO-buffer component (IOBUF , IIRC)
or to
> write something like
>
> DIO <= DOUT when noten = '0'
> else (others => 'Z');
> DIN <= DIO;
>
> I used both veriants in the past and they worked fine.
> Good luck,
>  Jens



Article: 35939
Subject: Re: Are there any Coolrunner P5Z22V10 (PLCC) devices left anywhere?
From: Peter Alfke <peter.alfke@xilinx.com>
Date: Wed, 24 Oct 2001 09:55:11 -0700
Links: << >>  << T >>  << A >>

--------------2C8BDDEA2291AD3BE7579621
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Here is the answer from Xilinx in Albuquerque ( the former Philips CoolRunner
group)

"We have misc. inventory on the Philips-marked product as follows:

P5Z22V10IDA (10 ns industrial) - thousands
P5Z22V10-7A (7.5ns commercial) - hundreds

We don't have any excess die on this one, so no Xilinx marked (XCR22V10) devices

can be ordered.  Anybody can purchase the Philips marked devices through any
Xilinx
franchised distributor on a NCNR basis.  Order multiple is 26, a minimum order
will most probably apply, but if they're buying appx. 500 pieces they will meet
it."

Hope that helps.  Sounds like good news!

Peter Alfke, Xilinx Applications
===========================================
Peter wrote:

> Hi,
>
> Xilinx bought this line from Philips, then discontinued it!
>
> Are there any stocks left anywhere? I need a few hundred pieces.
>
> Any speed is OK.
>
> Peter.
> --
> Return address is invalid to help stop junk mail.
> E-mail replies to zX80@digiYserve.com but remove the X and the Y.
> Please do NOT copy usenet posts to email - it is NOT necessary.

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<!doctype html public "-//w3c//dtd html 4.0 transitional//en">
<html>
Here is the answer from Xilinx in Albuquerque ( the former Philips CoolRunner
group)
<p>"<b>We have misc. inventory on the Philips-marked product as follows:</b><b></b>
<p><b>P5Z22V10IDA (10 ns industrial) - thousands</b>
<br><b>P5Z22V10-7A (7.5ns commercial) - hundreds</b>
<p>We don't have any excess die on this one, so no Xilinx marked (XCR22V10)
devices
<br>can be ordered.&nbsp; Anybody can purchase the Philips marked devices
through any&nbsp; Xilinx
<br>franchised distributor on a NCNR basis.&nbsp; Order multiple is 26,
a minimum order
<br>will most probably apply, but if they're buying appx. 500 pieces they
will meet it."
<p>Hope that helps.&nbsp; Sounds like good news!
<p>Peter Alfke, Xilinx Applications
<br>===========================================
<br>Peter wrote:
<blockquote TYPE=CITE>Hi,
<p>Xilinx bought this line from Philips, then discontinued it!
<p>Are there any stocks left anywhere? I need a few hundred pieces.
<p>Any speed is OK.
<p>Peter.
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Article: 35940
Subject: Re: Bidirectional port is converted to input during synthesis
From: Andy Peters <andy@exponentmedia.deletethis.com>
Date: Wed, 24 Oct 2001 16:59:39 GMT
Links: << >>  << T >>  << A >>
Dave,

I think Jens' point is that you're doing things the hard way.

Why instantiate the library component when the synthesis tool can figure
things out for you?

--a

Dave Brown wrote:
> 
> Hi,
>     Thanks for the reply. I've got it working now, it was a problem with the
> enable signal. As for using an IOBUF, I can't, that's not supported in a
> SpartanXL, so what I posted is correct, you have to make your own IOBUF
> using an OBUFT and an IBUF. If you look at the Libraries Guide in the Xilinx
> PDF documentation, the little schematic for the IOBUF is basically an IBUF
> and an OBUFT anwyay.
> Thanks,
> Dave
> 
> "Jens Hildebrandt" <jens.hildebrandt@etechnik.uni-rostock.de> wrote in
> message news:3BD6A962.229FD0A7@etechnik.uni-rostock.de...
> > Dave Brown wrote:
> > >
> > > The design is using VHDL and below is the architecture of my bidi ports,
> in
> > > case this helps. As a side note, other ports in the design that are
> > > bidirectional synthesize correctly I'm stumped.
> > > entity bidi is
> > >    port
> > >    (
> > >          EN    : in std_ulogic;   -- output enable
> > >          DIN   : out std_ulogic;  -- input data from bus
> > >          DOUT  : in std_ulogic;   -- output data to bus
> > >          DIO   : inout std_ulogic -- I/O bus
> > >    );
> > > end bidi;
> > > architecture behavioural of bidi is
> > >    component OBUFT
> > >    port(
> > >       O                              : out   STD_ULOGIC;
> > >       I                              : in    STD_ULOGIC;
> > >       T                              : in    STD_ULOGIC);
> > >    end component;
> > >  component IBUF
> > >    port(
> > >       O                              : out   STD_ULOGIC;
> > >       I                              : in    STD_ULOGIC);
> > >    end component;
> > >    signal noten : std_ulogic;
> > > begin
> > >    noten <= not EN;
> > >     U1 : OBUFT port map
> > >    (
> > >       O  => DIO,
> > >       I  => DOUT,
> > >       T  => noten
> > >    );
> > >  U2 : IBUF port map
> > >    (
> > >       O  => DIN,
> > >       I  => DIO
> > >    );
> > > end behavioural;
> > >
> > > "Dave Brown" <dbrown@novatel.ca> wrote in message
> > > news:9r4f1t$qom$1@pallas.novatel.ca...
> > > > Hi,
> > > >     I'm using Xilinx ISE 4.1 for a SpartanXL design. I have a
> > > bidirectional
> > > > port that works great during simulation. When I sysnthesize it
> however, at
> > > > the top level where the bidi is formed from an input, an output, and
> an
> > > > enable signal, the tool removes the output signal at the top level and
> > > says
> > > > this signal is unused, and I end up with only an input. I'm scratching
> my
> > > > head here, what have I missed?
> > > > Thanks,
> > > > Dave
> > > >
> > > >
> > > >
> >
> > Hi Dave,
> >
> > although your code is logically correct, I doubt it could be synthesized
> > correctly. IBUF, OBUF, OBUFT etc. components are mapped to IOBLOCKS in the
> FPGA
> > and these blocks are connected to a pin (if not unbound).  An IOBLOCK ,
> AFAIK,
> > can be configured to be either an input (IBUF), output (OBUF),
> > three-state-output (OBUFT) or bidirectional port (IOBUF) etc. but not IBUF
> and
> > OBUFT at the same time. This is what your code says and hence the compiler
> has
> > to decide what to do with port DIO. Obviously, it decides for DIO to be an
> > input, may be because this is the safe variant in case you have some
> device
> > outside the FPGA driving the DIO pin.
> > A solution would be to instantiate an IO-buffer component (IOBUF , IIRC)
> or to
> > write something like
> >
> > DIO <= DOUT when noten = '0'
> > else (others => 'Z');
> > DIN <= DIO;
> >
> > I used both veriants in the past and they worked fine.
> > Good luck,
> >  Jens

Article: 35941
Subject: Re: Are there any Coolrunner P5Z22V10 (PLCC) devices left anywhere?
From: Andy Peters <andy@exponentmedia.deletethis.com>
Date: Wed, 24 Oct 2001 17:00:38 GMT
Links: << >>  << T >>  << A >>
Jim,

Sounds like Peter has boards he needs stuffed and a different package
won't work!

--a

Jim Granville wrote:
> 
> Peter wrote:
> >
> > Hi,
> >
> > Xilinx bought this line from Philips, then discontinued it!
> >
> > Are there any stocks left anywhere? I need a few hundred pieces.
> >
> > Any speed is OK.
> >
>  Peter,
> 
>  I would think they are 'long gone' - web searches turn up some
> 'dusty numbers', but no stocks.
> 
>  There is no perfect match, but closest are the ATF22V10CQZ, and
> PEEL22V10Z.
>  Both are available as 'web samples', so you could qualify them.
> 
>  Longer term, look at the ATF1502ASL - this has an ITD option
> ( not well explained in the data), that allows a clock that
> is NOT in the prod terms ( ie -> Reg CLK only), to not activate the
> ITD, and this can greatly reduce Icc.
>  Best results are from paused state engines, worst, but still 50%
> saving, is from a simple counter.
>  In QFP44, it's appx the same/smaller than PLCC28
> 
> -jg

Article: 35942
Subject: Re: S/PDIF interface for FPGA
From: Andy Peters <andy@exponentmedia.deletethis.com>
Date: Wed, 24 Oct 2001 17:04:27 GMT
Links: << >>  << T >>  << A >>
Robert Staven wrote:
> 
> Anyone have (free) code for a S/PDIF receiver?
> 
> (target is a Altera (ACEX) for now on, but it may change)

Big problem with S/PDIF is you'll need a PLL to sync on the recovered
clock.  Either that, or you'll need a switch to select sample rates, and
some higher-speed logic to synchronize things.

Why not just buy one of the Crystal Semiconductor (owned by Lattice)
parts and be done with it?

Do yourself a favor, and don't directly use the Crystal
MCLK/LRCLK/BCLK/data outputs to drive a converter.  Use a FIFO in
between, and generate your clocks locally.  You'll cut the jitter down.

--a

Article: 35943
Subject: Re: Verilog vs. VHDL
From: Andy Peters <andy@exponentmedia.deletethis.com>
Date: Wed, 24 Oct 2001 17:09:58 GMT
Links: << >>  << T >>  << A >>
AME wrote:
> 
> "Ray Andraka" <ray@andraka.com> wrote in message
> news:3BD5A1AF.EE18E655@andraka.com...
> > I'm in the learn the synthesis subset first camp
> 
> Is there a resource (book/website?) with a list of the synthesizeable
> elements?

Try the web sites of the synthesis tool vendors: exemplar, synplicity,
synopsys.  you may be able to download their manuals, one of which will
detail which language constructs are valid for synthesis.

> As an interesting note, I'm attending a government research conference and
> I've run into a number of people voicing frustration with the fact that we
> are still using arcane ASCII-based technologies in many areas of computing.
> Most of these individuals had nothing to do with FPGA design and work in
> such diverse areas as medical databases and manufacturing.  The overall
> feeling is that these tools seriously damage productivity because they don't
> permit the user to elevate to levels of abstraction that can enhance
> throughput and permit far and wide exploration.

The biggest problem with graphic design entry is that the tools are
always changing.  How many times have you "upgraded" your software, only
to discover that the new tool won't process your old designs?  Of if you
need to move from one tool vendor to another?  All of you guys who do
board layout know what I'm talkin' about here.  PCAD libraries read by
Mentor or OrCAD?  Fuhgetaboutit.

A text file, readable by any editor, is the most maintainable format, if
not always the most obvious.  Of course, you really can't do board
layout in a text editor, so bullets have to be bitten somewhere!

--a

Article: 35944
Subject: Re: Verilog vs. VHDL
From: Andy Peters <andy@exponentmedia.deletethis.com>
Date: Wed, 24 Oct 2001 17:13:45 GMT
Links: << >>  << T >>  << A >>
tgingold@pc204.ipricot.fr wrote:

> BTW, what's about:
>   when '1' => a <= '1';
> bad coding style...

Well, that's more than bad coding style -- it's pathological!

-a

Article: 35945
Subject: Re: how to dublicate logic?
From: Jens-Christian Lache <lache@tu-harburg.de_removeTheUnderscore>
Date: Wed, 24 Oct 2001 20:41:52 +0200
Links: << >>  << T >>  << A >>
Vasudeva Kamath wrote:

> Jens-Christian Lache <lache@tu-harburg.de_removeTheUnderscore> wrote in message news:<3BB2DFB8.BA6A9116@tu-harburg.de_removeTheUnderscore>...
> > John_H wrote:
> >
> > > >
> > > > Hi!
> > > > To reduce the fanout of a tristate signal leading to 64 iobs I
> > > > tried dublicate this signal. How do I tell
> > > > the synthesis tool now not to remove my dublicated logic?
> > > > ( I tried to use a BUFG as well, but that didn't work at all)
> > > > thanks for your help,
> > > > -jc-
> >
> > The synthesis tool is synopsis fpga express.
> > -jc-
>
> You can try the "dont touch" option in fpga express, to prevent the
> synthesis tool from removing any logic.
>
> --Vasudeva

I'm using Foundation 3.1. Could you tell me where I can set this option?

What is the right way to have it dublicated automatically? I still don't know
how to set a max fanout, even though I got the message from the xilinx
support center .

They wrote:
----
Regarding your question:
If I use Synopsys FPGA Express as synthesis tool,
  how do I specify a max fanout?

With the process windows of  Foundation ISE, expand the synthesize tree.
Click on: Create Functional Function -> Edit Constraint.
That will open the constraint window.
click on the Register Tab to set up the fanout.

If you are using FPGA express in standalone, the maximum fan out can be set
in: Synthesis -> Option -> Optimization.
----
Since the ucf file is read in after the synthesis step, I don't believe the first
suggestion will work. I don't have a "register "tab anyway, only "Global",
"Ports", "advanced", "ucf Constraints (read-write), "ucf constraints (read-only)"
and "Source constraints (read only)". They talk propably about a different version.

In "Synthesis -> Option -> Optimization" I don't have a fanout entry either.

Thanks,
-jc-


Article: 35946
Subject: Re: High-speed Logic, Military/Space Grade
From: Rene Tschaggelar <tschaggelar@dplanet.ch>
Date: Wed, 24 Oct 2001 21:45:05 +0200
Links: << >>  << T >>  << A >>
One rule still holds , the simpler the logic, the faster.
The whole is slowly being overtaken by FPGAs. 
10 years ago, a synchronous 32bit counter in ECL didn't reach 100MHz,
now you can have multiple of them in one FPGA.

There are new logic families that are faster than ECL, but they only 
consist of simple gates, except when it comes to 16bit drivers.
Above a certain complexity, I'd favor an FPGA. This single flipflop
stuff
just uses too much space and is hard to route when optimized for
speed.

The currently fastest stuff is SiGe ASICs, they are said to be 
clocked at several GHz.

Rene
-- 
Ing.Buero R.Tschaggelar - http://www.ibrtses.com

rk wrote:
> 
> Hi,
> 
> Perhaps a bit off-topic for an FPGA group but I think the right audience
> is here.
> 
> I haven't used ECL in a number of years (silly FPGAs taking up too much
> time) but would like to know what the current families (and
> manufacturers) are for very high-speed logic, US military/space
> qualified, with "reasonable" power levels and worst-case clock
> frequencies of 600 MHz, min.  I'm looking at some operations such as
> synchronous counters, Johnson twisted ring counters, etc.  The output of
> the logic will be fed into an FPGA (there, that should make this
> on-topic :-).
> 
> Thanks in advance.
> 
> --
> rk

Article: 35947
Subject: Re: JTAG question
From: Mike <none@null.net>
Date: Wed, 24 Oct 2001 12:52:27 -0700
Links: << >>  << T >>  << A >>
Dean,

Would the Spartan-II be driving the TDI of the CPLD, or it's own TDI?  If it's the former, this could cause problems.  When TMS is common to all the devices (as it would be if you are implementing a single chain) that means all the devices are always in the same JTAG state.  If the Spartan-II has loaded the bypass instruction and is in the SDR state, this means it is driving it's TDO pin with whatever is on the TDI pin (delayed by one TCK cycle).  If the Spartan-II is also driving the TDI pin of the first CPLD, you will get contention on this signal.  If however, the Spartan-II is driving it's <i> own </i> JTAG signals, and the Spartan-II is first in the chain, you will not hit this contention issue.

HTH,

Mike

Article: 35948
Subject: Re: comp.arch.fpg : Reconfiguring of a virtex via JTAG
From: Mike <none@null.net>
Date: Wed, 24 Oct 2001 12:59:54 -0700
Links: << >>  << T >>  << A >>
Anton-

I see a couple of issues with the above flow.  I would look at XAPP139 closely, for this includes a example sequence of instructions needed to perform this type of operation.  In terms of your CRC question, the CRC is only calculated on the data loaded into specific registers- details of that are in XAPP138.

HTH,

Mike

Article: 35949
Subject: SpartanXL Device Utilization Summary
From: "Dave Brown" <dbrown@novatel.ca>
Date: Wed, 24 Oct 2001 16:19:51 -0600
Links: << >>  << T >>  << A >>
Hi all,
    Thanks for all the great help so far, this is a great newsgroup! I'm
looking at my Device Utilization Summary in Foundation ISE 4.1, for a
Spartan 05XL, and I'm not sure why the overall CLB utilization is so high
when my other numbers are low, is there some tool setting I'm missing, if
not, what is eating up all my CLBs? Here's the exerpt from the summary:

Device utilization summary:

   Number of External IOBs            52 out of 80     67%
      Flops:                           0
      Latches:                         0

   Number of CLBs                     87 out of 100    87%
      Total Latches:                   0 out of 200     0%
      Total CLB Flops:                68 out of 200    34%
      4 input LUTs:                  137 out of 200    68%
      3 input LUTs:                   27 out of 100    27%

   Number of BUFGLSs                   5 out of 8      62%

Thanks,
Dave





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