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Messages from 36375

Article: 36375
Subject: Quadrature Encoder Sampling Time
From: anon7864@hushmail.com (anon7864)
Date: 7 Nov 2001 16:41:34 -0800
Links: << >>  << T >>  << A >>
I was wondering if anyone would like to share their experience in
doing quadrature encoder decoding in programmable logic.

I am trying to deduce the minimal sampling rate for a hand-turned knob
that is a 2 channel, 16 position device. Currently I use a 12 state
Finite State Machine running at 6MHz to decode the encoders. I am
trying to reduce this to a more reasonable level to reduce power
consumption/heat.

The spec sheet on the encoders we use says that the maximum RPM is
100. A call to the factory reveals that: "Encoder section - 300 RPM
max, average manual operation is in the range of 1 to 16 RPM max.
...tested (Per MIL-3786/39) @rate of 10 cycles per miv, which is 20
RPM (One cycle is a rotation thru all positions and full return.)"

I would like to design for worst case of 300RPM.

position_time=200ms/16positions=13msec

Shannon's theorem says that scan_rate=13msec/2=6msec (round down)

This scan rate is not what I expected. I would have expected to scan
at around 1msec or less. I have proven this empirically on the
o-scope.

So why in the encoder world, is the emperical to calculated comparison
so bad? What am I missing in my analysis? Am I just starting out with
a bogus initial RPM? What has your experience been on this problem??

Thanks in advance!

Article: 36376
Subject: Re: FPGA Wish list
From: "Pete Fraser" <pfraser@dnai.com>
Date: Wed, 7 Nov 2001 19:13:03 -0800
Links: << >>  << T >>  << A >>

"Peter Alfke" <peter.alfke@xilinx.com> wrote in message
news:3BE9A84C.EAF321C4@xilinx.com...

> Very soon,  we will have 3 Gbps serial data I/O

Any idea how much this will add to the price?

e.g., I'm using 2V1000s now. How many fast
serdes will I get on a similarly sized device, and
what will the premium be?



Article: 36377
Subject: Re: How dense are FPGA/CPLD's
From: kevinbraceusenet@hotmail.com (Kevin Brace)
Date: 7 Nov 2001 19:35:23 -0800
Links: << >>  << T >>  << A >>
Rene Tschaggelar <tschaggelar@dplanet.ch> wrote in message news:<3BE993A3.F854175D@dplanet.ch>...
> A few corrections :
> 
> Altera FPGA's can be EEPROM or SRAM based depending on the density.
> 

        As far as I know, all FPGA devices from Altera are SRAM-based.
Perhaps you are talking about MAX series which is EEPROM-based, but I
will call MAX a CPLD because they are product term based devices.
Although it is not always correct, I still think it is a fairly
accurate way to categorize programmable devices that most CPLDs are
based on EEPROM and most FPGAs are based on SRAM or antifuse.
Occasionally there is an exception like Actel/GateField's EEPROM-based
FPGA called ProASIC.
It looks like an interesting device, but I don't hear or see it that
often.



> I wouldn't learn Verilog nor VHDL to start with but use the graphic
> editors provided. They allow rather complex stuff and are
> self-documenting.
> 
> 
> Rene
> 
> 
> 

        I think that depends on the person.
I find HDL easier to work than with schematic entry.
I don't have any good memories of working with schematic entry.
Especially, if you have to design a state machine.



Regards,



Kevin Brace (don't respond to me directly, respond within the
newsgroup)

Article: 36378
Subject: Re: Quadrature Encoder Sampling Time
From: Jim Granville <jim.granville@designtools.co.nz>
Date: Thu, 08 Nov 2001 16:45:10 +1300
Links: << >>  << T >>  << A >>
anon7864 wrote:
> 
> I was wondering if anyone would like to share their experience in
> doing quadrature encoder decoding in programmable logic.
> 
> I am trying to deduce the minimal sampling rate for a hand-turned knob
> that is a 2 channel, 16 position device. Currently I use a 12 state
> Finite State Machine running at 6MHz to decode the encoders. I am
> trying to reduce this to a more reasonable level to reduce power
> consumption/heat.
> 
> The spec sheet on the encoders we use says that the maximum RPM is
> 100. A call to the factory reveals that: "Encoder section - 300 RPM
> max, average manual operation is in the range of 1 to 16 RPM max.
> ...tested (Per MIL-3786/39) @rate of 10 cycles per miv, which is 20
> RPM (One cycle is a rotation thru all positions and full return.)"
> 
> I would like to design for worst case of 300RPM.
> 
> position_time=200ms/16positions=13msec
> 
> Shannon's theorem says that scan_rate=13msec/2=6msec (round down)
> 
> This scan rate is not what I expected. I would have expected to scan
> at around 1msec or less. I have proven this empirically on the
> o-scope.
> 
> So why in the encoder world, is the emperical to calculated comparison
> so bad? What am I missing in my analysis? Am I just starting out with
> a bogus initial RPM? What has your experience been on this problem??
> 
> Thanks in advance!

There are two real-world effects, not covered by a simple RPM edge rate
calculation.

i) Shock. Not such an issue in a knob, but on shaft encoders, or
anything 
mechanically coupled, very high peak count rates can occur.

ii) Edge Chatter. A system can stop, with a conting edge active.
Ideally, this just causes +1 / -1 counts, but a faster sampling time
helps
this track.

 Then, avaiable ICs target not just Knobs, but shaft applications, and
that's
another reason for a big ratio between sampling rates.

 For a knob, you should be able to go much lower than 6MHz, and if you
use the ITD feature of the ATF150x CPLD, the current drops significantly
in
'state idle' or non-change conditions ( <<1mA achievable ).

 In the encoder design, keep an eye open for 'aperture effects', which
is
where more than a single state transistion bit depends on an async 
IP.

-jg


-- 
======= 80x51 Tools & PLD IP Specialists  =========
= http://www.DesignTools.co.nz

Article: 36379
Subject: Re: FPGA Wish list
From: "Rob Finch" <robfinch@sympatico.ca>
Date: Wed, 7 Nov 2001 23:15:48 -0500
Links: << >>  << T >>  << A >>
> Are there any fpga's containing high capacity dram's on chip ? There seem
to
> be quite a few people interfacing to external drams.
>
I've have thought it through more carefully and realized it just doesn't
make sense to provide on chip dram. Once again I have posted something and
regretted it. I've managed to prevent myself from posting most of my dumb
ideas, but this one escaped me. Sorry.

>




Article: 36380
Subject: Question about pipelining a design
From: mohaase@nilenet.com (Marty)
Date: Wed, 07 Nov 2001 22:18:33 -0600
Links: << >>  << T >>  << A >>
I am working on a waveform generator that gets data from a dual-port RAM,
and outputs it. It also has timing and jump instructions in the RAM data.
The goal is to run at 50 MHz.  The RAM, is 64K deep, and 15 nS access time.

I can get the machine to simulate at 33 MHz, but not at 50 MHz.  I think the
way to solve this is to redesign the machine in a pipelined form.
I have fit the non pipelined design into an Altera 7512AE.
Some of the problems are getting the machine to do relative jumps - absolute 
jumps work.

Does anyone know of any tools to help visualize or design a project like this?

Marty

Article: 36381
Subject: "Illegal assignment" message, NEED HELP, PLEASE!!!
From: jaime.aranguren@ieee.org (Jaime Andres Aranguren Cardona)
Date: 7 Nov 2001 21:50:24 -0800
Links: << >>  << T >>  << A >>
With Xilinx tools, with the following part of code I get this message:

Error   L315/C0 : #0 Error: Illegal assignment to 'clk_rb_inter'.  It
depends on a non-edge    in routine CtrlUnit_A line 315 in file '' 
(HDL-110)

How can I solve it?

PS/ we_inter, re_inter and clk_rb_inter are std_logic signals.


   -- Register bank clock processes
   rb_clock1 : process (we_inter)
   --------------------------------------
   begin
   	if (we_inter'event and we_inter = '1') then
   		clk_rb_inter <= '1';
   	else
   		clk_rb_inter <= '0';
   	end if;

   end process rb_clock1;
   
   rb_clock2 : process (re_inter)
   --------------------------------------
   begin
   	if (re_inter'event and re_inter = '1') then
   		clk_rb_inter <= '1';
   	else
   		clk_rb_inter <= '0';
   	end if;   	
   end process rb_clock2;
   
   final_process: process (clk_rb_inter, we_inter, re_inter)
   ---------------------------------------------------------
   begin
   	clk_rb <= clk_rb_inter;
   	we <= we_inter;
   	re <= re_inter;
   end process final_process;

Article: 36382
Subject: Re: Synplicity, Xilinx, & unwanted BUFGs
From: assaf_sarfati@yahoo.com (Assaf Sarfati)
Date: 7 Nov 2001 21:58:26 -0800
Links: << >>  << T >>  << A >>
hamish@cloud.net.au wrote in message news:<3be93443$0$385$afc38c87@news.optusnet.com.au>...
> Assaf Sarfati <assaf_sarfati@yahoo.com> wrote:
> > As far as I could see, Synplicity simply ignored syn_noclockbuf in the
> > HDL code, since it know better than me what was and what wasn't a clock...
> 
> It does work, but you usually have to put it inside your entity section;
> inside the architecture doesn't work.
> 
> Hamish

How can I put the attribute in the entity? after all, it is an internal 
signal within the architecture...

Article: 36383
Subject: Re: Virtex2 gate-level simulation: SDF and timing errors
From: assaf_sarfati@yahoo.com (Assaf Sarfati)
Date: 7 Nov 2001 22:06:31 -0800
Links: << >>  << T >>  << A >>
allan_herriman.hates.spam@agilent.com (Allan Herriman) wrote in message news:<3be88ba4.6211972@netnews.agilent.com>...
> On 6 Nov 2001 06:42:09 -0800, assaf_sarfati@yahoo.com (Assaf Sarfati)
> wrote:
> 
> >Hi everyone,
> >
> >I am trying to simulate the gate-level VHDL file generated by Xilinx
> >P&R tools. My test design is a bunch of counters connected to an 
> >inferred distributed-RAM. The target device is a Virtex-2 chip.
> >
> >When I simulate the gate-level VHDL by itself, I get timing violation 
> >warnings (sometimes) when writing to the distributed-RAM; watching the
> >simulator waveforms, it appears that the clock to the RAM has a 100-pS
> >phase difference to the counters' clock (the clock is routed as a 
> >global clock net).
> >
> >When I add the gate-level SDF file to the simulation, all the timing
> >violation warnings disappear (for all cases: min, max and typ).
> >
> >Trying to trace the generated VHDL code, I see that signals are routed
> >through buffer entities, with built-in delays; apparently the VHDL
> >design itself contains all required delays.
> >
> >Why would adding the SDF to the simulation make errors _disappear_? 
> >it should be a more thorogh timing-check and find _more_ timing
> >errors.
> >
> >Can anyone explain?
> 
> There are clock delays built in to the simprim (& unisim) components
> that are present regardless of whether you use the SDF.  These delays
> can cause hold time problems, and using the SDF will delay the data
> signals sufficiently to avoid the hold time issues.
> 
> You can disable these delays in your simulator.  (If using Modelsim,
> try vsim +notimingchecks)
> 
> Regards,
> Allan.

Aren't there also delays built-in for the data signals in the
time_sim.vhd file? (BTW, I use Active-HDL; I haven't tried to find
how to disable timing checks - I've seen that I can modify a constant
in the Virtex library source to disable these checks, if they become
too nagging).
     Assaf

Article: 36384
Subject: QuickLogic Programmer (s) for Sale
From: jesse@jumboprawn.net (jesse)
Date: 7 Nov 2001 22:11:04 -0800
Links: << >>  << T >>  << A >>
We're selling some QuickLogic programmer components:

the QA-PF100144 head for flat-pack 100 & 144 pin parts
the Desk Fab programming base

Please visit:
http://www.jumboprawn.net/for_sale/ql_100144.html
http://www.jumboprawn.net/for_sale/ql_base.html

Article: 36385
Subject: Re: Xilinx machine readable package info
From: "Leon Heller" <leon_heller@hotmail.com>
Date: Thu, 8 Nov 2001 06:11:48 -0000
Links: << >>  << T >>  << A >>


"Petter Gustad" <newsmailcomp1@gustad.com> wrote in message
news:87zo5yp87r.fsf@filestore.home.gustad.com...
>
> I'm working on a program to aid me in the tedious allocation of pins
> for a Virtex-II device. But I need to obtain package information,
> presumably in machine readable form. I can use partgen to generate a
> plain ASCII file, but this does not contain any information regarding
> the bank number for each pin. Is there an ASCII (or documented binary
> file) file where I can find this information?
>

I found pinouts for the Spartan-II chips in the form of an Excel spreadsheet
somewhere on the Xilinx web site. It should be available for the Virtex
chips as well.


Leon
--
Leon Heller, G1HSM leon_heller@hotmail.con
http://www.geocities.com/leon_heller
Low-cost Altera Flex design kit: http://www.leonheller.com




Article: 36386
Subject: Re: Xilinx machine readable package info
From: "Leon Heller" <leon_heller@hotmail.com>
Date: Thu, 8 Nov 2001 06:34:03 -0000
Links: << >>  << T >>  << A >>

"Petter Gustad" <newsmailcomp1@gustad.com> wrote in message
news:87zo5yp87r.fsf@filestore.home.gustad.com...
>
> I'm working on a program to aid me in the tedious allocation of pins
> for a Virtex-II device. But I need to obtain package information,
> presumably in machine readable form. I can use partgen to generate a
> plain ASCII file, but this does not contain any information regarding
> the bank number for each pin. Is there an ASCII (or documented binary
> file) file where I can find this information?

http://www.xilinx.com/products/virtex/vpackages.htm

--
Leon Heller, G1HSM leon_heller@hotmail.con
http://www.geocities.com/leon_heller
Low-cost Altera Flex design kit: http://www.leonheller.com





Article: 36387
(removed)


Article: 36388
(removed)


Article: 36389
Subject: How can I implement such a counter in Verilog?
From: "duola" <deerlux@hotmail.com>
Date: Wed, 7 Nov 2001 22:45:06 -0800
Links: << >>  << T >>  << A >>
I want implement such a counter in verilog.
input clk,en;
output [4:0]out;
"en" is low enable and the negative edge of "clk" is used.When the negative
edge of "en" arrive,"out" must be reset to 0.When the negative edge of "clk"
arrived,the counter begin counting.When "en" is high level, "clk" is high
level too.There is not any high frequency clock to use.How should I do?
Thank you!



Article: 36390
Subject: Re: count and divide Idea needed
From: cappellainfuocata@yahoo.it (Banana)
Date: 7 Nov 2001 23:07:34 -0800
Links: << >>  << T >>  << A >>
I implement your code in this way :


library	ieee;
use ieee.std_logic_1164.all;

entity raycounter3 is
	port(clk	     	:	in std_logic   ;  
		 clk33			:	out std_logic  ;
		 count_output	:	out std_logic_vector(1 downto 0)
		 );
end raycounter3;

architecture raycounter3_arch of raycounter3 is
begin
	signal cnt 		: 	std_logic_vector(1 downto 0);
	signal cnt0_fe	:	std_logic;
	begin
		process(clk)
		begin
    		if clk'event and clk='1' then
        		cnt<= cnt(0) & not(cnt(0) or cnt(1));
    		end if;
		end process;

		process(clk)
		begin
    		if clk'event and clk='0' then
        		cnt0_fe<=cnt(0);
    		end if;
		end process;

		count_output<=cnt;
		clk33<=cnt(0) or cnt0_fe;
	end;
end raycounter3_arch ;



but seems there's an error in the first instruction
	signal cnt 		: 	std_logic_vector(1 downto 0);

what you think about ??

Article: 36391
Subject: Implementation of filter with three set of coeffs
From: cappellainfuocata@yahoo.it (Banana)
Date: 7 Nov 2001 23:09:16 -0800
Links: << >>  << T >>  << A >>
I have a filter and want to use it with three different set of
coefficients, I'm not sure
about the vhdl implementation of this, I arrange the following :

1) I define a package SRRC_coeffs where I define the coeff type and
the coeffs type, here it is :

library	ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;

package SRRC_coeffs is
	subtype coeff is std_logic_vector(11 downto 0);
	type coeffs is array(1 to 42) of coeff;
end SRRC_coeffs ;	


2) I define an entity named coeffs_selector in this way :

library	ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
use work.SRRC_coeffs.all;

entity coeffs_selector is
		port( coeffs_sel	:	in  std_logic_vector( 1 downto 0);
	 	  	  coeffs_SRRC	:	out coeffs
		 );
end coeffs_selector;


architecture coeffs_selector_arch of coeffs_selector is

	Constant coeffs_SRRCx3 : coeffs := coeffs'(
						coeff'("111111100010") , --  1
						coeff'("111111111100") , --  2
						coeff'("000001000001") , --  3
						-- .....................
						coeff'("000000000000")); -- 42
	

	Constant coeffs_SRRCx4 : coeffs := coeffs'(
						coeff'("111111100110") , --  1						
						coeff'("111111110001") , --  2
						coeff'("000000011010") , --  3
						-- .....................
						coeff'("000000000000")); -- 42
	
						

	Constant coeffs_SRRCx6 : coeffs := coeffs'(
						coeff'("000000000110") , --  1
						coeff'("111111110011") , --  2
						coeff'("111111100010") , --  3
						-- .....................
						coeff'("000000000110")); -- 42	
						
begin				  
	
	with coeffs_sel select			   
		coeffs_SRRC <=	coeffs_SRRCx3 when "00",	
	  			coeffs_SRRCx4 when "01",	
				coeffs_SRRCx6 when others ; 
end coeffs_selector_arch;





3) On the filter where arrive the coefficient bus I've something like
this :

library IEEE;
use IEEE.std_logic_1164.all;
use work.SRRC_coeffs.all;

entity SRRC_x_N is
  port(
       SRRCxN_coeffs : in coeffs;
       clk_div_n : in STD_LOGIC;
       in_fir_MSB : in STD_LOGIC;
       reset : in STD_LOGIC;
       count_n : in STD_LOGIC_VECTOR (2 downto 0);
       polyphase_out : out STD_LOGIC_VECTOR (11 downto 0)
  );
end SRRC_x_N;

architecture SRRC_X_N of SRRC_x_N is

signal COEFF_1 : coeff ;
signal COEFF_2 : coeff ;
signal COEFF_3 : coeff ;
-- ...............
signal COEFF_42 : coeff ;





component FIR_1
  port (
       clk_div_n : in STD_LOGIC;
       coeff_a : in coeff;
       coeff_b : in coeff;
       coeff_c : in coeff;
       coeff_d : in coeff;
       coeff_e : in coeff;
       coeff_f : in coeff;
       coeff_g : in coeff;
       in_fir_MSB : in STD_LOGIC;
       reset : in STD_LOGIC;
       out_fir : out STD_LOGIC_VECTOR (11 downto 0)
  );
end component ;





begin
	coeff_1   <= SRRCxN_coeffs(1);
	coeff_2   <= SRRCxN_coeffs(2);
	coeff_3   <= SRRCxN_coeffs(3);
	-- ...............
	coeff_42  <= SRRCxN_coeffs(42);




U1 : FIR_1
  port map(
       clk_div_n => clk_div_n,
       coeff_a => coeff_1,
       coeff_b => coeff_2,
       coeff_c => coeff_3,
       coeff_d => coeff_4,
       coeff_e => coeff_5,
       coeff_f => coeff_6,
       coeff_g => coeff_7,
       in_fir_MSB => in_fir_MSB,
       out_fir => to_in_0,
       reset => reset
  );



-- ...............


end SRRC_X_N;




AND FINALLY HERE ARE MY QUESTION :
A) Aldec don't permit me to do directly the assignment
	U1 : FIR_1
		port map(
		       coeff_a => SRRCxN_coeffs(1);
			.......
			);

    I can't understand why and if there is another solution to avoid
this double assignment

B) there's a clever way to do this assignment of three different set
of coefficients to the filter ??



Thanks for your help

Article: 36392
Subject: Can I enhance this Counter 4 and Counter 6 ???
From: cappellainfuocata@yahoo.it (Banana)
Date: 7 Nov 2001 23:10:58 -0800
Links: << >>  << T >>  << A >>
I need a counter that counts 0 , 1 , 2 , 3 and also divide the
incoming clock by four,
for this I use the following code , my question is that there is a
more simple way to do the
same, in any case something that give it more speed and less area. I
don't want to use DLL.
Thanks for your help.

library IEEE;
use IEEE.std_logic_1164.all;	  
use IEEE.std_logic_unsigned.all;

entity counter_divider_4 is
	port (
		clk		: in  STD_LOGIC;
		reset		: in  STD_LOGIC;
		count_4		: out STD_LOGIC_VECTOR (2 downto 0);
		clk_div_4 	: out STD_LOGIC 
		);
end counter_divider_4;

architecture counter_divider_4_arch of counter_divider_4 is
begin
	process (clk, reset)
		variable count_4_internal : STD_LOGIC_VECTOR (2 downto 0);
	begin
		if reset='1' then  
			count_4_internal := "000"; 
		else
			if falling_edge(clk) then
				if count_4_internal < 3 then
					count_4_internal := count_4_internal + 1;
					if count_4_internal = 2 then
						clk_div_4 <= '1' ;
					else null;
					end if ;
				else
					count_4_internal := "000";
					clk_div_4	<= '0' ;
				end if;
			end if;
		end if;
		count_4 <= count_4_internal;
	end process;
end counter_divider_4_arch;



By the way I use a really similar code to obtain the same with a
counter modulo 6
In that case this is the code , the question is the same, what about
the answer ??





library IEEE;
use IEEE.std_logic_1164.all;	  
use IEEE.std_logic_unsigned.all;

entity counter_divider_6 is
	port (
		clk		: in  STD_LOGIC;
		reset		: in  STD_LOGIC;
		count_6		: out STD_LOGIC_VECTOR (2 downto 0);
		clk_div_6 	: out STD_LOGIC 
		);
end counter_divider_6;



architecture counter_divider_6_arch of counter_divider_6 is
begin
	process (clk, reset)
		variable count_6_internal : STD_LOGIC_VECTOR (2 downto 0);
	begin
		if reset='1' then  
			count_6_internal := "000"; 
		else
			if falling_edge(clk) then
				if count_6_internal < 5 then
					count_6_internal := count_6_internal + 1;
					if count_6_internal = 3 then
						clk_div_6 <= '1' ;
					else null;
					end if ;
				else
					count_6_internal := "000";
					clk_div_6	<= '0' ;
				end if;
			end if;
		end if;
		count_6 <= count_6_internal;
	end process;
	
end counter_divider_6_arch;

Article: 36393
Subject: Can Xilinx recognize the critical path in the design
From: Kuan Zhou <zhouk@rpi.edu>
Date: Thu, 8 Nov 2001 02:18:26 -0500
Links: << >>  << T >>  << A >>
Hi,
   I did a fir design but don't know what's the critical 
path in my design.Can Xilinx tool has someway to mesure and
recognize it?

sincerely
-------------
Kuan Zhou
ECSE department



Article: 36394
Subject: Bit scaling
From: "Noddy" <g9731642@campus.ru.ac.za>
Date: Thu, 8 Nov 2001 09:19:04 +0200
Links: << >>  << T >>  << A >>
I was wondering if anyone could point me to a reference/newsgroup/answer for
the following question.

I have in my FPGA a 6 Bit white noise signal going into a squarer
(implemented by LUT), with a 6 bit output (MSBs). I have designed graphs to
show the power of the signal (vs. sigma) after it has been squared (by taken
the signal, normalised to sigma, and multiplying by a transformed normal
distribution). My question is, the squarer seems to be losing some of the
power (its lossy), and so I want to be able to design the same graphs, but
this time vs. the bits I take.

Anyone have ANY clue as to how I can do this?

Thanks

adrian



Article: 36395
Subject: about ise4.1 solaris install
From: wrth <etu@weg.ejy>
Date: Thu, 8 Nov 2001 00:25:38 -0700
Links: << >>  << T >>  << A >>
when i install ISE4.1 for Solaris7,it says:
Exception occurred during event dispatching:
java.util.MissingResourceException: can't find resource for ResourceBundle_zh_CN
        at java.lang.Throwable.<init>(Compiled Code)
        at java.lang.Exception.<init>(Compiled Code)
        at java.lang.RuntimeException.<init>(Compiled Code)
        at java.util.MissingResourceException.<init>(Compiled Code)
        at java.util.ResourceBundle.getBundle(Compiled Code)
        at java.util.ResourceBundle.getBundle(Compiled Code)
        at com.xilinx.install.QuestionDialog.getString(Compiled Code)
        at com.xilinx.install.QuestionDialog.<init>(Compiled Code)
        at com.xilinx.install.QuestionDialog.<init>(Compiled Code)
        at com.xilinx.install.setup.storeDD(Compiled Code)
        at com.xilinx.install.setup.panel5Nextbutton_MouseClicked(Compiled Code)
        at com.xilinx.install.setup$SymMouse.mouseClicked(Compiled Code)
        at java.awt.Component.processMouseEvent(Compiled Code)
        at java.awt.Component.processEvent(Compiled Code)
        at java.awt.Button.processEvent(Compiled Code)
        at java.awt.Component.dispatchEventImpl(Compiled Code)
        at java.awt.Component.dispatchEvent(Compiled Code)
        at java.awt.EventDispatchThread.run(Compiled Code)

Article: 36396
Subject: Re: "Illegal assignment" message, NEED HELP, PLEASE!!!
From: Tim Hubberstey <sendme@no.spam>
Date: Thu, 08 Nov 2001 07:52:29 GMT
Links: << >>  << T >>  << A >>
Jaime Andres Aranguren Cardona wrote:
> 
> With Xilinx tools, with the following part of code I get this message:
> 
> Error   L315/C0 : #0 Error: Illegal assignment to 'clk_rb_inter'.  It
> depends on a non-edge    in routine CtrlUnit_A line 315 in file ''
> (HDL-110)
> 
> How can I solve it?
> 
> PS/ we_inter, re_inter and clk_rb_inter are std_logic signals.
> 
>    -- Register bank clock processes
>    rb_clock1 : process (we_inter)
>    --------------------------------------
>    begin
>         if (we_inter'event and we_inter = '1') then
>                 clk_rb_inter <= '1';
>         else
>                 clk_rb_inter <= '0';
>         end if;
> 
>    end process rb_clock1;
> 
>    rb_clock2 : process (re_inter)
>    --------------------------------------
>    begin
>         if (re_inter'event and re_inter = '1') then
>                 clk_rb_inter <= '1';
>         else
>                 clk_rb_inter <= '0';
>         end if;
>    end process rb_clock2;
> 
>    final_process: process (clk_rb_inter, we_inter, re_inter)
>    ---------------------------------------------------------
>    begin
>         clk_rb <= clk_rb_inter;
>         we <= we_inter;
>         re <= re_inter;
>    end process final_process;

What it's complaining about in this rather confusing error message is
that you have two different processes assigning to the same signal,
clk_rb_inter. While this appears to be legal VHDL (assuming clk_rb_inter
is of type std_logic) it is not synthesizable. You need to rewrite your
code to combine the two rb_clock processes into one process. 

Further, you need to think about whether you really want to generate a
clock using combinational processes like this.
-- 
Tim Hubberstey, P.Eng. . . . . . . . . . . . . . .  Marmot Engineering
Vancouver, BC, Canada  . . . . . Hardware/Software Consulting Engineer

Article: 36397
Subject: Re: Fifo books
From: Russell Shaw <rjshaw@iprimus.com.au>
Date: Thu, 08 Nov 2001 19:58:51 +1100
Links: << >>  << T >>  << A >>


Edwin Naroska wrote:
> 
> Hi,
> 
> Russell Shaw wrote:
> 
> > Hi all,
> >
> > Are there any good books that have (vhdl) fifo designs and
> > discussion on asynchronous clock domains etc?
> >
> this is not a book but might help as well:
> 
>         http://img.cmpnet.com/deepchip/downloads/cliffsnug01.pdf

That's quite good. I found some other interesting things too:

http://www.geocities.com/deepakgeorge2000/vlsi_book/Asynch1.pdf
http://www.geocities.com/deepakgeorge2000/vlsi_book/async_fifo2.pdf

Article: 36398
Subject: Re: "Illegal assignment" message, NEED HELP, PLEASE!!!
From: Nicolas Matringe <nicolas.matringe@ipricot.com>
Date: Thu, 08 Nov 2001 10:34:26 +0100
Links: << >>  << T >>  << A >>
Tim Hubberstey a écrit :
> 
> What it's complaining about in this rather confusing error
> message is that you have two different processes assigning to
> the same signal, clk_rb_inter. While this appears to be legal
> VHDL (assuming clk_rb_inter is of type std_logic) it is not
> synthesizable. You need to rewrite your code to combine the two
> rb_clock processes into one process.
> 
> Further, you need to think about whether you really want to
> generate a clock using combinational processes like this.

What puzzles me is the purpose of this description. clk_rb_inter should go high
only when there is an event on we_inter or re_inter and go low when nothing
happens? I can't find any sense in that, this would mean that it's high during
the event (which, ideally, takes no time).

-- 
Nicolas MATRINGE           IPricot European Headquarters
Conception electronique    10-12 Avenue de Verdun
Tel +33 1 46 52 53 11      F-92250 LA GARENNE-COLOMBES - FRANCE
Fax +33 1 46 52 53 01      http://www.IPricot.com/

Article: 36399
Subject: Re: How dense are FPGA/CPLD's
From: Russell Shaw <rjshaw@iprimus.com.au>
Date: Thu, 08 Nov 2001 21:27:07 +1100
Links: << >>  << T >>  << A >>


Kevin Brace wrote:
> 
> Rene Tschaggelar <tschaggelar@dplanet.ch> wrote in message news:<3BE993A3.F854175D@dplanet.ch>...
> > A few corrections :
> >
> > Altera FPGA's can be EEPROM or SRAM based depending on the density.
> >
> 
>         As far as I know, all FPGA devices from Altera are SRAM-based.
> Perhaps you are talking about MAX series which is EEPROM-based, but I
> will call MAX a CPLD because they are product term based devices.
> Although it is not always correct, I still think it is a fairly
> accurate way to categorize programmable devices that most CPLDs are
> based on EEPROM and most FPGAs are based on SRAM or antifuse.
> Occasionally there is an exception like Actel/GateField's EEPROM-based
> FPGA called ProASIC.

There's a .pdf on the altera site that categorizes FPGAs as things
with segmented interconnects, whereas CPLDs don't have segments,
making routing easier.


> It looks like an interesting device, but I don't hear or see it that
> often.
> 
> > I wouldn't learn Verilog nor VHDL to start with but use the graphic
> > editors provided. They allow rather complex stuff and are
> > self-documenting.
> >
> >
> > Rene
> >
> >
> >
> 
>         I think that depends on the person.
> I find HDL easier to work than with schematic entry.
> I don't have any good memories of working with schematic entry.
> Especially, if you have to design a state machine.
> 
> Regards,
> 
> Kevin Brace (don't respond to me directly, respond within the
> newsgroup)



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