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Messages from 34025

Article: 34025
Subject: Re: how to acheive high frquency in Xinlinx Virtex E
From: "Kevin Neilson" <kevin_neilson@removethis-yahoo.com>
Date: Sat, 11 Aug 2001 20:50:25 GMT
Links: << >>  << T >>  << A >>
Feedback for Xilinx for Virtex-III:  the BRAMS need to have optional output
data registers built into the BRAM units.

Manjunath, you have discovered the biggest problem with the block RAMs in a
Xilinx.  The Tbcko (clk->out) is only about 3ns, but to use the BRAMs at
speeds near 200MHz (5ns period) is almost impossible because even if you
immdediately register the BRAM outputs, it can take up to 3ns for the data
to reach the registers if the automatic placer is used.  Even careful hand
placement can result in routes that meander through numerous switchboxes for
>2ns delays.

Through much trial and error, my colleague discovered the optimal placement
for up to 36 registers on the outputs of a Virtex-II BRAM.  This placement,
in a -4, yields net delays of less than 1.15ns for a speed of over 200MHz.
I wrote a Perl script that creates a constraint file to optimally place
these registers for a given BRAM location.  (The script is, I am guessing,
proprietary.)  It would help somewhat if Xilinx would allow one to create a
blockRAM CoreGen with optimally placed output registers.  Perhaps this is
true of the latest CoreGen; bandwidth precludes me from downloading the most
recent version.  However, I don't think RPMs can be created that contain
both BRAM and flops.  Does anyone know the answer to that?

The best solution, (too late now for Virtex-II), would be to place a set of
optional output registers on the die next to the  BRAM data outputs.  The
period could be as low as Tbcko + flop setup, or under 4ns.  Then the output
data would have a full period to get to anywhere else on the chip.

If you experiment with hand-placement, noting carefully in the FPGA editor
the alignment of the data outputs on the BRAM, it is possible find a
placement for every output register which will result in only two switchbox
connections and net delays less than 1.5ns.

-Kevin

"Manjunathan" <manjunathan_s1@yahoomail.com> wrote in message
news:ee71e8b.-1@WebX.sUN8CHnE...
> Hello everyone,
>
>   iam using virtex E device for my Design, my design has block memories
its outputs are registered.
>
>    even if i place the register near to the block memory, the net delay
from the block memory output to the register input is 3.ns
>   how can we redude the net delay ?
>
> Thanks in Advance,
>
> Regards,
>
> Manjunath
>



Article: 34026
Subject: Re: Reconfigurable Computational Accelerator
From: "Dave Feustel" <dfeustel1@home.com>
Date: Sat, 11 Aug 2001 21:30:25 GMT
Links: << >>  << T >>  << A >>
My interest in FPGAs is currently mainly in implementing cpus to directly execute the
virtual instruction sets used by Snobol and Icon/Unicon language interpreters.
I also have some interest in cpus with complex arithmetic operations supported in
hardware.

"Mike Butts" <mbutts@realizer.com> wrote in message news:3B758FB0.B98CA76A@realizer.com...
> Dave Feustel wrote:
> > The real short version is
> > that the PCI bus interface is so slow relative to the
> > speeds of the cpu and accelerator that it usually
> > isn't worth adding an accelerator if the interface
> > is via the PCI bus.
>
> This is often, but not necessarily true.  Accelerator architecture
> totally depends on your application.  This is exactly what Philip
> meant by "how long should a piece of string be".  Not ridicule,
> just maybe a little drier wit than we're used to...
>
> If your application depends on lots of back-and-forth
> between the host and the card in its core kernel, PCI is usually
> a barrier.  Many early research projects in this field found this
> out the hard way.  It's not the bandwidth that matters in such
> cases, it's the latency, the round-trip time for a single operation.
>
> PCI, especially as implemented in modern PCs and workstations,
> can be very bad at that.  Mark Shand gave an excellent and
> most useful paper about this at FCCM '97, that anyone using PCI
> must study:
> Laurent Moll and Mark Shand. Systems performance measurement on
> PCI Pamette. In FPGAs for Custom Computing Machines
>      (FCCM'97). IEEE, April 1997.
> http://www.research.compaq.com/SRC/staff/shand/bib.html
>
> If, on the other hand, your app is a self-contained kernel that
> grinds away mostly on its own, PCI can be fine.  Often signal
> processing apps are like this, with the signal I/O direct to
> the card.
>
> I believe a very big win for reconfigurable computing is for
> apps that demand lots of parallel memory bandwidth, since the
> processor-memory bottleneck is so fundamental to conventional
> computing.  I'm working with a project at Oregon Graduate Institute
> lately to develop a neural network accelerator.  In our case, it's all
> about memory bandwidth.  I/O to/from the host is orders of
> magnitude less.  We're planning a PCI card with as many SDRAM DIMMs
> as we can hook up to some FPGAs for them to grind away on matrix-
> vector multiplies in parallel at 100 MHz.  PCI will just control
> and program the card, and feed inputs and collect results at a
> lazy and latency-insensitive pace.
>
> So tell us more about your application, and maybe we can give you
> better advice.
>
>    --Mike



Article: 34027
(removed)


Article: 34028
Subject: Re: prospects for tiny FPGA supercomputer?
From: Jason Stratos Papadopoulos <jasonp@y.glue.umd.edu>
Date: 12 Aug 2001 00:02:29 GMT
Links: << >>  << T >>  << A >>
rodger <rodger@bit.bucket> wrote:
: Have you taken a look at Xilinx' new MicroBlaze processor?

: http://www.xilinx.com/ipcenter/processor_central/microblaze.htm

: The other possibilities are the diffused processors such as
: the PowerPC in Xilinx and ARM9 in Altera.

: http://www.xilinx.com/xlnx/xil_prodcat_landingpage.jsp?title=Processor+Centr
: al

Altera's Excalibur series is very interesting; I'll have to look at the
Xilinx offering soon.

Based on a bunch of papers and PhD dissertations I've read on the subject,
it looks like the main difficulty would involve building one (or more) 
pipelined 64-bit integer multipliers into an FPGA. Having an embedded
processor isn't strictly necessary; I've looked at the docs on several FFT
chips which manage incredible performance with no programmability at all
(albeit for smaller size data). Alternately, a system could look like


           SRAM

            |

SRAM  <->  FPGA  <->  SRAM

            |

       PCI controller

where the top SRAM contains constants for an integer FFT, and the
programmable logic performs an integer FFT (on 64-bit two's-complement
integer data), with vectorized FFT butterflies ping-ponging back and 
forth between the left-hand and right-hand SRAM arrays. This FFT isn't a
conventional one; it doesn't use complex data and doesn't emulate floating
point arithmetic. The structure is the same, though.

In order to be competitive with a general purpose computer, the design
needs a massive amount of IO, although it would help to have a local
memory in the FPGA (if there's any room left over after packing several
64-bit FFT butterfly engines, which I doubt).

doublebw.com has an FFT chip that can do a 1024-pt FFT of complex 32-bit
data in something like 10us at 100MHz, and that's 5x-10x faster than
anything you can put on your desk. I'm just hoping that with more MHz and
a simpler problem to solve I can do similar performance but in
programmable logic.

Thanks for the help,
jasonp

Article: 34029
Subject: Xilinx WebPack .UCF file
From: Mark Borgerson <mark@oes.to>
Date: Sun, 12 Aug 2001 00:29:39 GMT
Links: << >>  << T >>  << A >>
I've put together my first design targeting a Coolrunner CPLD and
gotten it to compile and generate the output files.  I would
now like to edit the .ucf file so that I can arrange pins
to simplify layout on my PCB.  Apparently, there are two
options:

1. Generate the default .ucf file  with the 'lock pins' process, then
edit the .ucf file as text with notepad.  The problem I'm having
is that if I go back and click on Edit UCF file under User
Constraints,  Notepad opens with a blank file in the My Documents
directory.  There is also a XILPerl window showing a file not 
found error.  Have I missed the setup of a Path variable or 
something of this sort??

2.  If I manually open the Constraints Editor and try to open
the default UCF file I generated, I also need to provide the
name of a .NGD file.  But my design process so far has not
produced a .NGD file!  Have I missed a step somewhere??

Any help or hints would be greatly appreciated.  The web pack tools
seem to be great stuff for free tools,  but it seems that there
is a definite learning curve!  

Mark Borgerson

Article: 34030
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Article: 34031
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Article: 34032
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Article: 34033
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Article: 34034
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Article: 34035
Subject: Use of lpm in Xilinx Foundation 2.1i
From: "Mark Walter" <maw@nospam.com>
Date: Sun, 12 Aug 2001 07:39:06 GMT
Links: << >>  << T >>  << A >>
Does anyone know how to get Xilinx Foundation 2.1i to use the lpm_ram_dq
package in the lpm library.  I tried some VHDL code from a book I got and it
wanted to use this for a ram component.  It fails when I compile on the
"library lpm;" line saying it can't find the lpm library..

Thanks,
Mark



Article: 34036
(removed)


Article: 34037
Subject: Re: Q: Revision and Database Control for FPGA Designs
From: allan_herriman.hates.spam@agilent.com (Allan Herriman)
Date: Sun, 12 Aug 2001 11:50:40 GMT
Links: << >>  << T >>  << A >>
On Sat, 11 Aug 2001 11:41:51 -0400, Rick Collins
<spamgoeshere4@yahoo.com> wrote:

>Allan Herriman wrote:
>> 
>> On Wed, 08 Aug 2001 13:22:48 +0100, Gary Cook <gc@sonyoxford.co.uk>
>> wrote:
>> 
>> >I've read the previous threads relating to source control for
>> >FPGA designs (RCS,CVS,CC etc. etc..) but would like
>> >to discuss more of a general topic around this....
>> 
>> [snip description of the sort of thing I do in Clearcase at least a
>> few times each week.]
>> 
>> You set up a "view" which contains the appropriate versions of each
>> element.  When you are happy with your design, you can label all the
>> elements (after you've checked them in, of course), and then you can
>> always get that exact set of elements back by refering to them by that
>> label.
>> 
>> With Clearcase under NT, you can map a view to a drive letter.  For
>> example, on my laptop, I have my Z: drive looking at the latest
>> version of everything.  My Y: drive looks at my development branch for
>> the particular set of files I'm working on at the moment.  When I'm
>> finished, I'll merge them to the main branch and label the lot.  Oh,
>> these particular files are shared by an international development
>> team, and Clearcase synchronises everyones views correctly.  Well,
>> most of the time, anyway.
>> 
>> It's expensive, but if you want to play with the big boys...
>> 
>> Regards,
>> Allan.
>
>Allan,
>
>I would not recommend Clearcase to anyone working on FPGAs. Clearcase
>has a lot of capabilities (and added complexities) that are just not
>needed by someone doing FPGA work. To be honest, I am not sure it is
>needed by anyone doing software work. But if you are a carpenter, you
>use a lot of fancy wood in your tools. If you are a machinist, you use a
>lot of fancy metal tools in your work. Software people tend to use a lot
>of fancy software tools in their work that are often a matter of
>guilding the lily. 
>
>I have used PVCS in the past and it worked very well for both software
>and hardware. I expect that a new user would find this much easier to
>use than an overly complex tool like Clearcase. 
>
>The way we worked in PVCS was to add labels to mark the exact version of
>every file used in a make. Then to repeat the make, the label was used
>as a reference. This tool was quite powerful enough for all of our needs
>and still was relatively easy to use. 

Hi Rick,

I agree with you about clearcase - it's definitely overkill for most
FPGA designers.  But I would hesitate to say that it's overkill for
all FPGA designers.

I find it a comfortable fit for the work I'm doing (multiple
developers at multiple sites, multiple products built from the same
code base, etc).  I guess this doesn't apply to most FPGA designers
though.

If I was working on a project with only say, 10 people at a single
site developing the code, then I'd probably find one of the simpler
tools to be the best one, and I would baulk at Clearcase's complexity
and cost.

Regards,
Allan.

Article: 34038
(removed)


Article: 34039
Subject: Keep Xilinx Webpack from removing unused NETs?
From: m.weymarn@iname.com (Martin v. Weymarn)
Date: 12 Aug 2001 08:37:17 -0700
Links: << >>  << T >>  << A >>
Hi,

I'm starting a new FPGA-design in VHDL using Xilinx Webpack. I defined
all the connections/LOCs to the device in the UCF file and added them
as ports in my top-level entity. However it seems that my input ports
get optimized away because ngdbuild complains that the NETs cannot be
found. Is there a way to keep the NETs although they are not used
(yet)? I already tried to set the keep attribute to "yes" but that
didn't help. Neither did unchecking the Map Option "Trim Unconnected
Signals"...

Thanks,
Martin.

Article: 34040
Subject: Xilinx webpack vs. Student edition software
From: "kryten_droid" <kryten_droid@ntlworld.com>
Date: Sun, 12 Aug 2001 17:15:47 +0100
Links: << >>  << T >>  << A >>
Hi all.

I recently downloaded the webpack software, with a view to installing it
after buying an introductory VHDL book.

I bought "introductory VHDL" by Sudhakar Yalamanchili.
Besides being fairly cheap (25 UKP), it came with a CD
of the Xilinx Foundation Series software, v2.1i.

Anyone have opinions as to which would be wiser to use,
and why?

Seems a bit odd that I have to register to use the VHDL/Verilog features of
the foundation software, while the webpack has no such restriction (AFAIK).


Also, does anyone know good sources of FPGA chips in the UK?

Farnell sell Atmel clones of the Xilinx 3000 series (up to XC3042) but not
the 4000 series or above.
Altera sell samples direct via their web site, but I think I will start off
with Xilinx parts and preferably those with JTAG.

TIA, Kryten.



Article: 34041
Subject: Re: PCI Postcode Display
From: czhou1949@home.com
Date: Sun, 12 Aug 2001 16:54:25 GMT
Links: << >>  << T >>  << A >>
Is it required to implement Configuration? I guess the only problem
without configurarion is that the system won't be able to tell if
there is a PCI device on the bus.

Now,I am converting a lagacy ISA I/O card to PCI card (no need for
plug-n-play). But It uses Interrupt. Do I have to implement
Configurarion and let the system to assign a ramdon interupt or I can
assign it myself? It would be great if I can fix #INTA to a specific
IRQ. Because I would like to keep the exsiting software driver
untouched and let it handle the interrupt. Is there a way of doing so.


>        Even though it might seem like implementing Configuration
>Cycle is not needed, it is a requirement according to the PCI standard
>to implement it.
>However, because it is a legacy device, you don't have to implement
>BAR (Base Address Register, Configuration Register 10H through 24H).
>Most Configuration Registers can be hardwired to zero (except some of
>them like Vendor ID, Device ID, Class Code, etc.).
>        Although all PCI devices are suppose to implement a parity
>checker, I don't think it is that important to implement it, so you
>can omit that, but you are still required to implement a parity
>generator for read cycle.
>
>
>
>
>Regards,
>
>
>
>Kevin Brace (don't respond to me directly, respond within the
>newsgroup)
>
>
>
>
>Entwicklung <entw@madex.com> wrote in message news:<3B711BD4.D0A8F7E3@madex.com>...
>> Hi All,
>> i'm looking for a Description how i can build a Display Card for showing
>> the Postcode from Bios on the PCI Bus.
>> The Card must look for an I/O Write Access on Adress 80H and then
>> display's the data on 2 7seg Display's as HEX.
>> Thank You for any Idea.


Article: 34042
Subject: Fast Mux and low power voltage reference
From: Kuan Zhou <zhouk@rpi.edu>
Date: Sun, 12 Aug 2001 12:58:56 -0400
Links: << >>  << T >>  << A >>
Hi,
   Does any one know how to design the fast multiplexer
and low power voltage reference?
   I used bipolar current mode logic trees for multiplexer.But
the power consumption is too high.
   Can anyone give me some suggestions?

sincerely
-------------
Kuan Zhou
ECSE department



Article: 34043
Subject: Re: Q: Revision and Database Control for FPGA Designs
From: Rick Collins <spamgoeshere4@yahoo.com>
Date: Sun, 12 Aug 2001 13:20:57 -0400
Links: << >>  << T >>  << A >>
Allan Herriman wrote:
> I agree with you about clearcase - it's definitely overkill for most
> FPGA designers.  But I would hesitate to say that it's overkill for
> all FPGA designers.
> 
> I find it a comfortable fit for the work I'm doing (multiple
> developers at multiple sites, multiple products built from the same
> code base, etc).  I guess this doesn't apply to most FPGA designers
> though.
> 
> If I was working on a project with only say, 10 people at a single
> site developing the code, then I'd probably find one of the simpler
> tools to be the best one, and I would baulk at Clearcase's complexity
> and cost.
> 
> Regards,
> Allan.

I am currenly working with Clearcase because it was mandated. We are
working onsite as well as remotely and I don't see where Clearcase has
any special advantages in this case. We log into our office LAN so that
it is the same as working in the office. In that scenario, we could use
any VCS that works over the LAN. 

Can you explain what you are doing that Clearcase provides special
features that facilitates your work? 


-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 34044
Subject: Re: Slightly off topic - PCs for running FPGA tools
From: Rick Collins <spamgoeshere4@yahoo.com>
Date: Sun, 12 Aug 2001 13:29:11 -0400
Links: << >>  << T >>  << A >>
"Keith R. Williams" wrote:
> I'm a well known AMD fan, but wouldn't give up the bells and whistles
> on this A21p for anything.  In particular, the 1600x1200 LCD display.
> I also have a graphics card in a docking station and run a secondary
> 20" display (combined 3200x1200 desktop).  I can keep all of the
> ModelSim windows, along with my synthesis tools/VHDL editor open on the
> LCD and move the ModelSim waveform window to fill the entire secondary
> display. Of course, I don't haul the secondary display around with me.
> ;-)
> 
> ----
>   Keith

Is this secondary display something that Windows supports natively? Or
does it require special drivers? This would be a BIG advantage of using
a secondary graphics card. I assume that I could do this in my desktop
as well, right? 

Just out of curiosity, when a dialog box pops up that is in the center
of the display, does it pop up to the center of the TWO screens, or the
center of the first screen? 

I am also surprised that a 1600, 15" display is readable. Aren't the
fonts and icons rather small on the laptop display? But then again, I am
getting my first pair of bifocals and have been hurting to read the
newspaper for the last 6 months or so. That may be skewing my perception
of what is readable... :)


-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 34045
Subject: Re: Slightly off topic - PCs for running FPGA tools
From: "Dave Feustel" <dfeustel1@home.com>
Date: Sun, 12 Aug 2001 18:02:01 GMT
Links: << >>  << T >>  << A >>

"Rick Collins" <spamgoeshere4@yahoo.com> wrote in message
news:3B76BCE7.8589021D@yahoo.com...
> "Keith R. Williams" wrote:
> > I'm a well known AMD fan, but wouldn't give up the bells and whistles
> > on this A21p for anything.  In particular, the 1600x1200 LCD display.
> > I also have a graphics card in a docking station and run a secondary
> > 20" display (combined 3200x1200 desktop).  I can keep all of the
> > ModelSim windows, along with my synthesis tools/VHDL editor open on the
> > LCD and move the ModelSim waveform window to fill the entire secondary
> > display. Of course, I don't haul the secondary display around with me.
> > ;-)
> >
> > ----
> >   Keith
>
> Is this secondary display something that Windows supports natively? Or
> does it require special drivers? This would be a BIG advantage of using
> a secondary graphics card. I assume that I could do this in my desktop
> as well, right?

Windows 2000 supports multiple display adaptors. Sevral companies make
PCI display adapters that support up to 25 displays attached to a single
computer.

> Arius - A Signal Processing Solutions Company
> Specializing in DSP and FPGA design      URL http://www.arius.com
> 4 King Ave                               301-682-7772 Voice
> Frederick, MD 21701-3110                 301-682-7666 FAX



Article: 34046
Subject: Re: Athlon 1.4 vs Pentium 4 1.7 for Foundation ISE/ModelSim?
From: Rick Collins <spamgoeshere4@yahoo.com>
Date: Sun, 12 Aug 2001 14:03:04 -0400
Links: << >>  << T >>  << A >>
Srinivasan Venkataramanan wrote:
> 
> Hi,
>   Very interesting facts, where do you normally find such benchmarks? I
> tried at AMD's site at
> http://www.amd.com/products/cpg/athlon/benchmarks/benchmarks.html but didn't
> find stuff that you have quoted like Linux compile, MPEG etc. Also what is
> "vectorizable code" - pardon me for this newbie question (perhaps a stupid
> one), but I am not a SW guy at all.
> 
> TIA for any pointers,
> Srini

I can't say anything about the benchmark data, but vectorizable code
means data is being processed in a set of equations that can be
performed on a "vector" of data such as an array. This means you can
have a tight loop with identical instructions and so fits into a
pipeline very well. Code with conditional branches (when taken) requires
you to flush out and restart the pipeline which greatly slows the
operation when the pipeline is long. 

Here is an example, if you are in a loop which tests data for the
minimum value and takes a branch each time a new minimum if found, it
can run at the full pipeline speed if the first (or last) item is the
only one requiring a branch. But if you get a case where the data is
sorted highest to lowest, the branch will be taken for each data item
and the pipeline will never help you run faster. You will get 100 MHz
performance from a 1 GHz CPU (or something like that). 

However, if you are performing a FIR filter which multiplies and adds
arrays of numbers, the code is run exactly the same each time. So you
get the full speed of the pipeline each time. This is considered
"vector" data. 


-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 34047
Subject: Re: Why did Zephram spool outside all the users? We can't post
From: Rick Collins <spamgoeshere4@yahoo.com>
Date: Sun, 12 Aug 2001 14:10:42 -0400
Links: << >>  << T >>  << A >>
Just a note to all the newbies and maybe a few of the more experienced
usenet posters. In general, when you see a post that seems to be out of
place or makes no sense, it is best to just ignore it. Unless you can
clearly see that the poster has made some mistake that he needs to be
told about, your reply will just add to the noise. 

This is true for all messages, not just the ones that are an attack of
some kind. 

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 34048
Subject: Digilab 10K10 resources / samples?
From: "Christopher J. Holland" <Personality_2@yahoo.com>
Date: Sun, 12 Aug 2001 21:46:01 GMT
Links: << >>  << T >>  << A >>
Hi,

I am a newbie.
I took a VHDL class (long time ago)
I have the Digilab 10K10 Prototyping board.
I have the Maxplus2 Compiler v9.21 w/key & license.
I am ready to go...

I was wondering if anybody else was working with the Digilab 10K10?

I would like to decode the keyboard input. Not sure how to do that yet.

Basically, I am looking for more samples, other than the "squash" program
that came with the board.

Regards,



Article: 34049
(removed)




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Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarApr2017

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

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