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Messages from 34050

Article: 34050
Subject: FPGA or CPLD data compression
From: "Hu Chen" <y917@hotmail.com>
Date: Sun, 12 Aug 2001 18:30:39 -0700
Links: << >>  << T >>  << A >>
I am interested in implementing a simple (or standard) data compression algorithm in an Xilinx FPGA or CPLD. I
would appreciate any information from people who have done work on this
topic or any pointers to literature or web sites.

Thanks a lot!

Article: 34051
Subject: Re: FPGA or CPLD data compression
From: Jim Granville <jim.granville@designtools.co.nz>
Date: Mon, 13 Aug 2001 15:07:01 +1200
Links: << >>  << T >>  << A >>
Hu Chen wrote:
> 
> I am interested in implementing a simple (or standard) data compression algorithm in an Xilinx FPGA or CPLD. I
> would appreciate any information from people who have done work on this
> topic or any pointers to literature or web sites.
> 
> Thanks a lot!

 You need to specify what data you wish to compress, and what resource
you are willing to
throw at the problem.

 We have experimented with Run Length compression in CPLD/SPLD, 
for both data and bandwidth domain limited designs.
 This uses minimal resource, and gives usefull compression on non random
data.

-jg

-- 
======= 80x51 Tools & PLD IP Specialists  =========
= http://www.DesignTools.co.nz

Article: 34052
Subject: Re: Digilab 10K10 resources / samples?
From: Russell Shaw <rjshaw@iprimus.com.au>
Date: Mon, 13 Aug 2001 13:21:27 +1000
Links: << >>  << T >>  << A >>
If you look in c:\max2work\vhdl, there's lots of examples. Also can
find lots of examples using google.


"Christopher J. Holland" wrote:
> 
> Hi,
> 
> I am a newbie.
> I took a VHDL class (long time ago)
> I have the Digilab 10K10 Prototyping board.
> I have the Maxplus2 Compiler v9.21 w/key & license.
> I am ready to go...
> 
> I was wondering if anybody else was working with the Digilab 10K10?
> 
> I would like to decode the keyboard input. Not sure how to do that yet.
> 
> Basically, I am looking for more samples, other than the "squash" program
> that came with the board.
> 
> Regards,

--
   ___                                           ___
  /  /\                                         /  /\
 /  /__\ Russell Shaw, B.Eng, M.Eng(Research)  /  /\/\
/__/   / Victoria, Australia, Down-Under      /__/\/\/
\  \  /  http://home.iprimus.com.au/rjshaw    \  \/\/
 \__\/                                         \__\/

Article: 34053
Subject: Re: Use of lpm in Xilinx Foundation 2.1i
From: Utku Ozcan <ozcan@netas.com.tr>
Date: Mon, 13 Aug 2001 09:08:48 +0300
Links: << >>  << T >>  << A >>
Mark Walter wrote:

> Does anyone know how to get Xilinx Foundation 2.1i to use the lpm_ram_dq
> package in the lpm library.  I tried some VHDL code from a book I got and it
> wanted to use this for a ram component.  It fails when I compile on the
> "library lpm;" line saying it can't find the lpm library..
>
> Thanks,
> Mark

"lpm" sounds like "altera" to me but you are using a xilinx tool.

utku



Article: 34054
Subject: Re: PCI Postcode Display
From: Klaus Falser <notvalid@notvalid.it>
Date: Mon, 13 Aug 2001 09:29:17 +0200
Links: << >>  << T >>  << A >>
In article <og6dntk8c4qkpjjmgpjaeb14dbdo4fpu7b@4ax.com>, 
czhou1949@home.com says...
> Is it required to implement Configuration? I guess the only problem
> without configurarion is that the system won't be able to tell if
> there is a PCI device on the bus.
> 
> Now,I am converting a lagacy ISA I/O card to PCI card (no need for
> plug-n-play). But It uses Interrupt. Do I have to implement
> Configurarion and let the system to assign a ramdon interupt or I can
> assign it myself? It would be great if I can fix #INTA to a specific
> IRQ. Because I would like to keep the exsiting software driver
> untouched and let it handle the interrupt. Is there a way of doing so.
> 
> 
You card must use #INTA, look at the PCI specs.
It is the responsability of the board maker and the BIOS to map this 
to a specific interrupt line of the interrupt controller.

[...]
-- 
Falser Klaus
R&D Electronics Department
Company	: Durst Phototechnik AG
	  Vittorio Veneto Str. 59
	  I-39042 Brixen
Voice	: +0472/810235
	: +0472/810111
FAX	: +0472/830980
Email	: kfalser@IHATESPAMdurst.it 

Article: 34055
Subject: Virtex-II and LVDS clocks.
From: etohli@eto.ericsson.se (=?ISO-8859-1?Q?H=E5kon?=)
Date: 13 Aug 2001 00:56:43 -0700
Links: << >>  << T >>  << A >>
I have seen that Xilinx Virtex-E have LVDS clock inputs, but I am not
able to find any good information about LVDS clocks in Virtex-II. If
anybody has used this I would be happy to know!

Article: 34056
Subject: Re: Q: Revision and Database Control for FPGA Designs
From: allan_herriman.hates.spam@agilent.com (Allan Herriman)
Date: Mon, 13 Aug 2001 07:57:17 GMT
Links: << >>  << T >>  << A >>
On Sun, 12 Aug 2001 13:20:57 -0400, Rick Collins
<spamgoeshere4@yahoo.com> wrote:

>Allan Herriman wrote:
>> I agree with you about clearcase - it's definitely overkill for most
>> FPGA designers.  But I would hesitate to say that it's overkill for
>> all FPGA designers.
>> 
>> I find it a comfortable fit for the work I'm doing (multiple
>> developers at multiple sites, multiple products built from the same
>> code base, etc).  I guess this doesn't apply to most FPGA designers
>> though.
>> 
>> If I was working on a project with only say, 10 people at a single
>> site developing the code, then I'd probably find one of the simpler
>> tools to be the best one, and I would baulk at Clearcase's complexity
>> and cost.
>> 
>> Regards,
>> Allan.
>
>I am currenly working with Clearcase because it was mandated. We are
>working onsite as well as remotely and I don't see where Clearcase has
>any special advantages in this case. We log into our office LAN so that
>it is the same as working in the office. In that scenario, we could use
>any VCS that works over the LAN. 
>
>Can you explain what you are doing that Clearcase provides special
>features that facilitates your work? 

Hi Rick,

I just looked at PVCS for the first time.  The "special features" of
Clearcase all seem to be in PVCS too.  So I would have to say that
Clearcase has no unique features.  (Of course, I've never used PVCS,
so I can't really compare them.  There may be little hidden features
of a tool that make a lot of difference to real-life operation - like
the way SourceSafe would sometimes irreversibly corrupt your database
for example.  These sorts of things are not apparent when reading the
"glossy brochure" specifications.)

Rick, you've used both Clearcase and PVCS.  How do they compare?

Bye,
Allan.

Article: 34057
Subject: Re: Map report question
From: "Arnaud Dion" <arnaud.dion@mvd-fpga.com>
Date: Mon, 13 Aug 2001 09:57:04 GMT
Links: << >>  << T >>  << A >>
Hi
You can write in the UCF file :"NET "XXXX" FAST;" (XXXX is the name of your
net)
You can also use the constraint editor, check the "IO configuration Options"
in the "ports"window, then you'll have access to the fast/slow configuration
option.
It will increase the speed of your communications with the outside world but
use this only on critical paths because if you increase the speed, you will
decrease the quality of your signal and may have some problems.

Arnaud

"Antonio" <dottavio@ised.it> a écrit dans le message news:
fb35ea96.0108082249.4596dce2@posting.google.com...
> Really often when I try to map my project on Xilinx , the mapper show
> me the following warning :
>
> " All of the external outputs in this design are using slew rate
> limited output drivers. The delay on speed critical outputs can be
> dramatically reduced by designating them as fast outputs in the
> schematic  ??? "
>
>
> How I can do this, I mean designate output as fast output ?? This
> could speed up all my project ??
>
> Thanks you all ...
>
>
> Antonio D'Ottavio
>



Article: 34058
Subject: Re: this code doesn't work properly
From: "Harjo Otten" <h.otten@rohill.geen.spam.nl>
Date: Mon, 13 Aug 2001 12:19:35 +0200
Links: << >>  << T >>  << A >>
> And stop gating your clocks, please!


About gating clocks....... Why not, and how not to  ????

I've got a design and my compiler also says something about gated clocks.
I've checked where these 'gated clocks' were used, and it seems to be in a
clock-selector circuit (It's a serial port design, with a clock selector for
the baud rate). The design works well, so I've never paid much attention to
it and besides that, I haven't got the slightest idea on how to solve these
gated clocks. Any hints ???


H.




Article: 34059
Subject: Re: Digilab 10K10 resources / samples?
From: "Leon Heller" <leon_heller@hotmail.com>
Date: Mon, 13 Aug 2001 13:29:11 +0100
Links: << >>  << T >>  << A >>
> I was wondering if anybody else was working with the Digilab 10K10?
>
> I would like to decode the keyboard input. Not sure how to do that yet.

You'll find lots of stuff for the Altera UP1 kit here:

http://users.ece.gatech.edu/~hamblen/ALTERA/altera.htm

which should work OK on the Digilab board.

Leon
--
Leon Heller, G1HSM leon_heller@hotmail.con
http://www.geocities.com/leon_heller
Low-cost Altera Flex design kit: http://www.leonheller.com





Article: 34060
Subject: Re: Xilinx webpack vs. Student edition software
From: "Leon Heller" <leon_heller@hotmail.com>
Date: Mon, 13 Aug 2001 13:31:14 +0100
Links: << >>  << T >>  << A >>
>
> Also, does anyone know good sources of FPGA chips in the UK?

I get my Xilinx chips from Insight and Altera ones from Impact, both part of
Memec

Leon
--
Leon Heller, G1HSM leon_heller@hotmail.con
http://www.geocities.com/leon_heller
Low-cost Altera Flex design kit: http://www.leonheller.com



Article: 34061
Subject: Re: Slightly off topic - PCs for running FPGA tools
From: Keith R. Williams <krw@btv.ibm.com>
Date: Mon, 13 Aug 2001 08:46:21 -0400
Links: << >>  << T >>  << A >>
In article <3B76BCE7.8589021D@yahoo.com>, spamgoeshere4@yahoo.com 
says...
> "Keith R. Williams" wrote:
> > I'm a well known AMD fan, but wouldn't give up the bells and whistles
> > on this A21p for anything.  In particular, the 1600x1200 LCD display.
> > I also have a graphics card in a docking station and run a secondary
> > 20" display (combined 3200x1200 desktop).  I can keep all of the
> > ModelSim windows, along with my synthesis tools/VHDL editor open on the
> > LCD and move the ModelSim waveform window to fill the entire secondary
> > display. Of course, I don't haul the secondary display around with me.
> > ;-)
> > 
> > ----
> >   Keith
> 
> Is this secondary display something that Windows supports natively? Or
> does it require special drivers? This would be a BIG advantage of using
> a secondary graphics card. I assume that I could do this in my desktop
> as well, right?

Win2K supports this natively.  The display adapters don't even have to 
be the same, hence the ThinkPad's LCD and my Matrox Mystique. THe 
displays don't even have to run at the same resolution, though 
sometimes things look odd (like wall paper) when they're set 
differently.  

Yes, it can be done on a desktop in the same manner.  Matrox also sells 
a single card that will support two or four displays.  Unfortunately 
it's too big to fit in the half-sized PCI slot in the docking station.

Dual displays can also be done under WinNT, though it's more of a 
driver thing there.  Not all graphics cards support this and the cards 
must be the same.  I have this setup on my desktop (rarely used 
anymore) with two Matrox Mystique B220s (the standard Mystique doesn't 
support dual monitors). 

> Just out of curiosity, when a dialog box pops up that is in the center
> of the display, does it pop up to the center of the TWO screens, or the
> center of the first screen? 

It depends on the dialog box. If it's one that insists on popping up in 
the center it will be split, unfortunately. 

When a screen I s maximized it maximizes to only the screen it's in 
though.  To cover both screens (I often do this with Synplify) one has 
to drag the window across both.
   
> I am also surprised that a 1600, 15" display is readable. Aren't the
> fonts and icons rather small on the laptop display? But then again, I am
> getting my first pair of bifocals and have been hurting to read the
> newspaper for the last 6 months or so. That may be skewing my perception
> of what is readable... :)

The text on the 15" LCD display is more readable than it is on my 20" 
IBM P200.  I'd probably go to 1280x1024, except that non-native 
resolutions look strange on the LCD. I usually crank up the font size a 
little to compensate. I often change the font size based on what I'm 
doing.  I'm not quite ready for glasses, though perhaps cheaters.  I am 
30 (as in 0x30 ;-) so it won't be long :-(.

----
  Keith

Article: 34062
Subject: Re: Q: Revision and Database Control for FPGA Designs
From: Rick Collins <spamgoeshere4@yahoo.com>
Date: Mon, 13 Aug 2001 09:34:46 -0400
Links: << >>  << T >>  << A >>
Allan Herriman wrote:
> 
> On Sun, 12 Aug 2001 13:20:57 -0400, Rick Collins
> <spamgoeshere4@yahoo.com> wrote:
> >I am currenly working with Clearcase because it was mandated. We are
> >working onsite as well as remotely and I don't see where Clearcase has
> >any special advantages in this case. We log into our office LAN so that
> >it is the same as working in the office. In that scenario, we could use
> >any VCS that works over the LAN.
> >
> >Can you explain what you are doing that Clearcase provides special
> >features that facilitates your work?
> 
> Hi Rick,
> 
> I just looked at PVCS for the first time.  The "special features" of
> Clearcase all seem to be in PVCS too.  So I would have to say that
> Clearcase has no unique features.  (Of course, I've never used PVCS,
> so I can't really compare them.  There may be little hidden features
> of a tool that make a lot of difference to real-life operation - like
> the way SourceSafe would sometimes irreversibly corrupt your database
> for example.  These sorts of things are not apparent when reading the
> "glossy brochure" specifications.)
> 
> Rick, you've used both Clearcase and PVCS.  How do they compare?
> 
> Bye,
> Allan.

My PVCS experience is from the days of Windows 3.1. Most programs such
as PVCS were really DOS programs with no GUI, only command line
interfaces. We added a simple GUI once we had our procedures in place. 

What was nice about the way PVCS worked was that it seemed to require
little or no effort to keep it working and did not impact the way we
worked. Clearcase seems to require effort just to keep it running (the
office I am currently working in has a full time support person for it).
Clearcase also makes it hard to do some things such as using labels to
track builds. The software group only uses labels to track a released
build. In the FPGA group, we like to control our sources for each build
since a simple change can take us backward in terms of fitting or
timing. Often we don't know the full imnpact until we have a chip
running on the bench. (that is another discussion, I am amazed at how
one company's processes can differ from other's). 

Much of what I see as being a difficulty, may come from the change from
command line to GUI. I know that Clearcase has a command line tool, but
I have not been trained on it. 


-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 34063
Subject: Re: Q: Revision and Database Control for FPGA Designs
From: hamish@cloud.net.au
Date: Mon, 13 Aug 2001 13:55:08 GMT
Links: << >>  << T >>  << A >>
Rick Collins <spamgoeshere4@yahoo.com> wrote:
> Clearcase also makes it hard to do some things such as using labels to
> track builds. 

Really? Just an extra line in the config spec for your view.
I agree with Allan.. ClearCase is overkill for most FPGA work (it
excels for the software engineers), but it's nice overkill to have.
With project teams of 2-7 FPGA engineers, we use labels and branches
with good effect. We don't usually need to do much merging though.
The GUI integration is IMHO really good, but you do have to use
the command line for non-day-to-day stuff.

The original poster said he had design components which depended on
shared sub-components, and that different components might use different
versions of the same sub-components. I'm not sure how any version control
system would cope with that; you can only expect to see one version of
any particular entity at one time. I might even go so far as to say
that it sounds like a bad idea to need this feature.

Hamish
-- 
Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>

Article: 34064
Subject: Re: how to acheive high frquency in Xinlinx Virtex E
From: hamish@cloud.net.au
Date: Mon, 13 Aug 2001 14:00:18 GMT
Links: << >>  << T >>  << A >>
Kevin Neilson <kevin_neilson@removethis-yahoo.com> wrote:
> Xilinx.  The Tbcko (clk->out) is only about 3ns, but to use the BRAMs at

And surprisingly, Tbcko on a 2V -5 (about 3ns) is worse than a V-E -8
(2.5ns, up from 1.2 in an earlier service pack!). I was a bit disappointed
that this aspect of the 2V is slower.. otherwise the -5 seems very good.


regards
Hamish
-- 
Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>

Article: 34065
Subject: Re: Q: Revision and Database Control for FPGA Designs
From: allan_herriman.hates.spam@agilent.com (Allan Herriman)
Date: Mon, 13 Aug 2001 14:20:22 GMT
Links: << >>  << T >>  << A >>
On Mon, 13 Aug 2001 13:55:08 GMT, hamish@cloud.net.au wrote:

>Rick Collins <spamgoeshere4@yahoo.com> wrote:
>> Clearcase also makes it hard to do some things such as using labels to
>> track builds. 
>
>Really? Just an extra line in the config spec for your view.
>I agree with Allan.. ClearCase is overkill for most FPGA work (it
>excels for the software engineers), but it's nice overkill to have.
>With project teams of 2-7 FPGA engineers, we use labels and branches
>with good effect. We don't usually need to do much merging though.
>The GUI integration is IMHO really good, but you do have to use
>the command line for non-day-to-day stuff.
>
>The original poster said he had design components which depended on
>shared sub-components, and that different components might use different
>versions of the same sub-components. I'm not sure how any version control
>system would cope with that; you can only expect to see one version of
>any particular entity at one time. I might even go so far as to say
>that it sounds like a bad idea to need this feature.

Hi Hamish,

I just checked, and it's possible to see multiple versions of the same
element at the same time in Clearcase.  You need to use the internal
Clearcase filename for them though.

In the Version Tree Viewer, click on any version of the file, and say
"send to desktop as shortcut"  The shortcut created will have a target
that looks like:
\\<server_name>\<vob_name>\c\cdft\f\21\06809c698bd011d58ab20010a4045e3f

Not very user friendly, but at least it can be made to work.  I expect
there's some way of extracting these internal filenames given a config
spec, etc.

Regards,
Allan

Article: 34066
Subject: Re: this code doesn't work properly
From: "Wayne" <whalcomb@lucent.com>
Date: Mon, 13 Aug 2001 09:44:07 -0500
Links: << >>  << T >>  << A >>
I'm by no means an expert at this but this line does not make sense to
me ---


  (register[], data_word[]).clk = !up_ale;


Will this assign the .clk=!up_ale to both DFFE's ?

Regards,
Wayne



Article: 34067
Subject: Re: Virtex-II and LVDS clocks.
From: Austin Lesea <austin.lesea@xilinx.com>
Date: Mon, 13 Aug 2001 07:57:09 -0700
Links: << >>  << T >>  << A >>
Hi,

Virtex II has 16 global clock internal resources, with 16 global clock
inputs externally.  There are 8 primary and 8 secondary clock inputs.
When using LVDS which requires two IOB's for the differential input
(IBUFGDS), the number of supported external clocks is 8 due to the
dedicated resources involved.

All of this is covered int he on-line handbook, in Chapter 2: "Using
Global Clock Networks."

Austin

 http://www.support.xilinx.com/products/virtex/handbook/ug002_ch2_gcn.pdf

Håkon wrote:

> I have seen that Xilinx Virtex-E have LVDS clock inputs, but I am not
> able to find any good information about LVDS clocks in Virtex-II. If
> anybody has used this I would be happy to know!


Article: 34068
Subject: Re: FPGA or CPLD data compression
From: "Hu Chen" <>
Date: Mon, 13 Aug 2001 10:08:14 -0700
Links: << >>  << T >>  << A >>
Dear Jim

Thank you very much!
I only need to compress the binary file.
I just try to design an experiment to implement the standard data compression (such as the dcompr or gdcompr, LZH or gzip) on the CPLD (or FPGA). Then the binary file is as the input of the CPLD and a compressed binary file as the outputs.

Would you please give the further clues?

Thank you very much!
Hu

Article: 34069
Subject: Re: Digilab 10K10 resources / samples?
From: "Christopher J. Holland" <Personality_2@yahoo.com>
Date: Mon, 13 Aug 2001 17:19:38 GMT
Links: << >>  << T >>  << A >>
Thanks.

I had to go get the Digilab 10K10.
Shoulda got the UP1 kit. Oh well

Regards,
"Leon Heller" <leon_heller@hotmail.com> wrote in message
news:9l8h2i$762$1@neptunium.btinternet.com...
> > I was wondering if anybody else was working with the Digilab 10K10?
> >
> > I would like to decode the keyboard input. Not sure how to do that yet.
>
> You'll find lots of stuff for the Altera UP1 kit here:
>
> http://users.ece.gatech.edu/~hamblen/ALTERA/altera.htm
>
> which should work OK on the Digilab board.
>
> Leon
> --
> Leon Heller, G1HSM leon_heller@hotmail.con
> http://www.geocities.com/leon_heller
> Low-cost Altera Flex design kit: http://www.leonheller.com
>
>
>
>



Article: 34070
(removed)


Article: 34071
Subject: virtex2 Block Ram: dual port ram with different da
From: spyng <spyng@yahoo.com>
Date: Mon, 13 Aug 2001 10:42:12 -0700
Links: << >>  << T >>  << A >>
hi all,
I have a question regarding dual port ram with different data width.

I have a dual port ram configure as
port A 1024x13
port b 512x26

so how are the memory access from both side.

port a : addr[0] = [12:0] of data b location 0

port a: addr[1] = [25:13] of data b location 0
..

..

port a: addr[1022] = [12:0] of data b location 511

port a : addr[1023 = [25:0] of data b location 511

is this rigth?
any one know where is this in the virtex 2 manual? 

thank
spyng

Article: 34072
Subject: Re: Keep Xilinx Webpack from removing unused NETs?
From: "Andy Peters <andy [@] exponentmedia" <".> com">
Date: Mon, 13 Aug 2001 18:03:11 GMT
Links: << >>  << T >>  << A >>
Martin,

I've found that the easiest way to do this is to AND all of the unused
inputs together, and drive the result out a spare pin.

It's brute force, but it works.  And I don't have to remember which
silly synth/P+R switch to use...

-andy

"Martin v. Weymarn" wrote:
> 
> Hi,
> 
> I'm starting a new FPGA-design in VHDL using Xilinx Webpack. I defined
> all the connections/LOCs to the device in the UCF file and added them
> as ports in my top-level entity. However it seems that my input ports
> get optimized away because ngdbuild complains that the NETs cannot be
> found. Is there a way to keep the NETs although they are not used
> (yet)? I already tried to set the keep attribute to "yes" but that
> didn't help. Neither did unchecking the Map Option "Trim Unconnected
> Signals"...
> 
> Thanks,
> Martin.

Article: 34073
Subject: Re: Fast Mux and low power voltage reference
From: "Andy Peters <andy [@] exponentmedia" <".> com">
Date: Mon, 13 Aug 2001 18:03:55 GMT
Links: << >>  << T >>  << A >>
Kuan Zhou wrote:
> 
> Hi,
>    Does any one know how to design the fast multiplexer
> and low power voltage reference?
>    I used bipolar current mode logic trees for multiplexer.But
> the power consumption is too high.
>    Can anyone give me some suggestions?

My suggestion would be to ask this question in the relevant newsgroup.

-andy

Article: 34074
Subject: Re: virtex2 Block Ram: dual port ram with different da
From: "Andy Peters <andy [@] exponentmedia" <".> com">
Date: Mon, 13 Aug 2001 18:06:00 GMT
Links: << >>  << T >>  << A >>
I would imagine that the ports need to be the same width, and of course
your memory depth will be the same on both ends.

If you need to, for whatever reason (and I've needed to, actually), have
the memories "look" different on each side, you'll have to design some
logic to make it do so.

-andy

spyng wrote:
> 
> hi all,
> I have a question regarding dual port ram with different data width.
> 
> I have a dual port ram configure as
> port A 1024x13
> port b 512x26
> 
> so how are the memory access from both side.
> 
> port a : addr[0] = [12:0] of data b location 0
> 
> port a: addr[1] = [25:13] of data b location 0
> ..
> 
> ..
> 
> port a: addr[1022] = [12:0] of data b location 511
> 
> port a : addr[1023 = [25:0] of data b location 511
> 
> is this rigth?
> any one know where is this in the virtex 2 manual?
> 
> thank
> spyng



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