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Messages from 34900

Article: 34900
Subject: Using Synopsys Design Compiler to target Virtex-E FPGA
From: amey@controlnet.co.in (amey hegde)
Date: 13 Sep 2001 02:30:46 -0700
Links: << >>  << T >>  << A >>
Hi,
In Design Compiler which db do I use to synthesize my RTL to the
Virtex XCV1000E-6 ?
Can anyone send a sample .synopsys_dc.setup file listing the target
library, synthetic library and symbol library?
I tried using xdc_virtexe-6.db as the target library with virtexe.sdb
as the symbol library but I am getting a large violation (about 30ns
violation for my 16ns period clock)

-amey

Article: 34901
Subject: configuration latency for PCI bridge in FPGA
From: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
Date: Thu, 13 Sep 2001 13:42:14 +0200
Links: << >>  << T >>  << A >>
Hi,

we are considering about using the Xilinx PCI core in a future design.
Because of the high prices of 
configuration PROMs we are thinking about a little uC that does the FPGA
configuration after power on !
This seems to be very plexible because the uC can do other things after
booting the FPGA.

The problem I see is the configuration latency. Configuring the FPGA
through a small uCs I/O pins might be much slower than using a PROM
solution (serial PROM or PLD/Flash-combination).

Did anybody build a design with a uC configuring a PCI bridge FPGA ? How
much time is allowed until the FPGA must be booted to be detected by the
hosts plug and plug run ? Is there a way to extend or slow done the plug
and play stuff and to force retrys ?

Any idea ?

Matthias

Article: 34902
Subject: Re: Counter problem
From: Falk <>
Date: Thu, 13 Sep 2001 06:11:44 -0700
Links: << >>  << T >>  << A >>
Did you define ALL input signals in the simulation?

Regards
Falk

Article: 34903
(removed)


Article: 34904
Subject: Re: Using Synopsys Design Compiler to target Virtex-E FPGA
From: "Ansgar Bambynek" <a.bambynek_xxx_@avm.de>
Date: Thu, 13 Sep 2001 16:30:21 +0200
Links: << >>  << T >>  << A >>
Hi Amey

you could use synlibs which is a XILINX program to get the required
libraries. Just type in synlibs -help

To get the libraries for virtexe-6 just type

synlibs xdc_virtexe-6

the following is the result
    link_library = {xdc_virtexe-6.db xdw_virtex.sldb}
    target_library = {xdc_virtexe-6.db }
    symbol_library = {virtexe.sdb}
    define_design_lib xdw_virtex -path XilinxInstall +
/synopsys/libraries/dw/lib/virtex
    synthetic_library = {xdw_virtex.sldb standard.sldb}

Based on my experiences I would strongly recommend using fpga compiler II
instead of Design Compiler or FPGA Compiler.
If don't know if this holds true for virtexe but I got much better results
in terms of area and speed when using FC II.
My design was targeted for SPARTAN2

Unfortunately commands are not the same for DC and FCII so you can't just
your synthesis scripts one by one.

HTH

Ansgar
--
Attention reply address is invalid.
Please remove _xxx_
amey hegde <amey@controlnet.co.in> schrieb in im Newsbeitrag:
f8b003f9.0109130130.380ff99d@posting.google.com...
> Hi,
> In Design Compiler which db do I use to synthesize my RTL to the
> Virtex XCV1000E-6 ?
> Can anyone send a sample .synopsys_dc.setup file listing the target
> library, synthetic library and symbol library?
> I tried using xdc_virtexe-6.db as the target library with virtexe.sdb
> as the symbol library but I am getting a large violation (about 30ns
> violation for my 16ns period clock)
>
> -amey



Article: 34905
Subject: Re: Block RAM initialization
From: renaux <renaux.jacky@wanadoo.fr>
Date: 13 Sep 2001 15:44:41 GMT
Links: << >>  << T >>  << A >>

Try to read the XAPP199 page 21 . Coergen use a COE file and creates a MIF 
(memory Init file ). This file is an ascii one which would be easy to creates 
in the vhdl. But I am not sure it will work on synthesis . I have the same 
problem issue and I have to try myself to solve this 

regards

------
User of http://www.foorum.com/. The best tools for usenet searching.

Article: 34906
Subject: Re: convert
From: renaux <renaux.jacky@wanadoo.fr>
Date: 13 Sep 2001 15:53:56 GMT
Links: << >>  << T >>  << A >>

Try such 

 in the body 
 
 my_signal <= (CONV_STD_LOGIC_VECTOR(my_int , arg ) ;

 where my_int is my integer to convert  !! and arg is how wide will be 
 the std_logic_vector result 

 this convertion ( a function ) is included into a library which must be 
 openned  then 
 your first lines must have the proper library statement 
 use library ieee.std_logic_arith.all ; 

 check into that file you will find out more functions  

hope it will help 

regards

------
User of http://www.foorum.com/. The best tools for usenet searching.

Article: 34907
Subject: Re: SOS : A Question about synthesizng ROM
From: renaux <renaux.jacky@wanadoo.fr>
Date: 13 Sep 2001 16:06:38 GMT
Links: << >>  << T >>  << A >>

Hi 
I have quite the same issue to solve , try reading XAPP199 (Xilinx ) page 21

I am yet not sure which it is valid to synthesis 

regards

------
User of http://www.foorum.com/. The best tools for usenet searching.

Article: 34908
Subject: Re: Problems with Xilinx VirtexE (Newbie)
From: Falk Brunner <Falk.Brunner@gmx.de>
Date: Thu, 13 Sep 2001 18:28:21 +0200
Links: << >>  << T >>  << A >>
Paul schrieb:
> 
> Hi,
> 
> I'm trying to do my first examples with FPGA's and I am running into
> some problems with a Xilinx VirtexE in a demo board.
> 
> I want to make a counter and to display the count in a 7-segment
> display of the board. The clock for this counter schould be a
> press-button of the board. The problem is that the button is
> physically connected to the pin P95 of th FPGA and the Xilinx tool
> (ISE 3.1) doesn't allow me to place this input signal in this pin. If
> I constrain this signal to this pin I get the following error:
> 
> ERROR:MapLib:93 - Illegal LOC on symbol "clk.PAD" (pad signal=clk) or
> BUFGP
>    symbol "clk_BUFGP" (output signal=clk_BUFGP), IPAD-IBUFG should
> only be LOCed
>    to GCLKIOB site.

The synthesis software recognizes the clock signal and automatically
creates a clock buffer. This has to be disabled. This can be done in the
synthesis constraints editor. When you create a new version (menu entry)
, click the marker for EDIT SYNTHESIS CONSTRAINTS. When the windo pops
up, go to the PORTS window, and select for the default clock buffer
value (1st row) DONT USE.

-- 
MFG
Falk



Article: 34909
Subject: FPGA--? huh
From: "Thomas Schmidt" <thomasx@schmidtnet.dk>
Date: Thu, 13 Sep 2001 18:55:36 +0200
Links: << >>  << T >>  << A >>
Hi

I'm a student who's just been asigned to at projekt which involves building
a PID on a FPGA Spartan II.

The only problem (so far... ;-) ). Is that none of us really has any idea of
what a FPGA is? An my web-crawling hasn't revealled much to me.

Does any of you a good website for gathering info on FPGA's? (Especially the
Spartan II).

Thank's a lot.

Thomas Schmidt



Article: 34910
Subject: Re: Block RAM initialization
From: "Jan Pech" <j.pech@sh.cvut.cz>
Date: Thu, 13 Sep 2001 20:08:52 +0200
Links: << >>  << T >>  << A >>
Thanks for all answers. The best way I found in
http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=
1&getPagePath=10695
It works with both simulation and synthesis.

Jan

"renaux" <renaux.jacky@wanadoo.fr> wrote in message
news:2001913-174441-891180@foorum.com...
>
> Try to read the XAPP199 page 21 . Coergen use a COE file and creates a MIF
> (memory Init file ). This file is an ascii one which would be easy to
creates
> in the vhdl. But I am not sure it will work on synthesis . I have the same
> problem issue and I have to try myself to solve this
>
> regards
>
> ------
> User of http://www.foorum.com/. The best tools for usenet searching.



Article: 34911
(removed)


Article: 34912
Subject: Re: FPGA--? huh
From: Steve Shaver <steve.shaver@alcatel.com>
Date: Thu, 13 Sep 2001 16:33:22 -0400
Links: << >>  << T >>  << A >>
Try,

www.xilinx.com
www.optimagic.com

Best Regards,

Steve Shaver
Programmable Logic Solutions
Alcatel Canada


Thomas Schmidt wrote:

> Hi
>
> I'm a student who's just been asigned to at projekt which involves building
> a PID on a FPGA Spartan II.
>
> The only problem (so far... ;-) ). Is that none of us really has any idea of
> what a FPGA is? An my web-crawling hasn't revealled much to me.
>
> Does any of you a good website for gathering info on FPGA's? (Especially the
> Spartan II).
>
> Thank's a lot.
>
> Thomas Schmidt

--


Article: 34913
Subject: Re: convert
From: "Tim" <tim@rockylogic.com.nospam.com>
Date: Thu, 13 Sep 2001 21:35:53 +0100
Links: << >>  << T >>  << A >>

"renaux" <renaux.jacky@wanadoo.fr> wrote in message
news:2001913-175356-840658@foorum.com...
>
> Try such
>
>  in the body
>
>  my_signal <= (CONV_STD_LOGIC_VECTOR(my_int , arg ) ;
>
>  where my_int is my integer to convert  !! and arg is how wide will be
>  the std_logic_vector result
>
>  this convertion ( a function ) is included into a library which must be
>  openned  then
>  your first lines must have the proper library statement
>  use library ieee.std_logic_arith.all ;


9 out of 10 aesthetes who expressed a preference chose ieee.numeric_std





Article: 34914
Subject: Specifing global clocks on a Spartan II (Newbee Quest)
From: "Michael Strayer" <michael.strayer@sri.com>
Date: Thu, 13 Sep 2001 13:37:22 -0700
Links: << >>  << T >>  << A >>
Hello,
I'm trying to use Xilinx's Webpack software to implement
a design on a Spartan II.  Part the the design is a bitclock
generator that divides the system clock down to two other
freq's.  When I try to use these clocks in other parts of the
design Webpack complains that I am routing clocks using
non-dedicated resources.

I've read the section in the online help about assigning
signals to global clock buffers using the attribute statement
but when I try this I get a message stating the BUFG is an unknown
attribute.

How do I go about assigning an internally generated signal to
a global clock net??

Thanks
Mike Strayer




Article: 34915
Subject: Re: configuration latency for PCI bridge in FPGA
From: "Tim" <tim@rockylogic.com.nospam.com>
Date: Thu, 13 Sep 2001 21:41:09 +0100
Links: << >>  << T >>  << A >>
Look up amy previous discussions via groups.google.com or another archive.

Config via a micro can be really quick if you use select map or,
my favourite, use something like an SPI port on the micro which
matches the serial config requirements of the FPGA.  Check the
serial congig spec for format and maximum bit rate.


"Matthias Fuchs" <matthias.fuchs@esd-electronics.com> wrote in message
news:3BA09B96.5A7782A7@esd-electronics.com...
> Hi,
>
> we are considering about using the Xilinx PCI core in a future design.
> Because of the high prices of
> configuration PROMs we are thinking about a little uC that does the FPGA
> configuration after power on !
> This seems to be very plexible because the uC can do other things after
> booting the FPGA.
>
> The problem I see is the configuration latency. Configuring the FPGA
> through a small uCs I/O pins might be much slower than using a PROM
> solution (serial PROM or PLD/Flash-combination).
>
> Did anybody build a design with a uC configuring a PCI bridge FPGA ? How
> much time is allowed until the FPGA must be booted to be detected by the
> hosts plug and plug run ? Is there a way to extend or slow done the plug
> and play stuff and to force retrys ?
>
> Any idea ?
>
> Matthias



Article: 34916
Subject: Re: Innoveda and ISE Alliance 4.1i ?
From: "pete dudley" <padudle@spinn.net>
Date: Thu, 13 Sep 2001 17:53:42 -0600
Links: << >>  << T >>  << A >>
I want to say thanks to Philip Frieden with help on this issue. Xilinx does
still supply Innoveda Viewdraw libraries with the 4.1i release.

The trick is to select Custom install option while running the Xilinx
installation program. The Custom install gives the option to select Innoveda
libraries while the Typical install defaults to not installing them.

Anyway, life is good again.

--
Pete Dudley

"Pete Dudley" <padudle@sandia.gov> wrote in message
news:9nld5u$5en$1@sass1828.sandia.gov...
> I just installed ISE Alliance 4.1i and find no support for Innoveda tools.
> There are no Viewdraw libraries shipped with the software and no Innoveda
> Interface Guide in the online documentation. There is still a Mentor
> Graphics Interface Guide.
>
> Has Xilinx stopped working with Innoveda? I would consider that a shame.
>
> --
> Pete Dudley
>



Article: 34917
Subject: Re: configuration latency for PCI bridge in FPGA
From: Jim Granville <jim.granville@designtools.co.nz>
Date: Fri, 14 Sep 2001 15:36:01 +1200
Links: << >>  << T >>  << A >>
Matthias Fuchs wrote:
> 
> Hi,
> 
> we are considering about using the Xilinx PCI core in a future design.
> Because of the high prices of
> configuration PROMs we are thinking about a little uC that does the FPGA
> configuration after power on !
> This seems to be very plexible because the uC can do other things after
> booting the FPGA.
> 
> The problem I see is the configuration latency. Configuring the FPGA
> through a small uCs I/O pins might be much slower than using a PROM
> solution (serial PROM or PLD/Flash-combination).
> 
> Did anybody build a design with a uC configuring a PCI bridge FPGA ? How
> much time is allowed until the FPGA must be booted to be detected by the
> hosts plug and plug run ? Is there a way to extend or slow done the plug
> and play stuff and to force retrys ?
> 
> Any idea ?
> 
> Matthias

 It depends a little on how much config storage you need, and what else
you can
find for the uC to do.
 A uC with HW SPI port can pump close to the self-loading speed.
 Solutions I have seen used are 
- small uC, like 89C1051U used with external SO8 memory (eg AT25F1024)
- Larger uC, with FPGA code on-chip (64K Bytes storage), compressed
bitstream.
- Low cost CPLD, and external ByteWide memory
- Low cost CPLD, and external SO8 memory

 A new Tiny uC, suited to FPGA pump loading, is the C8051F303
see http://www.cygnal.com/products/C8051F303.htm
                         
-jg

-- 
======= 80x51 Tools & IP Specialists  =========
= http://www.DesignTools.co.nz

Article: 34918
Subject: Foundation 3.1i REINSTALLATION
From: jdiaz_pr@excite.com (jdiaz_pr)
Date: 13 Sep 2001 21:34:06 -0700
Links: << >>  << T >>  << A >>
Hi,

I got a virus that erased my C: drive, is there a way to reinstall de
S/W over the D: drive (yet installed) without requiring to do the
tedious patching/update procedure. I tried the installation over
another tool A-HDL giving me many headaches trying to enable the
floating license (no success so far). I am pondering to uninstall (or
erase) the whole D: drive's tools directories and start with some
'clean' installations. In any case a "XIE internal error 101" message
from Foundation may indicate several no registry entries available (I
think).

If you like to share some experiences, we ALL be grateful!

Peace!

Article: 34919
Subject: Looking for knowledge on CORDIC, division, correlators, TSBs, sorting, and path-delay handling
From: jdiaz_pr@excite.com (jdiaz_pr)
Date: 13 Sep 2001 22:01:16 -0700
Links: << >>  << T >>  << A >>
Hello everyone!

I got several questions; hope to have answers to some:

1. Can you share experiences on CORDIC using Xilinx 4K architecture
(i.e., strictly using its primitives) and how it compares with a
Virtex implementation?

2. Are there some good references on division by a constant techniques
based on iterative, CORDIC, KCM, etc?

3. Do you have a good resource about 1D correlators and 2D correlators
for imaging?

4. I'd like to find some good examples on TSB usage. Some intro info
will be greatly appreciated.

5. What is the best sorting method for area optimized design and for a
speed oriented one?

6. This is the last naive question: Implementing an intensive
arithmetic path, which for some instances its delay path, is shorted
by a no-intense arithmetic 'case' condition. How can I do the
reconciliation on the next stage input, in the sense of "data_ready"
condition taking in account a fixed clocking scheme?


Peace!

Article: 34920
Subject: Re: ISE 4.1
From: kevinbraceusenet@hotmail.com (Kevin Brace)
Date: 13 Sep 2001 22:39:15 -0700
Links: << >>  << T >>  << A >>
"David Wright" <dwright@srtorque.com> wrote in message news:<4S3m7.232735$NK1.21400208@bin3.nnrp.aus1.giganews.com>...
> Xilinx's ISE 4.1 sounds promising.  After talking to my local Xilinx
> representative, it should be available shortly.  My current project is 2300
> lines of untested VHDL code including a small test vector.  The WebPack has
> a limit of 500 lines.
> 
> I was assured the ISE 4.1 was all that I might need to do my design.
> However,  I am skeptical as to the adequacy of the simulator.  As I learned
> from past experience with Cypress and Altera, test and verification are of
> key importance to a design.



        If you check out Xilinx's website about ISE WebPack 4.1i
(http://www.xilinx.com/ise/products/webpack_config.htm), the simulator
that will come with ISE WebPack 4.1i will still be ModelSim Starter
(probably means ModelSim XE-Starter which already comes with the
current version of WebPack) which will likely still have the same
500-line code limitation you have been complaining about (see WebPack
Con-Game).
Again, as many have said before, even the current ModelSim XE-Starter
will still let you simulate a design even if it exceeds the 500-lines
of code.
Since you claim to already have your own design, are you afraid to
learn how to operate new tools?
Again, I still think you have nothing to lose because the tools are
free.
When I first installed ModelSim XE-Starter to my computer, the
software looked complicated, and hard to use.
In retrospect, that was because I never read the tutorial that came
with ModelSim, and after reading through the tutorial I was able to
simulate my design (functional simulation).
Xilinx Application Note 338 and Johnson Counter example in the WebPack
tutorial were very useful in learning how to do post-route simulation
which I think is important before firing up the FPGA in a real system.



Regards,



Kevin Brace (don't respond to me directly, respond within the
newsgroup)

Article: 34921
Subject: Re: ISE 4.1
From: kevinbraceusenet@hotmail.com (Kevin Brace)
Date: 13 Sep 2001 23:13:24 -0700
Links: << >>  << T >>  << A >>
"Andrew Dyer" <adyer@enteract.com> wrote in message news:<WeBn7.56903$xb.30261138@news1.mntp1.il.home.com>...
> "David Wright" <dwright@srtorque.com> wrote in message
> news:4S3m7.232735$NK1.21400208@bin3.nnrp.aus1.giganews.com...
> > Xilinx's ISE 4.1 sounds promising.  After talking to my local Xilinx
> > representative, it should be available shortly.  My current project is
>  2300
> > lines of untested VHDL code including a small test vector.  The WebPack
>  has
> > a limit of 500 lines.
> >
> > I was assured the ISE 4.1 was all that I might need to do my design.
> > However,  I am skeptical as to the adequacy of the simulator.  As I
>  learned
> > from past experience with Cypress and Altera, test and verification are of
> > key importance to a design.
> >
> 
> I tried installing it today at work - (someone had to be first...)
> 
> Beware if you have a machine with an Athlon CPU.  There are problems
> with "some" Athlon boards.  I have a 1.1 GHz Athlon on an ASUS mobo
> with 768 Mb of Micron memory running Win 2000 SP2 and I was getting
> lockups running ngdbuild that required a hard reset.  The system is
> otherwise
> very solid running Modelsim, older Xilinx tools, Foundation express, etc.
> 
>  Fortunately I didn't uninstall my old tools, just installed the 4.1i stuff
> in a new
> directory and changed the %XILINX% environement variable.
> 
> My advice is to wait for a few service packs to go by unless you want to be
> a guinea pig like me :-)


        Where did you purchase your memory module from?
Perhaps did you purchase your memory modules from a computer dealer?
Although I don't use the same OS as you do (I use Windows 98 SE), and
I run it on a 100MHz Socket 7 motherboard (a Giga-Byte motherboard
with SiS 530 chipset), I don't have any lockups when running any of
the WebPack applications.
I currently use Kingston 256MB PC133 CL3 module, but I haven't had any
lockups which I believe is memory related (most of the crashes I had
were related to using too much resources when having too many Internet
browser windows open at the same time).
I have been hearing rumors that some companies that assemble so called
"generic" memory modules have been lowering the quality of their
memory modules to cut cost during the recent downward spiral of memory
module price (128Mb chip @ less than US $2).
Although it probably varies by vendor to vendor, one example is using
fewer chip capacitors on the module.
Do you know if this problem happens with any other microprocessor and
chipset combination?
Perhaps is VIA chipset that is likely on your motherboard (just
guessing) causing the problem?




Regards,



Kevin Brace (don't respond to me directly, respond within the
newsgroup)

Article: 34922
Subject: Help!
From: "rAinStorms" <cburton@ihug.co.nz>
Date: Fri, 14 Sep 2001 18:49:29 +1200
Links: << >>  << T >>  << A >>
Hi There,

I am trying to put together a proposal for ASIC development using an
EP20K200 or similar style device as the development prototyping platform.
This is part of Alteras Apex II range.... 100k gates plus 53kbits SRAM in a
144pin TQFP.

However the actual vendor or family is not that important, as long as it's
similar in spac.

Looking at the volume pricing changes in FPGA technology over the last five
years I am concerned that in my 50-100k / year volume requirements that in
18-24 months the price of these devices will come down to levels where doing
an ASIC is pointless for this type of device.

Can anyone out there give me any feedback pertaining to forward pricing
models they may have seen from FPGA vendors out there .... you can strip
company names or whatever if needed. I am looking for an idea of how the
price of a device with the capability I indicated will change over the next
2 years. Note that the devices are I/O ring limitted right now ... and  only
need approx 90 I/O in a 144 Pin TQFP or 1mm BGA style device.

Any help appreciated!

Chris



Article: 34923
Subject: Virtex-E1600 unsupported?
From: Michael Boehnel <boehnel@iti.tu-graz.ac.at>
Date: Fri, 14 Sep 2001 11:09:58 +0200
Links: << >>  << T >>  << A >>
Hello!

I'm trying to implement a design on a VirtexE-1600 or higher. I use
Foundation 3.1i and Service Pack 8, FPGA Express.

While VirtexE-1000 is supported I get the following message with
XCV1600E or higher:
Error Message: The specified part XCV1600E-6-BG560 is either invalid or
not supported.

Is this a problem of FPGA Express or Foundation?

Can someone tell me where I can find a documentation (file or www) with
the supported single devices?

Thanks,

Michael



Article: 34924
Subject: Re: Block RAM initialization
From: "Arnaud Dion" <arnaud.dion@mvd-fpga.com>
Date: Fri, 14 Sep 2001 12:07:50 +0200
Links: << >>  << T >>  << A >>
Hi,
you should use a NCF file :
Create a file with a text editor, give it the name of your top level entity
and the extension .NCF, copy this in your file :

INST LEVEL1/LEVEL2/NAME INIT_00 =
333333333333BBBB999999999999DDDDCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC;
INST LEVEL1/LEVEL2/NAME INIT_01 =
000000000000CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCEEEE6666666666667777;
INST LEVEL1/LEVEL2/NAME INIT_02 =
0000000000000000000000000000000000000000000000000000000000000000;
INST LEVEL1/LEVEL2/NAME INIT_03 =
0000000000000000000000000000000000000000000000000000000000000000;
INST LEVEL1/LEVEL2/NAME INIT_04 =
0000000000000000000000000000000000000000000000000000000000000000;
INST LEVEL1/LEVEL2/NAME INIT_05 =
0000000000000000000000000000000000000000000000000000000000000000;
INST LEVEL1/LEVEL2/NAME INIT_06 =
0000000000000000000000000000000000000000000000000000000000000000;
INST LEVEL1/LEVEL2/NAME INIT_07 =
0000000000000000000000000000000000000000000000000000000000000000;
INST LEVEL1/LEVEL2/NAME INIT_08 =
0000000000000000000000000000000000000000000000000000000000000000;
INST LEVEL1/LEVEL2/NAME INIT_09 =
0000000000000000000000000000000000000000000000000000000000000000;
INST LEVEL1/LEVEL2/NAME INIT_0a =
0000000000000000000000000000000000000000000000000000000000000000;
INST LEVEL1/LEVEL2/NAME INIT_0b =
0000000000000000000000000000000000000000000000000000000000000000;
INST LEVEL1/LEVEL2/NAME INIT_0c =
0000000000000000000000000000000000000000000000000000000000000000;
INST LEVEL1/LEVEL2/NAME INIT_0d =
0000000000000000000000000000000000000000000000000000000000000000;
INST LEVEL1/LEVEL2/NAME INIT_0e =
0000000000000000000000000000000000000000000000000000000000000000;
INST LEVEL1/LEVEL2/NAME INIT_0f =
0000000000000000000000000000000000000000000000000000000000000000;

LEVEL1/LEVEL2 is the names of your different levels if you have a
hierarchical code.
LEVEL2 is the name of the VHDL entity where you declare your RAM component
and NAME is its name.
if your component is declared in your top level entity, you should write :
INST NAME INIT_00 =
333333333333BBBB999999999999DDDDCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC;

The numbers are the content of your blockRAM.
Don't forget that the extreme right of the lines are the LSBs and the left
the MSBs.
All the number are hexadecimals so we have 16 linesx64 numbers_per_linex4 =
4096 bits.

Save this file in the same folder of your VHDL source.

Arnaud.


"Jan Pech" <j.pech@sh.cvut.cz> a écrit dans le message news:
9noobo$1csk$1@ns.felk.cvut.cz...
> Hi,
> I'm using RAM description in my design which maps on the BlockRAM in
Xilinx
> Spartan-II. Is there any way how to initialize this RAM with my own
values?
> I'm using WebPACK 3.3.
>
> Thanks
> Jan
>
> ___________________________
>      j.pech@sh.cvut.cz
>      +420 (723) 760802
>      ICQ: 56431283
>
>
>





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