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Messages from 34800

Article: 34800
Subject: Re: Special counter for scheduling
From: Lasse Langwadt Christensen <langwadt@ieee.org>
Date: Sat, 08 Sep 2001 06:04:42 GMT
Links: << >>  << T >>  << A >>
Andy Holt wrote:
> 
> Michael Boehnel wrote:
> >
> > For scheduling I'd like to implement a special counter:
> >
> > The counter has an extra input "Marked" of type STD_LOGIC_VECTOR(N-1
> > downto 0). The counter jumps to the next value with Marked(i)='1'. E.g.:
> > Actual Counter=2,  Marked(2,3,4,6,7)='0' , Marked(1,5)='1',   => Next
> > actual counter := 5 ...
> >
> 
> Wearing my "Murthy was an optimist" hat ... and with experience of how
> programs can go wrong:
> 
> What happens if no Marked(i) is non-zero?
> In the software analogue we would have a rather nasty infinite loop - I
> would expect something equally unpleasant to occur in the hardware
> designed to the specification.
> 
> Andy

why would it be nasty? from the subject I assume Marked() represents 
tasks, or what ever, that needs to run, if no task needs to run 
it doesn't really what the counter is set to, 

I guess the SW analogue would be round-robbin scheduling with idle 
being the current task

-Lasse
-- Lasse Langwadt Christensen, 
-- A Dane in Phoenix, Arizona

Article: 34801
Subject: Re: Missing bits
From: Lasse Langwadt Christensen <langwadt@ieee.org>
Date: Sat, 08 Sep 2001 06:40:44 GMT
Links: << >>  << T >>  << A >>
Ray Andraka wrote:
> 
> The IOB cells in the FPGA have flip-flops in them, but unless you are careful
> your design may not be using them.  When these are used, the set-up time to the
> flip-flop in the design is quite deterministic, and is the smallest possible
> value.  If your signal does not get registered in the IOB, then there is a
> routing delay associated with getting the signal inside the FPGA where it
> eventually hits a flip-flop.  It sounds like that is the case in your design.
> What happens then, of course, is that the signal takes too long to get into the
> chip and you have a timing problem.
> 
snip

Wouldn't it make sense to try and force a possible skew to be large
enough, in 
the ín right direction, to make it's safe, i.e. run the ADC on the
inverted 
clock or possibly one of the shifted outputs from the DLL ?  

-Lasse
-- Lasse Langwadt Christensen, 
-- A Dane in Phoenix, Arizona

Article: 34802
Subject: synplify device configuration settings
From: "Frank Van de Sande" <fvds12@yahoo.com>
Date: Sat, 08 Sep 2001 07:58:45 GMT
Links: << >>  << T >>  << A >>
hello,

(I am using Synplify Pro & Quartus)

I want to pass the whole list of  settings to Synplify,  (i.e. also those
not used/recoginized by Synplify Pro such as treatment of non-used pins,
configuration options,  which programming files to generate etc) and let
Synplify generate the necessarey files and scripts forwarded to Quartus.
The goal is to have a single file (or at  least 1 interface -Scope) for
maintaining all option settings

Until now I have the synthesis constraints in *.sdc, but I still need
Quartus to set e.g.  abovementioned options;


anyone an idea how to do this?

best regards


FVdS





Article: 34803
Subject: SOS : A Question about synthesizng ROM
From: grad_student@telecomguide.net (grad_student)
Date: 8 Sep 2001 02:22:35 -0700
Links: << >>  << T >>  << A >>
The task requires writing code in VHDL for synthesizing a number of
ROM blocks on the FPGA. The ROM contents are located in an ASCII file,
word by word. So the question
is where would be the code that uses the File object to access the
files, get the words and passes them on to the ROM as a generic (array
of words) ? Configuration blocks ? .. but then are n't configurations
supposed to contain no simulation semantics ?

I came to know recently that ROMs cannot be synthesised by reading
from a file.. well that seems quite a limitation. The next thing that
comes to mind is declaring an array of vectors as a generic and then
passing that generic that to the ROM at the time of instansiation.Any
other suggestions ?

Help would be greatly appreciated

Cheers to all

Article: 34804
Subject: Re: Actel FPGA glitches
From: "Gregory C. Read" <xxxgread@voicenet.com>
Date: Sat, 08 Sep 2001 09:52:26 GMT
Links: << >>  << T >>  << A >>
We're using an A42MX09 and an A42MX24 with no problems. Is your clock signal
input very clean? It's amazing what a noisy clock will do.

--
Greg
xxxgread@voicenet.com
(Remove the 'xxx' to send Email)


"Paul McCallion" <paul.mccallion@mkg.com> wrote in message
news:4815c2ca.0109070304.6d644188@posting.google.com...
> Hi,
> Has anyone seen any glitch problems with Actel's A42MX series? I have
> seen 10nS glitches on outputs for several minutes after power on and
> with the application of freezer spray to the FPGA.
>
> Paul



Article: 34805
Subject: Re: SOS : A Question about synthesizng ROM
From: Ray Andraka <ray@andraka.com>
Date: Sat, 08 Sep 2001 14:29:39 GMT
Links: << >>  << T >>  << A >>
you can set up your data array as a constant in a separate package.  A
simple translate program can then read your array from your data file and
write it as a VHDL package (for that matter, if your data is already in
comma separated ascii integer format, all you need to do is add the
package around it with a text editor).  Then your VHDL can include the
package so that it has access to the constant array.

The other option is to initialize the ROM later in the tools flow, but I
think that is a) more difficult, and b) it makes it pretty hard to
simulate.  Note, that for the ROM data to make it through the synthesis,
it has to be entered as INIT attributes in the edif file.  If your are
instantiating the ROM, you'll need to put user attributes on it to
accomplish that.  If you are inferring it, then the synthesizer should do
that for you.  For small roms, be careful that the synthesizer doesn't
turn your ROM into a mess of gates.

grad_student wrote:

> The task requires writing code in VHDL for synthesizing a number of
> ROM blocks on the FPGA. The ROM contents are located in an ASCII file,
> word by word. So the question
> is where would be the code that uses the File object to access the
> files, get the words and passes them on to the ROM as a generic (array
> of words) ? Configuration blocks ? .. but then are n't configurations
> supposed to contain no simulation semantics ?
>
> I came to know recently that ROMs cannot be synthesised by reading
> from a file.. well that seems quite a limitation. The next thing that
> comes to mind is declaring an array of vectors as a generic and then
> passing that generic that to the ROM at the time of instansiation.Any
> other suggestions ?
>
> Help would be greatly appreciated
>
> Cheers to all

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com



Article: 34806
Subject: Re: Missing bits
From: Ray Andraka <ray@andraka.com>
Date: Sat, 08 Sep 2001 14:34:15 GMT
Links: << >>  << T >>  << A >>
Normally, the ADC output comes out as a result of the rising edge, and the additional
delay getting onto the FPGA just helps.  If the delay is too long, however, you start
getting into the next clock cycle.  If that is the case, using the opposite edge is
just going to aggravate the situation, assuming the clocks have a relatively small
skew between the FPGA and the ADC.  The CLKDLL will make sure the skews are small.
BTW, he mentioned he is using the BUFDLL. He may want to look at the DLL app notes to
see how to manage skew outside of the chip...it involves feeding the external clock
back into the FPGA, which the BUFDLL does not do.  I don't recall the app note number
off hand maybe xapp 232?

Lasse Langwadt Christensen wrote:

> Ray Andraka wrote:
> >
> > The IOB cells in the FPGA have flip-flops in them, but unless you are careful
> > your design may not be using them.  When these are used, the set-up time to the
> > flip-flop in the design is quite deterministic, and is the smallest possible
> > value.  If your signal does not get registered in the IOB, then there is a
> > routing delay associated with getting the signal inside the FPGA where it
> > eventually hits a flip-flop.  It sounds like that is the case in your design.
> > What happens then, of course, is that the signal takes too long to get into the
> > chip and you have a timing problem.
> >
> snip
>
> Wouldn't it make sense to try and force a possible skew to be large
> enough, in
> the ín right direction, to make it's safe, i.e. run the ADC on the
> inverted
> clock or possibly one of the shifted outputs from the DLL ?
>
> -Lasse
> -- Lasse Langwadt Christensen,
> -- A Dane in Phoenix, Arizona

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com



Article: 34807
Subject: Powering up a multi virtex fpga board
From: "jfh" <jfhasson@club-internet.fr>
Date: Sat, 8 Sep 2001 18:36:08 +0200
Links: << >>  << T >>  << A >>
Hi,

I am working on a board involving several virtex type fpgas and
I am worried about the min 2 amps needed for power-up of each fpga
as well as the ramp of the core voltage. Has anyone some experience
about powering up a multi fpga board with the power constraints ot the
virtex (min 2A and a ramp of 2ms to 50ms from 0 to Vccint) ? What about
the fact that the virtex datasheet doesn't mention anything about the max
of the power consumption at power up ? Doees that mean that the number of
amps if not limited can be destructive ?
Thank you.

J.F



Article: 34808
Subject: Xilinx dev. kit for Linux?
From: Andrew Rogers <andrew@rogerstech.freeserve.co.uk>
Date: Sat, 08 Sep 2001 20:52:05 +0100
Links: << >>  << T >>  << A >>
Is there a development kit for GNU/Linux to take a VHDL file and 
generate the bit stream file for the Xilinx XC3020?

I am still learning VHDL, but before I get to carried away I would like 
to be certain that I can configure the FPGA I have. Is Alliance suitable 
for the entire development process and if so, can anyone point me to a 
good tutorial or example?

Any help is appreciated.

Thanks
Andrew Rogers


Article: 34809
Subject: Re: Orcad Symbol
From: "remi-seglie" <remi-seglie@infonie.fr>
Date: Sat, 8 Sep 2001 22:43:13 +0200
Links: << >>  << T >>  << A >>
test
"Rémi SEGLIE" <remi.seglie@optrantechno.com> wrote in message
news:9mgg8b$16ul$1@news6.isdnet.net...
> Does anybody knows where to find Orcad symbol for Xilinx part ?
>
>



Article: 34810
(removed)


Article: 34811
Subject: Re: Xilinx dev. kit for Linux?
From: Ray Andraka <ray@andraka.com>
Date: Sat, 08 Sep 2001 23:01:41 GMT
Links: << >>  << T >>  << A >>
You need a VHDL synthesis tool plus the Xilinx place and route, which, for
third party front end tools is called Alliance.  I think there is also a
VHDL tool out there called alliance, but I know nothing about it.  You'll
need the xilinx tools at the back end regardless of what you use for the
front end.

Andrew Rogers wrote:

> Is there a development kit for GNU/Linux to take a VHDL file and
> generate the bit stream file for the Xilinx XC3020?
>
> I am still learning VHDL, but before I get to carried away I would like
> to be certain that I can configure the FPGA I have. Is Alliance suitable
> for the entire development process and if so, can anyone point me to a
> good tutorial or example?
>
> Any help is appreciated.
>
> Thanks
> Andrew Rogers

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com



Article: 34812
Subject: Re: To mix frequency with a FPGA
From: Ray Andraka <ray@andraka.com>
Date: Sun, 09 Sep 2001 00:21:18 GMT
Links: << >>  << T >>  << A >>
mixing sound is done by adding.  In this case you need to add two 1 bit
values and then limit the sum to 1 bit.  If you take the square wave as
having values of +/-1 (therefore no DC offset) then you get the
following sum table:

-1  -1    -2
-1 +1     0
+1 -1     0
+1 +1   +2

after scaling the output by 1/2 it is apparent the addition is simply
the exclusive nor of the input waveforms if -1 is represented by 0 and
+1 by 1.


olivier JEAN wrote:

> Hi everybody.
>
> Today I design a AY-3-8192 (sound chip) compatible in FPGA.
> My problem is to mix two frequency to generate one.
>
>  Explain :
>
>   A tone generator generates a square wave form with frequency ft.
>   A noise generator generates a square wave form with frequency fn.
>
>  I must mix 2 square wave form to generate 1 square wave form with
> fm = ft +/- fn.
>
>  My Question is how make it to implement in FPGA ?
>
>   Thank You.
>
>          Best regards.
>
>                  Olivier.

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com



Article: 34813
Subject: Re: Selection of a suitable FPGA board
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Sun, 09 Sep 2001 10:27:30 +0100
Links: << >>  << T >>  << A >>


Ray Andraka wrote:

> Wolfgang Loewer wrote:
>
> > You mentioned 60 MHz and I assume you need PCI @ 33 MHz so the slowest speed
> > grade will probably not be enough.
>
> If you are careful with your design, even the SpartanII in its slowest speed
> grade is
> plenty fast to handle 60 MHz....I have used the slow ones at twice that.  IIRC,
> the virtexE is not compatible with 5v PCI, so you'll either need to restrict to
> 3.3v PCI or use a straight virtex at the PCI interface.
> --

Its possible to use the Virtex-E with 5V PCI if you do one of 2 things:

o Use 100R series resistors between the PCI and the FPGA pins. Xilinx recommend
this but I'm not sure what this does to the PCI spec so if board space and
economics permits ...

o The alternative that I use is to place a bunch of QuickSwitch class buffers in
the PCI paths. You can either use the ``5V'' QS parts with their power pins
Zener'ed down to 3.9V [they actually work at 3.3V] or the 3V parts. But beware that
the 3V parts come in 2 flavours ``clamping'' and ``full-swing''.



Article: 34814
Subject: Alliance: xlmap, XC3020
From: Andrew Rogers <andrew@rogerstech.freeserve.co.uk>
Date: Sun, 09 Sep 2001 12:30:06 +0100
Links: << >>  << T >>  << A >>
I have installed alliance 3.2 for Linux but xlmap is missing.

The man page scmap.1 has a 'see also' entry of xlmap(1). I have searched 
on the internet and can't find it, it is not included with the Alliance 
distribution. Has it been replaced by fpmap or is it a seperate tool?

Has anyone used alliance to target a Xilinx XC3020 or similar? - I need 
a good tutorial or example guidance.

Thanks
Andrew Rogers


Article: 34815
Subject: Re: Xilinx dev. kit for Linux?
From: Duane Clark <junkmail@junkmail.com>
Date: Sun, 09 Sep 2001 08:12:04 -0700
Links: << >>  << T >>  << A >>
Andrew Rogers wrote:

> Is there a development kit for GNU/Linux to take a VHDL file and 
> generate the bit stream file for the Xilinx XC3020?

For Linux, the only synthesis tools available are third party tools. In 
other words, moderately expensive. If on a smaller budget, the best bet 
is to run the Xilinx version of FPGA Express in VMware or something 
similar, though I have given up on FPGA Express for serious work.

The Xilinx place and route tools can be run just fine in command line 
mode in Linux, using Wine. I do this on a regular basis. See:

http://www.polybus.com/xilinx_on_linux.html


-- 
My real email is akamail.com@dclark (or something like that).


Article: 34816
Subject: Re: Selection of a suitable FPGA board
From: Ray Andraka <ray@andraka.com>
Date: Sun, 09 Sep 2001 15:45:43 GMT
Links: << >>  << T >>  << A >>
The resistors work by limiting the input current when 5v is used.  This works fine for
dedicated input.   For bidirectional I/O, you need that series resistor to limit
currents when something else is driving the bus.  On the output side, the guaranteed
high level output from the virtexE is marginal for connection to 5v TTL.  Driving a
marginal high  through a resistor onto a loaded bus is asking for trouble.

I am pretty sure you won't meet 5v PCI specs with a virtexE.  Perhaps Austin Franklin
could add a bit to this discussion.  He's done far more with PCI using FPGAs  than most
of the people on this newsgroup.


Rick Filipkiewicz wrote:

> Ray Andraka wrote:
>
> > Wolfgang Loewer wrote:
> >
> > > You mentioned 60 MHz and I assume you need PCI @ 33 MHz so the slowest speed
> > > grade will probably not be enough.
> >
> > If you are careful with your design, even the SpartanII in its slowest speed
> > grade is
> > plenty fast to handle 60 MHz....I have used the slow ones at twice that.  IIRC,
> > the virtexE is not compatible with 5v PCI, so you'll either need to restrict to
> > 3.3v PCI or use a straight virtex at the PCI interface.
> > --
>
> Its possible to use the Virtex-E with 5V PCI if you do one of 2 things:
>
> o Use 100R series resistors between the PCI and the FPGA pins. Xilinx recommend
> this but I'm not sure what this does to the PCI spec so if board space and
> economics permits ...
>
> o The alternative that I use is to place a bunch of QuickSwitch class buffers in
> the PCI paths. You can either use the ``5V'' QS parts with their power pins
> Zener'ed down to 3.9V [they actually work at 3.3V] or the 3V parts. But beware that
> the 3V parts come in 2 flavours ``clamping'' and ``full-swing''.

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com



Article: 34817
Subject: Re: Alliance: xlmap, XC3020
From: Philip Freidin <philip@fliptronics.com>
Date: Sun, 09 Sep 2001 11:45:16 -0700
Links: << >>  << T >>  << A >>
Current Xilinx software does not support the XC3000 family.
The oldest family of parts that the current software supports
is XC3000A   XC3000L   XC3100A  and   XC3100L  These are
all architecturally different form the XC3000  which is the family
you are trying to use (they are all a minor superset of XC3000) .

The last version of Xilinx software that handled the XC3000
family was the XactStep 5.1/6.1 (cmd line/GUI) version and
they stopped shipping that version about 5  or 6 years ago.

If you are trying to support an existing design with these chips
in it, then you will need to get this old version.

If this is a new design (even just playing around) and you have
some of these chips lying around, you would be far better off
just putting them aside and getting more current products such
as the Spartan or Spartan-II parts. more fun, and current sw
understands them.

Philip

On Sun, 09 Sep 2001 12:30:06 +0100, Andrew Rogers
<andrew@rogerstech.freeserve.co.uk> wrote:

>I have installed alliance 3.2 for Linux but xlmap is missing.
>
>The man page scmap.1 has a 'see also' entry of xlmap(1). I have searched 
>on the internet and can't find it, it is not included with the Alliance 
>distribution. Has it been replaced by fpmap or is it a seperate tool?
>
>Has anyone used alliance to target a Xilinx XC3020 or similar? - I need 
>a good tutorial or example guidance.
>
>Thanks
>Andrew Rogers

Philip Freidin
Fliptronics

Article: 34818
Subject: LVPECL : 75 Ohm Output Circuitry
From: "Simon Gauntlett" <simon.gauntlett@rd.bbc.co.uk>
Date: Mon, 10 Sep 2001 01:13:26 -0700
Links: << >>  << T >>  << A >>
I am using a Virtex 200E to drive a differential LVPECL output pair at 270MHz with a 75 ohm output impedance. When the signal is looked at on a fast scope, there is significant ringing, possibly due to the fast rise time. I have taken the example LVPECL output circuit from the Xilinx datasheet and scaled the values, as they are given for a 50 ohm output impedance, however, the output does not look as smooth as a proprietary SDI line driver chip. What arrangement of circuitry and board layout should I employ to make this output smoother? Has anyone else tried this?

Article: 34819
Subject: Re: Open collector outputs
From: Ben Franchuk <bfranchuk@jetnet.ab.ca>
Date: Mon, 10 Sep 2001 02:27:44 -0600
Links: << >>  << T >>  << A >>
Noddy wrote:
> 
> Hi,
> 
> Can anyone tell me the quickest way to make an output on the Spartan XL
> (3.3V) open collector. I read in the documentation that you can use a
> tri-state buffer, but the method doesn't make sense to me. It says tie the
> tri-state pin to the output, and tie the input to  ground. If the input pin
> is to ground, where doesn my input signal go? To the tri-state pin?

Assuming a active high tri-state enable the inverted output goes
to the tristate enable. Zero is
then fed to the tristate input.The tri-state buffer is disabled
on a logic high output and enabled ONLY on a logic low
output.The buffer then will pull the output low. The pullup
resistor remember provides the high output level. Setting your
output to all 1's will disable output.

tri_enable = enable & ~ input
tri_input  = 0

Ben.
----- 
Standard Disclaimer : 97% speculation 2% bad grammar 1% facts.
"Pre-historic Cpu's" http://www.jetnet.ab.ca/users/bfranchuk
Now with schematics.

Article: 34820
Subject: Re: Actel FPGA glitches
From: paul.mccallion@mkg.com (Paul McCallion)
Date: 10 Sep 2001 01:42:33 -0700
Links: << >>  << T >>  << A >>
They are being driven by combinatorial logic, but are driving flip-flops.

 Ray Andraka <ray@andraka.com> wrote in message news:<3B99677B.4D6262DE@andraka.com>...
> What is driving the outputs?  Are they being driven directly by
> flip-flops (as opposed to combinatorial logic or tristates)?
> 
> Paul McCallion wrote:
> 
> > Hi,
> > Has anyone seen any glitch problems with Actel's A42MX series? I have
> > seen 10nS glitches on outputs for several minutes after power on and
> > with the application of freezer spray to the FPGA.
> >
> > Paul

Article: 34821
Subject: Re: Clock division in Xilinx Vertex-E.
From: "Ulises Hernandez" <ulises@britain.agilent.com>
Date: Mon, 10 Sep 2001 10:57:14 +0100
Links: << >>  << T >>  << A >>
Hello,

This is what I do to divide my clock (in this case using a XC2S200).

In my TOP module (i.e):
-- clk_in INPUT CLOCK
-- clk_dv DIVIDED CLOCK
-- clk_out DES-SKEWED CLOCK
 component ibufg
 port  ( i : in std_logic; o : out std_logic);
 end component;

 component bufg
 port  ( i : in std_logic; o : out std_logic);
 end component;

component clkdll
 port  ( clkin, clkfb, rst               : in  std_logic;
   clk0, clk90, clk180, clk270    : out std_logic;
   clk2x, clkdv, locked               : out std_logic );

   i_ibufg_clk_in : ibufg port map (i => clk_in, o => clk_in_i);

   i_clk_dll : clkdll port map

     clkin => clk_in_i,
     clkfb => clk_out_i,
     rst    => disabled,
     clkdv => clk_dv,
     clk0  => clk_out_d
   );

   i_bufg_clk_out : bufg port map (i => clk_out_d, o => clk_out_i);

   clk_out <= clk_out_i;        --And feedback to DLL

And in my UCF:
INST "i_clk_dll"    CLKDV_DIVIDE = 16;  # 16 in my case.

This works for me.
I hope this helps.
Regards

Ulises Hernandez
ECS Technology Ltd.

"Gyunseog Yang" <gsyang@lycos.co.kr> wrote in message
news:9naaao$hdn$1@news1.kornet.net...
> Hi all,
>
> I want to devide the externally input clock to use as the global clock in
> Xilinx Vertex-E.
> I'm using 'Xilinx Foundation 3.1i with service pack 2' and Synopsys 'FPGA
> Express(version 3.5)'
>
> Basically the clock devision by 2, with duty cycle of 50:50, is completely
> performed and I watched the result through the timing simulation.
>
> BUT, in the case of the clock devision by another(4 or 8), the simulation
> results are the same as the case of division by 2.
>
> Thinking that the default generic properties were not changed, I tried to
> use the generic map command. However it is impossible to synthesis  the
> generic properties.
> At the Xilinx's web, I found that even Xilinx uses the pragmas " --
synopsys
> translate_off " in thier example code using the generics.
>
> What is the best way I can do?
>
> advance thanks.
>
> Below is the part of code;
> -------------------------------------------
> library ieee;
>     use ieee.std_logic_1164.all;
>
> component CLKDLL
> --  generic ( CLKDV_DIVIDE : real);
>     port ( CLKIN   : in  std_ulogic := '0';
>            CLKFB   : in  std_ulogic := '0';
>            RST     : in  std_ulogic := '0';
>            CLK0    : out std_ulogic := '0';
>            CLK90   : out std_ulogic := '0';
>            CLK180  : out std_ulogic := '0';
>            CLK270  : out std_ulogic := '0';
>            CLK2X   : out std_ulogic := '0';
>            CLKDV   : out std_ulogic := '0';
>            LOCKED  : out std_ulogic := '0');
> end component;
>         :
>         :
>         :
> begin
>
> clkpad : IBUFG  port map (I=>CLKIN, O=>CLKIN_w);
> rstpad : IBUF   port map (I=>RESET, O=>RESET_w);
>
> dll_4  : CLKDLL
> --  generic map (CLKDV_DIVIDE=>4.0)
>     port map (CLKIN=>CLKIN_w,   CLKFB=>CLK_int_1x, RST=>RESET_w,
>               CLK0=>clk_int_1x, CLK90=>open, CLK180=>open, CLK270=>open,
>               CLK2X=>open, CLKDV=>CLK_4_dll, LOCKED=>LOCKED_4_dll);
>
> clk_4g : BUFG   port map (I=>CLK_4_dll,   O=>CLK_4_g);
>
> lckpad : OBUF   port map (I=>LOCKED_4_dll, O=>LOCKED);
>
>     CLK_4 <= CLK_4_g;
>
> end structural;
> ---------------------------------
>
>
>
>
>



Article: 34822
Subject: Re: Actel FPGA glitches
From: paul.mccallion@mkg.com (Paul McCallion)
Date: 10 Sep 2001 03:32:58 -0700
Links: << >>  << T >>  << A >>
Yea, the clock seems to be ok. Glitches were removed before from
different outputs, and when the FPGA was recompiled they appeared on
these outputs. The logic however was not changed on these lines.

Article: 34823
Subject: Re: Selection of a suitable FPGA board
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Mon, 10 Sep 2001 11:57:56 +0100
Links: << >>  << T >>  << A >>


Ray Andraka wrote:

> The resistors work by limiting the input current when 5v is used.  This works fine for
> dedicated input.   For bidirectional I/O, you need that series resistor to limit
> currents when something else is driving the bus.  On the output side, the guaranteed
> high level output from the virtexE is marginal for connection to 5v TTL.  Driving a
> marginal high  through a resistor onto a loaded bus is asking for trouble.
>
> I am pretty sure you won't meet 5v PCI specs with a virtexE.  Perhaps Austin Franklin
> could add a bit to this discussion.  He's done far more with PCI using FPGAs  than most
> of the people on this newsgroup.
>
>

You're right, it looks like the high signal spec is v. marginal.

In advance of Austin F. I'm going into our lab tomorrow to both try out a few 5V PCI cards
and have a look at the signal quality on a DSO.


Article: 34824
Subject: Re: Xilinx dev. kit for Linux?
From: Nicolas Matringe <nicolas.matringe@IPricot.com>
Date: Mon, 10 Sep 2001 13:03:22 +0200
Links: << >>  << T >>  << A >>
Ray Andraka a écrit :
> 
> I think there is also a VHDL tool out there called alliance,
> but I know nothing about it.

Hi
It's been developed by a team at the Universite Pierre et Marie Curie,
in Paris but it only supports a subset of VHDL (and no Verilog)

http://www-asim.lip6.fr/alliance.html

-- 
Nicolas MATRINGE           IPricot European Headquarters
Conception electronique    10-12 Avenue de Verdun
Tel +33 1 46 52 53 11      F-92250 LA GARENNE-COLOMBES - FRANCE
Fax +33 1 46 52 53 01      http://www.IPricot.com/



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