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Messages from 34775

Article: 34775
Subject: Re: Missing bits
From: "Noddy" <g9731642@campus.ru.ac.za>
Date: Fri, 7 Sep 2001 10:26:18 +0200
Links: << >>  << T >>  << A >>
Hi Ray,

The first register is in the FPGA. The board clock goes directly into the
FPGA first, and then is distributed to the internal register and the ADC on
an output pin. Am now using a DLL (BUFGDLL primitive). However, I still
appear to be missing one or two bits. Could you also clarify by what you
mean in the FPGA's IOB's on the ADC input having to be registered to? (Sorry
if this seems a basic question, but I'm the only person I know who has even
got close to using an FPGA)

The settling time for the ADC is not really known (the timing diagrams in
the datasheet are almost non-existent!), but it appears that there is always
valid data on the output at every positive clock edge for some time t_v. Can
I be certain that the register will be reading in this same valid data at
the same clock edge?

Thanks very much for your assistance
Regards
Adrian


> If the first register after the ADC is in the FPGA, then you are likely
getting
> nailed by clock skew.  Use the DLL to align the ADC clock and the FPGA's
> internal clock (see the app note).  The FPGA's IOBs on the ADC inputs
should be
> registered too. Check the ADC data sheet carefully, many have a long
settling
> time, which combined with long setup times in the FPGA inputs may spell
> trouble.  At a minimum, (at 35 MHz), you'll need to make sure you do
everything
> you can to minimize the FPGA set-up time.




Article: 34776
Subject: Re: cannot replace 'if' with 'case' ???
From: Thomas Stanka <Thomas.Stanka@de.bosch.com>
Date: Fri, 07 Sep 2001 10:40:46 +0200
Links: << >>  << T >>  << A >>
Harjo Otten wrote:
> if RST = '0' and (S_CH_OE ='1' and conv_integer(A_L) = 1) then
>    D_RD <= D_RX;
> elsif RST = '0' and (S_CH_OE ='1' and conv_integer(A_L) = 2) then
>   D_RD(7 downto 0) <= (RX_RDY, TX_RDY, IRQ_SL, IND, I_IRQ_RX_EN,
> I_IRQ_TX_EN, I_IRQ_SL_EN, I_IRQ_IN_EN);
> else
>    D_RD <= (others => 'Z');
> end if;

If Rst/='0' or S_CH_OE/='1 then D_RD will be 'Z'

> if S_CH_OE = '1' and RST = '0' then
>   case (conv_integer(A_L)) is
>     when 1       =>  D_RD <= D_RX;
>     when 2       =>  D_RD(7 downto 0) <= (RX_RDY, TX_RDY, IRQ_SL, IND,
> I_IRQ_RX_EN, I_IRQ_TX_EN, I_IRQ_SL_EN, I_IRQ_IN_EN);
>     when others  =>  D_RD <= (others => 'Z');
>   end case;
>  end if;

If Rst/='0' or S_CH_OE/='1 then nothing happens

Don't know if thats your problem, but the two parts are clearly
different in behavior.


-- 
Thomas Stanka	    
Bosch SatCom GmbH                         BC/EMD4
D-71522 Backnang      	   Tel. +49 7191 930-1690
Gerberstr. 49             Fax. +49 7191 930-21690      
Zi. 10/528             Thomas.Stanka@de.bosch.com

Article: 34777
Subject: To mix frequency with a FPGA
From: seilebost@aol.com (olivier JEAN)
Date: 7 Sep 2001 02:15:38 -0700
Links: << >>  << T >>  << A >>
Hi everybody.

Today I design a AY-3-8192 (sound chip) compatible in FPGA.
My problem is to mix two frequency to generate one.
 
 Explain :
 
  A tone generator generates a square wave form with frequency ft.
  A noise generator generates a square wave form with frequency fn.

 I must mix 2 square wave form to generate 1 square wave form with 
fm = ft +/- fn.

 My Question is how make it to implement in FPGA ?

  Thank You.

         Best regards.

                 Olivier.

Article: 34778
Subject: FPU core
From: "Andrew Gray" <andrew@tuks.co.za>
Date: Fri, 7 Sep 2001 11:39:06 +0200
Links: << >>  << T >>  << A >>
Hi

Does anyone know of a VHDL Floating point core that is capable of +, -, x,
div, int to FP & FP to int calculations?

Andrew



Article: 34779
Subject: Re: Spartan II configuration
From: Philip Freidin <philip@fliptronics.com>
Date: Fri, 07 Sep 2001 03:17:02 -0700
Links: << >>  << T >>  << A >>

I think you should read:

    http://www.fpga-faq.com/archives/33100.html#33108

On Thu, 06 Sep 2001 16:55:35 GMT, allan@hardware.dk (Allan Pedersen) wrote:
>I having great difficulties configurating a spartan XS15 by
>microprocessor. I'm doing this :
>
>	- I'm using Webfitter freeware.
>	- The XS15 is hardwired to SERIAL SLAVE MODE
>	
>	1. Create bit file with following attributes:
>
>- Use CCLK as startup clk.
>- Done should go high after success configuration (4 CCLK's)
>
>HAVE I FORGOTTEN ANYTHING?
>
>	2. Create MCS file with following att.
>
>- Serial HEX file
>
>	3. Import the HEX file into memory.
>
>- When I dump the memory in a viewer the first bytes look like this:
>	
> FF FF FF FF 55 99 AA 66 0C 00 01 80 00 00 00 E0
>0C 80 06 80 00 00 00 B0 0C 80 04 80 00 01 FC B4
>0C 00 03 80 00 00 00 00 0C 00 01 80 00 00 00 90
>0C 00 04 80 00 00 00 00 0C 00 01 80 00 00 00 80
>0C 00 02 00 0A 00 1A 58 00 48 0C 00 00 00 00 00
>
>wich i think is ok?
>
>
>	4. Then Start configuring.
>
>PROGRAM LOW
>wait
>PROGRAM HIGH
>
>wait for INIT to go HIGH
>
>wait 20 us
>
>read 1 byte from memory
>
>	TX byte with LSB FIRST
>
>repeat until 0x6088 bytes are transmitted
>
>THIS METHODE DOES'NT WORK................. WHY?????
>
>Please Help

Philip Freidin
Fliptronics

Article: 34780
Subject: Actel FPGA glitches
From: paul.mccallion@mkg.com (Paul McCallion)
Date: 7 Sep 2001 04:04:29 -0700
Links: << >>  << T >>  << A >>
Hi,
Has anyone seen any glitch problems with Actel's A42MX series? I have
seen 10nS glitches on outputs for several minutes after power on and
with the application of freezer spray to the FPGA.

Paul

Article: 34781
Subject: Clock division in Xilinx Vertex-E.
From: "Gyunseog Yang" <gsyang@lycos.co.kr>
Date: Fri, 7 Sep 2001 20:23:55 +0900
Links: << >>  << T >>  << A >>
Hi all,

I want to devide the externally input clock to use as the global clock in
Xilinx Vertex-E.
I'm using 'Xilinx Foundation 3.1i with service pack 2' and Synopsys 'FPGA
Express(version 3.5)'

Basically the clock devision by 2, with duty cycle of 50:50, is completely
performed and I watched the result through the timing simulation.

BUT, in the case of the clock devision by another(4 or 8), the simulation
results are the same as the case of division by 2.

Thinking that the default generic properties were not changed, I tried to
use the generic map command. However it is impossible to synthesis  the
generic properties.
At the Xilinx's web, I found that even Xilinx uses the pragmas " -- synopsys
translate_off " in thier example code using the generics.

What is the best way I can do?

advance thanks.

Below is the part of code;
-------------------------------------------
library ieee;
    use ieee.std_logic_1164.all;

component CLKDLL
--  generic ( CLKDV_DIVIDE : real);
    port ( CLKIN   : in  std_ulogic := '0';
           CLKFB   : in  std_ulogic := '0';
           RST     : in  std_ulogic := '0';
           CLK0    : out std_ulogic := '0';
           CLK90   : out std_ulogic := '0';
           CLK180  : out std_ulogic := '0';
           CLK270  : out std_ulogic := '0';
           CLK2X   : out std_ulogic := '0';
           CLKDV   : out std_ulogic := '0';
           LOCKED  : out std_ulogic := '0');
end component;
        :
        :
        :
begin

clkpad : IBUFG  port map (I=>CLKIN, O=>CLKIN_w);
rstpad : IBUF   port map (I=>RESET, O=>RESET_w);

dll_4  : CLKDLL
--  generic map (CLKDV_DIVIDE=>4.0)
    port map (CLKIN=>CLKIN_w,   CLKFB=>CLK_int_1x, RST=>RESET_w,
              CLK0=>clk_int_1x, CLK90=>open, CLK180=>open, CLK270=>open,
              CLK2X=>open, CLKDV=>CLK_4_dll, LOCKED=>LOCKED_4_dll);

clk_4g : BUFG   port map (I=>CLK_4_dll,   O=>CLK_4_g);

lckpad : OBUF   port map (I=>LOCKED_4_dll, O=>LOCKED);

    CLK_4 <= CLK_4_g;

end structural;
---------------------------------






Article: 34782
Subject: Re: Interfacing Verilog and VHDL
From: "Srinivasan Venkataramanan" <svenka3@siliconsystems.co.in>
Date: Fri, 7 Sep 2001 17:19:15 +0530
Links: << >>  << T >>  << A >>
Hi Sanjay,
        Thanks for the update. BTW what is this "set
cv-files-options -t" ? IIRC it is a command for Philips' internal tool
flow manager (tempo flow) - which is not a public utility, so how will
that help Andrew?

Srinivasan

> "Sanjay Kumar Sharma" <sanjaysharma@agere.com> wrote in message
news:3B962FF5.F088C28F@agere.com>
> HI,
Just an update on Srini's mail. NCSIM  is also able to compile and
elaborate mixted VHDL and Verilog **without a shell**. The only thing
you have to do if swithing back and forth between RTL and  GATE level
simulation is to add an option:
set cv-files-options  -t
This option will make sure that you are using the correct
configuration (rtl or gate).
Sanjay Sharma
Agere Systems
System on Chip IC Designer
3G Wireless Mobile Application
Allentown, PA
  --

Srinivasan Venkataramanan
ASIC Design Engineer
Software & Silicon Systems India Pvt. Ltd. (An Intel company)
Bangalore, India (http://www.vlsisrini.com)



Article: 34783
Subject: Re: cannot replace 'if' with 'case' ???
From: "Harjo Otten" <h.otten@rohill.geen.spam.nl>
Date: Fri, 7 Sep 2001 14:46:32 +0200
Links: << >>  << T >>  << A >>
> If Rst/='0' or S_CH_OE/='1 then nothing happens

Of course..... If OE (output enable) = '0' The bus should be left alone, and
in the last case it's still set. Fixed it ! Thank you !!

H.





Article: 34784
Subject: ISE 4.1
From: "David Wright" <dwright@srtorque.com>
Date: Fri, 07 Sep 2001 13:22:08 GMT
Links: << >>  << T >>  << A >>
Xilinx's ISE 4.1 sounds promising.  After talking to my local Xilinx
representative, it should be available shortly.  My current project is 2300
lines of untested VHDL code including a small test vector.  The WebPack has
a limit of 500 lines.

I was assured the ISE 4.1 was all that I might need to do my design.
However,  I am skeptical as to the adequacy of the simulator.  As I learned
from past experience with Cypress and Altera, test and verification are of
key importance to a design.





Article: 34785
Subject: Re: strange behaviour of LPM_FIFO_DC in altera 10k130e
From: Russell Shaw <rjshaw@iprimus.com.au>
Date: Fri, 07 Sep 2001 23:37:13 +1000
Links: << >>  << T >>  << A >>
You can get some extra details on lpm_fifo_dc operation by looking
at C:\maxplus2\max2lib\mega_lpm\lpm_fifo_dc.tdf. This is ahdl which
uses C:\maxplus2\max2lib\mega_lpm\dcfifo.tdf (has some notes on
operation in it). Also, look in the maxplus-ii help file on lpm_fifo.
It shows some waveforms the other help-files don't have.

Tony Proudfoot wrote:
> 
> Does anyone else have practical experience using an LPM_FIFO_DC in an Altera
> 10k130e device ?
> I have measured some very strange behaviour with this fifo and I can't
> figure it out.
> I am using two seperate clock domains to write and read the fifo.
> The behaviour goes like this;
> Fifo empty flag on the read side is logic 1, thus fifo is empty.
> I clock one qword into the fifo, using the wrreq signal on the write.
> Some clocks later (~6), the empty flag on the read side goes to logic 0.
> I assert rdreq on the read side and the qword emerges from the fifo. Hurrah.
> 
> Now the bit thats killing me.
> Everything same as above, except when I assert rdreq the qword does NOT
> emerge from the fifo. If I assert rdreq again, the qword emerges.
> 
> Does anyone know why this is happening ?
> Are there known 'gotchas' interfacing to these fifos ?
> 
> Any help, hints or tips are much appreciated,
> regards
> Tony.
> --
>  _________________________________
>  Tony Proudfoot, tonyp@vl.com.au
>  Hardware Design Engineer
>  Virtual Logic Pty Ltd
>  Ph: +61(0)2 9599 3255
>  _________________________________

--
   ___                                           ___
  /  /\                                         /  /\
 /  /__\ Russell Shaw, B.Eng, M.Eng(Research)  /  /\/\
/__/   / Victoria, Australia, Down-Under      /__/\/\/
\  \  /  http://home.iprimus.com.au/rjshaw    \  \/\/
 \__\/                                         \__\/

Article: 34786
Subject: Re: ISE 4.1
From: "John Moore" <johnmoore@iee.org>
Date: Fri, 7 Sep 2001 14:53:56 +0100
Links: << >>  << T >>  << A >>
> representative, it should be available shortly.  My current project is
2300
> lines of untested VHDL code including a small test vector.  The WebPack
has
> a limit of 500 lines.
>
I have just completed a project of a similar size using the Xilinx Webpack,
and did not see any limitation on size. The Modelsim simulator complains
about the size, but it works!

John Moore




Article: 34787
Subject: Re: Selection of a suitable FPGA board
From: Joey Oravec <joey@sun.science.wayne.edu>
Date: 7 Sep 2001 14:40:23 GMT
Links: << >>  << T >>  << A >>
Andreas Kugel <kugel@ti.uni-mannheim.de> wrote:
:>   Can anyone guide me in selecting a FPGA board meeting the following
:> requirements?
:>   1)We require to operate at 60MHz and need a PCI interface on 1 side (we
:> have our own PCI core)
:>   2)I think the size of our design is such that it will fit into an APEX1000
:> or a Xilinx VirtexE XCV2000
:
: Anything else you need ? Memory ? I/O connectors ?

The DINI group has a PCI board for around $4k which doesn't meet the $2k
constraint, but isn't too far off. Maybe they have something even cheaper,
ya never know

http://www.dinigroup.com/products/2000k10.html

-- 
  O..O    Arcade machine collection:
 (----)        http://www.science.wayne.edu/~joey/arcade/
( >__< )  IRC - EFNet #rgvac: demigod2k
^^ ~~ ^^

Article: 34788
Subject: Re: FPU core
From: "Mirek Klaczek" <mirfot@polbox.com>
Date: Fri, 7 Sep 2001 17:38:08 +0200
Links: << >>  << T >>  << A >>
> Hi
>
> Does anyone know of a VHDL Floating point core that is capable of +, -, x,
> div, int to FP & FP to int calculations?
>
> Andrew
>

Please check:
http://www.dcd.com.pl/english/dfpau.htm


Mirek



Article: 34789
(removed)


Article: 34790
Subject: Re: Virtex Architecture: Interconnect
From: Dereck <dereckaf@yahoo.com>
Date: Fri, 7 Sep 2001 10:13:46 -0700
Links: << >>  << T >>  << A >>
Hi,
I have some questions on Virtex Interconnect,

1. For the Local CLB routing. Does there exist between 2 CLBs to the East and west 2 lines each. for direct connection.
2. HOw many lines does the CLB use to connect to the
GRM. 
3. How many feedback lines are present.
4. Are the lines from the Output MUX multiplexed with
the lines that go to the input MUX (Which come from
the GRM). Are they multiplexed with the feedback lines
and the direct lines that go to the next CLB.
5. Do CLBs have access to Dedicated routing.
6. I don't have the Xilinx tools, can you send me a
snap shot of the interconnect as it looks from the
FPGA editor.
7. Does the CLB have access to GLobal routing.
I know that this is a very complex routing structure.
I was trying to understand how it exists.

Thanks 
Dereck

Article: 34791
Subject: Virtex: Interconnect Structure
From: Dereck <dereckaf@yahoo.com>
Date: Fri, 7 Sep 2001 13:35:04 -0700
Links: << >>  << T >>  << A >>
Hi 
Let me confirm this,
In a Virtex Tile,

1. Intra CLB routing 2 direct paths to horizontally adjacent CLBs.
Are they Output MUX(CLB1) to Input MUX(CLB2) connections. 

2. General Purpose routing

24 single length wires to adjacent GRMs each in 4 directions.
72 buffered hex wires to GRMs 6 blocks away in 4 directions.
So 72/4 = 18 wires in each direction.

4 * 4 LUTs inputs = 16 lines + 2 * 5 auxillary inputs
= 26 lines from GRM to CLB.

???? Number of Feedback lines.
???? Number of Output lines from CLB to GRM 

3. Global Routing
12 Long lines : 2 connected to each GRM at multiples of 6rows/coloumns

4. Dedicated Routing

24 backbone lines : 12 on top and 12 at the bottom.
4 Horizontal pseudo tri-state busses per CLB row.
How do they affect the GRM or CLB

Thanks,
Dereck

Article: 34792
Subject: Spartan II use of GCK[0:3] pins as general inputs
From: Dave Colson <dscolson@rcn.com>
Date: Fri, 07 Sep 2001 19:56:53 -0400
Links: << >>  << T >>  << A >>
Hello,
Can the GCK pins on the Spartan II be use for general inputs
if not used for clocks input?

I get an error when I try to use pin 185 as a normal input signal

Thanks

David Colson


Article: 34793
Subject: Re: Actel FPGA glitches
From: Ray Andraka <ray@andraka.com>
Date: Sat, 08 Sep 2001 00:31:07 GMT
Links: << >>  << T >>  << A >>
What is driving the outputs?  Are they being driven directly by
flip-flops (as opposed to combinatorial logic or tristates)?

Paul McCallion wrote:

> Hi,
> Has anyone seen any glitch problems with Actel's A42MX series? I have
> seen 10nS glitches on outputs for several minutes after power on and
> with the application of freezer spray to the FPGA.
>
> Paul

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com



Article: 34794
(removed)


Article: 34795
Subject: Re: Clock division in Xilinx Vertex-E.
From: Ray Andraka <ray@andraka.com>
Date: Sat, 08 Sep 2001 00:34:48 GMT
Links: << >>  << T >>  << A >>
The generics are only used by the simulator.  If you tried to synthesize without
the translate off's the synthesizer would complain, as it does not know how to
apply generics to a black box (the primitives are all black-boxed).  You need to
set up user attributes on the instantiated clock DLL to get the keywords into
the edif netlist, or you can put them in the ucf file.

Gyunseog Yang wrote:

> Hi all,
>
> I want to devide the externally input clock to use as the global clock in
> Xilinx Vertex-E.
> I'm using 'Xilinx Foundation 3.1i with service pack 2' and Synopsys 'FPGA
> Express(version 3.5)'
>
> Basically the clock devision by 2, with duty cycle of 50:50, is completely
> performed and I watched the result through the timing simulation.
>
> BUT, in the case of the clock devision by another(4 or 8), the simulation
> results are the same as the case of division by 2.
>
> Thinking that the default generic properties were not changed, I tried to
> use the generic map command. However it is impossible to synthesis  the
> generic properties.
> At the Xilinx's web, I found that even Xilinx uses the pragmas " -- synopsys
> translate_off " in thier example code using the generics.
>
> What is the best way I can do?
>
> advance thanks.
>
> Below is the part of code;
> -------------------------------------------
> library ieee;
>     use ieee.std_logic_1164.all;
>
> component CLKDLL
> --  generic ( CLKDV_DIVIDE : real);
>     port ( CLKIN   : in  std_ulogic := '0';
>            CLKFB   : in  std_ulogic := '0';
>            RST     : in  std_ulogic := '0';
>            CLK0    : out std_ulogic := '0';
>            CLK90   : out std_ulogic := '0';
>            CLK180  : out std_ulogic := '0';
>            CLK270  : out std_ulogic := '0';
>            CLK2X   : out std_ulogic := '0';
>            CLKDV   : out std_ulogic := '0';
>            LOCKED  : out std_ulogic := '0');
> end component;
>         :
>         :
>         :
> begin
>
> clkpad : IBUFG  port map (I=>CLKIN, O=>CLKIN_w);
> rstpad : IBUF   port map (I=>RESET, O=>RESET_w);
>
> dll_4  : CLKDLL
> --  generic map (CLKDV_DIVIDE=>4.0)
>     port map (CLKIN=>CLKIN_w,   CLKFB=>CLK_int_1x, RST=>RESET_w,
>               CLK0=>clk_int_1x, CLK90=>open, CLK180=>open, CLK270=>open,
>               CLK2X=>open, CLKDV=>CLK_4_dll, LOCKED=>LOCKED_4_dll);
>
> clk_4g : BUFG   port map (I=>CLK_4_dll,   O=>CLK_4_g);
>
> lckpad : OBUF   port map (I=>LOCKED_4_dll, O=>LOCKED);
>
>     CLK_4 <= CLK_4_g;
>
> end structural;
> ---------------------------------

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com



Article: 34796
Subject: Re: Missing bits
From: Ray Andraka <ray@andraka.com>
Date: Sat, 08 Sep 2001 00:47:14 GMT
Links: << >>  << T >>  << A >>
The IOB cells in the FPGA have flip-flops in them, but unless you are careful
your design may not be using them.  When these are used, the set-up time to the
flip-flop in the design is quite deterministic, and is the smallest possible
value.  If your signal does not get registered in the IOB, then there is a
routing delay associated with getting the signal inside the FPGA where it
eventually hits a flip-flop.  It sounds like that is the case in your design.
What happens then, of course, is that the signal takes too long to get into the
chip and you have a timing problem.

To register the IO, you need to set "Pack I/O registers/latches into IOBs" to
include the inputs (I believe it defaults to none).   You'll find it under the
optimize and map tab in the edit implementation options dialog box.  When that
is set, any registers on input signals that meet a set of rules will be
implemented in the IOB.  The rules require that the signal go to only one
register and that the signal passes through no logic (inverter is OK, but that's
it) before it gets to that register.  Violate either of these, and the register
can't get absorbed in the IOB.  (The IOB is the I/O logic cell, as opposed to
the CLBs which are in the FPGA's interior).

Noddy wrote:

> Hi Ray,
>
> The first register is in the FPGA. The board clock goes directly into the
> FPGA first, and then is distributed to the internal register and the ADC on
> an output pin. Am now using a DLL (BUFGDLL primitive). However, I still
> appear to be missing one or two bits. Could you also clarify by what you
> mean in the FPGA's IOB's on the ADC input having to be registered to? (Sorry
> if this seems a basic question, but I'm the only person I know who has even
> got close to using an FPGA)
>
> The settling time for the ADC is not really known (the timing diagrams in
> the datasheet are almost non-existent!), but it appears that there is always
> valid data on the output at every positive clock edge for some time t_v. Can
> I be certain that the register will be reading in this same valid data at
> the same clock edge?
>
> Thanks very much for your assistance
> Regards
> Adrian
>
> > If the first register after the ADC is in the FPGA, then you are likely
> getting
> > nailed by clock skew.  Use the DLL to align the ADC clock and the FPGA's
> > internal clock (see the app note).  The FPGA's IOBs on the ADC inputs
> should be
> > registered too. Check the ADC data sheet carefully, many have a long
> settling
> > time, which combined with long setup times in the FPGA inputs may spell
> > trouble.  At a minimum, (at 35 MHz), you'll need to make sure you do
> everything
> > you can to minimize the FPGA set-up time.

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com



Article: 34797
Subject: Re: Selection of a suitable FPGA board
From: Ray Andraka <ray@andraka.com>
Date: Sat, 08 Sep 2001 00:54:31 GMT
Links: << >>  << T >>  << A >>


Wolfgang Loewer wrote:

> You mentioned 60 MHz and I assume you need PCI @ 33 MHz so the slowest speed
> grade will probably not be enough.

If you are careful with your design, even the SpartanII in its slowest speed
grade is
plenty fast to handle 60 MHz....I have used the slow ones at twice that.  IIRC,
the virtexE is not compatible with 5v PCI, so you'll either need to restrict to
3.3v PCI or use a straight virtex at the PCI interface.
--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com



Article: 34798
Subject: Re: Clock division in Xilinx Vertex-E.
From: "Gyunseog Yang" <gsyang@lycos.co.kr>
Date: Sat, 8 Sep 2001 10:47:28 +0900
Links: << >>  << T >>  << A >>
"Ray Andraka" <ray@andraka.com> wrote in message
news:3B996858.5BD497AB@andraka.com...
> The generics are only used by the simulator.  If you tried to synthesize
without
> the translate off's the synthesizer would complain, as it does not know
how to
> apply generics to a black box (the primitives are all black-boxed).  You
need to
> set up user attributes on the instantiated clock DLL to get the keywords
into
> the edif netlist, or you can put them in the ucf file.
>

Thank you Ray,

Unfortunately I have no idea how setup my attributes on the instantiated
clock DLL, and couldn't find any place to inform about it.

I couldn't get any information from my edif file and ucf file, too.

Would please introduce the skill a little?

Regards.

Below is a part of my edif file:
------------------------------------
(edif  dll_standard
     :
     :
  (external VIRTEXE
     :
     :
    (cell CLKDLL
      (cellType GENERIC)
      (view Netlist_representation
 (viewType NETLIST)
 (interface
   (port CLK0
     (direction OUTPUT)
   )
   (port CLK90
     (direction OUTPUT)
   )
     :
     :
  (library DESIGNS
    (edifLevel 0)
    (technology
      (numberDefinition)
     :
     :
   (instance dll_16
     (viewRef Netlist_representation
       (cellRef CLKDLL
  (libraryRef VIRTEXE)
       )
     )
   )
     :
     :
    (property PART
      (string "V300E-PQ240-8")
    )
  )
)




Article: 34799
Subject: Re: Clock division in Xilinx Vertex-E.
From: Ray Andraka <ray@andraka.com>
Date: Sat, 08 Sep 2001 03:57:29 GMT
Links: << >>  << T >>  << A >>
If your synthesis tool permits user attributes then:

attribute CLKDV_DIVIDE: string;
attribute CLKDV_DIVIDE of U1: label is "1.5";

begin
U1 : CLKDLL port map(
CLKIN => CLK,
RST => RST,
CLKFB => CLKFB,
CLK0 => a,
CLK90 => b,
CLK180 => c,
CLK270 => d,
CLKDV => e,
CLK2x => f,
LOCKED => lock);

If you do a search    CLKDLL attribute  on the xilinx website you will get
several answer records that describe this.
The attributes are necessary to pass the non-default values through the
synthesis, the generics are needed to get them into the
behavioral synthesis model.



Gyunseog Yang wrote:

> "Ray Andraka" <ray@andraka.com> wrote in message
> news:3B996858.5BD497AB@andraka.com...
> > The generics are only used by the simulator.  If you tried to synthesize
> without
> > the translate off's the synthesizer would complain, as it does not know
> how to
> > apply generics to a black box (the primitives are all black-boxed).  You
> need to
> > set up user attributes on the instantiated clock DLL to get the keywords
> into
> > the edif netlist, or you can put them in the ucf file.
> >
>
> Thank you Ray,
>
> Unfortunately I have no idea how setup my attributes on the instantiated
> clock DLL, and couldn't find any place to inform about it.
>
> I couldn't get any information from my edif file and ucf file, too.
>
> Would please introduce the skill a little?
>
> Regards.
>
> Below is a part of my edif file:
> ------------------------------------
> (edif  dll_standard
>      :
>      :
>   (external VIRTEXE
>      :
>      :
>     (cell CLKDLL
>       (cellType GENERIC)
>       (view Netlist_representation
>  (viewType NETLIST)
>  (interface
>    (port CLK0
>      (direction OUTPUT)
>    )
>    (port CLK90
>      (direction OUTPUT)
>    )
>      :
>      :
>   (library DESIGNS
>     (edifLevel 0)
>     (technology
>       (numberDefinition)
>      :
>      :
>    (instance dll_16
>      (viewRef Netlist_representation
>        (cellRef CLKDLL
>   (libraryRef VIRTEXE)
>        )
>      )
>    )
>      :
>      :
>     (property PART
>       (string "V300E-PQ240-8")
>     )
>   )
> )

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com





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