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Messages from 34725

Article: 34725
Subject: Re: Looking for a synthesizable JPEG coder core
From: "Vincenzo Liguori" <enzo@nospam.com>
Date: Wed, 05 Sep 2001 10:59:35 GMT
Links: << >>  << T >>  << A >>

"KJ" <Kevin.Jennings@Unisys.com> wrote in message
news:9me37g$on4$1@mail.pl.unisys.com...
> - Grayscale (8 bit) video input
> - Compression only, baseline lossy JPEG (ISP/IEC 10918-1) only required
> - VHDL or Verilog
> - Planning on targetting an FPGA

Try to contact inSilicon Corporation (http://www.insilicon.com). They
acquired our JPEG
core a few months ago.
It has been proved in silicon various times including by ST
Microelectronics.
At least on of our customers had also a FPGA implementation. A FPGA demo
board
used to be available.

>
> Thanks in advance
>
>

Regards,
Enzo

------------------------------------------------------------------
Vincenzo Liguori
Ocean Logic Pty Ltd
PO BOX 768
Manly NSW 1655
Australia

Ph : +61-2-99054152
Fax : +61-2-99050921
WWW : http://www.ocean-logic.com




Article: 34726
Subject: Re: WebPack Con-Game
From: "David Wright" <dwright@srtorque.com>
Date: Wed, 05 Sep 2001 12:50:46 GMT
Links: << >>  << T >>  << A >>
False advertising is unlawful.

Eric Smith wrote in message ...
>"David Wright" <dwright@srtorque.com> writes:
>> The "free" Xilinix Webpack should be classified as a Demo and not a real
>> system to do even realistic small designs.
>
>You get what you pay for.  Naturally the free package provides less
>functionality than the expensive package; how can you rationally expect
>otherwise?  Calling it a "con game" seems entirely uncalled for; the
>features and limitations of WebPack are plainly described on the web site.
>
>I've found it to be perfectly usable for a design with a 32-bit RISC
>core, memory, UART, Ethernet, and timers.  I did my simulation using
>Savant.
>



Article: 34727
Subject: Re: Special counter for scheduling
From: hamish@cloud.net.au
Date: Wed, 05 Sep 2001 13:17:54 GMT
Links: << >>  << T >>  << A >>
Michael Boehnel <boehnel@iti.tu-graz.ac.at> wrote:
> This is very brute force.
> Are there any suggestions for a better (at least more general - with
> "for" or so) implementation than mine?
> Is this a standard counter described somewhere in literature (name?
> references?)

If you only need 4 bits (16 values), wouldn't it be simpler to
just code a case statement with the next value for each possible
current value?

eg

     case current is
         when 1 =>
             next := 2;
         when 2 | 3 | 4 => 
             next := 5;

     ...

Or even better, perhaps an array mapping from current to next eg

type map_type is array(0 to 15) of natural;
constant next_map: map_type := (0, 1, 5, 5, 5, ....);

Then next := next_map(current);.


Hamish
-- 
Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>

Article: 34728
Subject: Re: Interfacing Verilog and VHDL
From: "Srinivasan Venkataramanan" <svenka3@siliconsystems.co.in>
Date: Wed, 5 Sep 2001 19:15:46 +0530
Links: << >>  << T >>  << A >>
Hi,
    If your tool set supports it, it is straight forward, just declare
the component in  VHDL as if you had this component in VHDL and
instantiate it. Now linking this VHDL "component" to a Verilog
"module" is kind of simulator dependent. Modelsim takes it cool, just
compile VHDL with vcom and Verilog with vlog - the rest will be done
by vsim for you (provided you have the same port names etc.). NC tools
used to have some issues with this - they needed a "shell" around
Verilog (as Johan explained). Better check their manuals for the
latest.

HTH,
Srini


--
Srinivasan Venkataramanan
ASIC Design Engineer
Software & Silicon Systems India Pvt. Ltd. (An Intel company)
Bangalore, India (http://www.vlsisrini.com)


"Andrew Gray" <andrew@tuks.co.za> wrote in message
news:999585905.440006@nntp.up.ac.za...
> Hi
>
> I downloaded a floating point arithmetic core from opencores.org.
The core
> is written in verilog. I have never used verilog before, how can I
implement
> it into a VHDL design. Do I incorporate it as a component and then
use port
> mapping as in VHDL?
>
> Does anyone have any examples on how to do this?
>

  See your tool's manual(s)

> Thanks
>
> Andrew :-)
>
>



Article: 34729
Subject: DLL locks with no clock present
From: Graham
Date: Wed, 05 Sep 2001 13:57:25 GMT
Links: << >>  << T >>  << A >>
My design has two clocks and hence i use two seperate DLLs within the
virtex xcv300 architecture.

Clock 1 
has no frequency division or multiplication  and the clock is present
on the GClk input before configuration is complete. If i switch the
external clock generator off and then on again, the DLL locks once
again to the clock

Clock 2
The clock output is divided by 2 , However is not present on the GClk
input until some 40 ms after configuration has completed. 
This time if the external clock generator is switched off and then on
again, the DLL does NOT  lock, and the DLL exibits a Logic high level
i.e 3.3V

I took the DLL  LOCKED output to an external test point on my board
and it was a logic high saying it was Locked. At not time does the
LOCKED output go low

Must all clocks be present on the GClk inputs before configuration ?


Graeme

Article: 34730
Subject: Re: Interfacing Verilog and VHDL
From: Sanjay Kumar Sharma <sanjaysharma@agere.com>
Date: Wed, 05 Sep 2001 10:00:21 -0400
Links: << >>  << T >>  << A >>


HI,
Just an update on Srini's mail. NCSIM  is also able to compile and
elaborate mixted VHDL and Verilog **without a shell**. The only thing you
have to do if swithing back and forth between RTL and  GATE level
simulation is to add an option:
set cv-files-options  -t
This option will make sure that you are using the correct configuration
(rtl or gate).

Sanjay Sharma

Agere Systems
System on Chip IC Designer
3G Wireless Mobile Application
Allentown, PA


Srinivasan Venkataramanan wrote:

> Hi,
>     If your tool set supports it, it is straight forward, just declare
> the component in  VHDL as if you had this component in VHDL and
> instantiate it. Now linking this VHDL "component" to a Verilog
> "module" is kind of simulator dependent. Modelsim takes it cool, just
> compile VHDL with vcom and Verilog with vlog - the rest will be done
> by vsim for you (provided you have the same port names etc.). NC tools
> used to have some issues with this - they needed a "shell" around
> Verilog (as Johan explained). Better check their manuals for the
> latest.
>
> HTH,
> Srini
>
> --
> Srinivasan Venkataramanan
> ASIC Design Engineer
> Software & Silicon Systems India Pvt. Ltd. (An Intel company)
> Bangalore, India (http://www.vlsisrini.com)
>
> "Andrew Gray" <andrew@tuks.co.za> wrote in message
> news:999585905.440006@nntp.up.ac.za...
> > Hi
> >
> > I downloaded a floating point arithmetic core from opencores.org.
> The core
> > is written in verilog. I have never used verilog before, how can I
> implement
> > it into a VHDL design. Do I incorporate it as a component and then
> use port
> > mapping as in VHDL?
> >
> > Does anyone have any examples on how to do this?
> >
>
>   See your tool's manual(s)
>
> > Thanks
> >
> > Andrew :-)
> >
> >

--
Sanjay Kumar Sharma
Agere Systems
System on Chip IC Designer
3G Wireless Moblie Appliances






Article: 34731
Subject: Re: LPM_FIFO_DC
From: lyqin@cti.com.cn (Leon Qin)
Date: 5 Sep 2001 07:05:31 -0700
Links: << >>  << T >>  << A >>
martin.j.thompson@trw.com wrote in message news:<usne2hwwa.fsf@trw.com>...
> martin.j.thompson@trw.com writes:
> 
> > lyqin@cti.com.cn (Leon Qin) writes:
> > 
> > > When I implement a Duol Clock Fifo in an EPF10k10 chip. I found the
> > >signal RDEmpty,rdusedw are strange from common SysncFifo(For instance
> > >:CY7C4265).  RDEmpty turn to right('0') after a long time !!!!!!
> > > 
> > 
>  <snip>
> > On the other hand, the Cypress part you mentioned is an
> > asynchronous part 
> <snip>
> 
> And now I've read the whole page (not just the part of the line that
> says 'fully asynchronous...' - I didn't read the bit that continues
> '... read and write operation'), I've seen the block diagram that
> shows the clock pins!  Sorry about that!
> 
> In which case, the LPM_DC_FIFO sounds like the part you need to use,
> there are parameters you can tweks to affect the latency of the flag
> signals.  Let me know if you want more guidance.
> 
> Cheers,
> Martin

 I need move data from one port to another port which hao a diffrent clock.
Both clock are diffrent  freq( both about 27MHz) and phase.
  I found the RDempty delay has more 3 period (about 8).

Article: 34732
Subject: Re: Special counter for scheduling
From: Michael Boehnel <boehnel@iti.tu-graz.ac.at>
Date: Wed, 05 Sep 2001 16:24:36 +0200
Links: << >>  << T >>  << A >>
hamish@cloud.net.au wrote:

> Michael Boehnel <boehnel@iti.tu-graz.ac.at> wrote:
> > This is very brute force.
> > Are there any suggestions for a better (at least more general - with
> > "for" or so) implementation than mine?
> > Is this a standard counter described somewhere in literature (name?
> > references?)
>
> If you only need 4 bits (16 values), wouldn't it be simpler to
> just code a case statement with the next value for each possible
> current value?

Hi, Hamish!

Thank you for your suggestion.

I think your solution doesn't take the Marker-array in account. Marker
isn't fixed! It changes during operation. And so the count sequence
changes dynamically.

Michael


Article: 34733
Subject: Re: Special counter for scheduling
From: "Ulf Samuelsson" <ulf@atmel.dot.com>
Date: Wed, 5 Sep 2001 16:28:12 +0200
Links: << >>  << T >>  << A >>
Looks to me like a two stage approach.
Create two bit vectors of the same size.
In the first, clear all values which are equal or lower than the current
counter
In the second, clear all values which are higher than the current counter.
Do a FIND FIRST SET function on both vectors.
If any bit present within the first vector, load the counter with that value
else if any bit present in the second vector, load the counter with that
value
else keep counter value.

--
Best regards,
ulf at atmel dot com
The contents of this message is intended to be my private opinion and
may or may not be shared by my employer Atmel Sweden

"Michael Boehnel" <boehnel@iti.tu-graz.ac.at> skrev i meddelandet
news:3B95F0B5.22E65CB0@iti.tu-graz.ac.at...
> For scheduling I'd like to implement a special counter:
>
> The counter has an extra input "Marked" of type STD_LOGIC_VECTOR(N-1
> downto 0). The counter jumps to the next value with Marked(i)='1'. E.g.:
> Actual Counter=2,  Marked(2,3,4,6,7)='0' , Marked(1,5)='1',   => Next
> actual counter := 5
>
> I plan to implement the counter for a fixed count length of 4 bit. At
> the moment my approach looks like follows:
>
> In a case statement I differentiate the actual counter value. Within the
> case I make a series of if statements:
>
> case Counter of
>   '0'
>
>       if Marked(1) then Counter:=1 else
>         if Marked(2) then Counter:= 2 else
>
>           if Marked(0) then Counter:=..0
>           else Counter:=0;
>  '1'
>      if Marked(2) then Counter:=2; else
>      if Marked(3) then Counter:=3; else
>     :
>
> This is very brute force.
> Are there any suggestions for a better (at least more general - with
> "for" or so) implementation than mine?
> Is this a standard counter described somewhere in literature (name?
> references?)
>
> Michael
>
>



Article: 34734
Subject: Re: Interfacing Verilog and VHDL
From: "Andrew Gray" <andrew@tuks.co.za>
Date: Wed, 5 Sep 2001 17:04:41 +0200
Links: << >>  << T >>  << A >>
Thanks, I will try that.

I want to simulate the project on modelsim using a testbench, your method
should work well.
Will maxplus or Leonardo Spectrum be able to synthesise it, or will I need
to use a shell for the synthesis?

Thanks

Andrew

"Srinivasan Venkataramanan" <svenka3@siliconsystems.co.in> wrote in message
news:9n5a90$72l@news.or.intel.com...
> Hi,
>     If your tool set supports it, it is straight forward, just declare
> the component in  VHDL as if you had this component in VHDL and
> instantiate it. Now linking this VHDL "component" to a Verilog
> "module" is kind of simulator dependent. Modelsim takes it cool, just
> compile VHDL with vcom and Verilog with vlog - the rest will be done
> by vsim for you (provided you have the same port names etc.). NC tools
> used to have some issues with this - they needed a "shell" around
> Verilog (as Johan explained). Better check their manuals for the
> latest.
>
> HTH,
> Srini
>
>
> --
> Srinivasan Venkataramanan
> ASIC Design Engineer
> Software & Silicon Systems India Pvt. Ltd. (An Intel company)
> Bangalore, India (http://www.vlsisrini.com)
>
>
> "Andrew Gray" <andrew@tuks.co.za> wrote in message
> news:999585905.440006@nntp.up.ac.za...
> > Hi
> >
> > I downloaded a floating point arithmetic core from opencores.org.
> The core
> > is written in verilog. I have never used verilog before, how can I
> implement
> > it into a VHDL design. Do I incorporate it as a component and then
> use port
> > mapping as in VHDL?
> >
> > Does anyone have any examples on how to do this?
> >
>
>   See your tool's manual(s)
>
> > Thanks
> >
> > Andrew :-)
> >
> >
>
>



Article: 34735
Subject: Re: Virtex II sizing rule of thumb
From: jennifer.koehler@exchange.sp.trw.com (Jen)
Date: 5 Sep 2001 11:08:46 -0700
Links: << >>  << T >>  << A >>
I guess what I was really looking for was what other people have seen
in there designs.  I know it depends primarily on your
design(obviously if I use a lot of FIFOs I will use more regs)..but
usually with FPGAs there is some warm fuzzy guestimate of what
percentage of LUTs and FFs are used..that tends to be true across
designs.

Article: 34736
Subject: Xilinx design flow
From: Noelia <paulanm@usc.es>
Date: Wed, 5 Sep 2001 11:40:45 -0700
Links: << >>  << T >>  << A >>
Hello,

I have my VHDL code and I want to
map it to a FPGA. I have used the Synopsys tools to compile, to 
simulate and to synthetize my design. However, I want
to know if I can do all the design
flow using the Xilinx tools. That is, a Xilinx compiler, a Xilinx simulator, a Xilinx synthetizer. 
If it is possible, which tools I need?

Thanks and kind regards.

Article: 34737
Subject: Re: WebPack Con-Game
From: Eric Smith <eric-no-spam-for-me@brouhaha.com>
Date: 05 Sep 2001 12:51:44 -0700
Links: << >>  << T >>  << A >>
"David Wright" <dwright@srtorque.com> writes:
> The "free" Xilinix Webpack should be classified as a Demo and not a real
> system to do even realistic small designs.

I wrote:
> You get what you pay for.  Naturally the free package provides less
> functionality than the expensive package; how can you rationally expect
> otherwise?  Calling it a "con game" seems entirely uncalled for; the
> features and limitations of WebPack are plainly described on the web site.
>
> I've found it to be perfectly usable for a design with a 32-bit RISC
> core, memory, UART, Ethernet, and timers.  I did my simulation using
> Savant.

"David Wright" <dwright@srtorque.com> writes:
> False advertising is unlawful.

True, but irrelevant.

You still haven't explained what false claims you believe they've made.
The WebPack software seems to me to do everything they said it would.
If you're so convinced that they have used false advertising, you should
either:

1)  Convince them that they've screwed up, and get them to give you a
    copy of the "real" software.

2)  Sue them.

Article: 34738
Subject: Re: DLL locks with no clock present
From: Andreas Kugel <kugel@ti.uni-mannheim.de>
Date: Wed, 05 Sep 2001 22:57:41 +0200
Links: << >>  << T >>  << A >>


HI.

Minimum frequency for a DLL to lock is 15MHz (experience, spec is 25). If
your clock is not in range from the beginning you must reset the DLL
(there is a pin for that. YOu can connect it to a pin or an internal
resource).

Andreas


Graham schrieb:

> My design has two clocks and hence i use two seperate DLLs within the
> virtex xcv300 architecture.
>
> Clock 1
> has no frequency division or multiplication  and the clock is present
> on the GClk input before configuration is complete. If i switch the
> external clock generator off and then on again, the DLL locks once
> again to the clock
>
> Clock 2
> The clock output is divided by 2 , However is not present on the GClk
> input until some 40 ms after configuration has completed.
> This time if the external clock generator is switched off and then on
> again, the DLL does NOT  lock, and the DLL exibits a Logic high level
> i.e 3.3V
>
> I took the DLL  LOCKED output to an external test point on my board
> and it was a logic high saying it was Locked. At not time does the
> LOCKED output go low
>
> Must all clocks be present on the GClk inputs before configuration ?
>
> Graeme

--
Andreas Kugel - University of Mannheim - Dept. of Computer Science V
FPGA-Processor Group
B6,23-29/A - 68131 Mannheim - Germany
Phone:+(49)621 181 2632 - Fax:+(49)621 181 3580
mailto:kugel@ti.uni-mannheim.de
http://www-li5.ti.uni-mannheim.de/fpga/index.shtml





Article: 34739
Subject: Virtex-2 engineering samples
From: Andreas Kugel <kugel@ti.uni-mannheim.de>
Date: Wed, 05 Sep 2001 23:01:34 +0200
Links: << >>  << T >>  << A >>


I will get our new Virtex-2 board (supports 64 Bit PCI with a PLX bridge
- sorry, no Xilinx PC- ) end of september. Devices I have are
XC2V3000-4BF957CES (engineering samples). Is anyone aware of particular
features of the ES devices (e.g. something doesn't work ...)

Thanks,
Andreas


--
Andreas Kugel - University of Mannheim - Dept. of Computer Science V
FPGA-Processor Group
B6,23-29/A - 68131 Mannheim - Germany
Phone:+(49)621 181 2632 - Fax:+(49)621 181 3580
mailto:kugel@ti.uni-mannheim.de
http://www-li5.ti.uni-mannheim.de/fpga/index.shtml





Article: 34740
Subject: Re: Virtex-2 engineering samples
From: Austin Lesea <austin.lesea@xilinx.com>
Date: Wed, 05 Sep 2001 16:28:02 -0700
Links: << >>  << T >>  << A >>
Andreas,

Please contact a Xilinx FAE, or a Xilinx sales office to obtain the ES
Errata Sheet.  This document contains detailed information about any
discrepancies that may exist in the ES material from the data sheet.

This information was shipped with every ES shipment, but it has come to our
attention that sometimes this information was not passed along with the
parts.

Austin Lesea
FPGA Lab Manager
FPG
ICDES
Xilinx

Andreas Kugel wrote:

> I will get our new Virtex-2 board (supports 64 Bit PCI with a PLX bridge
> - sorry, no Xilinx PC- ) end of september. Devices I have are
> XC2V3000-4BF957CES (engineering samples). Is anyone aware of particular
> features of the ES devices (e.g. something doesn't work ...)
>
> Thanks,
> Andreas
>
> --
> Andreas Kugel - University of Mannheim - Dept. of Computer Science V
> FPGA-Processor Group
> B6,23-29/A - 68131 Mannheim - Germany
> Phone:+(49)621 181 2632 - Fax:+(49)621 181 3580
> mailto:kugel@ti.uni-mannheim.de
> http://www-li5.ti.uni-mannheim.de/fpga/index.shtml


Article: 34741
Subject: HOW LONG WOULD LAST LONG
From: KAMRAN <kamran@teraoptic.com>
Date: Wed, 5 Sep 2001 17:11:22 -0700
Links: << >>  << T >>  << A >>
I WOULD LIKE TO ASK YOU THE XC2V6000 chip ( Package code: FF1152) HOW LONG WOULD LAST LONG (BE SAFE) TO OPERATE AT 15W WITOUTH USING HEATSINK AT ROOM TEMP. (55 DEG.)?
 SOME DATA MIGHT HELP:Thermal data and Maximum power dissipation of the selected Device and Package based on Tj-max and Ta-ambient: (Tj = 100 deg C ,Ta = 45  deg C.)
-------------------------------------------------------------------------------------
JA(0) = 11.4 C/Watt
 JC     =  1.1 C/Watt
JA(250) = 7.3  C/Watt
JA(500)   = 5.8 C/Watt
JA(750)  = 5.0  C/Watt
------------------------------------------------------------------------------------
POWER 0 LFM = 4.8  Watts
POWER 250 LFM = 7.5 
POWER  500 LFM =  9.4

THANKING YOU IN ADVANCE,
KAMRAN

Article: 34742
(removed)


Article: 34743
Subject: Re: Virtex II sizing rule of thumb
From: Ray Andraka <ray@andraka.com>
Date: Thu, 06 Sep 2001 01:35:10 GMT
Links: << >>  << T >>  << A >>
Depends on the design and the design style.  If you are careful in your
design to keep logic at one level (ie deeply pipelined) the ratio of
flip-flops to logic will be larger than if you have multiple logic levels
in most of your design.  In my stuff, it is not unusual to have some 70%
of the LUTs used as SRL16s, and the ff count is often about 120% of the
LUT count.

Jen wrote:

> I guess what I was really looking for was what other people have seen
> in there designs.  I know it depends primarily on your
> design(obviously if I use a lot of FIFOs I will use more regs)..but
> usually with FPGAs there is some warm fuzzy guestimate of what
> percentage of LUTs and FFs are used..that tends to be true across
> designs.

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com



Article: 34744
(removed)


Article: 34745
Subject: Re: Virtex-2 engineering samples
From: Ray Andraka <ray@andraka.com>
Date: Thu, 06 Sep 2001 01:41:15 GMT
Links: << >>  << T >>  << A >>
Austin,

That information should be made easily available to people before they get the
chips in their hands.  Some of the broken things are show stoppers if you need
them in your design (eg. SRL16's).  The time to find that out is before you do
your concept design, not when you receive the errata sheet with your parts
order.

Austin Lesea wrote:

> Andreas,
>
> Please contact a Xilinx FAE, or a Xilinx sales office to obtain the ES
> Errata Sheet.  This document contains detailed information about any
> discrepancies that may exist in the ES material from the data sheet.
>
> This information was shipped with every ES shipment, but it has come to our
> attention that sometimes this information was not passed along with the
> parts.
>
> Austin Lesea
> FPGA Lab Manager
> FPG
> ICDES
> Xilinx
>
> Andreas Kugel wrote:
>
> > I will get our new Virtex-2 board (supports 64 Bit PCI with a PLX bridge
> > - sorry, no Xilinx PC- ) end of september. Devices I have are
> > XC2V3000-4BF957CES (engineering samples). Is anyone aware of particular
> > features of the ES devices (e.g. something doesn't work ...)
> >
> > Thanks,
> > Andreas
> >
> > --
> > Andreas Kugel - University of Mannheim - Dept. of Computer Science V
> > FPGA-Processor Group
> > B6,23-29/A - 68131 Mannheim - Germany
> > Phone:+(49)621 181 2632 - Fax:+(49)621 181 3580
> > mailto:kugel@ti.uni-mannheim.de
> > http://www-li5.ti.uni-mannheim.de/fpga/index.shtml

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com



Article: 34746
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Article: 34747
Subject: Re: Interfacing Verilog and VHDL
From: "Srinivasan Venkataramanan" <svenka3@siliconsystems.co.in>
Date: Thu, 6 Sep 2001 11:45:18 +0530
Links: << >>  << T >>  << A >>

"Andrew Gray" <andrew@tuks.co.za> wrote in message
news:999702207.322389@nntp.up.ac.za...
> Thanks, I will try that.
>
> I want to simulate the project on modelsim using a testbench, your
method
> should work well.
> Will maxplus or Leonardo Spectrum be able to synthesise it, or will
I need
> to use a shell for the synthesis?
>

  Haven't used either of the 2, but I know that DC can take it easily
without a shell - a shell is generally used for Simulator(s). IIRC
Ambit can also handle it without any issues (provided you have proper
license of-course).

HTH,
Srinivasan

> Thanks
>
> Andrew
>
> "Srinivasan Venkataramanan" <svenka3@siliconsystems.co.in> wrote in
message
> news:9n5a90$72l@news.or.intel.com...
> > Hi,



--
Srinivasan Venkataramanan
ASIC Design Engineer
Software & Silicon Systems India Pvt. Ltd. (An Intel company)
Bangalore, India (http://www.vlsisrini.com)




Article: 34748
Subject: Re: Model sim vhdl simulation crash
From: "Srinivasan Venkataramanan" <svenka3@siliconsystems.co.in>
Date: Thu, 6 Sep 2001 12:58:56 +0530
Links: << >>  << T >>  << A >>
Hi,
  Here is a part from a previous post (posted by David Jones) on this
topic, he has laid out a few dos and don'ts with Modelsim:

  - Ensure that your FLI routines are perfectly coded, with no
segfaults or
  memory leaks or file descriptor leaks.  ModelSim is extremely
intolerant of
  bad arguments passed to its FLI functions.
- Do not have the signals or structure windows open while the
simulator is
  running or restarting. It's OK to have the waveform window open.  If
you
  need to use the signals or structure windows, then close them before
  rerunning the simulation.
- Do not use mixed Verilog/VHDL simulation.
- Occasionally quit and re-invoke from scratch.


But as my experience goes it is no issue with mixed language
simulation, that's cool with Modelsim. You may want to run till "run
300" and do a single stepping to see where it crashes. Also explain in
more detail about your environment (like do you have C-FLI, Verilog +
VHDL, PLI etc.).

Good Luck,

Srinivasan


"Jack Tai" <jtai@3dsp.com> wrote in message
news:12eb99cf.0108291319.2ec7788e@posting.google.com...
> Hi,
> I am running testbench under Modelsim SE 5.5c. Somehow, the modelsim
> program is been closed when I run the simulation to a fix place. The
> only message before the program close is the text message in the
> Transcription file.
> run 400
> #
> # Problem with simulator...  vsim U/I closing. (1)
> #
> #
> # Problem with simulator...  vsim U/I closing. (2)
> #
> Can anyone tell me ? Is any way or command that will force Modelsim
to
> tell me more message or reason about the crash ? Or, anyone know why
> crash ? I have try same simulation under different version of
> modelsims and different computers.
>
> Thank you


--
Srinivasan Venkataramanan
ASIC Design Engineer
Software & Silicon Systems India Pvt. Ltd. (An Intel company)
Bangalore, India (http://www.vlsisrini.com)




Article: 34749
Subject: strange behaviour of LPM_FIFO_DC in altera 10k130e
From: "Tony Proudfoot" <tonyp@vl.com.au>
Date: Thu, 6 Sep 2001 17:29:06 +1000
Links: << >>  << T >>  << A >>
Does anyone else have practical experience using an LPM_FIFO_DC in an Altera
10k130e device ?
I have measured some very strange behaviour with this fifo and I can't
figure it out.
I am using two seperate clock domains to write and read the fifo.
The behaviour goes like this;
Fifo empty flag on the read side is logic 1, thus fifo is empty.
I clock one qword into the fifo, using the wrreq signal on the write.
Some clocks later (~6), the empty flag on the read side goes to logic 0.
I assert rdreq on the read side and the qword emerges from the fifo. Hurrah.

Now the bit thats killing me.
Everything same as above, except when I assert rdreq the qword does NOT
emerge from the fifo. If I assert rdreq again, the qword emerges.


Does anyone know why this is happening ?
Are there known 'gotchas' interfacing to these fifos ?

Any help, hints or tips are much appreciated,
regards
Tony.
--
 _________________________________
 Tony Proudfoot, tonyp@vl.com.au
 Hardware Design Engineer
 Virtual Logic Pty Ltd
 Ph: +61(0)2 9599 3255
 _________________________________






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