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Messages from 35175

Article: 35175
Subject: Xilinx Virtex RLOC question
From: Nicolas Matringe <nicolas.matringe@IPricot.com>
Date: Tue, 25 Sep 2001 10:26:22 +0200
Links: << >>  << T >>  << A >>
Hi
The placer gives me this error message. I under'stand what it means but
I don't know how to fix the problem.

ERROR:Place - Components dvbwriter/BuffAddr(4) and
iosys/addr/bytecount(4) are using the F5/F6MUX resources. The component
iosys/addr/bytecount(4) is part of a carry chain macro. Please RLOC the
components dvbwriter/BuffAddr(4) and iosys/addr/bytecount(4) together.

I am currently searching Xilinx web site but RLOC help is hard to find
(and the search engine has been disabled)

-- 
Nicolas MATRINGE           IPricot European Headquarters
Conception electronique    10-12 Avenue de Verdun
Tel +33 1 46 52 53 11      F-92250 LA GARENNE-COLOMBES - FRANCE
Fax +33 1 46 52 53 01      http://www.IPricot.com/

Article: 35176
Subject: Re: comp.arch.fpga : Unusual clock divider ckt
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Tue, 25 Sep 2001 09:28:45 +0100
Links: << >>  << T >>  << A >>


Ray Andraka wrote:

>
>  "They that give up essential liberty to obtain a little
>   temporary safety deserve neither liberty nor safety."
>                                           -Benjamin Franklin, 1759

That's a really apposite quote. Might be called the "roots of dictatorship".


Article: 35177
Subject: verification problems please help
From: "timnicolson" <timnicolson@hotmail.com>
Date: Tue, 25 Sep 2001 10:46:06 +0100
Links: << >>  << T >>  << A >>
Help

Can anyone experienced with fpga design suggest what I maybe doing wrong.

I have quite a large design for an 8-bit space vector motor controller, for
implementation on a SpartanII device.

I have design the system using Xilinx's foundation software.

I have used a mixture of coregen modules and VHDL macros stuck together in
the schematic editor.

The design simulates as intended.

Problems arise when implementing, I get some warnings because some of my
coregen signals do not connect to anything (do I need them too?), and I get
some other warnings saying 100% back annotation not possible for some of the
blocks.  It finishes and says its implemented OK.

Now I go to verify the design.  It doesn't work as intended, I've searched
around, and found the problem, a CoreGen "pipelined divider" module is
producing rubbish, not remotely what it should do.... but only when I verify
the whole design!  if I enter verification and then select "verify single
component" from the file menu, and select the next hierarchy down, which
contains the divider, the module verifies correctly.

This problem is really beyond me at the moment, can someone give me any
pointers to what the problem maybe.
Thanks for your time/effort

Tim Nicolson
University of Sheffield
UK



Article: 35178
Subject: ROM initialisation on Xilinx Virtex design
From: renaux <renaux.jacky@wanadoo.fr>
Date: 25 Sep 2001 11:08:41 GMT
Links: << >>  << T >>  << A >>

I 
A RAM as ROM is very usefull as lookup table but RAMs initialisation is 
time consuming : simulation and synthesis does requires differents statements  

Does anybody already wrote an utility program which convert either text
file or Excel spreadsheet to translates datas into INIT_xx format 
in order to speed up any vhdl based design ROMs contents changes  
 
thanks 

jacky

------
User of http://www.foorum.com/. The best tools for usenet searching.

Article: 35179
Subject: How does Altera FLEX 10k communicate with PC?
From: m8931612@student.nsysu.edu.tw (Ru-Chin Tsai)
Date: 25 Sep 2001 05:26:44 -0700
Links: << >>  << T >>  << A >>
Hi folks!
                                                                               
I implement a image processing algorithm.
Because testbench must be preprocess by PC then sending to FLEX 10k.
I hope when FLEX 10k finishing task,it sending result to PC so that I can
view the result on screen.

But how can I let FLEX 10k to communicate with PC?
Which interface should I choice(ISA or PCI or others)?
Does any exist PCI or ISA interface Soft-IP I can get?

Thank you for your help!

Article: 35180
Subject: Logical constraints of LUT
From: "Noddy" <g9731642@campus.ru.ac.za>
Date: Tue, 25 Sep 2001 14:58:11 +0200
Links: << >>  << T >>  << A >>
Hi,

I was wondering how/if it were possible to make a distributed memory LUT
created as an RPM to be placed within the RAM memory blocks of a Spartan II.
Each LUT is 128 deep, 8 bit wide.

adrian




Article: 35181
Subject: fir filter
From: kkdeep@mailcity.com (kuldeep)
Date: 25 Sep 2001 05:58:19 -0700
Links: << >>  << T >>  << A >>
i have to implement a 64 tap FIR filter with fixed coefficients in
hardware. I have found some architecture suitable for fpga (using LUTs
of fpga) which don't use multipliers. can somebody point me to
architecture suitable for ASIC?. Since the coefficients are fixed, i
want to optimize or avoid the multipliers.The input sample rate is 16
MHz with 12 bits (in 2s complement).
thanx 
kuldeep

Article: 35182
Subject: FPGA with embedded Memory
From: "Peter Lang" <Peter.Lang@rmvmachinevision.de>
Date: Tue, 25 Sep 2001 15:24:44 +0200
Links: << >>  << T >>  << A >>
Hello,
I am looking for an FPGA with embedded Memory.
There should be 16 times of a 8Kx8 Ram.
I found the Xilinx XCV812E.
Does anybody has experience with that chip?
Is it available now and in future?
I found a price of about $1000 US.
Are there any cheaper alternatives?
thanks
peter




Article: 35183
Subject: Re: FPGA with embedded Memory
From: Laurent Gauch <laurent.gauch@amontec.com>
Date: Tue, 25 Sep 2001 16:15:34 +0200
Links: << >>  << T >>  << A >>
For cheaper PFGAs, try Xilinx SpartanII having embedded ram block.
Laurent
Amontec

Peter Lang wrote:

> Hello,
> I am looking for an FPGA with embedded Memory.
> There should be 16 times of a 8Kx8 Ram.
> I found the Xilinx XCV812E.
> Does anybody has experience with that chip?
> Is it available now and in future?
> I found a price of about $1000 US.
> Are there any cheaper alternatives?
> thanks
> peter
> 
> 
> 
> 


Article: 35184
Subject: Re: fir filter
From: "RM" <yeren@gmx.de>
Date: Tue, 25 Sep 2001 16:18:41 +0200
Links: << >>  << T >>  << A >>
the following reference (you can get more by google'ing with FIR BIT SERIAL
ftp://ftp.ittc.ukans.edu/pub/projects/DSP/FPGA/Bit_Serial.pdf
is intended for FPGA use, but it _might_ be suitable for asic, too, because
it
is on designs that only include bit shift operations and additions instead
of
multiplications. Bad side effect: you will have to calculate a new filter
that
meets the restrictions of the method..
robert

"kuldeep" <kkdeep@mailcity.com> schrieb im Newsbeitrag
news:a0f016a9.0109250458.7bb874f1@posting.google.com...
> i have to implement a 64 tap FIR filter with fixed coefficients in
> hardware. I have found some architecture suitable for fpga (using LUTs
> of fpga) which don't use multipliers. can somebody point me to
> architecture suitable for ASIC?. Since the coefficients are fixed, i
> want to optimize or avoid the multipliers.The input sample rate is 16
> MHz with 12 bits (in 2s complement).
> thanx
> kuldeep



Article: 35185
Subject: CLKDLL question
From: "Noddy" <g9731642@campus.ru.ac.za>
Date: Tue, 25 Sep 2001 16:25:53 +0200
Links: << >>  << T >>  << A >>
I have a high-fan out clock signal. They all fan-out from the output of a
single BUFGDLL symbol. My question is:

Does the BUFGDLL (IBUGG -> CLKDLL -> BUFG) have low skew on all my clock
signals, or only along the primary clock lines (One down each side of
FPGA?). If so, how can I get low skew over every clock input pin. Also, is
there a need to se more than one BUFGDLL if I am only using one clock input?

thanks
adrian




Article: 35186
Subject: Re: How to fix the hold time violation (clock skew>data skew) in QuartusII
From: "Noddy" <g9731642@campus.ru.ac.za>
Date: Tue, 25 Sep 2001 16:27:48 +0200
Links: << >>  << T >>  << A >>

Jean-Baptiste Monnard <jmonnard@horizon-tech.fr> wrote in message
news:9opa87$7je$1@wanadoo.fr...
>
> You should enable the Global Signal option for your clock signals.

Sorry, but how do you do this? (I am using Foundation 3.1)

adrian






Article: 35187
Subject: Xilinx implementation problem
From: Nicolas Matringe <nicolas.matringe@IPricot.com>
Date: Tue, 25 Sep 2001 18:17:12 +0200
Links: << >>  << T >>  << A >>
Hi
I am trying to implement a design in an XCV300E. I worked fine until I
removed some unnecessary logic. Now I come across this problem: par
gives me this message
ERROR:Place:1993 - Components dvb/if_dvb_inst/data_rd_del and
iosys/addr/bytecount(4) are using the F5/F6MUX resources. The component
iosys/addr/bytecount(4) is part of a carry chain macro. Please RLOC
components dvb/if_dvb_inst/data_rd_del and iosys/addr/bytecount(4)
together.

Th eproblem is that the two components have absolutely no relation. They
are in different modules/entities which are synthesized separately, and
after looking at the edif files, I can't see any connection between
them. So where does this F5/F6MUX come from?
Thanks for any help, I am going crazy...
-- 
Nicolas MATRINGE           IPricot European Headquarters
Conception electronique    10-12 Avenue de Verdun
Tel +33 1 46 52 53 11      F-92250 LA GARENNE-COLOMBES - FRANCE
Fax +33 1 46 52 53 01      http://www.IPricot.com/

Article: 35188
Subject: Re: comp.arch.fpga : Unusual clock divider ckt
From: Peter Alfke <peter.alfke@xilinx.com>
Date: Tue, 25 Sep 2001 09:38:08 -0700
Links: << >>  << T >>  << A >>


Allan Herriman wrote:

> Note that in no case does the jitter actually get as high as one
> period of the input clock.
>

That is in the nature of DDS.
Max jitter = one clock period.
If that is acceptable, go for it.

Peter


Article: 35189
Subject: Re: fir filter
From: renaux <renaux.jacky@wanadoo.fr>
Date: 25 Sep 2001 16:41:46 GMT
Links: << >>  << T >>  << A >>

Hi 

I would suggest you read an excellent paper on distributed arithmetic 
where part of the calculation is done before running while the remaining 
is done during the run 

go to http://www.andraka.com/ ,  DSP with FPGA and distributed arith 

this is intended to fpga , but using a case statement it can be targetted to
any technology . in addittion , using a ram as table would simplify the 
FIR filter implementation : a tap per add line , and output bus is as wide as 
sum of coefficients values ( if 16   12 bits coefficients => 4+12 bits bus )
do not miss the fact which is coefficients are symetrical you better add 
coefficient before feeding the partial products table ) 

do not hesitate to drop me a mail in case it is not clear enough 

regards , jacky 

------
User of http://www.foorum.com/. The best tools for usenet searching.

Article: 35190
Subject: Re: FPGA with embedded Memory
From: Peter Alfke <peter.alfke@xilinx.com>
Date: Tue, 25 Sep 2001 09:52:13 -0700
Links: << >>  << T >>  << A >>
SpartanII does not go up to that size. The largest device XC2S150 has 12
dual-ported RAM blocks of 4k bits each.
VirtexE goes up to 655360 bits, still less than you want.
Except for the XCV812 part, that is exceptionally memory-oriented, your best bet
is
XC2V3000 with 96 blocks of 8Kx2 dual-ported BlockRAMs.
The more popular XC2V2000 just misses your target. It has 56 such blocks.
These BlockRAMs are dual-ported, fast, flexible, and nicely integrated with the
FPGA fabric, but they are not really cheap. Depending on your speed and
pin-count requirements, you may be better of with external SRAM.

Peter Alfke, Xilinx Applictions.
=====================
Laurent Gauch wrote:

> For cheaper PFGAs, try Xilinx SpartanII having embedded ram block.
> Laurent
> Amontec
>
> Peter Lang wrote:
>
> > Hello,
> > I am looking for an FPGA with embedded Memory.
> > There should be 16 times of a 8Kx8 Ram.
> > I found the Xilinx XCV812E.
> > Does anybody has experience with that chip?
> > Is it available now and in future?
> > I found a price of about $1000 US.
> > Are there any cheaper alternatives?
> > thanks
> > peter
> >
> >
> >
> >


Article: 35191
Subject: Re: FPGA with embedded Memory
From: "Ulf Samuelsson" <ulf@atmel.dot.com>
Date: Tue, 25 Sep 2001 19:05:29 +0200
Links: << >>  << T >>  << A >>
The Xilinx Spartan II XC2S150 has 49kbit so you need 32 of these chips.

The Atmel AT94K05 FPSLIC has up to 12kB x 8 of SRAM, useable by the FPGA
so you need 16 of these devices, but they are probably more like $10 each in
medium
volume.

--
Best regards,
ulf at atmel dot com
The contents of this message is intended to be my private opinion and
may or may not be shared by my employer Atmel Sweden

"Laurent Gauch" <laurent.gauch@amontec.com> skrev i meddelandet
news:3BB09186.60406@amontec.com...
> For cheaper PFGAs, try Xilinx SpartanII having embedded ram block.
> Laurent
> Amontec
>
> Peter Lang wrote:
>
> > Hello,
> > I am looking for an FPGA with embedded Memory.
> > There should be 16 times of a 8Kx8 Ram.
> > I found the Xilinx XCV812E.
> > Does anybody has experience with that chip?
> > Is it available now and in future?
> > I found a price of about $1000 US.
> > Are there any cheaper alternatives?
> > thanks
> > peter
> >
> >
> >
> >
>



Article: 35192
Subject: Re: FPGA with embedded Memory
From: Falk Brunner <Falk.Brunner@gmx.de>
Date: Tue, 25 Sep 2001 19:08:40 +0200
Links: << >>  << T >>  << A >>
Peter Lang schrieb:
> 
> Hello,
> I am looking for an FPGA with embedded Memory.
> There should be 16 times of a 8Kx8 Ram.
> I found the Xilinx XCV812E.

Thats a BIG one. You better use Virtex-E, its cheaper and faster (better
IC process)

> Does anybody has experience with that chip?

Not yet.

-- 
MFG
Falk



Article: 35193
Subject: Re: CLKDLL question
From: Falk Brunner <Falk.Brunner@gmx.de>
Date: Tue, 25 Sep 2001 19:10:50 +0200
Links: << >>  << T >>  << A >>
Noddy schrieb:
> 
> I have a high-fan out clock signal. They all fan-out from the output of a
> single BUFGDLL symbol. My question is:
> 
> Does the BUFGDLL (IBUGG -> CLKDLL -> BUFG) have low skew on all my clock
> signals, or only along the primary clock lines (One down each side of

The DLL will just keep an eye on one clock net. But you have 4 clock net
and 4 DLLs, so no problem at all.

> FPGA?). If so, how can I get low skew over every clock input pin. Also, is
> there a need to se more than one BUFGDLL if I am only using one clock input?

No. Just one clock, one DLL.

-- 
MFG
Falk


Article: 35194
Subject: Re: FPGA with embedded Memory
From: Eric Smith <eric-no-spam-for-me@brouhaha.com>
Date: 25 Sep 2001 11:48:34 -0700
Links: << >>  << T >>  << A >>
Peter Alfke <peter.alfke@xilinx.com> writes:
> SpartanII does not go up to that size. The largest device XC2S150 has 12
> dual-ported RAM blocks of 4k bits each.

Actually there is an XC2S200, which has 14 block RAMs.

If the new WebPACK is to be believed, there is a Spartan IIE family
in the works, with an XC2S300E.  Presumably it is similar to the
XCV300E.

Article: 35195
Subject: Xilinx 4.1 software
From: Tom Brooks <tbrooks@corepower.com>
Date: Tue, 25 Sep 2001 15:00:22 -0400
Links: << >>  << T >>  << A >>
So, I installed Xilinx 4.1i software today and
my results were much worse than with Xilinx
3.3i.  I have a 5 ns path that was turned into
a 7 ns path with the new software.  So, I'm
going back to 3.3i.


Article: 35196
Subject: Virtex2 slice level instantiation in verilog question
From: hooiwai@yahoo.com (J.Ho)
Date: 25 Sep 2001 12:03:45 -0700
Links: << >>  << T >>  << A >>
Hi all,

I am trying to instantiate specific elements inside a Virtex 2 slice
in verilog, such as XORG, GYMUX.  Does anyone know if that is possible
with synthesis and PAR tools?

For example, if I want a 8-input xor gate, Synplicity would just map
it across 3 LUTs.  But if you look at the virtex slice, there is an
XOR gate that you can route the output of the 2 4-input LUTS to.  If I
can force the tool to use those resources, then I can fit a 8-input
XOR in one slice instead of two.

I know this is really low level, but if the hardware is there, why
waste it?

Thanks,

Jon

Article: 35197
Subject: Re: Virtex2 slice level instantiation in verilog question
From: "Tim" <tim@rockylogic.com.nospam.com>
Date: Tue, 25 Sep 2001 20:24:45 +0100
Links: << >>  << T >>  << A >>

"J.Ho" <hooiwai@yahoo.com> wrote in message

> I am trying to instantiate specific elements inside a Virtex 2 slice
> in verilog, such as XORG, GYMUX.  Does anyone know if that is possible
> with synthesis and PAR tools?

You can instantiate anything you find in the Xilinx Library Guide.
Put it in as a black box - the default in Verilog as I recall.





Article: 35198
Subject: Re: FPGA with embedded Memory
From: Ray Andraka <ray@andraka.com>
Date: Tue, 25 Sep 2001 20:27:13 GMT
Links: << >>  << T >>  << A >>
Spartan doesn't have enough memory for what he is asking.  As long as it
meets your speed requirements, the cheapest alternative is often a small
FPGA plus an external memory.  You can use the internal block rams as
staging buffers when you need fast or simultaneous access to the data.

Laurent Gauch wrote:

> For cheaper PFGAs, try Xilinx SpartanII having embedded ram block.
> Laurent
> Amontec
>
> Peter Lang wrote:
>
> > Hello,
> > I am looking for an FPGA with embedded Memory.
> > There should be 16 times of a 8Kx8 Ram.
> > I found the Xilinx XCV812E.
> > Does anybody has experience with that chip?
> > Is it available now and in future?
> > I found a price of about $1000 US.
> > Are there any cheaper alternatives?
> > thanks
> > peter
> >
> >
> >
> >

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 35199
Subject: Re: Virtex2 slice level instantiation in verilog question
From: "Bryan" <bryan@srccomp.com>
Date: Tue, 25 Sep 2001 14:35:03 -0600
Links: << >>  << T >>  << A >>

>
> I know this is really low level, but if the hardware is there, why
> waste it?
>


The same question I ask myself every time somebody tries to convince me to
use verilog instead of schematic capture.

Bryan





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