Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarApr2017

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search

Messages from 35125

Article: 35125
Subject: Re: Virtex Clock Enable and Synplify
From: Ray Andraka <ray@andraka.com>
Date: Sat, 22 Sep 2001 00:50:18 GMT
Links: << >>  << T >>  << A >>


John_H wrote:

> I didn't reply immediatly because I have a Verilog bent.  Knowing what I
> do about Synplify, you should be able to get the Virtex CLB clock enable
> pins worked into your code easily.  No tricks.  There is one directive
> (attribute?) that might help for some signals - look up syn_isenable on
> Synplify's online help; I think that's valid but can't check quickly.
>
> Be aware that CLBram and SRL instances won't pack nicely with write
> enables and register resets.  BlockRams also may need a little help.
>

THe issue is clock enables and resets are shared by both flip-flops in a
slice.  If both
use the same signals, they pack fine, but if they don't it won't pack.  This
can be a
problem when you have a whole bunch of loads on a common ce or rst, as the
synthesizer will duplicate those signals willy-nilly if you exceed the max
fanout
parameter.  You can keep the local names the same if you are doing generates
by
passing them through a keep buffer (syn_keep).

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 35126
Subject: Analyse static timing for Xilinx FPGA
From: "David" <e-love@21cn.com>
Date: Sat, 22 Sep 2001 10:02:24 +0800
Links: << >>  << T >>  << A >>
Hi, how to use PrimeTime to analyse static timing for Xilinx FPGA?
is the Xilinx library have enough and correct timing information
for PrimeTime? How to convert Xilinx constraints to PrimeTime?



Article: 35127
Subject: Re: Stopping a DLL
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Sat, 22 Sep 2001 09:45:43 +0100
Links: << >>  << T >>  << A >>


Austin Lesea wrote:

> You got it.
>
> The problem is entirely the change in the delay line with the changing environment.  If
> the voltage, or temperature changes, you are going to be unlocked when that next rising
> edge comes along.
>
> We estimated that it would take about 1 ms for the micro-environment to change enough to
> lose lock this way...it is really hard to estimate what the worst case drift of a few
> hundred buffers are in the delay line chain.
>
> When you add in power supply ripple, SSO's, and all of the other normal stuff, it isn't
> recommended.
>
> Thanks,
>
> Austin
>
> John_H wrote:

>

The quote from the Virtex-E manual that started me off on this (v1.9 pg 45) is

``It is possible to stop the clock with little impact on the DLL. Stopping the clock should
be limited to less than 100usec. to keep device cooling to a minimum ....''

If its as unstable as you say wrt to all the other variations then it seems that even
100usec. may be optimistic.

It seems that if I want a power-down circuit in a V-E to stop/start the clock(s) for an
arbitrary period I'll have to:

o Flush all pending transactions, stop any new ones happening,

o Make sure that all the FF's state I want to preserve have clock enables connected to some
``freeze'' signal. The rest would probably go into reset.

o Stop the clock on a low & then put the DLL in reset.

o To restart I'd unreset the DLL, wait for it to aquire lock (pretty fast at ~20usec),.

o Un-freeze & run.

This is o.k. for the CPU clock but -

Question: Can this be made compatible with the Rev 2.2 PCI ``stop clock'' protocol ?

Looks like using V-2s with the ``Alfke-Mux'' is a whole lot simpler.



Article: 35128
Subject: Re: Analyse static timing for Xilinx FPGA
From: "Tim" <tim@rockylogic.com.nospam.com>
Date: Sat, 22 Sep 2001 11:14:53 +0100
Links: << >>  << T >>  << A >>
Interesting.  What would be the advantage of PrimeTime over the
Xilinx static timing analyzer?

"David" <e-love@21cn.com> wrote in message news:9ogrme$av9$1@mail.cn99.com...
> Hi, how to use PrimeTime to analyse static timing for Xilinx FPGA?
> is the Xilinx library have enough and correct timing information
> for PrimeTime? How to convert Xilinx constraints to PrimeTime?
>
>



Article: 35129
Subject: Re: Mixing VHDL and EDIF in FPGA Compiler II (Xilinx)
From: Marius Vollmer <marius.vollmer@uni-dortmund.de>
Date: 22 Sep 2001 14:50:38 +0200
Links: << >>  << T >>  << A >>
Gavin Hurlbut <gjhurlbu@beirdo.ott.uplink.on.ca> writes:

> > I'm not there yet.  I can functionally simulate the generated cores,
> > but I haven't tried `physical' timing yet.
> 
> I try to do my functional simulations first :) I never quite get the
> silly Foundation Simulator to get the black-box EDIF imported with
> my top-level design, but the timing simulation output worked great.
> I think it's just a matter of sitting there for another Saturday
> with mucho beer and threatening the tools a bit more. :)

Hehe, yes.  When I said `functionally simulate', I meant simulating
the VHDL code generated by CoreGen.  It puts out a configuration for
the generated core that links to a pure behavioral implementation
provided by Xilinx.  No EDIF involved.

> > It helped tremendously.  Please have a virtual beer on me. :)
> 
> Will do.  Unfortunately, I don't have any German beer right now (ran
> out), so I'll have to deal with Moosehead (an eastern Canadian
> beer), which I do have in my fridge. :)

As long as its sufficiently cold... ;) What kind of German beer do you
get in Canada?  Off hand, I can't think of any Canadian brand that
would be available here.

Article: 35130
Subject: Re: Mixing VHDL and EDIF in FPGA Compiler II (Xilinx)
From: Gavin Hurlbut <gjhurlbu@beirdo.ott.uplink.on.ca>
Date: Sat, 22 Sep 2001 14:35:50 GMT
Links: << >>  << T >>  << A >>
Marius Vollmer <marius.vollmer@uni-dortmund.de> wrote:
> Gavin Hurlbut <gjhurlbu@beirdo.ott.uplink.on.ca> writes:
>> > I'm not there yet.  I can functionally simulate the generated cores,
>> > but I haven't tried `physical' timing yet.
>> 
>> I try to do my functional simulations first :) I never quite get the
>> silly Foundation Simulator to get the black-box EDIF imported with
>> my top-level design, but the timing simulation output worked great.
>> I think it's just a matter of sitting there for another Saturday
>> with mucho beer and threatening the tools a bit more. :)

> Hehe, yes.  When I said `functionally simulate', I meant simulating
> the VHDL code generated by CoreGen.  It puts out a configuration for
> the generated core that links to a pure behavioral implementation
> provided by Xilinx.  No EDIF involved.

Ahhh.  That would explain it :)  My EDIF files are from non-Xilinx cores, and
I had to compile them.  I don't think there is a separate behavioral
implementation possible to generate.  Something else for me to look into.  And
I'm out of swill... er Canadian beer, so I'll have to go get more.

>> > It helped tremendously.  Please have a virtual beer on me. :)
>> 
>> Will do.  Unfortunately, I don't have any German beer right now (ran
>> out), so I'll have to deal with Moosehead (an eastern Canadian
>> beer), which I do have in my fridge. :)

> As long as its sufficiently cold... ;) What kind of German beer do you
> get in Canada?  Off hand, I can't think of any Canadian brand that
> would be available here.

Well, Beck's is pretty easy to get, and there are a few others, but off hand
I can't remember which.  The interesting thing is that the beer stores for the
province of Ontario (where I live) have an online presence, so you can actually
search for such details if you are interested. :)
	http://www.thebeerstore.ca
Of course, either the page is slightly out of it, or my Netscape is, so I can't
actually search for the German beers.  YMMV.

I'm not surprised that not many Canadian beers can be found in Germany.  I 
certainly didn't see any in Austria when I was there earlier this year.  Trust
me, you aren't missing much.  The German, Austrian and Czech beers I had in
Vienna were *much* better than Canadian beers.  There are a few decent ones 
brewed here, but they are the minority, most is swill.  Yet, strangely enough,
they are all better than any American beer I've ever been brave (or drunk)
enough to try.

Now, I have to get to the beer store to replenish the fridge.

Ciao.
Gavin

Article: 35131
Subject: Complex mixer LUT
From: "Noddy" <g9731642@campus.ru.ac.za>
Date: Sat, 22 Sep 2001 23:53:21 +0200
Links: << >>  << T >>  << A >>
Hi all,

I've designed a complex mixer using a 10 bit address line (4bit I signal - 4
bit Q signal - 2 bit phasor) to mix by +/- 90 degrees, with an 8 bit output.
This makes the LUT 1024 rows deep. The problem is that the LUT seems to
generate fine using Xilinx Core generator, but simulation gives incorrect
data bytes. I know that the data I initialised the LUT with is correct, so
has anyone have any bright ideas as to what is going on?

Before you say so, I know of a far more efficient in which to do the mixing,
using approximately 1/10th the space that this LUT does, but I'm trying to
test out the different designs for performance.

Regards
adrian




Article: 35132
Subject: Re: Complex mixer LUT
From: "Noddy" <g9731642@campus.ru.ac.za>
Date: Sat, 22 Sep 2001 23:58:17 +0200
Links: << >>  << T >>  << A >>
Never mind... found the answer!

adrian




Article: 35133
Subject: Re: Complex mixer LUT
From: Chris Eilbeck <chris@yordas.demon.co.uk>
Date: 22 Sep 2001 23:03:29 +0100
Links: << >>  << T >>  << A >>
"Noddy" <g9731642@campus.ru.ac.za> writes:

> Never mind... found the answer!

Do tell!

Chris
-- 
Chris Eilbeck                             mailto:chris@yordas.demon.co.uk
MARS Flight Crew                                  http://www.mars.org.uk/
UKRA #1108 Level 1                                                   BSMR


Article: 35134
Subject: Re: Analyse static timing for Xilinx FPGA
From: "David" <e-love@21cn.com>
Date: Sun, 23 Sep 2001 12:28:21 +0800
Links: << >>  << T >>  << A >>
I'm afraid that Xilinx timing analyzer will not be powerful and fast
enough to analyse Virtex-II(with CPU core,IP,RAM,STAMP)

"Tim" <tim@rockylogic.com.nospam.com> wrote in message
news:1001165782.22620.0.nnrp-13.9e9832fa@news.demon.co.uk...
> Interesting.  What would be the advantage of PrimeTime over the
> Xilinx static timing analyzer?
>
> "David" <e-love@21cn.com> wrote in message
news:9ogrme$av9$1@mail.cn99.com...
> > Hi, how to use PrimeTime to analyse static timing for Xilinx FPGA?
> > is the Xilinx library have enough and correct timing information
> > for PrimeTime? How to convert Xilinx constraints to PrimeTime?
> >
> >
>
>



Article: 35135
Subject: Re: how to simulate virtex components?
From: hamish@cloud.net.au
Date: Sun, 23 Sep 2001 13:50:58 GMT
Links: << >>  << T >>  << A >>
Tim <tim@rockylogic.com.nospam.com> wrote:
> For RTL/pre-synth simulation use this:

> -- synthesis translate_off
> library unisim;
> use unisim.vcomponents.all;
> -- synthesis translate_on

You might as well do this at synthesis time too (ie take out the
translate_off/on); you have to get the component declarations
from somewhere. If you're including them in your code anyway,
you can take out the use line and just leave 'library unisim;'.


Hamish
-- 
Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>

Article: 35136
Subject: Re: Synplicity logic replication
From: hamish@cloud.net.au
Date: Sun, 23 Sep 2001 13:56:07 GMT
Links: << >>  << T >>  << A >>
Don Husby <husby_d@yahoo.com> wrote:
> For the following code, synplify will merge the two instances
> of Shift into the same net:

>  wire  [1:0] Shift                            /* synthesis syn_keep=1 */;
>  assign Shift[0]= Sending & !Stall | !Ready;  // 
>  assign Shift[1]= Sending & !Stall | !Ready;  // Replicated

Use syn_preserve on the signal. syn_keep won't do it, I think.
I don't know what the syntax for that is in Verilog.



Hamish
-- 
Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>

Article: 35137
Subject: Re: Clockin on rising AND falling edge
From: hamish@cloud.net.au
Date: Sun, 23 Sep 2001 14:03:15 GMT
Links: << >>  << T >>  << A >>
lennart <lennartheijnen@hotmail.com> wrote:
> You can never use a rising and a falling edge of a signal in a process. 

You can, you just can't synthesise it.

It's quite useful in simulation (only) to register some DDR signals using

reg_ddr: process (ddr_clk)
begin
  if ddr_clk'event then
    ddr_q <= ddr_d;
  end if;
end process;

I contacted Synplicity support a while ago and asked if Synplify could
infer the DDR outputs available in the Virtex-II; they told me it
was illegal in VHDL :-( I'm not sure what that means.



Hamish
-- 
Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>

Article: 35138
Subject: Re: problem with location constraints in Verilog
From: "Austin Franklin" <austin@darkroom87.com>
Date: Sun, 23 Sep 2001 12:23:49 -0400
Links: << >>  << T >>  << A >>

> Putting the placement in the code allows you to build the structure
hierarchically
> instead of flat.  You can floorplan even pretty big designs rather quickly
that
> way.

Perhaps you would be so kind as to post an example ;-)




Article: 35139
Subject: Re: problem with location constraints in Verilog
From: Ray Andraka <ray@andraka.com>
Date: Sun, 23 Sep 2001 21:09:12 GMT
Links: << >>  << T >>  << A >>
here is a bottom level for an adder.  Next level up in the code just needs an
RLOC attribute on the instance done the same way as the RLOCs in the bottom
level.  The RLOCs at the lowest level must go on primitives, just like you did
with schematics.

c(0) <=cin;
co<= c(width);
L:for i in 0 to width-1 generate
     constant rloc_str : string := "R" & itoa( ((width-1)/2)-(i/2))  & "C0" &
".S" & itoa(slice mod 2);
     signal l,s: STD_LOGIC;
     attribute RLOC   of U1 : label is rloc_str;
     attribute RLOC   of U2 : label is rloc_str;
     attribute RLOC   of U3 : label is rloc_str;
     attribute RLOC   of U4 : label is rloc_str;
 begin
      U1: fmap_xor2 port map(
       a=> ax(i),
       b=> bx(i),
       z=> l);

      U2: MUXCY port map (
       O  => c(i+1),
       CI => c(i),
       DI => ax(i),
       S  => l );

      U3: XORCY port map (
       O  => s,
       CI => c(i),
       LI => l );

    U4: FDE port map (
        Q  => q(i),
        D  => s,
       CE => ce,
       C  => clk );
 end generate L;


Austin Franklin wrote:

> > Putting the placement in the code allows you to build the structure
> hierarchically
> > instead of flat.  You can floorplan even pretty big designs rather quickly
> that
> > way.
>
> Perhaps you would be so kind as to post an example ;-)

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 35140
Subject: Re: how to simulate virtex components?
From: Ray Andraka <ray@andraka.com>
Date: Sun, 23 Sep 2001 21:12:11 GMT
Links: << >>  << T >>  << A >>
You want the primitives black-boxed at synthesis to keep the tools from
trying to go inside the behavoral models found in unisim.

hamish@cloud.net.au wrote:

> Tim <tim@rockylogic.com.nospam.com> wrote:
> > For RTL/pre-synth simulation use this:
>
> > -- synthesis translate_off
> > library unisim;
> > use unisim.vcomponents.all;
> > -- synthesis translate_on
>
> You might as well do this at synthesis time too (ie take out the
> translate_off/on); you have to get the component declarations
> from somewhere. If you're including them in your code anyway,
> you can take out the use line and just leave 'library unisim;'.
>
> Hamish
> --
> Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 35141
Subject: Re: Analyse static timing for Xilinx FPGA
From: "Tim" <tim@rockylogic.com.nospam.com>
Date: Mon, 24 Sep 2001 01:39:34 +0100
Links: << >>  << T >>  << A >>
Herewith a quote from the current ESNUG.  I wonnder what the speed would
be on X tools...

"David" <e-love@21cn.com> wrote in message news:9ojoi1$3g1$1@mail.cn99.com...
> I'm afraid that Xilinx timing analyzer will not be powerful and fast
> enough to analyse Virtex-II(with CPU core,IP,RAM,STAMP)
>
> "Tim" <tim@rockylogic.com.nospam.com> wrote in message
> news:1001165782.22620.0.nnrp-13.9e9832fa@news.demon.co.uk...
> > Interesting.  What would be the advantage of PrimeTime over the
> > Xilinx static timing analyzer?
> >
> > "David" <e-love@21cn.com> wrote in message
> news:9ogrme$av9$1@mail.cn99.com...
> > > Hi, how to use PrimeTime to analyse static timing for Xilinx FPGA?
> > > is the Xilinx library have enough and correct timing information
> > > for PrimeTime? How to convert Xilinx constraints to PrimeTime?
> > >

-- ==================================================================== --

( ESNUG 377 Item 18 ) ------------------------------------------- [09/19/01]

From: xxxxxxxxxxxxxxx
Subject: Two Users Question PrimeTime On Its Interface Logic Models (ILMs)

John,

Has anyone used PrimeTime's new ILM capability?  I'm interested in other
people's experiences.

    - xxxxxxxxxx
      ATI

         ----    ----    ----    ----    ----    ----   ----

From: [ A Modern Major General ]

John,

I need to remain anonymous please ... thanks!

I am closing out on a 2 M gate equivalent chip (mix of logic, memory and
cores) and I'm moving onto something nearly 4X the complexity.

I used Primetime for timing closure, both on a block and top level -- two
levels of hierarchy from a physical design perspective.  One thing is clear
for the next chip -- there is no way I'll be able to run a full netlist in
PrimeTime, especially if I want to have results in a reasonable amount of
time.

To read in the full netlist, back annotate (DSPFs) and do an update_timing
took about 2 hours.   Generating very detailed timing reports, including
full path, clock skew, histograms, etc, took nearly 18 hours -- on a 900
MHz P-III running Linux with sufficient memory.  (The chip has a dozen+
different clock domains to deal with, plus scan, bist, jtag, etc.)

To get run time down in the highly iterative early stages of timing closure,
I created block level ILMs to use for top level timing.   This brought the
top level runtime down to 5-6 hours.

Overall, the ILM procedure worked reasonably well, but of course, wasn't
without its problems.  Synopsys helped work around the problems in the
2000.11 drop with a set of procs, and the 2001.08 drop due shortly is
supposed to fix these problems, so that the procs are no longer needed.

As I ramp toward the next project, I'm interested in the ESNUG community's
experience on 5-10 M gate ASICs, especially comments on ILM usage, if anyone
has succeeded in staying on 32-bit CPUs or if they've had to move to 64-bit
platform, or any other information that can be shared.

I was surprised to look on the Synopsys SolvNet pages and only find one
article related to ILMs.  Does that mean it hasn't been hammered on by the
design community to any great extent?

I would also be interested in any user feedback on PrimeTime-SI.

    - [ A Modern Major General ]

-- ==================================================================== --




Article: 35142
Subject: Forcing a LUT logic function (was Synplicity logic replication)
From: "Tim" <tim@rockylogic.com.nospam.com>
Date: Mon, 24 Sep 2001 02:13:13 +0100
Links: << >>  << T >>  << A >>
"Don Husby" <husby_d@yahoo.com> wrote

>   This is what I ended up doing.  I guess the Golden Age of high level
> HDL hasn't arrived yet.  The sad thing is that everyone thinks it has,
> so when I write something simple, the tool trys to second guess me and
> make an "optimization".  I have to go to great effort to tell it to
> just fucking do what I say.  Instantiating a LUT is to HDL programming
> as instantiating machine op-codes is to C programming.
>
>   Here's how to instantiate a LUT in Synplicity/Verilog:
>
>     LUT3 #('h2f) shift0(Shift[0], Sending, Stall, Ready);
>
>   Unfortunately, not all synthesis/simulation tools accept
> the same format.
>

Please excuse the VHDL in the code below.  (A fuller version is
at http://www.rockylogic.com/freestuff )

It seems that what we really want is something like:

  signal a,b,c,d,x : std_logic;
  x <= LUT((a and b) xor ( c and (not d)));

but that is beyond the language.  The nearest I have managed is:

   LU1: VLut4 generic map ( ExprStr => "((I0*I1)@(I2*~I3))" )
              port map (I0=>a, I1=>b, I2=>c, I3=>d, O=>x );

which evaluates x <= (a and b) xor ( c and (not d));


VLut4 is the this entity:

-- =========================================================== --
entity VLut4 is generic(ExprString  : string := "(I0*I1*I2*I3)" );
                port   (I0,I1,I2,I3 : in  std_logic := '0';
                        O           : out std_logic);
end VLut4;

architecture struct of VLut4 is
    attribute xc_map of struct : architecture is "lut";
    constant LutBits  : bit_vector(0 to 15) := VExprEval(ExprString);
    signal   AddrBits : std_logic_vector(3 downto 0);
    signal   Addr     : integer range 0 to 15;
begin
    AddrBits <= (I3, I2, I1, I0);
    Addr     <= to_integer( AddrBits );
    O        <= to_stdulogic(LutBits(Addr));
end struct;
-- =========================================================== --

Which works as like this:
  1. the 16-bit constant (A.K.A. the LUT contents) is evaluated
     (once only) via the function VExprEval().
  2. the incoming signals are catenated and used to index into
     LutBits, which is pretty efficient for simulation.

The xc_map is probably not needed as just about any reasonable synth
will map a 16-bit ROM to a LUT.  I hope.

The tricky part is constructing VExprEval().  What I do is this:
  1. convert ExprString to a reverse polish (RP) equivalent.
  2. scan through the RP 16 times, with the 16 possible values of the
     input vector.  Each scan fills in 1 bit of the LUT constant.

Here is the function:

-- =========================================================== --
    -- calculate the 16-bit INIT string corresponding to an arbitrary
    -- function of I0..I3.
    -- the operators are
    --    op      priority (0=lowest)
    --    (       0                       left paren
    --    +       1                       OR
    --    *,@     2                       AND,XOR
    --    ~       3                       NOT
    --    Ix      4                       one of the I0..I3 variables
    --
    -- the method is to
    --   convert the infix expression to a postfix (reverse polish) string
    --   evaluate the RP for all 16 possible sets of Ix
    --
function VExprEval( s : string; DEBUG : boolean := false) return bit_vector is
      variable r: bit_vector(0 to 15);
      variable iInputStr: integer;
      variable I0,I1,I2,I3: boolean;
      type TRps is array (0 to 100) of character;
      variable Rps    : TRps;       -- reverse polish (RP) string
      variable RpsLen : integer;

      type TPri is array (0 to 15) of integer;        -- priority
      type TStk is array (0 to 15) of character;      -- stack
      variable Pri    : TPri;
      variable Stk    : TStk;
      variable StkLen : integer;
      variable Priority: integer;

      type TEStack is array (0 to 15) of boolean;
      variable EStack  : TEStack;
      variable ELen    : integer;
      variable EResult : boolean;
      variable iRps    : integer;

      variable ch      : character;
      variable Obuff   : string (1 to 80);
      --synthesis translate_off
      variable Lout    : line;
      --synthesis translate_on

  begin

      --synthesis translate_off
      if DEBUG then
        write(Lout, "Input string : ");
        write(Lout, s);
        writeline(OUTPUT, Lout);
      end if;
      --synthesis translate_on

      -- first build the Reverse Polish sequence
      RpsLen := 0;
      iInputStr := 1;
      StkLen := 0;

      SCAN_LOOP: for iInputStr in s'low to s'high loop

        -- crude GetToken() routine
        ch := s(iInputStr);
        next SCAN_LOOP when ch=' ';     -- skip spaces
        next SCAN_LOOP when ch='I';     -- I0/I1/I2/I3

        -- prioritise token
        case ch is
          when '('              => Priority := 0;
          when '+'              => Priority := 1;
          when '*'|'@'          => Priority := 2;
          when '~'              => Priority := 3;
          when '0'|'1'|'2'|'3'  => Priority := 4;
          when others           => Priority := 99;
        end case;

        -- evaluate token
        case ch is
          when '(' =>
            Stk(StkLen) := ch;
            Pri(StkLen) := Priority;
            StkLen := StkLen+1;
          when '+'|'*'|'@'|'~' =>
            while (StkLen /= 0) and (Priority <= Pri(StkLen-1)) loop
              StkLen := StkLen-1;               -- pop TOS to RP string
              Rps(RpsLen) := Stk(StkLen);
              RpsLen := RpsLen+1;
            end loop;
            Stk(StkLen) := ch;                  -- then push this operator
            Pri(StkLen) := Priority;
            StkLen := StkLen+1;
          when '0'|'1'|'2'|'3' =>               -- variable
            Rps(RpsLen) := ch;
            RpsLen := RpsLen+1;
          when ')' =>
            RBLOOP: loop
              if StkLen=0 then                  -- unexpected all done
                report "Unexpected unmatched ')' in input string.";
                exit RBLOOP;
              elsif Stk(StkLen-1)='(' then      -- pop and discard
                StkLen := StkLen-1;
                exit RBLOOP;
              else
                StkLen := StkLen-1;             -- pop TOS to RP string
                Rps(RpsLen) := Stk(StkLen);
                RpsLen := RpsLen+1;
              end if;
            end loop;
          when others =>
            report "Unexpected token in source string: " & ch;
        end case;
      end loop;

      if StkLen /= 0 then
        report "Unexpected end of input string. Unparsed characters remain.";
      end if;
      Rps(RpsLen) := '.';                       -- add an 'end' flag
      RpsLen := RpsLen+1;

      --synthesis translate_off
      if DEBUG then
        write(Lout, "RP string is : ");
        for iRps in 0 to RpsLen-1 loop
          Obuff(iRps+1) := Rps(iRps);
        end loop;
        write(Lout, Obuff(1 to RpsLen));
        writeline(OUTPUT, Lout);
      end if;
      --synthesis translate_on

      -- evaluate the reverse polish for 0..15
      for i in 0 to 15 loop
        I0 := ((i  ) rem 2)=1;
        I1 := ((i/2) rem 2)=1;
        I2 := ((i/4) rem 2)=1;
        I3 := ((i/8) rem 2)=1;
        ELen := 0;
        iRps := 0;
        EX_LOOP: loop
          ch := Rps(iRps);
          iRps := iRps+1;
          case ch is
            when '~' =>
              EStack(ELen-1) := not EStack(ELen-1);
            when '+' =>
              EStack(ELen-2) := EStack(ELen-1) or EStack(ELen-2);
              ELen := ELen-1;
            when '*' =>
              EStack(ELen-2) := EStack(ELen-1) and EStack(ELen-2);
              ELen := ELen-1;
            when '@' =>
              EStack(ELen-2) := EStack(ELen-1) xor EStack(ELen-2);
              ELen := ELen-1;
            when '0' => EStack(ELen) := I0; ELen := ELen+1;
            when '1' => EStack(ELen) := I1; ELen := ELen+1;
            when '2' => EStack(ELen) := I2; ELen := ELen+1;
            when '3' => EStack(ELen) := I3; ELen := ELen+1;
            when '.' =>                         -- all done
              EResult := EStack(ELen-1);
              exit EX_LOOP;
            when others =>
              report "Unexpected token in RP string: " & ch;
          end case;
        end loop;

        if EResult then r(i) := '1';
                   else r(i) := '0';
        end if;
      end loop;

      --synthesis translate_off
      if DEBUG then
        write(Lout,"INIT(15..0) is : ");
        for i in 0 to 15 loop
          if r(i)='1' then Obuff(16-i) := '1';
                      else Obuff(16-i) := '0';
          end if;
        end loop;
        write(Lout, Obuff(1 to 16));
        writeline(OUTPUT, Lout);
      end if;
      --synthesis translate_on

      return r;

  end VExprEval;
-- =========================================================== --






Article: 35143
Subject: Re: Clockin on rising AND falling edge
From: przemek <przemek@nist.gov>
Date: Mon, 24 Sep 2001 05:23:59 GMT
Links: << >>  << T >>  << A >>
Peter Alfke <peter.alfke@xilinx.com> writes:

> You first have to generate a double-frequency clock.
> It's easy and uses only one ff, one inverter,and one XOR:
> Feed the input frequency into the XOR, feed the other input of the XOR together
> with the D input of the flip-flop from the inverted Q output of that flip-flop.
> Then use the XOR output to clock the flip-flop, and also use the XOR as the
> double-frequency output.

This circuit seems to make short ones of a single FF delay length.
How is it better than a simple XOR gate fed with the input clock and a
negated input clock (or an odd number of inverters, in a row)? 

-- 
przemek Klosowski (przemek@nist.gov) tel 301/975-6249

Article: 35144
Subject: Re: Clockin on rising AND falling edge
From: Peter Alfke <palfke@earthlink.net>
Date: Mon, 24 Sep 2001 05:45:42 GMT
Links: << >>  << T >>  << A >>
I think it is safer, since it includes the toggling of a flip-flop. So the pulse
will never be so short that it does not toggle a flip-flop.
And also, it is no more expensive than the basic circuit you describe. Flip-flops
are cheap  :-)

Peter Alfke, Xilinx Applications
==================================
przemek wrote:

> Peter Alfke <peter.alfke@xilinx.com> writes:
>
> > You first have to generate a double-frequency clock.
> > It's easy and uses only one ff, one inverter,and one XOR:
> > Feed the input frequency into the XOR, feed the other input of the XOR together
> > with the D input of the flip-flop from the inverted Q output of that flip-flop.
> > Then use the XOR output to clock the flip-flop, and also use the XOR as the
> > double-frequency output.
>
> This circuit seems to make short ones of a single FF delay length.
> How is it better than a simple XOR gate fed with the input clock and a
> negated input clock (or an odd number of inverters, in a row)?
>
> --
> przemek Klosowski (przemek@nist.gov) tel 301/975-6249


Article: 35145
Subject: Coefficient scaling question
From: dottavio@ised.it (Antonio)
Date: 24 Sep 2001 00:17:28 -0700
Links: << >>  << T >>  << A >>
Good Morning
I'm developing a QPSK passband modulator for my thesis, on it I use a
37 taps polyphase SRRC filter for each branch of the transmission 

	delay              = 3              ;       
	roll_off           = 0.35           ;       
	input_rate_SRRC    = 27.5e6	    ;       
	output_rate_SRRC   = 165e6          ;       
	num_fir = rcosine( input_rate_SRRC , output_rate_SRRC, 'fir/sqrt',
roll_off, delay);
	data_out_SRRC_tx_I = rcosflt(data_in_SRRC_tx_I, input_rate_SRRC ,
output_rate_SRRC , 'filter' , num_fir);
	data_out_SRRC_tx_Q = rcosflt(data_in_SRRC_tx_Q, input_rate_SRRC ,
output_rate_SRRC , 'filter' , num_fir);


on the receiving pat I use the same 37 taps SRRC filter but without
interpolate nor decimate, simply
	data_out_SRRC_rx_I = filter(num_fir, 1 , data_in_SRRC_rx_I);
	data_out_SRRC_rx_Q = filter(num_fir, 1 , data_in_SRRC_rx_Q);


My problem is that when I compare the simbol transmitted to the symbol
received, the first symbols are not good,
this is due to the answers of the filters, looking at the two sequence
I can see that the shift between them is
of 10 bits so 5 symbols for a QPSK modulator but how I can determine
this in a not empirical way ??



By the way another question, with this code matlab produce a 37 taps
filter that is not well suited for an FPGA
implementation of the polyphase filter, it is better to have 36 for an
SRRC that have to interpolate 6 otherwise
I've to put inside other coefficients of value zero until I arrive to
a total number of taps that is multiple of 6.
How I can do it with Matlab ??

I also try to use systolix to design this filter and it seems OK, the
only problem is that the coefficients are
between about -0.2 and +0.2 , in my design I use 2's complement, 1 bit
for the sign and 11 bits for the fractional part,
no bit for the integer part, to better use this range can I scale the
coefficients ?? This could give me some problem ??



Thanks in any case ...

				Antonio D'Ottavio

Article: 35146
Subject: Re: Clockin on rising AND falling edge
From: Jim Granville <jim.granville@designtools.co.nz>
Date: Mon, 24 Sep 2001 20:53:22 +1200
Links: << >>  << T >>  << A >>
Peter Alfke wrote:
> 
> I think it is safer, since it includes the toggling of a flip-flop. So the pulse
> will never be so short that it does not toggle a flip-flop.
> And also, it is no more expensive than the basic circuit you describe. Flip-flops
> are cheap  :-)
> 
> Peter Alfke, Xilinx Applications
> ==================================
> przemek wrote:
> 
> > Peter Alfke <peter.alfke@xilinx.com> writes:
> >
> > > You first have to generate a double-frequency clock.
> > > It's easy and uses only one ff, one inverter,and one XOR:
> > > Feed the input frequency into the XOR, feed the other input of the XOR together
> > > with the D input of the flip-flop from the inverted Q output of that flip-flop.
> > > Then use the XOR output to clock the flip-flop, and also use the XOR as the
> > > double-frequency output.
> >
> > This circuit seems to make short ones of a single FF delay length.
> > How is it better than a simple XOR gate fed with the input clock and a
> > negated input clock (or an odd number of inverters, in a row)?

 Also, some tools will optimise out the redundant inverters, unless 
watched carefully :-)
 
 You can, of course, add a 'delay line' in the Q->XOR path, and so
widen the pulse, if desired. 

-jg

Article: 35147
Subject: Re: Complex mixer LUT
From: "Noddy" <g9731642@campus.ru.ac.za>
Date: Mon, 24 Sep 2001 11:20:05 +0200
Links: << >>  << T >>  << A >>
Something happened to the data I generated between the spreadsheet and the
configuration file. I copied across 5 rows of 200 elements each, but the
rows split up somehow, and so the orders wre mixed up.

adrian


> Do tell!
>
> Chris
> --
> Chris Eilbeck                             mailto:chris@yordas.demon.co.uk
> MARS Flight Crew                                  http://www.mars.org.uk/
> UKRA #1108 Level 1                                                   BSMR
>



Article: 35148
Subject: comp.arch.fpga : Unusual clock divider ckt
From: "Ted Moreno" <>
Date: Mon, 24 Sep 2001 08:01:36 -0700
Links: << >>  << T >>  << A >>
I want to design unusual clock dividers in a Virtex FPGA. I have a 
slow clock (in couple of Hz) and I want to make 16  clock dividers <br>   with equal increments. For example if the input clock in 4Hz, I want to have clock dividers from 0.25Hz, 0.5Hz, 0.75Hz, 1Hz, 1.25Hz ..........3.25Hz, 3.5Hz, 3.75Hz.

I can use binary counter 16 for 0.25, 0.5, 1, 2 Hz clocks. What would be the best way for other freq.? 

It would be easy if I can get 50% duty cycle, but if not what are the other ways of doing this?
Any advice would be greatly appreciated

-Ted

Article: 35149
Subject: Re: comp.arch.fpga : Unusual clock divider ckt
From: Peter Alfke <peter.alfke@xilinx.com>
Date: Mon, 24 Sep 2001 08:58:10 -0700
Links: << >>  << T >>  << A >>
What you are trying to do can only be done with a phase-locked-loop, or by dividing down from a very high frequency.
Digital circuits do not work in the frequency domain, they work in the time domain. If you look at the 16 different period you want to generate, you see that they do not share edges.
Why do you want to do this? Thre may be a simpler way to achieve you goal...

Peter Alfke

Ted Moreno wrote:

> I want to design unusual clock dividers in a Virtex FPGA. I have a
> slow clock (in couple of Hz) and I want to make 16  clock dividers <br>   with equal increments. For example if the input clock in 4Hz, I want to have clock dividers from 0.25Hz, 0.5Hz, 0.75Hz, 1Hz, 1.25Hz ..........3.25Hz, 3.5Hz, 3.75Hz.
>
> I can use binary counter 16 for 0.25, 0.5, 1, 2 Hz clocks. What would be the best way for other freq.?
>
> It would be easy if I can get 50% duty cycle, but if not what are the other ways of doing this?
> Any advice would be greatly appreciated
>
> -Ted




Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarApr2017

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search