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Messages from 34575

Article: 34575
Subject: Re: Version Control
From: "Tim" <tim@rockylogic.com.nospam.com>
Date: Wed, 29 Aug 2001 21:20:43 +0100
Links: << >>  << T >>  << A >>

"Austin Franklin" quoted from someone else:
> >  I don't use Schem for Logic Entry, ( as lack of conditional compile
> > is a 'killer', as well as poor handling of Table, Condition and State
> > designs ), but do use it a lot for PCB design.
>

I am designing an array of FF1517 Virtex2 parts and using mostly VHDL for
the PCB design, lightly tied together with schematics.  The sheer pain,
and consequent error rate, when doing these big parts in schematic...

A picture had better be worth a thousand words, because that's how long
it takes to draw.





Article: 34576
Subject: Urgent Please
From: "Abhimanyu Rastogi" <abhi_rastogi@hotmail.com>
Date: Wed, 29 Aug 2001 20:28:25 GMT
Links: << >>  << T >>  << A >>

hello all,

I need a /rdy flag (bit) such that it stays high only until the last
data_word[7..0] bit is written and after that /rdy flag should go low
and should enable the new_clk and the DATA_OUT and as soon as
all 22 bits are clocked out on DATA_OUT... /rdy should go back high and
new_clk and DATA_OUT should stop as well...

Does ne one has ne clue how to establish this /rdy bit or flag???
Here is the part of the code where its used...  (code is in AHDL)


--Hi Band I/O pins
band_out[2..0], new_clk, DATA_OUT                      :OUTPUT;

data_word[21..0]   :DFFE;
band[2..0]    :DFFE;
pll_sel     :DFFE;
new_clk     :DFFE;
count[4..0]    :DFFE;
/rdy     :DFFE;
new_word[21..0]   :DFFE;
DATA_OUT    :DFFE;

 /rdy.clk = in_clk;
 --/rdy.ena = p186_sel[UP_HCTRL] & p186_read;
 /rdy = !count4.q;
 (pll_sel,band[], data_word[], new_word[]).clk = in_clk;
 new_clk.ena = !/rdy;
 new_clk.clk = in_clk;
 new_clk = !new_clk;
 DATA_OUT.clk = new_clk;
 count[].clk = in_clk;
 (new_word[21..16], data_word[21..16]).ena = p186_write &
p186_sel[UP_HDATA2];
 (new_word[15..8], data_word[15..8]).ena = p186_write & p186_sel[UP_HDATA1];
 (new_word[7..0], data_word[7..0]).ena = p186_write & p186_sel[UP_HDATA0];

 pll_sel.ena = p186_sel[UP_HCTRL] & p186_write;
 band[].ena = p186_sel[UP_HCTRL] & upad[3] & p186_write;
 band[2..0].d = upad[2..0];
 band_out[2..0] = band[2..0];
    pll_sel = upad[4];

 (new_word[21..16], data_word[21..16]).d = upad[5..0];
 (new_word[15..8], data_word[15..8]).d = upad[7..0];
 (new_word[7..0], data_word[7..0]).d = upad[7..0];


 --serial output of data_word[] to the synth
 IF count[] == 22 THEN
  count[] = GND;
 ELSE
  count[] = count[] + 1;
  new_word[21..0] = (new_word[20..0], new_word[21]);
  DATA_OUT = new_word[0];
 END IF;


Thanks
Abhimanyu Rastogi






Article: 34577
Subject: Re: star-wars ascii-animation:)
From: Ben Franchuk <bfranchuk@jetnet.ab.ca>
Date: Wed, 29 Aug 2001 14:57:50 -0600
Links: << >>  << T >>  << A >>
Ron Huizen wrote:
> 
> Great beer cooler, but I think he should make some use of all that
> wasted heat - maybe a combo beer cooler, hot dog roaster ...

Na! fryed chicken and de-feather-or attachment. Ben.
-- 
Standard Disclaimer : 97% speculation 2% bad grammar 1% facts.
"Pre-historic Cpu's" http://www.jetnet.ab.ca/users/bfranchuk
Now with schematics.

Article: 34578
Subject: Model sim vhdl simulation crash
From: jtai@3dsp.com (Jack Tai)
Date: 29 Aug 2001 14:19:42 -0700
Links: << >>  << T >>  << A >>
Hi,
I am running testbench under Modelsim SE 5.5c. Somehow, the modelsim
program is been closed when I run the simulation to a fix place. The
only message before the program close is the text message in the
Transcription file.
run 400
# 
# Problem with simulator...  vsim U/I closing. (1)
# 
# 
# Problem with simulator...  vsim U/I closing. (2)
# 
Can anyone tell me ? Is any way or command that will force Modelsim to
tell me more message or reason about the crash ? Or, anyone know why
crash ? I have try same simulation under different version of
modelsims and different computers.

Thank you

Article: 34579
Subject: Re: download bitstream to FPGA
From: Alan Nishioka <alann@accom.com>
Date: Wed, 29 Aug 2001 14:37:46 -0700
Links: << >>  << T >>  << A >>
Neil Franklin wrote:

> Alan Nishioka <alann@accom.com> writes:
>
> > However,  the format is pretty simple.  It uses keys and lengths to
> > divide the file.
> >
> > 1 byte                  key 0x65
> > 2 bytes                 length 0x000c9090
> > 8233440 bytes     raw bit stream starting with 0xffffffff aa995566 sync
> > word documented below.
>
> There is at least one error in that. The config data comes in 3
> chunks: CLBs+IOBs+BRAMctrl, and then 2 columns of BRAMdata (for
> standard Virtex that is, more BRAMdata chunks for V-E and V-EM).

I don't see the error.  What I am describing is the format of the .bit file
that bitgen produces.  What XAPP151 describes is the format of the bit stream
that is part of that file.

Alan Nishioka
alann@accom.com



Article: 34580
Subject: Re: Xilinx FPGA Editor - how to route to an internal macro net?
From: arast@inficom.com (Alex Rast)
Date: Wed, 29 Aug 2001 22:22:26 GMT
Links: << >>  << T >>  << A >>
In article <3b8b9869.9160001@news.compuserve.com>, 101551.3434@compuserve.com (Mark Taylor) wrote:
>On Mon, 27 Aug 2001 20:09:17 GMT, arast@inficom.com (Alex Rast) wrote:
>
>>In article <3b86ed56.46990212@news.compuserve.com>, 101551.3434@compuserve.com
> (Mark Taylor) wrote:
>>>On Fri, 24 Aug 2001 00:19:48 GMT, arast@inficom.com (Alex Rast) wrote:
>>>
>>>>This is one I think I've done before, so I probably just need my memory 
>>>>jogged. I'm sure it's something that happens, and that you need, all the
> time.
>>>>
>>>>I've defined a hard macro, call it custommacro.nmc. .... Now, at least one
> of the nets connects to an 
>>>>external pin and an internal route. One common example, for instance, is
> CLK. 
>>>>You want the signal to be common to the internal CLB's of the macro and to 
>>>>connect to external routes (in the case of CLK, to the global clock net). 
>>>
>>>As far as I know, nets could never be included in hard macros.
>>>(despite documentation suggesting otherwise, right back to before EPIC)
>>
>>No, I have no problem including a net in a macro. What I have difficulty doing
>>is routing an external net *to* the macro's internal net.
>>
>>>Just use the hard macro to configure slices/CLBs or whatever,
>>>then embed the macro within a soft macro
..
>>I don't think this would work, for 2 reasons. First, I *have* to have a 
>>specific routing within the hard macro (indeed, the routing itself is a key 
>>part of the design), so I can't afford to let the software take care of any 
>>routing at the hardware level. Second, a lot of the things we're doing are 
>>functions you simply can't enter properly in Schematic Editor...
>Get rid of any general purpose routing within your hard macro.
>Keep all interconnections within a CLB. (These doesn't really count as nets at
>a low level)

I don't think I can do that because some of the nets are both general-purpose 
to the design and special-purpose to the macro. In other words, we have 
logic-to-logic connections within the macro that also connect to nets going 
between macros. And the connections within the macro are routing-sensitive.

>Ensure the number of macro pins is enough to complete all needed routing.

I *hope* I've done that, except if you mean that the number of macro pins must 
include a separate pin for *each* separate input of a high-fanout net in which 
case it's a pretty hopeless task.

>Now you will have a hard macro, with perhaps somewhat more pins than you had
>before.
>When you instantiate this macro you will be able to complete ALL routing.
>(there won't be any strange nets for the software to complain about.)
>This approach has worked for me in the past.
>Bear in mind that the router is usually pretty good.

IME it actually sucks rather than being pretty good, because it fails to 
consider routing strategies like multi-drop nets or symmetric "bank-shot" nets 
among other things. Again, it seems to work via a "one resource, one 
connection" strategy. Again, for giggles, I experimented with a program-routed 
net against my hand-routed net for the same design. I tested it with a design 
occupying 6 CLB's. My manually routed version created a symmetrical route 
using only the routing resources adjacent to the CLB's in use, while the 
program's version implemented the routing in an asymmetric net over resources 
adjacent to CLB's in a 12-row 7-column (84-CLB) block centered on the 6. 
 
>It's just the mapping & placement that sometimes needs working on.
>The mapping & placement is totally defined by the given approach, so
>theres nothing much to foul up on afterwards. (unlike the M1 software)
>If you don't like the routing around an instance of the macro you can still 
>change it.
>The routing will generally be optimal, unless you have RAMs
>within your macro.

Given the results of my little test, it was clearly not optimal - and the 
design I tested it on didn't have RAMs.

> You can pretend (with very great care) that the RAMS are
>LUTs , which will allow excellent routing. You will then have to patch the RAMS
>back in later (perhaps using fpga_editor ,  or XDL if you have a large number
>of instances.)
>Note that XST (VHDL) sometimes doesn't keep RLOCS.
>This is a bug that I have recently complained about.
>If you are not using XST , you should have no problems.

I should make it very clear that the design I have has to be very carefully 
fitted together like a jigsaw puzzle. I have to design the *shape* and exact 
configuration of the routing resources for each macro I have, so that I won't 
be stymied by either lack of an available specific resource or inability to 
abut a macro against another because of space versus shape restrictions in the 
CLB, in the overall design.

Does any of this make any sense or am I bringing up needless issues?

Alex Rast
arast@inficom.com
arast@qwest.net

Article: 34581
Subject: Virtex II sizing rule of thumb
From: jennifer.koehler@exchange.sp.trw.com (Jen)
Date: 29 Aug 2001 15:57:29 -0700
Links: << >>  << T >>  << A >>
I am curious to know from any Virtex II users what they have typically
found
to be their %LUTs used and %Flip-Flops used.  I have a design and I am
trying to pick the correct part.  I am pretty sure how many FFs I will
be using..but a little weary on my estimates on combinational logic. 
I would feel better knowing ratios others have found

Article: 34582
Subject: Re: Urgent Please
From: John_H <johnhandwork@mail.com>
Date: Wed, 29 Aug 2001 23:16:13 GMT
Links: << >>  << T >>  << A >>
Some general comments to start off with:

Notice that new_word is set in two places.  I believe AHDL logically ORs
multiple equations together.

Notice that your new_clk will be at half the rate of your in_clk yet your
counter is running at the in_clk rate and your DATA_OUT at the new_clk.

The suggestion I gave you the other day had the counter load hooked in with the
transfer of (in the case of your code below) data_word to new_word.

Since you appear to want to shift out the data only once with your /rdy signal
as a gate, you can use the start condition to preload the counter and the
counter completion to end the whole process.

You had the right initial idea with the /rdy value - using the counter's MSbit
but you need to 1) increase the counter size by a bit [5..0] and 2) treat the
load and/or count a little differently;  alternatively you can leave the counter
simple and add the /rdy in with the start and edn conditions.  You want the
start event to 1) load the new_word, 2) clear the /rdy, and 3) initialize the
counter.  You want the end condition to 4) set the /rdy and 5) stop the counter
from counting.

If you choose to extend the counter, read on.  Given where you are in digital
design basics it might get a bit confusing.  The start and end conditions might
be a better way for you to code at this point.

One trick that most designers learn along the way is to preload a counter with a
set value and count from there until overflow.  Since Altera parts work nicely
with down counters, consider what the result would be if you load the new_word
and set a 6 bit DOWN counter to 21 on the same clock.  Bit 21 shows up at
new_word[21] and the count is 21 at the start condition.  As you clock through,
bit n shows up at new_word[21] when the count is n.  After bit 0 is shifted out
and the data is invalid (bit -1 ?) the count will underflow to -1 setting the
most significant bit of the count (you probably also want to stop counting once
you've gone past zero).  As long as the initial counter value is -1 (on power up
or at reset), the MSbit of the counter can be your /rdy flag.


Article: 34583
Subject: sharing a PROM between configuration and the FPGA
From: Muzaffer Kal <muzaffer@dspia.com>
Date: Wed, 29 Aug 2001 16:40:05 -0700
Links: << >>  << T >>  << A >>
hi,
I am looking at a design where I want to use the excess ROM area in a
spartan II prom to store some FPGA specific data. For this I need to
share the IOs of the PROM with the dedicated configuration IOs. The
configuration mode will be master serial. The main problem is to take
over the CCLK after configuration is done. I can't seem to find what
happens to CCLK at that point. Has anyone done this ? Any suggestions?

thanks,

Muzaffer


Article: 34584
Subject: Re: Ethernet CRC
From: "Tracy Briscoe" <tmb15@computerscience.waikato.ac.newzealand>
Date: Thu, 30 Aug 2001 15:03:15 +1200
Links: << >>  << T >>  << A >>
I'm trying to generate the CRC in hardware.  The problem that I've got is
that every combination that I've tried to generate the CRC, and place it in
a frame, comes back as invalid.  I've attached my vhdl testbench, in which I
doing all this. This is all part of a custom hardware project, that will
transmit and receive frames to and from Ethernet.

"Douglas Grant" <douglas.grant@xilinx.com> wrote in message
news:3B8D49A8.60A5A49E@xilinx.com...
> What do you want to do? Create some hardware? Software? Test your SW/HW?
>
> DG
>


begin 666 crc32test2.vhd
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`
end


Article: 34585
Subject: Re: download bitstream to FPGA
From: <khtsoi@pc90026.cse.cuhk.edu.hk>
Date: 30 Aug 2001 04:16:04 GMT
Links: << >>  << T >>  << A >>
Philip Freidin <philip@fliptronics.com> wrote:
> On 29 Aug 2001 03:07:42 GMT, <khtsoi@pc90026.cse.cuhk.edu.hk> wrote:
>>Thanks for the info. I am still looking for a way to download the bit file.

> This is documented in Xilinx data sheets, in Xilinx App Notes, and in
> the Xilinx on-line documentation. You couldn't ask for more. (well maybe
> you could, but I dont know why)

>>I just wondering if the file format is not open.

> While the exact details of what each bit in the bitstream represents is
> proprietory, you do not need this information to download a design into
> your FPGA. The bitstream is created by the P&R tools, and the resulting
> file can be copied into a serial or parallel EPROM/EEPROM, or saved
> on disk, or stored any other way. The documentation clearly describes
> the format of the data, and how it should be presented to the FPGA.

>>And nobody can do this except Xilinx and the licenced parties.

> Hardly !   All of Xilinx's tens of thousands of customers do this every day.

>>So sad. It's not possible to require the client to have a copy of
>>download program and the bit file can be changed s.t. cannot
>>stored in ROM.

> Well, this is just plain wrong. ( ? s.t. ?)

>>---- Brittle

> Philip
> Philip Freidin
> Fliptronics

Thank you all very much for the useful info. I have one more question.
Actually I know how to download using the JTAG pins. But once I check
the raw bit file, I found that there is some text string in the header
(e.g. Xilinx, xcv300, etc.). I just not sure if this should be downloaded
to the FPGA and for what? If I download the wrong data/header, will the
FPGA be demaged? For these questions, I just want to make sure it works
before actually perform the download. I cannot affort to demage the
proto board I am using :) anyway, thanks again

---- Brittle

Article: 34586
Subject: Re: download bitstream to FPGA
From: <khtsoi@pc90026.cse.cuhk.edu.hk>
Date: 30 Aug 2001 04:19:00 GMT
Links: << >>  << T >>  << A >>
>>So sad. It's not possible to require the client to have a copy of
>>download program and the bit file can be changed s.t. cannot
>>stored in ROM.

> Well, this is just plain wrong. ( ? s.t. ?)

s.t. = such that
forgive my poor English

---- Brittle

Article: 34587
Subject: XC2V3000-4BF957
From: jaideep@sasken.com (jaideep)
Date: 29 Aug 2001 22:32:17 -0700
Links: << >>  << T >>  << A >>
Hello,
We are working on schematic entry for the Virtex II device
XC2V3000-4BF957, but finding it difficult to enter manually.
It is time consuming to create this symbol as there are over
900 pins.
If someone has this symbol, we would appreciate very much
if they can pass on the symbol.We are using an older version
of Orcad which doesn't have the CIS feature, hence this
request.
Thanking in advance.
Jaideep

Article: 34588
Subject: Re: Version Control
From: hmurray-nospam@megapathdsl.net (Hal Murray)
Date: Thu, 30 Aug 2001 07:14:11 -0000
Links: << >>  << T >>  << A >>

>I am designing an array of FF1517 Virtex2 parts and using mostly VHDL for
>the PCB design, lightly tied together with schematics.  The sheer pain,
>and consequent error rate, when doing these big parts in schematic...

Write a program to "draw" the schematics for you.

This is a good example of why well documentated file formats is high on my
list of requirements for a good tool collection.

-- 
These are my opinions, not necessarily my employeers.  I hate spam.


Article: 34589
Subject: Re: download bitstream to FPGA
From: Philip Freidin <philip@fliptronics.com>
Date: Thu, 30 Aug 2001 00:32:22 -0700
Links: << >>  << T >>  << A >>
On 30 Aug 2001 04:16:04 GMT, <khtsoi@pc90026.cse.cuhk.edu.hk> wrote:
>Thank you all very much for the useful info. I have one more question.
>Actually I know how to download using the JTAG pins. But once I check
>the raw bit file, I found that there is some text string in the header
>(e.g. Xilinx, xcv300, etc.). I just not sure if this should be downloaded
>to the FPGA and for what?

You are right to question this. You should not download the header
information. If you go look at Alan Nishioka's article, he gives a good
description of the stuff in the file. The stuff that is the raw bit stream
    (from his article)

>1 byte                  key 0x65
>2 bytes                 length 0x000c9090
>8233440 bytes     raw bit stream starting with 0xffffffff aa995566 sync
>word documented below.

is the stuff for actual download. i.e. the first 32 bits are all '1' , then the
AA995566 sync word, then all the rest of the raw bit stream.

You may also find the following brilliant article of use, although it
is addressing a different issue.

    http://www.fpga-faq.com/archives/33100.html#33108

By the way, all this sync word stuff assumes you are working with
Spartan-II or one of the Virtex families. If it is any XC3K or XC4K or
Spartan device, the .BIT file format as described is still correct, but the
content of the raw bit stream section looks different, as it does not
have a sync word.

> If I download the wrong data/header, will the
>FPGA be demaged?

Yes, it could. But the reality is that (assuming S-II or V family device)
unless you have something that looks like the Sync Word in the data
that shouldn't be loaded, you will be ok, because it will never get into
the configuration state. Most of the header you are skipping is text,
and the sync word includes AA and 99, neither of wich occur in
normal 7 bit ASCII stored in 8 bit bytes. On the older XC3K and XC4K
products, there is protection, but not as good.

>For these questions, I just want to make sure it works
>before actually perform the download. I cannot affort to demage the
>proto board I am using :) anyway, thanks again
>
>---- Brittle

Philip Freidin
Fliptronics

Article: 34590
Subject: Re: Version Control
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Thu, 30 Aug 2001 09:15:51 +0100
Links: << >>  << T >>  << A >>


Hal Murray wrote:

> >I am designing an array of FF1517 Virtex2 parts and using mostly VHDL for
> >the PCB design, lightly tied together with schematics.  The sheer pain,
> >and consequent error rate, when doing these big parts in schematic...
>
> Write a program to "draw" the schematics for you.
>
> This is a good example of why well documentated file formats is high on my
> list of requirements for a good tool collection.

... and IMO all the files should either be text or have a text equivalent e.g.
Xilinx's .ncd/.xdl. A good counter example is FPGA Express where the report
files are in binary ??!

[Although the .xdl doesn't really pass the "well documented" test its not that
hard to decrypt and is pretty amenable to simple-minded Perl hacking].


Article: 34591
Subject: Big SR in Virtex-E
From: Michael Boehnel <boehnel@iti.tu-graz.ac.at>
Date: Thu, 30 Aug 2001 10:18:30 +0200
Links: << >>  << T >>  << A >>
I want to implement several big shift-registers with parallel load
(parallel to serial converter) in a Virtex-E. Beside these SRs I also
want to implement SRs with serial input and (big) parallel output.

The number of CLB FFs in the FPGA are limited (Rows x Columns x 4).

Is there a way to implement one of these SRs (parallel load or output!)
without using the CLBs FF's.
Can one of the synthesis tools manage this for me automatically(FPGA
Express, Synplify, ..)?

Michael


Article: 34592
Subject: Re: download bitstream to FPGA
From: <khtsoi@pc90026.cse.cuhk.edu.hk>
Date: 30 Aug 2001 09:03:14 GMT
Links: << >>  << T >>  << A >>

Hi,

I will test it asap. Thank you all. I will report
the results.

---- Brittle

Article: 34593
Subject: Re: Version Control
From: "Tim" <tim@rockylogic.com.nospam.com>
Date: Thu, 30 Aug 2001 11:28:00 +0100
Links: << >>  << T >>  << A >>

"Hal Murray" <hmurray-nospam@megapathdsl.net> wrote
>
> >I am designing an array of FF1517 Virtex2 parts and using mostly VHDL for
> >the PCB design, lightly tied together with schematics.  The sheer pain,
> >and consequent error rate, when doing these big parts in schematic...
>
> Write a program to "draw" the schematics for you.
>

I would rather write the netlist.  Looking at repetive schematics
of this size doesn't illuminate much.  The story is different for
stuff like power supplies.  We need an EE version of Don Knuth's
'literate programming'







Article: 34594
Subject: Re: Big SR in Virtex-E
From: "Tim" <tim@rockylogic.com.nospam.com>
Date: Thu, 30 Aug 2001 11:33:43 +0100
Links: << >>  << T >>  << A >>

"Michael Boehnel" <boehnel@iti.tu-graz.ac.at> wrote
> I want to implement several big shift-registers with parallel load
> (parallel to serial converter) in a Virtex-E. Beside these SRs I also
> want to implement SRs with serial input and (big) parallel output.
>
> The number of CLB FFs in the FPGA are limited (Rows x Columns x 4).
>
> Is there a way to implement one of these SRs (parallel load or output!)
> without using the CLBs FF's.

The Xilinx SRLs give you a x16 density gain.  They are serial-in/serial-out
so you need to play with the algorithm.

BRAMs can give you parallel load (x32) and serial out (x1) by using the
dual-port feature.

> Can one of the synthesis tools manage this for me automatically(FPGA
> Express, Synplify, ..)?

Synplify can.  And probably FGPA Express - check with Synopsys.
For funky stuff, instantiation is probably less trouble to you.






Article: 34595
Subject: WebPack Con-Game
From: "David Wright" <dwright@srtorque.com>
Date: Thu, 30 Aug 2001 07:15:19 -0500
Links: << >>  << T >>  << A >>
The "free" Xilinix Webpack should be classified as a Demo and not a real
system to do even realistic small designs.

By the time you install the design and even a small test vector, you easily
exceed the 500-line ModelSim Starter Design Limit.  There are even
limitations on Test Bench and probably other portions of the package.

Xilinx needs to stop misleading its customers and tell them what they really
need to know:

  What package is adequate to the design and what does it cost and will
actually work?  We also need something that is supported and does not
time-out before we are done with the design.

 To justify any design, the Engineer needs to know how much the tool will
cost beforehand and not in the "oh, by the way, if you need a real
system..."

Stop the deception - Xilinix





Article: 34596
Subject: Re: Version Control
From: "Austin Franklin" <austin@darkr99oom.com>
Date: Thu, 30 Aug 2001 08:20:15 -0400
Links: << >>  << T >>  << A >>
> >I am designing an array of FF1517 Virtex2 parts and using mostly VHDL for
> >the PCB design, lightly tied together with schematics.  The sheer pain,
> >and consequent error rate, when doing these big parts in schematic...
>
> Write a program to "draw" the schematics for you.
>
> This is a good example of why well documentated file formats is high on my
> list of requirements for a good tool collection.

ViewDraw has always been text based as far as I know.  Also, there are some
utilities that automate the symbol process at least.  One takes a PDF spec
sheet and creates a symbol for you.  One draws the symbol for a particular
function as well as the underlying schematics, placed and mapped...




Article: 34597
Subject: FPGA: time_sim.sdf does not have the setup times f
From: "Nisreen Taiyeby" <nisreen@blr.paxonet.com>
Date: Thu, 30 Aug 2001 05:29:43 -0700
Links: << >>  << T >>  << A >>
I am working with virtexE speed grade 8, xilinx alliance series with service pack 8.

When I generate the sdf file for timing simulation, the setup times for flops placed in the IOB is given as 271 ps which happens to be the setup for CLB flops too.

But the latest datasheets on VietexE device gives the IOB setup of 1.3 ns.

That means that my timing simulation is faulty.

Can anyone out there help me.

Regards,
Nisreen.

Article: 34598
Subject: Re: WinMe installation
From: G E Geiger <ggeiger@REMOVETHISairmail.net>
Date: Thu, 30 Aug 2001 09:17:41 -0500
Links: << >>  << T >>  << A >>
Has anyone tried the Xilinx download cable "Parallel III" on a Win ME
machine?  

I have installed the entire tool chain on my Win ME laptop and I can
get all parts working except this cable.  The Xilinx hotline said that
it was probably "noise" on the cable since this is a 900MHz machine
but that ME would not actually be supported until release 4.1 of the
Alliance tools.  

The cable works fine in the lab on a slower PC running Win 98 SE.

Could MS have actually messed up a parallel port going from 98 to ME?



On Tue, 14 Aug 2001 13:50:01 GMT, "Paul Teagle"
<pteagle@bigpond.net.au> wrote:

>I had a ME related problem a while ago (look back for some archive
>material - Xilinx solution 9253 was most appropriate).
>
>Basically, it was a problem with the path. Be careful how you attempt to
>modify the autoexec.bat file. You have to use the system utilities to
>modifiy, not just a text editor on the autoexec.bat files. There's registry
>issues involved.
>
>I've now got a problem with the ModelSim package not finding the design. Oh
>well...


Article: 34599
Subject: Re: Urgent Help Needed
From: "Jim E" <jim@e3c.2ndmail.com>
Date: Thu, 30 Aug 2001 07:35:36 -0700
Links: << >>  << T >>  << A >>
From 1) -  I don't know what you mean about the return key. Are you referring to the lack of use of returns in the body of my message? The box they gave me has "autowrap". I'll be happy to comply.

From 2) - Since I am using previously tested firmware to configure the XC4003E (in asynchronous peripheral mode) I assumed that a successful configuration process was a given. Maybe not. I thought that the cclk signal was generated by the part automatically. The difference in the hardware of this design and the design which works is the address decoding. In the successful design I had a free port pin from a microcontroller attached to CS1. That input was simply held high throughout the configuration process. The /CS0 input was controlled by an address line qualified by a RAM space select line. In the unsuccessful design the address line and the RAM CS line control CS1 and /CS0, respectively. The only difference in the firmware controlling the configuration is that in the successful design there is the delay involved in changing the state of the port pin (CS1) to low. Then the code loops until DONE goes active.

Both these designs use the XC4003E. I did not mean to imply that the two designs were different my original note. The reference in parentheses was abbreviated.

Further notes:

Some of the signals which do not function are "pass through" signals. In three places there are address lines used in the XC4003E for some decoding, but they also pass through the chip to output buffers and pads.

One output is the simple logic "OR" of an address line (inverted) and an I/O select line (low true). The output appears, but is only the inversion of the address line. 

A number of outputs are FDC blocks. These outputs are all stuck high after configuration, which certainly supports your premise about the missing cclk transitions at the end of the process.

I greatly appreciate your input on this. You may be right about the missing clocks at the end of the process. I'm just not yet aware of how to force a few extras, since in asynchronous peripheral mode the master generates the clocks.



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