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Messages from 34550

Article: 34550
Subject: Re: System Requirements
From: Nial Stewart <nials@britain.agilent.com>
Date: Wed, 29 Aug 2001 12:12:12 +0100
Links: << >>  << T >>  << A >>
Rick Filipkiewicz wrote:
> > Has anyone reading this had any experience with DDR Ram
> > with PAR tools?
> >
> > The thought of a 1.4G Athlon with >512M DDR Ram appeals :-).
> >
> > Nial.
> 
> I'm writing this on one right now - well 1.3G anyway. Its about 40% faster for
> both simulation [ModelSim-PE] and Xilinx P&R than my old PIII-650-PC100. The only
> problem with the one I've got is that it only has 2 DDR stick slots - its all we
> could find at the time but I think you can do better now that fast Athlon boxes
> have become more mainstream.


Can you judge if the DDR ram has any appreciable effect?

I'd have expected a 1.3G Athlon with PC133 memory to have been ~ 40% quicker 
than a PIII-650 anyway.

I can upgrade to a 1.4G processor on my current system fairly 
cheaply, but the step to DDR meory means a new motherboard and
replacing all the ram (obviously).


Nial.

Article: 34551
Subject: global VHDL signals and FPGA express
From: "Johan Ditmar" <johan.ditmar@nospam.celoxica.com>
Date: Wed, 29 Aug 2001 12:20:54 +0100
Links: << >>  << T >>  << A >>
Hello,

I have a problem with using global signals in VHDL. I would like to share a
signal between different entities. The way I tried to do this is by defining
the signal in a package and including this package in the different
entities. This seems to work well in simulation (modelsim), but not when
syntesizing using FPGA express.
An example VHDL using a global signal is given below. There are two
entities, test1 and test, that both use a signal called 'MyGlobal'. The top
entity is test, which should simply wire its input to its output. However,
when using FPGA express, signal MyGlobal is optimised away and the design is
empty. Does someone have a solution for this?

Thanks,

Johan Ditmar

--------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
PACKAGE globals IS

SIGNAL MyGlobal: std_logic;

END;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
library work;
use use work.globals.all;
ENTITY Test1 IS
PORT(
 OUTPUT: OUT std_logic;
);
END;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
library work;
use use work.globals.all;
ENTITY Test IS
PORT(
  INPUT: IN std_logic;
  OUTPUT: OUT std_logic
);
END;

ARCHITECTURE Behave OF Test1 IS

BEGIN
Output <= MyGlobal;
END

ARCHITECTURE Behave OF Test IS

COMPONENT Test1
PORT(
 OUTPUT: OUT std_logic;
);
END COMPONENT;

BEGIN

U1: Test1 PORT MAP (Output => Output);

MyGlobal <= Input;

END;




Article: 34552
Subject: Re: System Requirements
From: "H.L" <alphaboran@yahoo.com>
Date: Wed, 29 Aug 2001 14:46:47 +0300
Links: << >>  << T >>  << A >>
My design is a MAC controller, not too big but pretty complex. I am gonna
use a Xilinx Virtex family FPGA and i have heard that this type uses a lot
of system's memory and also needs about 2G of disk space.
Thank all for your info!

"Leon Heller" <leon_heller@hotmail.com> wrote in message
news:9mdvjc$2nh$1@plutonium.btinternet.com...
>
>
> "H.L" <alphaboran@yahoo.com> wrote in message
> news:9mcvnp$1r11$1@ulysses.noc.ntua.gr...
> > Hello all,
> > I am going to program a Xilinx FPGA for the first time. I wanna setup
the
> > synthesis tools on a pc, what must be the system's requirements for
proper
> > (and relatively fast) function?
> > Thanks
> >
> >
>
> It obviously depends on the size and complexity of your design. I find a 1
> GHz Athlon with 512 Mbytes of RAM works quite well with the Xilinx and
> Altera tools.
>
> Leon
> --
> Leon Heller, G1HSM leon_heller@hotmail.con
> http://www.geocities.com/leon_heller
> Low-cost Altera Flex design kit: http://www.leonheller.com
>
>
>
>



Article: 34553
Subject: beginner
From: connect_ananth@yahoo.com (ananth)
Date: 29 Aug 2001 05:42:19 -0700
Links: << >>  << T >>  << A >>
Hi,
I am a beginner... 

I would like to know the product cycle of FPGA and

 how important is the coding techniques/styles related to FPGA/ASIC.

In Warp we have lots of devices listed ...How to select it?.

And is it mandatory to know all the specification of each and every device? 

Where can we get the details?

Thanks for time/support
With best Wishes,
ananth

Article: 34554
Subject: Re: Defending Austin Franklin
From: Ivar <ivar@stantech.dk>
Date: Wed, 29 Aug 2001 05:45:49 -0700
Links: << >>  << T >>  << A >>
Hi

very interesting !

I've got hardware-background.

Maybe Xilinx could do an investigation among its customers about their background and what they prefer.

nb. i agree with Austin.

regards

Ivar

Article: 34555
Subject: Re: Urgent Help Needed
From: "Jim E" <jim@e3c.2ndmail.com>
Date: Wed, 29 Aug 2001 06:07:49 -0700
Links: << >>  << T >>  << A >>
I have an XC4003E design which configures correctly but doesn't function. Only two output signals of the twenty one actually appear. One other appears but it incorrect. All others remain high. This is a simple design, which is mainly a collection of glue logic, some address decoding and some signal multiplexing and clock division. Some of the signals simply pass through the array. In one case a chip select  output is supposed to be the  inversion of an address line qualified by an I/O chip select signal. But the output is just the inversion of the address line. 

The design is a schematic captured by Foundation F2.1i. Functional and timing simulations function correctly. But the hardware doesn't function. It's almost as though most of the outputs are disabled after configuration. But some are active, so even that premise doesn't hold. Since there is considerable checking of bit counts and CRC's during the configuration, I do not believe that there is a problem during configuration. This same part number (4003) and the drivers which configure it both work correctly in another design. Boundary scan is not used. 

Does anyone have a clue as to what may be the problem here? I will be glad to provide more details, if necessary

Article: 34556
Subject: Ethernet CRC
From: "Tracy Briscoe" <tmb15@computerscience.waikato.ac.newzealand>
Date: Thu, 30 Aug 2001 01:22:25 +1200
Links: << >>  << T >>  << A >>
Hi.

I've been fighting with Ethernet CRCs for to long now.  Could someone please
tell me how to generate a valid Ethernet CRC.  I'm using a function
generated by http://www.easics.be/webtools/crctool, that takes the data in
in 4bit nibbles at a time.

Thanks
-Tracy
ps replace computerscience with cs, and newzealand with nz when repling to
me.





Article: 34557
Subject: Re: global VHDL signals and FPGA express
From: AlexP <>
Date: Wed, 29 Aug 2001 06:30:11 -0700
Links: << >>  << T >>  << A >>
For all I know, there are no synthesis tools supported global signals. Several months ago I asked some vendors but they just plan to do this stuff.

Article: 34558
Subject: Re: Level sensitive latches in Xilinx Virtex
From: Chris Softley <c.i.softley@ncl.ac.uk>
Date: Wed, 29 Aug 2001 15:40:54 +0100
Links: << >>  << T >>  << A >>
Rick Filipkiewicz wrote:
> 
[SNIP]

> One thing you might want to consider is that, looking at the Verilog simprims
> model, it appears to have a min pulse width check for both high *and* low pulses.
> For simulation your glitch is probably triggering the timing check & sending the
> output to `X'. Only a data input change would then allow it to recover.

	This is exactly what we're seeing. I've had a look in X_LATCH.v and I
see what you mean.
 
> Now why a latch should need a PW-low check is an interesting question and might
> represent something physical.

	Well, it either represents an odd physical implementation of the
so-called latch, or it's a bug in the model.

	But if its a bug in the model, the bug carries over into sdf
backannotation, since the minimum low time specparam (PWCLKLO) has been
given a value by it. If they've gone to the effort of coming up with a
number for this minimum lowtime, then maybe it does somehow represent
something physical. This then represents a bug (or 'feature') in the
implementation of a level sensitive latch in Virtex. It's pretty
unlikely that such an issue would not have been found and fixed yet, and
it's hard to imagine how you could design a latch at the circuit level
that would behave in quite this way, but if it's done as some odd
modification of a D flip-flop (since the storage element in a slice is
configurable as either) then I guess it could just be possible.

	I plan to ask Xilinx support about this. Thanks for pointing me to the
verilog model. I'll let you know if I get anywhere...

Cheers,
	Chris

----------------------------------------------------------------------
chris softley,                phone: +44 (0)191 2225775
dept of electrical &          email: c.i.softley@ncl.ac.uk
electronic engineering,       computer arith/digital design/vhdl/dsp/
newcastle university, uk.     approximation/perl/c++/asic/fpga/lns...
   high speed logarithmic arithmetic: http://napier.ncl.ac.uk/hsla

Article: 34559
Subject: Re: Gate Count Definition
From: Austin Lesea <austin.lesea@xilinx.com>
Date: Wed, 29 Aug 2001 08:26:05 -0700
Links: << >>  << T >>  << A >>
Rick,

Since Peter is on vacation, I have to provide the "Peter" answer, that the gate count is whatever a particular industry feels is advantageous.

If you are an ASIC vendor, you reduce everything to a nand gates cause it looks good.

If you are an FPGA vendor, you reduce everything to LUT's and FF's, because that looks even better.

Bottom line, you must ask what someone is talking about.

When we say "million gate design" we are talking about the kind of designs being done for Virtex 1000, and 1000 E's.  Do they use a million gates?  I have no
clue.  But they certainly have piles of verilog or VHDL code, which instantiate Block RAMs, DLLs, LUTs, FFs, resulting in the entire device being from 80 to 95%
utilized in almost all of the cases I have looked at.

These same designs may also be targeted at ASIC's and compared with the result in Virtex.  These designs usually do end up using a million or more nand gates.
You could cry "foul" and be partially correct:  DLLs, BRAMs, shift register LUTs don't mao very well into nand gates, but then, which design ends up working
sooner?  The ASIC or the FPGA?  That one is easy, the FPGA not only gets done first, and can be modfied and changed as required.

Ever see anyone get a million gate ASIC right the first time?

Austin

Rick Filipkiewicz wrote:

> kahhean wrote:
>
> > Hi,
> >
> > What is the Xilinx's Definition of System Count and Logic Gate?
> >
> > E.g. the XCV400E (virtex-e) is documented to have 569,952 system gates and 129,600 logic gates.  What is the difference between system gate and logic gate?
> >
>
> The realistic answer is that on this NG at least these are generally known as ``marketing gates'' whose connection to reality is tenuous at best.
>
> >
> > When somebody says "I am working on a million gate design", is he referring to system gate or logic gate?
> >
> >
>
> Most likely the person would be referring to an ASIC gate count. An experienced FPGA designer would probably quote a device type & percent utilisation [unless
> they'd been got at by the Xilinx marketing dept.].


Article: 34560
Subject: Re: download bitstream to FPGA
From: Alan Nishioka <alann@accom.com>
Date: Wed, 29 Aug 2001 08:53:17 -0700
Links: << >>  << T >>  << A >>
I could not find the *.bit file explicitly documented anywhere.  I asked
this newsgroup and didn't get any responses.

However,  the format is pretty simple.  It uses keys and lengths to
divide the file.

2 bytes     length 0x0009 (big endian)
9 bytes     some sort of header (the length given above)
2 bytes     length 0x0001

1 byte      key 0x61
2 bytes     length 0x000a
10 bytes   string giving design name

1 byte      key 0x62
2 bytes     length 0x000c
12 bytes   string giving part name

1 byte       key 0x63
2 bytes      length 0x000b
11 bytes    string giving date

1 byte        key 0x64
2 bytes      length 0x0009
9 bytes      string giving time

1 byte                  key 0x65
2 bytes                 length 0x000c9090
8233440 bytes     raw bit stream starting with 0xffffffff aa995566 sync
word documented below.

Once you get the raw bits, XAPP138 "Virtex FPGA Series Configuration and
Readback" and XAPP139 "Configuration and Readback of Virtex FPGAs using
(JTAG) Boundary-Scan will tell you what to do with them.

Unfortunately, I don't know how to drive a DL4 cable.  My application is
embedded so I have direct access to the JTAG lines.

Alan Nishioka
alann@accom.com


khtsoi@pc90026.cse.cuhk.edu.hk wrote:

> Hi,
>
> I want to download a bitstream (*.bit file) to a Xilinx
> FPGA (e.g. xcv600) through a DB9 serial cable (model: DLC4).
> Must I use the tools provided by Xilinx? Is there any
> possibility I can write a segment of codes to do this in
> my application? Thanks in advnce!
>
> ---- Brittle


Article: 34561
Subject: Re: Urgent Help Needed
From: Mike Treseler <mike.treseler@flukenetworks.com>
Date: Wed, 29 Aug 2001 09:11:37 -0700
Links: << >>  << T >>  << A >>
Jim E wrote:
> 
> I have an XC4003E design which configures correctly but doesn't function. 
> Only two output signals of the twenty one actually appear.

Check the place and route pin assigment file.
Check what place and route did with unused i/o pins.

 --Mike Treseler

Article: 34562
Subject: Re: Any body used ACEX1K series for testing the design??
From: Mike Treseler <mike_dot_treseler@flukenetworks.com>
Date: Wed, 29 Aug 2001 09:22:52 -0700
Links: << >>  << T >>  << A >>
sadik khan wrote:
> 
> My design is very big(200k gate count) and i am porting it into the
> four ACEX chips. 

Are you simulating all four 
designs as separate entities?

Did you verify the interconnections
on the circuit board?

Have you considered making a board
with a single apex or virtex device?

  --Mike Treseler

Article: 34563
Subject: Re: global VHDL signals and FPGA express
From: Mike Treseler <mike_dot_treseler@flukenetworks.com>
Date: Wed, 29 Aug 2001 09:42:04 -0700
Links: << >>  << T >>  << A >>
Johan Ditmar wrote:
> 
> Hello,
> 
> I have a problem with using global signals in VHDL. 
> I would like to share a
> signal between different entities. 

For synthesis you need a top entity with
its "global" signals mapped to ports
of other instansiated entities.

Packaged signals are legal vhdl,
however I don't know of a synth
that can handle them.

 --Mike Treseler

Article: 34564
Subject: Re: Defending Austin Franklin
From: Richard Dungan <postmaster@[127.0.0.1]>
Date: Wed, 29 Aug 2001 18:17:50 +0100
Links: << >>  << T >>  << A >>
Ivar <ivar@stantech.dk> wrote:

>Hi
>
>very interesting !
>
>I've got hardware-background.
>
>Maybe Xilinx could do an investigation among its customers about their background and what they prefer.
>
>nb. i agree with Austin.

I have a hardware background and I agree with Austin as well. I have
produced designs in schematic and VHDL (Xilinx target devices).

I wonder if one of the things that works in favour of schematics is that
the tools are much more highly evolved, over a long period of time.

Richard

------------Richard Dungan-------------
Radix Electronic Designs, Orpington, UK
   richardATradixDASHdesignDOTcoDOTuk
    Web page: www.radix-design.co.uk
---------------------------------------

Article: 34565
Subject: Re: Logic Emulation
From: Ben Franchuk <bfranchuk@jetnet.ab.ca>
Date: Wed, 29 Aug 2001 12:03:51 -0600
Links: << >>  << T >>  << A >>
Falk Brunner wrote:
> 
> Tim schrieb:
> >
> >    Gated clocks in ASICs, less common in FPGAs
> 
> AHHHHH, there it is again, the ugly word.
> 
> GATED CLOCKS!!!
> 
> Jehova, Jehova, Jehova. ;-))
> 
> Can someone tell, how common they truely are? Are there special tecnics
> that simpifies verification of gated clocks?
> 
> --
> MFG
> Falk
Just remember your FPGA dedicated clock lines are limited.
Ben.
-- 
Standard Disclaimer : 97% speculation 2% bad grammar 1% facts.
"Pre-historic Cpu's" http://www.jetnet.ab.ca/users/bfranchuk
Now with schematics.

Article: 34566
Subject: Re: Urgent Help Needed
From: Philip Freidin <philip@fliptronics.com>
Date: Wed, 29 Aug 2001 11:09:27 -0700
Links: << >>  << T >>  << A >>
1) You need to learn to use the return key when posting articles.

2) The XC4003 and the XC4003E are different parts. The 4003E is a
superset of the 4003.

If you compile a design for a 4003, it should load and run in a 4003E
If you compile a design for a 4003E, it may not run correctly in a 4003.

Check the following: are the paths that seem to work purely combinatorial
logic, but the ones that fail include flip flops. If this is the case, then the
problem is that although DONE has gone high, the startup state machine
has not finished, and you need a few more config clocks.

for example:

   http://www.fpga-faq.com/archives/22825.html#22828

   http://www.fpga-faq.com/archives/23475.html#23491

Hope this helps

Philip Freidin

On Wed, 29 Aug 2001 06:07:49 -0700, "Jim E" <jim@e3c.2ndmail.com> wrote:
>I have an XC4003E design which configures correctly but doesn't function. Only two output signals of the twenty one actually appear. One other appears but it incorrect. All others remain high. This is a simple design, which is mainly a collection of glue logic, some address decoding and some signal multiplexing and clock division. Some of the signals simply pass through the array. In one case a chip select  output is supposed to be the  inversion of an address line qualified by an I/O chip select signal. But the output is just the inversion of the address line. 
>
>The design is a schematic captured by Foundation F2.1i. Functional and timing simulations function correctly. But the hardware doesn't function. It's almost as though most of the outputs are disabled after configuration. But some are active, so even that premise doesn't hold. Since there is considerable checking of bit counts and CRC's during the configuration, I do not believe that there is a problem during configuration. This same part number (4003) and the drivers which configure it both work correctly in another design. Boundary scan is not used. 
>
>Does anyone have a clue as to what may be the problem here? I will be glad to provide more details, if necessary

Philip Freidin
Fliptronics

Article: 34567
Subject: Re: Level sensitive latches in Xilinx Virtex
From: Philip Freidin <philip@fliptronics.com>
Date: Wed, 29 Aug 2001 11:15:26 -0700
Links: << >>  << T >>  << A >>
On Wed, 29 Aug 2001 15:40:54 +0100, Chris Softley <c.i.softley@ncl.ac.uk> wrote:
>Rick Filipkiewicz wrote:
>> 
>[SNIP]
>
> 
>> Now why a latch should need a PW-low check is an interesting question and might
>> represent something physical.
>
>	Well, it either represents an odd physical implementation of the
>so-called latch, or it's a bug in the model.

Yes it is real. There is a min pulse width that can be reliably distributed
through the clock tree. The check is for that limit.

>	But if its a bug in the model, the bug carries over into sdf
>backannotation, since the minimum low time specparam (PWCLKLO) has been
>given a value by it. If they've gone to the effort of coming up with a
>number for this minimum lowtime, then maybe it does somehow represent
>something physical.

yep.

>This then represents a bug (or 'feature') in the
>implementation of a level sensitive latch in Virtex. It's pretty
>unlikely that such an issue would not have been found and fixed yet, and
>it's hard to imagine how you could design a latch at the circuit level
>that would behave in quite this way, but if it's done as some odd
>modification of a D flip-flop (since the storage element in a slice is
>configurable as either) then I guess it could just be possible.
>
>	I plan to ask Xilinx support about this. Thanks for pointing me to the
>verilog model. I'll let you know if I get anywhere...
>
>Cheers,
>	Chris
>
>----------------------------------------------------------------------
>chris softley,                phone: +44 (0)191 2225775
>dept of electrical &          email: c.i.softley@ncl.ac.uk
>electronic engineering,       computer arith/digital design/vhdl/dsp/
>newcastle university, uk.     approximation/perl/c++/asic/fpga/lns...
>   high speed logarithmic arithmetic: http://napier.ncl.ac.uk/hsla

Philip Freidin
Fliptronics

Article: 34568
Subject: Atmel JTAG cable
From: Sosgez <bacon@sosgez.co.uk>
Date: Wed, 29 Aug 2001 19:26:03 +0100
Links: << >>  << T >>  << A >>
Does anyone know how I can build a JTAG lead for use with ATMELs CPLD
software for ATF15xx series?   I understand there is very little in a
standard lead, but the signal lines are inverted thru 74HC14.  

I guess its something like the following, which I have made up off the
top of my head.

TMS = NOT D25.Pin2 (D0)
TCK =  NOT D25.Pin3 (D1)
TDI  =  NOT D24.Pin4  (D2)
D25.Pin13 (SEL?)  = NOT TDI

There may be a few other pins, I've no idea what tho.

Sosgez


Article: 34569
Subject: Re: Defending Austin Franklin
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Wed, 29 Aug 2001 20:12:31 +0100
Links: << >>  << T >>  << A >>


Austin Franklin wrote:

> > > > Seriously this does raise the point that with logic synth tools you
> are at
> > > > the mercy of the tool Vendor for bug fixing and/or getting logic
> > > > optimisation right whereas with schems all the bugs are down to the
> user
> > > > (?!).
> > >
> > > And you are at their mercy for changing the results of the synthesis
> between
> > > tool revisions!
> > >
> >
> > Again I would say that I don't really care if the result meets timing &
> fits in
> > my chosen device. The trick here is not to change tool versions unless you
> have
> > to i.e. to fix a really critical bug. I always keep the last version
> available
> > [and the last 3 in the pre-install .exe file form] so I can always go back
> just
> > by pointing the make file at it.
>
> What if you upgraded the synthesis tools for one project, but it changed
> something for you in another project, and now you don't make timing?  You
> can't always go back, unless you uninstall the new tools and re-install the
> old tools...especially if they use environment variables or registry
> settings.
>

The *second* key to sane HDL design is to choose a tool that works purely from
the command line & uses no registry settings. I would put it even more strongly
than that - if a tool does do this sort of thing then it should be rejected. Env
variables you can over-ride in the makefile.

>
> I'll repeat.  The KEY to "correct" synthesis is to have a document that
> states precisely what the output of the synthesis tool is for any given
> input.  This makes the process deterministic.  That is what schematics
> offer, synthesis does not.
>

IMO determinism at the gate level is not necessary. All you need is:

o The design fits into a device that makes economic sense.

o it meets timing.

o it works. [thank Jim].

o it gets OTD & into customers hands before some other company grabs the market.




> I am hearing that something that I (and a number of others) have been doing
> quite successfully is somehow believed to be a major problem for others.
> Also, that there are major "holes" in schematic tools, yet these purported
> holes don't exist, at least to those of us who actually use the tools.  It
> sounds more to me like some people have been convinced, IMO wrongly so, that
> HDLs are the "correct" way to do logic design, and any other way is, at
> best, wrong.  What scares me about this isn't engineering.  Engineering is
> about evaluating alternatives...not about being glued to one "method" simply
> for comfort and security.
>

If I were convinced that schems would get me to where I want to go as fast as
HDL then I'd probaby use them, but I'm not so convinced.

>
> I am curious if quite a number of HDL coders came from a software
> background, instead of a hardware engineering background, and an HDL feels
> more "familiar" to them, so it is good (to them, that is).  It feels that
> way.  Obviously, the HDL companies have done their marketing job well to
> convince so many people that (in a monotonic chant) "synthesis is best, all
> else is evil".  I am not saying there is anything wrong with synthesis, I
> own Synplify, and use it...it is a very good tool, but the lack of
> flexibility and understanding (and good engineering sense) simply amazes me.

My bg is pure h/w and I can remember the sheer, beyond nightmare, awfulness of
doing ASICs [more esp ASIC macro libs] with schem packages in the mid 1980s ...
almost as bad was designing PCBs in schems with huge numbers of TTL parts.
Watching the s/w guys  forge ahead with `C' while I was stuck with something
more primitive than machine code pissed me off something cronic.

My road-to-Damascus was the discovery of ABEL and, simultaneously, the RCS
revision control system.


Article: 34570
Subject: Re: System Requirements
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Wed, 29 Aug 2001 20:21:42 +0100
Links: << >>  << T >>  << A >>


Nial Stewart wrote:

> Rick Filipkiewicz wrote:
> > > Has anyone reading this had any experience with DDR Ram
> > > with PAR tools?
> > >
> > > The thought of a 1.4G Athlon with >512M DDR Ram appeals :-).
> > >
> > > Nial.
> >
> > I'm writing this on one right now - well 1.3G anyway. Its about 40% faster for
> > both simulation [ModelSim-PE] and Xilinx P&R than my old PIII-650-PC100. The only
> > problem with the one I've got is that it only has 2 DDR stick slots - its all we
> > could find at the time but I think you can do better now that fast Athlon boxes
> > have become more mainstream.
>
> Can you judge if the DDR ram has any appreciable effect?
>
> I'd have expected a 1.3G Athlon with PC133 memory to have been ~ 40% quicker
> than a PIII-650 anyway.
>
> I can upgrade to a 1.4G processor on my current system fairly
> cheaply, but the step to DDR meory means a new motherboard and
> replacing all the ram (obviously).
>
> Nial.

Firsly for the big P&R and simulation task the system is pretty much memory bounded.
Hence the step from 450MHz -> 1.3GHz probably wins very little. As evidence stepping up
from 450->650 gained 2-5%. I think that almost all the improvement comes from memory
speed.

Second. I was being a bit unfair to the Athlon since the P&R ratio for my test design
is 56min:38min i.e. 1.47:1 for the PIII-650 vs. the Athlon.


Article: 34571
Subject: Re: Ethernet CRC
From: Douglas Grant <douglas.grant@xilinx.com>
Date: Wed, 29 Aug 2001 20:59:36 +0100
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
--------------F315E435748716769A0AABBF
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

What do you want to do? Create some hardware? Software? Test your SW/HW?

DG

--------------F315E435748716769A0AABBF
Content-Type: text/x-vcard; charset=us-ascii;
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Content-Transfer-Encoding: 7bit
Content-Description: Card for Douglas Grant
Content-Disposition: attachment;
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begin:vcard 
n:Grant;Douglas
tel;work:+44-131-666-2600x235
x-mozilla-html:FALSE
org:Xilinx Inc.
adr:;;;;;;
version:2.1
email;internet:Douglas.Grant@xilinx.com
title:Staff Design Engineer
x-mozilla-cpt:;30608
fn:Dr. Douglas Grant
end:vcard

--------------F315E435748716769A0AABBF--


Article: 34572
Subject: Re: Version Control
From: Jim Granville <jim.granville@designtools.co.nz>
Date: Thu, 30 Aug 2001 08:01:36 +1200
Links: << >>  << T >>  << A >>
Austin Franklin wrote:
> 
> >  I don't use Schem for Logic Entry, ( as lack of conditional compile
> > is a 'killer', as well as poor handling of Table, Condition and State
> > designs ), but do use it a lot for PCB design.
> 
> I've never missed "conditional compile", so it's hardly been a "killer" for
> me...but what problem do you have with tables, condition and state designs?
> Perhaps you can give an example.  I do table driven stuff all the time.

 How about things like 7 segment font displays, for LED/LCD (table), and 
saturating Up/Dn counters, for example.
 Some non-graphical entry is needed for this ?

<paste> I'll repeat.  The KEY to "correct" synthesis is to have a
document that
> states precisely what the output of the synthesis tool is for any given
> input.  This makes the process deterministic.  That is what schematics
> offer, synthesis does not.
> 

<paste> I am not saying there is anything wrong with synthesis, I
> own Synplify, and use it...it is a very good tool, but the lack of
> flexibility and understanding (and good engineering sense) simply amazes me.

 True. The examples I have seen of VHDL 'hiccups' make it what I'd 
call a 'request language', deterministic it is not.

 It school report card should read 'Works only when watched' :-)

-jg

Article: 34573
Subject: Re: Version Control
From: "Austin Franklin" <austin@dar98kroom.com>
Date: Wed, 29 Aug 2001 16:10:43 -0400
Links: << >>  << T >>  << A >>

> > but what problem do you have with tables, condition and state designs?
> > Perhaps you can give an example.  I do table driven stuff all the time.
>
>  How about things like 7 segment font displays, for LED/LCD (table), and
> saturating Up/Dn counters, for example.
>  Some non-graphical entry is needed for this ?

No, not that I know of...I've done both of those, and I don't recall much
problem...especially with the large RAMs on the later parts ;-)




Article: 34574
Subject: Re: download bitstream to FPGA
From: Neil Franklin <neil@franklin.ch.remove>
Date: 29 Aug 2001 22:17:39 +0200
Links: << >>  << T >>  << A >>
Alan Nishioka <alann@accom.com> writes:

> However,  the format is pretty simple.  It uses keys and lengths to
> divide the file.
>
> 1 byte                  key 0x65
> 2 bytes                 length 0x000c9090
> 8233440 bytes     raw bit stream starting with 0xffffffff aa995566 sync
> word documented below.

There is at least one error in that. The config data comes in 3
chunks: CLBs+IOBs+BRAMctrl, and then 2 columns of BRAMdata (for
standard Virtex that is, more BRAMdata chunks for V-E and V-EM).

The basic structure of the bitstream format is documented in:
XAPP151   Virtex Series Configuration Architecture User Guide
http://www.xilinx.com/xapp/xapp151.pdf

The info there is even enough to read out and alter LUT and BRAM data
bits and regenerate the CRCs.


> Once you get the raw bits, XAPP138 "Virtex FPGA Series Configuration and
> Readback" and XAPP139 "Configuration and Readback of Virtex FPGAs using
> (JTAG) Boundary-Scan will tell you what to do with them.

Both are a good read.
http://www.xilinx.com/xapp/xapp138.pdf
http://www.xilinx.com/xapp/xapp139.pdf

--
Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/
Hacker, Unix Guru, El Eng HTL/BSc, Sysadmin, Archer, Roleplayer
- Intellectual Property is Intellectual Robbery



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