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Messages from 29475

Article: 29475
Subject: Re: Virtex E:Sample price
From: Peter Alfke <peter.alfke@xilinx.com>
Date: Thu, 22 Feb 2001 13:26:03 -0800
Links: << >>  << T >>  << A >>


Eric Smith wrote:

> > The -6 would be about half that price...
>
> Speaking of which, why are the speed grades -5 and -6?

Virtex has speed grades -4, -5,and -6
Virtex-E has -6,-7. and -8
Virtex-II lists -4,-5, and -6 today, expect faster once we are in volume
production.

In my opinion, these are just numbers, the higher the number, the faster.

I have long given up trying to see a physical significance.

Xilinx started with the noble idea of designating parts by max toggle rate (
-30, -50, -70, but users misread that as systems clock rate promise, and
attacked us for the "exaggeration" ( today, we would have to call the fastest
Virtex-II " -850" )

Then we changed to prop delay in ns through a look-up table, starting with -5
down to -1 and then -9, meaning 0.9 ns. Now we are at 0.4 ns, so that didn't
work either.

Now we just use numbers without any physical meaning. But larger again means
faster and more expensive, you can rely on that.

Peter Alfke, Xilinx Applications



Article: 29476
Subject: Re: Programming Altera CPLD?
From: Brian Goudy <briangoudy@earthlink.net>
Date: Thu, 22 Feb 2001 23:09:47 GMT
Links: << >>  << T >>  << A >>
If you use the JTAG pins for programming they cannot be used
for user I/O. If you're stuck with your current pinout you will
need the MPU programmer, which unfortunatly has been phased
out by Altera. Sorry I couldn't be more help.

Brian Goudy


"Jon S." wrote:

> Well, I need the pins that are assigned to be JTAG pins in the "S" chips to
> be user I/O.  So then if I configure an "S" device that way, does that mean
> that I lose the JTAG programmability?
>
> Brian Goudy wrote in message <3A94BFAF.965F8172@earthlink.net>...
> >Hi Jon,
> >
> >As far as I've seen you need an Altera MPU programmer. I would
> >recommend getting an EPM7032S device that can be programmed
> >in circuit.
> >
> >Brian Goudy


Article: 29477
Subject: Announcement of MVSIS release
From: Yunjian William Jiang <wjiang@eecs.berkeley.edu>
Date: Thu, 22 Feb 2001 15:43:56 -0800
Links: << >>  << T >>  << A >>
MVSIS is a program modeled after SIS (a binary logic optimization
program for hardware), but the logic network it works  on can have
all its variables multi-valued each with its own range. Included 
are all the technology-independent logic transformations of SIS for
combinational logic synthesis (but extended to multi-values) 
as well as transformations specific to multi-valued nodes such as
merge, pair_decode, encode, elim_part, print_part_value, print_range,
reset_default. MVSIS is interactive and has been made to have the 
look and feel of SIS. MVSIS can read and write BLIF-MV
files (used by VIS) with the read_blifmv and write_blifmv commands,
or read BLIF files (used by SIS) with the read_blif command.


To find out more about it and possibly download it or look at
documentation,
go to
    http://www-cad.eecs.berkeley.edu/Respep/Research/mvsis/

We welcome potential users and feedback on the use and potential
applications of MVSIS.

This is release 0.9 of MVSIS. The current release includes a binary
executable for Redhat Linux 6.1 (or Linux kernel 2.2.x and glibc 2.1).


--
The MVSIS group
University of California, Berkeley
mvsis-devel@ic.eecs.berkeley.edu

Article: 29478
Subject: Re: Virtex II availability
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Thu, 22 Feb 2001 23:46:50 +0000
Links: << >>  << T >>  << A >>


Mark wrote:

> Hi,
>
> Does anybody have any information on the expected availability of the Virtex
> II family, especially the 6000 part?

Probably depends on who you work for.



Article: 29479
Subject: Re: Virtex USB solution
From: "Simon Bacon" <simonb@tile.demon.co.cuthis.uk.>
Date: Fri, 23 Feb 2001 00:15:26 -0000
Links: << >>  << T >>  << A >>

"Andy Peters noao [.] edu>" <"apeters <"@> wrote in message
news:973ib2$fdq$1@noao.edu...

> I think doing USB in a big Virtex part is exactly the wrong thing to
do.

And the Virtex start-up current could be a problem is you plan
on being bus-powered.




Article: 29480
Subject: Re: Virtex E:Sample price
From: "Simon Bacon" <simonb@tile.demon.co.cuthis.uk.>
Date: Fri, 23 Feb 2001 00:18:16 -0000
Links: << >>  << T >>  << A >>

"Peter Alfke" <peter.alfke@xilinx.com> wrote in message
news:3A9557D0.F17DE8B1@xilinx.com...
> It is, because you are asking for the fastest speed grade.
> The -6 would be about half that price...
>

AFAIK it used to be approx 10% to 20% extra per speed
grade improvement.  Is it now 25% to 40%?



Article: 29481
Subject: Partial reconfig
From: JAneja@nuron.com ("Jaimeet Aneja")
Date: 23 Feb 2001 01:31:00 +0100
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.

------=_NextPart_000_011C_01C09CEB.5CCFE530
Content-Type: text/plain;
	charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable

I need help in trying to partially reconfigure a Virtex FPGA.
how do I=20
1. generate partial reconfig bitstreams ?
2. fix the in-out nets of modules so that they can be replaced by a new =
module and still line up perfectly with the rest of the design.


------=_NextPart_000_011C_01C09CEB.5CCFE530
Content-Type: text/html;
	charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable

<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META content=3D"text/html; charset=3Diso-8859-1" =
http-equiv=3DContent-Type>
<META content=3D"MSHTML 5.00.3103.1000" name=3DGENERATOR>
<STYLE></STYLE>
</HEAD>
<BODY bgColor=3D#ffffff>
<DIV><FONT face=3DArial size=3D2>I need help in trying to partially =
reconfigure a=20
Virtex FPGA.<BR>how do I <BR>1. generate partial reconfig bitstreams =
?<BR>2. fix=20
the in-out nets of modules so that they can be replaced by a new module =
and=20
still line up perfectly with the rest of the=20
design.<BR></FONT></DIV></BODY></HTML>

------=_NextPart_000_011C_01C09CEB.5CCFE530--


-- 
Posted from mail.nuron.com [63.100.168.245] 
via Mailgate.ORG Server - http://www.Mailgate.ORG

Article: 29482
Subject: Re: Partial reconfig
From: Kent Orthner <korthner@hotmail.nospam.com>
Date: 23 Feb 2001 10:16:10 +0900
Links: << >>  << T >>  << A >>
JAneja@nuron.com ("Jaimeet Aneja") writes:
> I need help in trying to partially reconfigure a Virtex FPGA.
> how do I=20
> 1. generate partial reconfig bitstreams ?
> 2. fix the in-out nets of modules so that they can be replaced by a new =
> module and still line up perfectly with the rest of the design.


I highly suggest getting the JBits package from Xilinx.

i haven't actually used it to do anything yet, but after 
reading through the documentation and everything that came 
with it, I understand the partial configuration thing much better.


http://www.xilinx.com/products/jbits/index.htm

(You have to send an email to the address on that 
web page to get it.)

HTH,
-Kent

Article: 29483
Subject: programmable coefficient fir filter?
From: wayne <tiderhuang@yahoo.com>
Date: Thu, 22 Feb 2001 17:28:12 -0800
Links: << >>  << T >>  << A >>
Hi,
I need 32-tap, 16-bit data, 14-bit coefficient fir filter at 100MHz, the coefficient can change on the fly, and 4 such filters can fit into 1 FPGA chip. Please give me some help! Thank you very much.

Article: 29484
Subject: Re: PCI : Not booting on ASUS
From: Sosgez <bacon@sosgez.co.uk>
Date: Fri, 23 Feb 2001 02:26:47 +0000
Links: << >>  << T >>  << A >>
On Thu, 22 Feb 2001 05:06:24 -0800, "James Wallis"
<james.wallis@centurionworld.com> pondered the meaing of life while
writing:

>We have developed a PCI 33/32 device, works correctly on all systems we have tested on, except 3 different ASUS motherboards.
>On these systems the motherboard never starts the power on self tests. 
>The core is loaded but system halts.

I had problems like this too, varying with chipset on the mobo.
e.g.  If my PCI card requested a memory region in the <1MB region.

You can also get problems where the region cannot be allocated - due
to insufficient suitable free space, and another problem where the
region is cached.  I spent a lot of time going through different
chipset datasheets and emails with Intel.

None of these problems showed up when the <1MB restriction was
removed.

Sosgez


Article: 29485
Subject: Re: Virtex USB solution
From: "Felix Bertram" <fbertram@gmx.net>
Date: Fri, 23 Feb 2001 09:30:31 +0100
Links: << >>  << T >>  << A >>
George,

Trenz Electronic developed a USB Function Controller as a commercial product
at a very reasonable price point. There is a datasheet as well as an
application note including a behavioral model and testbench available for
free- after completing our registration form.

We have implemented the core in a Xilinx Spartan device (less than 200
CLBs). Furthermore I am currently finalizing a new application note
implementing USB, an 8051 derivative, glue logic and firmware in a single
XV300 (XESS' XSV300 development board). If you are interested in this
application note, please contact me directly and I will be happy to send you
further details.

Implementing USB in an FPGA does make sense- even from the price point of
view. If you are looking for Spartan-II devices you can meet a price point
quite close to the Cypress chips. You will gain a lot more flexibility,
especially when streaming high datarates.


Hope this helps,
best regards

Felix Bertram
_____
Dipl.-Ing. Felix Bertram
Trenz Electronic
Duenner Kirchweg 77
D - 32257 Buende
Tel.: +49 (0) 5223 41652
Fax.: +49 (0) 5223 48945
Mailto:felix.bertram@trenz-electronic.de
http://www.trenz-electronic.de




Article: 29486
Subject: Re: programmable coefficient fir filter?
From: Phil James-Roxby <jamespb@xilinx.com>
Date: Fri, 23 Feb 2001 09:01:34 +0000
Links: << >>  << T >>  << A >>


wayne wrote:
> 
> Hi,
> I need 32-tap, 16-bit data, 14-bit coefficient fir filter at 100MHz, the coefficient can change on the fly, and 4 such filters can fit into 1 FPGA chip. Please give me some help! Thank you very much.

Assuming you are not changing the coefficients too often, use a look-up
table based multiplier (KCM or some sort of distributed arithmetic),
with the tables stored in RAM.  There are a ton of resources on these
sort of multipliers on the Xilinx web site for starters.
Phil

Article: 29487
Subject: Re: Partial reconfig
From: Phil James-Roxby <jamespb@xilinx.com>
Date: Fri, 23 Feb 2001 09:09:23 +0000
Links: << >>  << T >>  << A >>
> Jaimeet Aneja wrote:
> 
> I need help in trying to partially reconfigure a Virtex FPGA.
> how do I
> 1. generate partial reconfig bitstreams ?

Use the Jbits run-time reconfiguration (JRTR) API

> 2. fix the in-out nets of modules so that they can be replaced by a
> new module and still line up perfectly with the rest of the design.

Ermm, there in lies the rub.  When you hand over your design to the
mainstream implementation tools, you are basically telling them to make
single, optimised, static version of your design.  The tools are free to
do things like move blocks of logic around to achieve this goal.  Most
people just want a version of their design that a. meets timing
requirements and b. uses enough resources to justify the size of chip.
Even if you work at the lowest level and hand place each primitive LUT
and FF, the tools will still conspire against you in order to meet
timing, and do things like swap address lines into the look-up tables. 
Similarly routes will pass through the middle of the module you wish to
swap out.
AFAIK, the only tool that will help you out here is JBits, allowing you
total control over placement and mapping, and also allow run-time
routing of your modules. This allows cooperation with other parts of
your design, allowing your new module to talk to the same parts of the
circuit the previous module did.
Drop us a line at jbits@xilinx.com and we can sort you out.  
Phil

Article: 29488
Subject: UCF mode for Emacs?
From: Nicolas Matringe <nicolas.matringe@IPricot.com>
Date: Fri, 23 Feb 2001 10:20:58 +0100
Links: << >>  << T >>  << A >>
Hi
I was wondering if someone had a 'UCF' (Xilinx constraint format, for
those who wouldn't know) mode for Emacs before I try and make one
myself.

-- 
Nicolas MATRINGE           IPricot European Headquarters
Conception electronique    10-12 Avenue de Verdun
Tel +33 1 46 52 53 11      F-92250 LA GARENNE-COLOMBES - FRANCE
Fax +33 1 46 52 53 01      http://www.IPricot.com/

Article: 29489
Subject: Help : Question about Synopsis
From: "mygenie" <mygenie@icu.ac.kr>
Date: Fri, 23 Feb 2001 18:43:22 +0900
Links: << >>  << T >>  << A >>
I use synopsis for synthesis.

It takes 6 to 7 hours for one synthesis?

I revised one line in vhd file.

Should I perform the synthesis step taking 6 to 7 hours agian?

Can I use the synthesis I have performed before so that I can go through
with the steps quicker?



Article: 29490
Subject: Re: Help : Question about Synopsis
From: "Simon Bacon" <simonb@tile.demon.co.cuthis.uk.>
Date: Fri, 23 Feb 2001 11:44:19 -0000
Links: << >>  << T >>  << A >>

What a long time.  How big is the target device?

To use partial resynthesis you need to (obviously)
separately compile the lower-level modules to separate
EDIF files.  Then define the lower level modules as
black boxes to the top level.  In VHDL this becomes

  attribute black_box of abcdef: component is true;

In Verilog insert the appropriate comment.  The Xilinx
tools tie all the EDIF files together.  The lower-level
compilation/EDIF modules need not be a single source module.

There used to be a bug in one of the tools such that
this would only work if the black box modules had names
which were all lower-case.

It goes without saying that you will sacrifice inter-module
optimisation if you adopt this approach.

Another tip: if you are not already with Synplicity...


"mygenie" <mygenie@icu.ac.kr> wrote in message
news:975bjq$p4r$1@green.kreonet.re.kr...
> I use synopsis for synthesis.
>
> It takes 6 to 7 hours for one synthesis?
>
> I revised one line in vhd file.
>
> Should I perform the synthesis step taking 6 to 7 hours agian?
>
> Can I use the synthesis I have performed before so that I can go
through
> with the steps quicker?
>
>



Article: 29491
Subject: Is anybody using Quicklogic PCI/FPGA devices?
From: Alan Hall <alan@[127.0.0.1]>
Date: Fri, 23 Feb 2001 11:44:29 +0000
Links: << >>  << T >>  << A >>
I will shortly be starting a new design with the intention of using the 
Quicklogic combined FPGA and PCI interface devices. There seems to have 
been little or no discussion of these parts on this group, and I'm not 
sure if this is a good sign or not. Does anyone have anything good or 
bad to say about these devices, the development tools, technical support 
etc? In fact has anyone actually used them?
-- 
Alan Hall, Ipswich, UK

Article: 29492
Subject: Re: UCF mode for Emacs?
From: Utku Ozcan <ozcan@netas.com.tr>
Date: Fri, 23 Feb 2001 13:50:39 +0200
Links: << >>  << T >>  << A >>
Nicolas Matringe wrote:

> Hi
> I was wondering if someone had a 'UCF' (Xilinx constraint format, for
> those who wouldn't know) mode for Emacs before I try and make one
> myself.

Also is there any *.vim file for UCF to be used in Vim?

Utku




Article: 29493
Subject: how do i?
From: W.Turk <kgut@dotuy.com>
Date: Fri, 23 Feb 2001 04:06:14 -0800
Links: << >>  << T >>  << A >>
Hi:
  i generate a fifo with BlockRam by
CoreGen in Foundation3.1,but how i do  initial? Can anyone give me a example of 511x32 fifo with Verilog Language?
  thanks

Article: 29494
Subject: Re: programmable coefficient fir filter?
From: "Wolfgang Loewer" <wolfgang.loewer@elca.de>
Date: Fri, 23 Feb 2001 13:13:58 +0100
Links: << >>  << T >>  << A >>
If it's a commercial project you might want to give the Altera FIR Compiler
2.0 a try. You can find the user guide at
http://www.altera.com/literature/ug/fircompiler_ug.pdf . The FIR Compiler
supports variable coefficient filters and also allows to trade speed for
area. It should just be a question of size whether it's doable or not. You
can also test drive the FIR compiler free of charge and determine whether
you can fit 4 such filters into a single chip.

Regards
Wolfgang


wayne <tiderhuang@yahoo.com> wrote in message
news:ee6fc71.-1@WebX.sUN8CHnE...
> Hi,
> I need 32-tap, 16-bit data, 14-bit coefficient fir filter at 100MHz, the
coefficient can change on the fly, and 4 such filters can fit into 1 FPGA
chip. Please give me some help! Thank you very much.



Article: 29495
Subject: UCF mode for vim (Re: UCF mode for Emacs?)
From: gyles@whars07h.savanna (Gyles Harvey)
Date: 23 Feb 2001 13:53:08 GMT
Links: << >>  << T >>  << A >>
In article <3A964E8F.FCFFD600@netas.com.tr>,
Utku Ozcan  <ozcan@netas.com.tr> wrote:
>Also is there any *.vim file for UCF to be used in Vim?

Here's a proto-vim file, with a few of the most common words.

" Vim syntax file
" Language:	ucf - Xilinx User Constraints File

" Remove any old syntax stuff hanging around
syn clear
" ucf syntax is not case sensitive?
" syn case match

syn keyword	shTodo		contained TODO
syn match	shComment		"#.*$" contains=shTodo

" A bunch of useful sh keywords
syn keyword shStatement    NET TIMESPEC PERIOD MHz HIGH LOW TIMEGRP BEFORE
syn keyword shStatement    LOC CONFIG PROHIBIT TNM FROM TO AFTER OFFSET IN OUT

hi link shStatement		Statement
hi link shComment		Comment

let b:current_syntax = "ucf"

" vim: ts=8

I'm sure there's plenty of scope for improvement.

Gyles.

-- 
gyles@nortelnetworks.com
All opinions expressed are my own, not those of Nortel Networks.

Article: 29496
Subject: Getting started
From: "Dmitri Katchalov" <dmitrik@my-deja.com>
Date: Fri, 23 Feb 2001 14:54:29 GMT
Links: << >>  << T >>  << A >>
Hi,

I want to get started with programmable logic.
I have this idea for my first project. It's a motor 
controller for a toy robotic arm. 

All I want is to produce 5 independent PWM signals to drive 
5 DC motors (using L293E H-bridges) and decode 5 quadrature 
encoders . I also want SPI, I2C or similar serial bus control interface.

What to you think, is it OK for a first-time project?
If yes, can you suggest a suitable device?

It is a one-off hobby project so I'd prefer something in DIP
package, easy reprogrammable (in-circuit preferably) and 
with free development tools.

Also I just started with Verilog/VHDL but I think I already 
have 3 different solutions for the PWM part: one using 
magnitude comparator another using identity comparator 
and a flip-flop and yet another using a separate counter. 
Which one is better?

Your suggestions / references / links are welcome.

Thanks,
Dmitri



Article: 29497
Subject: Searching for FPGA designer (PCI interface,DES, IDE)
From: AvdL <erikl80@nospam.hotmail.com>
Date: Fri, 23 Feb 2001 16:20:38 +0100
Links: << >>  << T >>  << A >>
Dear Sir/Madam,

We (Argolis) are a small company that develops smartcard technology.
For our new project we need a PCI card that communicates with our
reader (RS232-protocol). We want to place a FPGA on the PCI board that
communicates with the smartcard reader, the computer (PCI) and IDE
port. The FPGA must also be able to do DES. It would be nice if the
FPGA also could handle compression of the data. The last option is not
necessary. 
Please contact us if your are interested in this project. We will
provide the hardware and we ask from you to develop the source for the
FPGA.

Kind regards,
Argolis

Ad van de Laar

email to : info<at>argolis<dot>nl

Article: 29498
Subject: ERROR on Xilinx fundation
From: "Seb C" <Seb@stien.bizland.com>
Date: Fri, 23 Feb 2001 16:34:49 GMT
Links: << >>  << T >>  << A >>
hi,

i obtained this error message :

ERROR:baste:314 - NCD was not produced. All logic was removed from design.
This
   is usually due to having no input or output PAD connections in the design
and
   no nets or symbols marked as 'SAVE'. You can either add PADs or 'SAVE'
   attributes to the design, or run 'map -u' to disable logic trimming in
the
   mapper.

what means, NCD, PAD connections, because i used hierarchy connectors for
inputs and outputs and finally i don't understand this message, it's my
single error !!

If somebody can help me, don't hesitate !!

THX

SEB

--

****************************
Seb@stien.bizland.com
****************************



Article: 29499
Subject: Re: Searching for FPGA designer (PCI interface,DES, IDE)
From: Laurent Gauch <laurent.gauch@amontec.com>
Date: Fri, 23 Feb 2001 17:55:35 +0100
Links: << >>  << T >>  << A >>
Dear Argolis,

Amontec compagny is very interested in your project.
Why? Because we are actually able to integrate very quickly our own 
ezPCI core in a FPGA (Xilinx / Altera or others).

Using our ezPCI core, our last customer ( 3Vision www.3vision.com ) has 
developed a new specific PCI product in 2 weeks.
How can Amontec assure this 'Time-to-Market': because Amontec has 
developed not only the ezPCI core, but also we have developed the 
specific drivers for all the Windows OS (95/98/NT/2000).
Actually, our ezPCI Development System has been tested on different 
boards with XC4000E SPARTAN SPARTAN-II (3Vision board) and Virtex.

Using the ezPCI and the specific drivers, you just need to write your 
own high level software (C++ or Delphi or other) to run your specific 
application after our ezPCI core.
In fact, our ezPCI core generates an ezX bus (easy eXchange bus).
EzX accepts all the custom periph. your need.
Actually, we have 4 basic periph. supported by the ezX:
- a complet ezx/ISA bridge
- I2C master controler
- Xilinx FPGA loader (to download directly a second FPGA via the PCI bus)
- DDS (Direct Digital Synthetizer)
But we can build and add all the periph. your need.

Having experience in the SoCs, Amontec can propose you to design all 
digital parts of your project in one SPARTAN-II.

Actual ezPCI core performances:
-------------------------------------------------
Slave : Yes
Master : No
DMA : No
wait-state support : Yes
33 MHz : Yes
66 Mhz : Yes in some cases.
Fast back-to-back transfer : Yes
Prefetchable memory: Yes
Delayed transaction: Yes
Cached memory: No
Burst tranfert: Yes
Master Capability: No

With our experience, Amontec can help you in the totality of your 
project or only for the PCI part.
Since we are a small, efficient, and flexible organization, we have the 
ability to focus on solutions to your problems and to respond quickly to 
changing situations.

Best regards,

Laurent Gauch
Technical Director
Amontec
www.amontec.com
laurent.gauch@amontec.com
___________________________
Your FPGA Design Partner

AvdL wrote:

> Dear Sir/Madam,
> 
> We (Argolis) are a small company that develops smartcard technology.
> For our new project we need a PCI card that communicates with our
> reader (RS232-protocol). We want to place a FPGA on the PCI board that
> communicates with the smartcard reader, the computer (PCI) and IDE
> port. The FPGA must also be able to do DES. It would be nice if the
> FPGA also could handle compression of the data. The last option is not
> necessary. 
> Please contact us if your are interested in this project. We will
> provide the hardware and we ask from you to develop the source for the
> FPGA.
> 
> Kind regards,
> Argolis
> 
> Ad van de Laar
> 
> email to : info<at>argolis<dot>nl




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1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarApr2017

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

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